From patchwork Fri Jul 30 14:49:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 1511707 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=xBHhd9zv; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Gbr014FwJz9s1l for ; Sat, 31 Jul 2021 00:49:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239412AbhG3Otk (ORCPT ); Fri, 30 Jul 2021 10:49:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239423AbhG3Otf (ORCPT ); Fri, 30 Jul 2021 10:49:35 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5199C06179F for ; Fri, 30 Jul 2021 07:49:29 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id b7so13575234edu.3 for ; Fri, 30 Jul 2021 07:49:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U9K2fCuQkFkuejqJypW0+59cAZpu5FWH3o4en7PCa/U=; b=xBHhd9zvnsIklZ1GYG2DllDAjGkCvzS1dG3aJNp2jJBUjGCODD25G5qxsc2ero+kap RpCdICsb5OUgHCuWG7tnZnMbM3MenMlhhh6Us32/VRdY3+PzBzn8R4/DOJeoRZZE5rQ8 uzzVSVy/gCAn685CUUH8MSNnTu8iENv6JV7pC3EscmTCEj6NtZuXP58g8fwocXspBy1u MVIeizHdTl5IMp+ptpOLLfPsyg1TX0mDKnSatp61VSaOc1wiTWROa2J9DeGZvd/ygkHm X5duQR4eJDCRyu7okuNaMH+BeBYZyhWPWyAxgKidQsPo4pto1ZKIeHiRlfzVqJam76cc FA7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U9K2fCuQkFkuejqJypW0+59cAZpu5FWH3o4en7PCa/U=; b=e2zg7oKAcTPeKeyDIQP4F52WvV58Tp7VAlHirPSJJoeG/z5DJH9GO1KYfgp2H8zdh+ rPY0/RZUN1aXhi111gi/95mfm+yD+kozssohx/iHW6FBFM0Lu6Cp4cB8ywoP1DqBK+zN DbLndk+kY1YIBGzQKfc1WJZqpyPy3vDNgFMrgqttH9jSnZqft3Nuw2+3JNbOUbzv1Gak 5ZoA7/GM6+afhAb6mOBi2pE8jnWtZ1umQf0R6ngo1mABVyOpidD90H0KBBo0OwJO1ud4 C8vFDbSbnASs4+UOilTtQSBbusqopri/eWhuHQrs0n977PBxcdpsOiOnmNQBZTXa/6E4 IfFg== X-Gm-Message-State: AOAM530oxsO7yn3A0DX0KZ5soRCeNjxyv4PV+sK/l9pxUtkEeB2Nced3 nj+KU5UQ8+49G8/tKEBytcWsor1bW6CD4nfyY/4= X-Google-Smtp-Source: ABdhPJxvInSByeFK70X/NowaXTvQWPUys9gilEqsi8KsW2g7rqMqdK8b8pF3hHKfCXSK9nyni6+Zqg== X-Received: by 2002:a05:6402:411:: with SMTP id q17mr3370148edv.29.1627656568574; Fri, 30 Jul 2021 07:49:28 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id b15sm622945ejv.15.2021.07.30.07.49.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jul 2021 07:49:28 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa Cc: Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 03/12] dt-bindings: pinctrl: samsung: Add Exynos850 doc Date: Fri, 30 Jul 2021 17:49:13 +0300 Message-Id: <20210730144922.29111-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210730144922.29111-1-semen.protsenko@linaro.org> References: <20210730144922.29111-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document compatible string for Exynos850 SoC. Nothing else is changed, as Exynos850 SoC uses already existing samsung pinctrl driver. Signed-off-by: Sam Protsenko --- Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 38a1416fd2cd..e7a1b1880375 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -22,6 +22,7 @@ Required Properties: - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller. - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. + - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller. - reg: Base address of the pin controller hardware module and length of the address space it occupies. From patchwork Fri Jul 30 14:49:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 1511713 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=r4nEdjAh; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Gbr0R4lNSz9snk for ; Sat, 31 Jul 2021 00:49:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239542AbhG3OuC (ORCPT ); Fri, 30 Jul 2021 10:50:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239548AbhG3Otr (ORCPT ); Fri, 30 Jul 2021 10:49:47 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED98DC06179E for ; Fri, 30 Jul 2021 07:49:35 -0700 (PDT) Received: by mail-ed1-x52f.google.com with SMTP id h8so13546546ede.4 for ; Fri, 30 Jul 2021 07:49:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1JbUamQBQTeeK5FgvIv/xtu/RYU45rMZWaCOPLzo3D4=; b=r4nEdjAhktIKR3JHq/4i/7OL56PxGxvFITxQ2YHvG0hMvzdzChamM+0y7HGpkWbJ0S W+gaahiGEYZJUnwoDNHCjarA5xjhwRpvKFzpQyZDGaykdcbsRkh4558wVRz+Z6vpJs8C px0t8+H0rRgHvzTOo6hUMFbm6l8hJ1k37IG22v726mIIC9SUX9+Tu5sQW0Ln+zMk6csg mFMLPvdyYWuBUz+MzhlBRgy/0V7jyFjQScYnYv61AyqEXFA3IUpaHEn4xBpTgysWz5yS bmbfAZttptO2e72KrwJYsE4sdSw9ziBSCmW9nzXZwvJjEBIOz2XTBqIK2e8bPPNSEGIU MTwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1JbUamQBQTeeK5FgvIv/xtu/RYU45rMZWaCOPLzo3D4=; b=tYDJiWf0sfEmjgai6mynGyJkjZCox2YFc2t6KujWM2fJ0SR+GNyYwlUenVEropJ+M4 KueuX+pengrV1/ZkZTBN8Ar+QWJ7E/nsCDhLVGQfGZ/48r3BkbOKmsmz/0XFn8hEY8lq aSWRSJHRCHdBHF5yYIu5D0YL0Ty6LfOjbysvS3zxSYLmblIvM1f++S7j5Jzu50wsYBIA 8jpy3VUaxD2jP9xNGdNhJXLANbFyFYG+i3xAJnZA3/LrqH0P6aiL5OPEYgltfJl5Uob9 vQdy/6JJRmabvCajl8I56zVgtaxvofSz3kHwDo286HkQ0h1wXVNP0Fn8spgkKkMUL6zv MXgw== X-Gm-Message-State: AOAM532z8nSHkBSS42jrSBFUqhlQ81vWMq/tsVbe/b/CO83cD5owz/gV L/IALcs9kFJ+7S8hNcx/kFvhmg== X-Google-Smtp-Source: ABdhPJz42jwFfl72k417UQvTasfCAm8Hz1S5wW2zANurMaS3m2WAqU3tYXM2it7TQZzrU0ZmdahAYg== X-Received: by 2002:a05:6402:278e:: with SMTP id b14mr3338823ede.277.1627656574578; Fri, 30 Jul 2021 07:49:34 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id og35sm647731ejc.28.2021.07.30.07.49.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jul 2021 07:49:34 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa Cc: Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 07/12] dt-bindings: serial: samsung: Add Exynos850 doc Date: Fri, 30 Jul 2021 17:49:17 +0300 Message-Id: <20210730144922.29111-8-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210730144922.29111-1-semen.protsenko@linaro.org> References: <20210730144922.29111-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add compatible string for Exynos850 SoC. Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/serial/samsung_uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index f064e5b76cf1..2940afb874b3 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -26,6 +26,7 @@ properties: - samsung,s3c6400-uart - samsung,s5pv210-uart - samsung,exynos4210-uart + - samsung,exynos850-uart reg: maxItems: 1 From patchwork Fri Jul 30 14:49:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 1511715 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=hprBOmjD; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Gbr0Z6KZTz9t1r for ; Sat, 31 Jul 2021 00:50:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239294AbhG3OuH (ORCPT ); Fri, 30 Jul 2021 10:50:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239530AbhG3Ot5 (ORCPT ); Fri, 30 Jul 2021 10:49:57 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D346C06136B for ; Fri, 30 Jul 2021 07:49:39 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id b7so13575870edu.3 for ; Fri, 30 Jul 2021 07:49:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZLLSVppmE/RVCbEA1xTEsZE8W6wm39t886R9xa0xNrY=; b=hprBOmjDWtssr6PK7cLmgxAg2ovHOPaZumX+uWzBmSlXfpMGzu8z1alzVsckt8o1wK TWfpOiQRO7jOyKJBWt3hHikxhGhbiVpcQMZL/8GQGLRxeL8poHWeAXQX2442VL7A/5oE COBQ1eg3tlyZSuY+0jJOhve+U+F+iGTiDBdMZ/3SZkTZdtVEXoXYYuZpICn3k0e3EXmF krRW+tzZAjSk9HQhFLtsncCvwk6wQaSrwtp1+ZTwFMfIPzHhlAV5a9DN7D/fTWLK7nCf n7vsW16cg0zDrtNGMwa7nHUn/sRCElFEgdpMtupT/IYbKA5WJ2k7DQv84r5Uywhq4tgQ 0RKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZLLSVppmE/RVCbEA1xTEsZE8W6wm39t886R9xa0xNrY=; b=cDYPMClx33CIU0IEhFkyJKWysCa2qwoqcl96/1RBJ0JNU7u1adT+4lVjl6PIU3B7k4 /YNchnDdksewuw9yloEz75K9TmCAEaKPizaeooABBVn6lNQ/jqPojzzIONcwGJmPDHnP 2wwJDs866ix4rR3DOgMbdSnXHFEzbqBhojfSB/QMWBxIhxwxoI44SmfOUlfJxdhFOzok YwtM+/w+WgqDGadVVRj/dhfozwWDubGCUND1aEO5DswoWBVWWLugsS0k2pUoaPh0oRMR iyBddugGS1p3okxdGUFj73GUJgxx2FvD7PLw7HP2sd9fyiGQHIXiYZeXRlNXbk1I/2+T YiwA== X-Gm-Message-State: AOAM530xcD1VpuZ/dC5ZNbQfBMwKD5F8C4f0Jt/noqQgDmUjwA/eTihy iac1dnrsgZe5sAiMvVwIxu2VCA== X-Google-Smtp-Source: ABdhPJxaYUDPRno24m4L2mhXRl4xDHcwWipM1H7LYxjuZZp5osFydXTtJwofiJL/mifZMPo80yBrVA== X-Received: by 2002:a50:cf8c:: with SMTP id h12mr3308585edk.360.1627656577615; Fri, 30 Jul 2021 07:49:37 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id s24sm664883ejd.19.2021.07.30.07.49.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jul 2021 07:49:37 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa Cc: Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 09/12] dt-bindings: clock: Add bindings for Exynos850 clock controller Date: Fri, 30 Jul 2021 17:49:19 +0300 Message-Id: <20210730144922.29111-10-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210730144922.29111-1-semen.protsenko@linaro.org> References: <20210730144922.29111-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation for Exynos850 clock driver bindings and corresponding clock ID constants, which will be used further both in clock driver and in device tree files. Constants are grouped per domain basis (CMU) for more convenient usage, but those are just unique numbers and have nothing to do with register offsets, etc. Signed-off-by: Sam Protsenko --- .../bindings/clock/exynos850-clock.yaml | 70 +++++ include/dt-bindings/clock/exynos850.h | 267 ++++++++++++++++++ 2 files changed, 337 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos850-clock.yaml create mode 100644 include/dt-bindings/clock/exynos850.h diff --git a/Documentation/devicetree/bindings/clock/exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/exynos850-clock.yaml new file mode 100644 index 000000000000..201c2b79e629 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos850-clock.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/exynos850-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Samsung Exynos850 clock controller + +maintainers: + - Sam Protsenko + +description: | + The Exynos850 clock controller generates and supplies clock to various + controllers within the SoC. Each clock is assigned an identifier and client + nodes can use this identifier to specify the clock which they consume. + + All available clocks are defined as preprocessor macros in + dt-bindings/clock/exynos850.h header and can be used in device tree sources. + +properties: + compatible: + const: samsung,exynos850-clock + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock controller node + - | + clock: clock-controller@0x120e0000 { + compatible = "samsung,exynos850-clock"; + reg = <0x0 0x120e0000 0x8000>; + #clock-cells = <1>; + }; + + # Required external clocks (should be provided in particular board DTS) + - | + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos850-oscclk"; + clock-frequency = <26000000>; + }; + }; + + # UART controller node that consumes the clock generated by the clock + # controller + - | + #include + + serial_0: uart@13820000 { + compatible = "samsung,exynos850-uart"; + reg = <0x0 0x13820000 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + clocks = <&clock GATE_UART_QCH>, <&clock DOUT_UART>; + clock-names = "gate_uart_clk0", "uart"; + }; + +... diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h new file mode 100644 index 000000000000..b197db4427fc --- /dev/null +++ b/include/dt-bindings/clock/exynos850.h @@ -0,0 +1,267 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Device Tree binding constants for Exynos850 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H +#define _DT_BINDINGS_CLOCK_EXYNOS_850_H + +#define NONE (0 + 0) +#define OSCCLK (0 + 1) + +#define CLK_APM_BASE (10) +#define UMUX_DLL_USER (CLK_APM_BASE + 0) +#define UMUX_CLK_APM_BUS (CLK_APM_BASE + 1) +#define GATE_APM_CMU_APM_QCH (CLK_APM_BASE + 2) +#define GATE_GREBEINTEGRATION_QCH_GREBE (CLK_APM_BASE + 3) +#define GATE_GREBEINTEGRATION_QCH_DBG (CLK_APM_BASE + 4) +#define GATE_I3C_APM_PMIC_QCH_S_I3C (CLK_APM_BASE + 5) +#define GATE_I3C_APM_PMIC_QCH (CLK_APM_BASE + 6) +#define GATE_INTMEM_QCH (CLK_APM_BASE + 7) +#define GATE_MAILBOX_APM_AP_QCH (CLK_APM_BASE + 8) +#define GATE_MAILBOX_APM_CHUB_QCH (CLK_APM_BASE + 9) +#define GATE_MAILBOX_APM_CP_QCH (CLK_APM_BASE + 10) +#define GATE_MAILBOX_APM_GNSS_QCH (CLK_APM_BASE + 11) +#define GATE_MAILBOX_APM_WLBT_QCH (CLK_APM_BASE + 12) +#define GATE_MAILBOX_AP_CHUB_QCH (CLK_APM_BASE + 13) +#define GATE_MAILBOX_AP_CP_QCH (CLK_APM_BASE + 14) +#define GATE_MAILBOX_AP_CP_S_QCH (CLK_APM_BASE + 15) +#define GATE_MAILBOX_AP_GNSS_QCH (CLK_APM_BASE + 16) +#define GATE_MAILBOX_AP_WLBT_QCH (CLK_APM_BASE + 17) +#define GATE_MAILBOX_CP_CHUB_QCH (CLK_APM_BASE + 18) +#define GATE_MAILBOX_CP_GNSS_QCH (CLK_APM_BASE + 19) +#define GATE_MAILBOX_CP_WLBT_QCH (CLK_APM_BASE + 20) +#define GATE_MAILBOX_GNSS_CHUB_QCH (CLK_APM_BASE + 21) +#define GATE_MAILBOX_GNSS_WLBT_QCH (CLK_APM_BASE + 22) +#define GATE_MAILBOX_WLBT_ABOX_QCH (CLK_APM_BASE + 23) +#define GATE_MAILBOX_WLBT_CHUB_QCH (CLK_APM_BASE + 24) +#define GATE_PMU_INTR_GEN_QCH (CLK_APM_BASE + 25) +#define GATE_ROM_CRC32_HOST_QCH (CLK_APM_BASE + 26) +#define GATE_SPEEDY_APM_QCH (CLK_APM_BASE + 27) +#define GATE_WDT_APM_QCH (CLK_APM_BASE + 28) + +#define CLK_AUD_BASE (50) +#define UMUX_CLK_AUD_CPU_HCH (CLK_AUD_BASE + 0) +#define GATE_ABOX_QCH_CPU (CLK_AUD_BASE + 1) +#define GATE_ABOX_QCH_ACLK (CLK_AUD_BASE + 2) +#define GATE_ABOX_QCH_BCLK0 (CLK_AUD_BASE + 3) +#define GATE_ABOX_QCH_BCLK1 (CLK_AUD_BASE + 4) +#define GATE_ABOX_QCH_FM (CLK_AUD_BASE + 5) +#define GATE_ABOX_QCH_BCLK2 (CLK_AUD_BASE + 6) +#define GATE_ABOX_QCH_CCLK_ASB (CLK_AUD_BASE + 7) +#define GATE_ABOX_QCH_BCLK3 (CLK_AUD_BASE + 8) +#define GATE_ABOX_QCH_BCLK4 (CLK_AUD_BASE + 9) +#define GATE_ABOX_QCH_BCLK5 (CLK_AUD_BASE + 10) +#define GATE_ABOX_QCH_BCLK6 (CLK_AUD_BASE + 11) +#define GATE_ABOX_QCH_BCLK_CNT (CLK_AUD_BASE + 12) +#define GATE_AUD_CMU_AUD_QCH (CLK_AUD_BASE + 13) +#define GATE_GPIO_AUD_QCH (CLK_AUD_BASE + 14) +#define GATE_SYSMMU_AUD_QCH_S1 (CLK_AUD_BASE + 15) +#define GATE_WDT_AUD_QCH (CLK_AUD_BASE + 16) +#define PLL_AUD_OUT (CLK_AUD_BASE + 17) +#define DOUT_CLK_AUD_CPU (CLK_AUD_BASE + 18) +#define DOUT_CLK_AUD_CPU_ACLK (CLK_AUD_BASE + 19) +#define DOUT_CLK_AUD_CPU_PCLKDBG (CLK_AUD_BASE + 20) +#define DOUT_CLK_AUD_BUSD (CLK_AUD_BASE + 21) +#define DOUT_CLK_AUD_UAIF0 (CLK_AUD_BASE + 23) +#define DOUT_CLK_AUD_UAIF1 (CLK_AUD_BASE + 24) +#define DOUT_CLK_AUD_FM (CLK_AUD_BASE + 25) +#define DOUT_CLK_AUD_BUSP (CLK_AUD_BASE + 26) +#define DOUT_CLK_AUD_UAIF2 (CLK_AUD_BASE + 27) +#define DOUT_CLK_AUD_CNT (CLK_AUD_BASE + 28) +#define DOUT_CLK_AUD_UAIF3 (CLK_AUD_BASE + 29) +#define DOUT_CLK_AUD_UAIF4 (CLK_AUD_BASE + 30) +#define DOUT_CLK_AUD_UAIF5 (CLK_AUD_BASE + 31) +#define DOUT_CLK_AUD_UAIF6 (CLK_AUD_BASE + 32) +#define DOUT_CLK_AUD_AUDIF (CLK_AUD_BASE + 33) +#define DOUT_CLK_AUD_MCLK (CLK_AUD_BASE + 34) +#define UMUX_CLK_AUD_FM (CLK_AUD_BASE + 35) + +#define CLK_CHUB_BASE (100) +#define GATE_BAAW_C_CHUB_QCH (CLK_CHUB_BASE + 0) +#define GATE_BAAW_D_CHUB_QCH (CLK_CHUB_BASE + 1) +#define GATE_CHUB_CMU_CHUB_QCH (CLK_CHUB_BASE + 2) +#define GATE_CM4_CHUB_QCH (CLK_CHUB_BASE + 3) +#define GATE_DMIC_AHB0_QCH (CLK_CHUB_BASE + 4) +#define GATE_DMIC_IF_QCH_PCLK (CLK_CHUB_BASE + 5) +#define GATE_DMIC_IF_QCH_DMIC_CLK (CLK_CHUB_BASE + 6) +#define GATE_HWACG_SYS_DMIC0_QCH (CLK_CHUB_BASE + 7) +#define GATE_PWM_CHUB_QCH (CLK_CHUB_BASE + 8) +#define GATE_SWEEPER_C_CHUB_QCH (CLK_CHUB_BASE + 9) +#define GATE_SWEEPER_D_CHUB_QCH (CLK_CHUB_BASE + 10) +#define GATE_TIMER_CHUB_QCH (CLK_CHUB_BASE + 11) +#define GATE_WDT_CHUB_QCH (CLK_CHUB_BASE + 12) +#define GATE_U_DMIC_CLK_SCAN_MUX_QCH (CLK_CHUB_BASE + 13) +#define DOUT_CLK_CHUB_BUS (CLK_CHUB_BASE + 14) +#define DOUT_CLK_CHUB_DMIC_IF (CLK_CHUB_BASE + 15) +#define DOUT_CLK_CHUB_DMIC_IF_DIV2 (CLK_CHUB_BASE + 16) +#define DOUT_CLK_CHUB_DMIC (CLK_CHUB_BASE + 17) + +#define CLK_CMGP_BASE (150) +#define UMUX_CLK_CMGP_USI_CMGP0 (CLK_CMGP_BASE + 0) +#define UMUX_CLK_CMGP_USI_CMGP1 (CLK_CMGP_BASE + 1) +#define GATE_ADC_CMGP_QCH_S0 (CLK_CMGP_BASE + 2) +#define GATE_ADC_CMGP_QCH_S1 (CLK_CMGP_BASE + 3) +#define GATE_ADC_CMGP_QCH_ADC (CLK_CMGP_BASE + 4) +#define GATE_CMGP_CMU_CMGP_QCH (CLK_CMGP_BASE + 5) +#define GATE_GPIO_CMGP_QCH (CLK_CMGP_BASE + 6) +#define GATE_USI_CMGP0_QCH (CLK_CMGP_BASE + 7) +#define GATE_USI_CMGP1_QCH (CLK_CMGP_BASE + 8) +#define DOUT_CLK_CMGP_ADC (CLK_CMGP_BASE + 9) +#define DOUT_CLK_CMGP_USI_CMGP0 (CLK_CMGP_BASE + 10) +#define DOUT_CLK_CMGP_USI_CMGP1 (CLK_CMGP_BASE + 11) + +#define CLK_TOP_BASE (200) +#define GATE_CMU_TOP_CMUREF_QCH (CLK_TOP_BASE + 0) +#define GATE_DFTMUX_CMU_QCH_CLK_CIS0 (CLK_TOP_BASE + 1) +#define GATE_DFTMUX_CMU_QCH_CLK_CIS1 (CLK_TOP_BASE + 2) +#define GATE_DFTMUX_CMU_QCH_CLK_CIS2 (CLK_TOP_BASE + 3) +#define GATE_OTP_QCH (CLK_TOP_BASE + 4) +#define GATE_ADM_AHB_SSS_QCH (CLK_TOP_BASE + 5) +#define GATE_BAAW_P_CHUB_QCH (CLK_TOP_BASE + 6) +#define GATE_BAAW_P_GNSS_QCH (CLK_TOP_BASE + 7) +#define GATE_BAAW_P_MODEM_QCH (CLK_TOP_BASE + 8) +#define GATE_BAAW_P_WLBT_QCH (CLK_TOP_BASE + 9) + +#define CLK_CORE_BASE (250) +#define GATE_CCI_550_QCH (CLK_CORE_BASE + 0) +#define GATE_CORE_CMU_CORE_QCH (CLK_CORE_BASE + 1) +#define GATE_GIC_QCH (CLK_CORE_BASE + 2) +#define GATE_GPIO_CORE_QCH (CLK_CORE_BASE + 3) +#define GATE_MMC_EMBD_QCH (CLK_CORE_BASE + 4) +#define GATE_PDMA_CORE_QCH (CLK_CORE_BASE + 5) +#define GATE_RTIC_QCH (CLK_CORE_BASE + 6) +#define GATE_SPDMA_CORE_QCH (CLK_CORE_BASE + 7) +#define GATE_SSS_QCH (CLK_CORE_BASE + 8) +#define GATE_TREX_D_CORE_QCH (CLK_CORE_BASE + 9) +#define GATE_TREX_P_CORE_QCH (CLK_CORE_BASE + 10) +#define GATE_CSSYS_DBG_QCH (CLK_CORE_BASE + 11) +#define GATE_SECJTAG_QCH (CLK_CORE_BASE + 12) +#define DOUT_CORE_MMC_EMBD (CLK_CORE_BASE + 13) + +#define CLK_DPU_BASE (300) +#define GATE_DPU_QCH_S_DPP (CLK_DPU_BASE + 0) +#define GATE_DPU_QCH_S_DMA (CLK_DPU_BASE + 1) +#define GATE_DPU_QCH_S_DECON (CLK_DPU_BASE + 2) +#define GATE_DPU_CMU_DPU_QCH (CLK_DPU_BASE + 3) +#define GATE_SMMU_DPU_QCH (CLK_DPU_BASE + 4) +#define DOUT_CLK_DPU_BUSP (CLK_DPU_BASE + 5) + +#define CLK_G3D_BASE (350) +#define GATE_G3D_CMU_G3D_QCH (CLK_G3D_BASE + 0) +#define GATE_GPU_QCH (CLK_G3D_BASE + 1) +#define DOUT_CLK_G3D_BUSP (CLK_G3D_BASE + 2) + +#define CLK_HIS_BASE (400) +#define GATE_GPIO_HSI_QCH (CLK_HIS_BASE + 0) +#define GATE_HSI_CMU_HSI_QCH (CLK_HIS_BASE + 1) +#define GATE_MMC_CARD_QCH (CLK_HIS_BASE + 2) +#define GATE_USB20DRD_TOP_QCH_LINK (CLK_HIS_BASE + 3) +#define GATE_USB20DRD_TOP_QCH_20CTRL (CLK_HIS_BASE + 4) +#define GATE_USB20DRD_TOP_QCH_REFCLK (CLK_HIS_BASE + 5) +#define GATE_USB20DRD_TOP_QCH_RTC (CLK_HIS_BASE + 6) +#define PLL_MMC_OUT (CLK_HIS_BASE + 7) +#define HSI_BUS (CLK_HIS_BASE + 8) +#define HSI_MMC_CARD (CLK_HIS_BASE + 9) +#define HSI_USB20DRD (CLK_HIS_BASE + 10) + +#define CLK_IS_BASE (450) +#define GATE_CSIS0_QCH (CLK_IS_BASE + 0) +#define GATE_CSIS1_QCH (CLK_IS_BASE + 1) +#define GATE_CSIS2_QCH (CLK_IS_BASE + 2) +#define GATE_IS_CMU_IS_QCH (CLK_IS_BASE + 3) +#define GATE_IS_TOP_QCH_S_00 (CLK_IS_BASE + 4) +#define GATE_IS_TOP_QCH_S_02 (CLK_IS_BASE + 5) +#define GATE_IS_TOP_QCH_S_03 (CLK_IS_BASE + 6) +#define GATE_IS_TOP_QCH_S_04 (CLK_IS_BASE + 7) +#define GATE_IS_TOP_QCH_S_05 (CLK_IS_BASE + 8) +#define GATE_IS_TOP_QCH_S_06 (CLK_IS_BASE + 9) +#define GATE_SYSMMU_IS0_QCH (CLK_IS_BASE + 10) +#define GATE_SYSMMU_IS1_QCH (CLK_IS_BASE + 11) +#define IS_BUS (CLK_IS_BASE + 12) +#define IS_VRA (CLK_IS_BASE + 13) +#define IS_ITP (CLK_IS_BASE + 14) +#define IS_GDC (CLK_IS_BASE + 15) +#define UMUX_CLK_IS_BUS (CLK_IS_BASE + 15) +#define UMUX_CLK_IS_ITP (CLK_IS_BASE + 16) +#define UMUX_CLK_IS_VRA (CLK_IS_BASE + 17) +#define UMUX_CLK_IS_GDC (CLK_IS_BASE + 18) +#define GATE_CLK_ITP (CLK_IS_BASE + 19) +#define GATE_CLK_VRA (CLK_IS_BASE + 20) +#define GATE_CLK_GDC (CLK_IS_BASE + 21) +#define CIS_CLK0 (CLK_IS_BASE + 22) +#define CIS_CLK1 (CLK_IS_BASE + 23) +#define CIS_CLK2 (CLK_IS_BASE + 24) + +#define CLK_MFCMSCL_BASE (500) +#define GATE_JPEG_QCH (CLK_MFCMSCL_BASE + 0) +#define GATE_M2M_QCH (CLK_MFCMSCL_BASE + 1) +#define GATE_MCSC_QCH (CLK_MFCMSCL_BASE + 2) +#define GATE_MFC_QCH (CLK_MFCMSCL_BASE + 3) +#define GATE_MFCMSCL_CMU_MFCMSCL_QCH (CLK_MFCMSCL_BASE + 4) +#define GATE_SYSMMU_MFCMSCL_QCH (CLK_MFCMSCL_BASE + 5) +#define GATE_CMU_MIF_CMUREF_QCH (CLK_MFCMSCL_BASE + 6) +#define GATE_DMC_QCH (CLK_MFCMSCL_BASE + 7) +#define GATE_MIF_CMU_MIF_QCH (CLK_MFCMSCL_BASE + 8) +#define GATE_CMU_MIF1_CMU_REF_QCH (CLK_MFCMSCL_BASE + 9) +#define GATE_DMC1_QCH (CLK_MFCMSCL_BASE + 10) +#define GATE_MIF1_CMU_MIF1_QCH (CLK_MFCMSCL_BASE + 11) +#define GATE_MODEM_CMU_MODEM_QCH (CLK_MFCMSCL_BASE + 12) +#define DOUT_CLK_MFCMSCL_BUSP (CLK_MFCMSCL_BASE + 13) +#define MFCMSCL_MFC (CLK_MFCMSCL_BASE + 14) +#define MFCMSCL_M2M (CLK_MFCMSCL_BASE + 15) +#define MFCMSCL_MCSC (CLK_MFCMSCL_BASE + 16) +#define MFCMSCL_JPEG (CLK_MFCMSCL_BASE + 17) +#define UMUX_CLKCMU_MFCMSCL_MFC (CLK_MFCMSCL_BASE + 18) +#define UMUX_CLKCMU_MFCMSCL_M2M (CLK_MFCMSCL_BASE + 19) +#define UMUX_CLKCMU_MFCMSCL_MCSC (CLK_MFCMSCL_BASE + 20) +#define UMUX_CLKCMU_MFCMSCL_JPEG (CLK_MFCMSCL_BASE + 21) + +#define CLK_PERI_BASE (550) +#define UMUX_CLKCMU_PERI_BUS_USER (CLK_PERI_BASE + 0) +#define UMUX_CLKCMU_PERI_UART_USER (CLK_PERI_BASE + 1) +#define UMUX_CLKCMU_PERI_HSI2C_USER (CLK_PERI_BASE + 2) +#define UMUX_CLKCMU_PERI_SPI_USER (CLK_PERI_BASE + 3) +#define GATE_BUSIF_TMU_QCH (CLK_PERI_BASE + 4) +#define GATE_GPIO_PERI_QCH (CLK_PERI_BASE + 5) +#define GATE_HSI2C_0_QCH (CLK_PERI_BASE + 6) +#define GATE_HSI2C_1_QCH (CLK_PERI_BASE + 7) +#define GATE_HSI2C_2_QCH (CLK_PERI_BASE + 8) +#define GATE_I2C_0_QCH (CLK_PERI_BASE + 9) +#define GATE_I2C_1_QCH (CLK_PERI_BASE + 10) +#define GATE_I2C_2_QCH (CLK_PERI_BASE + 11) +#define GATE_I2C_3_QCH (CLK_PERI_BASE + 12) +#define GATE_I2C_4_QCH (CLK_PERI_BASE + 13) +#define GATE_I2C_5_QCH (CLK_PERI_BASE + 14) +#define GATE_I2C_6_QCH (CLK_PERI_BASE + 15) +#define GATE_MCT_QCH (CLK_PERI_BASE + 16) +#define GATE_OTP_CON_TOP_QCH (CLK_PERI_BASE + 17) +#define GATE_PWM_MOTOR_QCH (CLK_PERI_BASE + 18) +#define GATE_SPI_0_QCH (CLK_PERI_BASE + 19) +#define GATE_UART_QCH (CLK_PERI_BASE + 20) +#define GATE_WDT_0_QCH (CLK_PERI_BASE + 21) +#define GATE_WDT_1_QCH (CLK_PERI_BASE + 22) +#define DOUT_CLK_PERI_SPI_0 (CLK_PERI_BASE + 23) +#define DOUT_CLK_PERI_HSI2C_0 (CLK_PERI_BASE + 24) +#define DOUT_CLK_PERI_HSI2C_1 (CLK_PERI_BASE + 25) +#define DOUT_CLK_PERI_HSI2C_2 (CLK_PERI_BASE + 26) +#define DOUT_I2C_0 (CLK_PERI_BASE + 27) +#define DOUT_I2C_1 (CLK_PERI_BASE + 28) +#define DOUT_I2C_2 (CLK_PERI_BASE + 29) +#define DOUT_I2C_3 (CLK_PERI_BASE + 30) +#define DOUT_I2C_4 (CLK_PERI_BASE + 31) +#define DOUT_I2C_5 (CLK_PERI_BASE + 32) +#define DOUT_I2C_6 (CLK_PERI_BASE + 33) +#define DOUT_UART (CLK_PERI_BASE + 34) + +#define CLK_CLKOUT_BASE (700) +#define OSC_NFC (CLK_CLKOUT_BASE + 0) +#define OSC_AUD (CLK_CLKOUT_BASE + 1) + +/* Must be greater than maximal clock ID */ +#define CLK_NR_CLKS (1125 + 1) + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */ From patchwork Fri Jul 30 14:49:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 1511718 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Oh/SWTvG; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with 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linux-serial@vger.kernel.org Subject: [PATCH 11/12] dt-bindings: interrupt-controller: Add IRQ constants for Exynos850 Date: Fri, 30 Jul 2021 17:49:21 +0300 Message-Id: <20210730144922.29111-12-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210730144922.29111-1-semen.protsenko@linaro.org> References: <20210730144922.29111-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add external GIC interrupt constants for SPI[479:0] for Exynos850 SoC. Interrupt names were taken from TRM without change, hence double underscore in const namings. Only level-sensitive interrupt is allowed for each SPI, so each SPI should be configured as level-sensitive in GIC. Also update MAINTAINERS file, so that Exynos interrupt binding headers are covered in "ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES" section. Signed-off-by: Sam Protsenko --- MAINTAINERS | 1 + .../interrupt-controller/exynos850.h | 290 ++++++++++++++++++ 2 files changed, 291 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/exynos850.h diff --git a/MAINTAINERS b/MAINTAINERS index 4483ccb46883..ceb929e6bfa7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2488,6 +2488,7 @@ F: drivers/pwm/pwm-samsung.c F: drivers/soc/samsung/ F: drivers/tty/serial/samsung* F: include/clocksource/samsung_pwm.h +F: include/dt-bindings/interrupt-controller/exynos*.h F: include/linux/platform_data/*s3c* F: include/linux/serial_s3c.h F: include/linux/soc/samsung/ diff --git a/include/dt-bindings/interrupt-controller/exynos850.h b/include/dt-bindings/interrupt-controller/exynos850.h new file mode 100644 index 000000000000..0c24ba2e27da --- /dev/null +++ b/include/dt-bindings/interrupt-controller/exynos850.h @@ -0,0 +1,290 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Device Tree binding constants for Exynos850 interrupt controller. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_850_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_850_H + +#include + +#define INTREQ__ADC_CMGP2AP 0 +#define INTREQ__ALIVE_EINT0 1 +#define INTREQ__ALIVE_EINT1 2 +#define INTREQ__ALIVE_EINT2 3 +#define INTREQ__ALIVE_EINT3 4 +#define INTREQ__ALIVE_EINT4 5 +#define INTREQ__ALIVE_EINT5 6 +#define INTREQ__ALIVE_EINT6 7 +#define INTREQ__ALIVE_EINT7 8 +#define INTREQ__ALIVE_EINT8 9 +#define INTREQ__ALIVE_EINT9 10 +#define INTREQ__ALIVE_EINT10 11 +#define INTREQ__ALIVE_EINT11 12 +#define INTREQ__ALIVE_EINT12 13 +#define INTREQ__ALIVE_EINT13 14 +#define INTREQ__ALIVE_EINT14 15 +#define INTREQ__ALIVE_EINT15 16 +#define INTREQ__ALIVE_EINT16 17 +#define INTREQ__ALIVE_EINT17 18 +#define INTREQ__ALIVE_EINT18 19 +#define INTREQ__ALIVE_EINT19 20 +#define INTREQ__ALIVE_EINT20 21 +#define INTREQ__ALIVE_EINT21 22 +#define INTREQ__ALIVE_EINT22 23 +#define INTREQ__ALIVE_EINT23 24 +#define INTREQ__ALIVE_EINT24 25 +#define INTREQ__ALIVE_EINT25 26 +#define INTREQ__ALIVE_EINT26 27 +#define INTREQ__ALIVE_EINT27 28 +#define INTREQ__ALIVE_EINT28 29 +#define INTREQ__ALIVE_EINT29 30 +#define INTREQ__ALIVE_EINT30 31 +#define INTREQ__ALIVE_EINT31 32 +#define INTREQ__ALIVE_EINT32 33 +#define INTREQ__ALIVE_EINT33 34 +#define INTREQ__ALIVE_EINT34 35 +#define INTREQ__ALIVE_EINT35 36 +#define INTREQ__ALIVE_GNSS_ACTIVE 37 +#define INTREQ__ALIVE_WLBT_ACTIVE 38 +#define INTREQ__CMGP_EXT_INTM00 39 +#define INTREQ__CMGP_EXT_INTM01 40 +#define INTREQ__CMGP_EXT_INTM02 41 +#define INTREQ__CMGP_EXT_INTM03 42 +#define INTREQ__CMGP_EXT_INTM04 43 +#define INTREQ__CMGP_EXT_INTM05 44 +#define INTREQ__CMGP_EXT_INTM06 45 +#define INTREQ__CMGP_EXT_INTM07 46 +#define INTREQ__COMB_SFI_CE_NONSECURE_SYSREG_APM 47 +#define INTREQ__COMB_SFI_UCE_NONSECURE_SYSREG_APM 48 +#define INTREQ__MAILBOX_APM2AP 49 +#define INTREQ__MAILBOX_CHUB2AP 50 +#define INTREQ__MAILBOX_CP2AP 51 +#define INTREQ__MAILBOX_CP2AP_S 52 +#define INTREQ__MAILBOX_GNSS2AP 53 +#define INTREQ__MAILBOX_WLBT2AP 54 +#define INTREQ__NOTIFY 55 +#define INTREQ__PMIC 56 +#define INTREQ__RTC_ALARM_INT 57 +#define INTREQ__RTC_TIC_INT_0 58 +#define INTREQ__SPEEDY_APM 59 +#define INTREQ__TOP_RTC_ALARM_INT 60 +#define INTREQ__TOP_RTC_TIC_INT_0 61 +#define INTREQ__USI_CMGP0 62 +#define INTREQ__USI_CMGP1 63 +#define INTREQ__AUD_ABOX_GIC400_MCPU 64 +#define INTREQ__AUD_WDT 65 +#define INTREQ__SYSMMU_ABOX_S1_NS 66 +#define INTREQ__SYSMMU_ABOX_S1_S 67 +#define INTREQ__PWM_CHUB_0 68 +#define INTREQ__PWM_CHUB_1 69 +#define INTREQ__PWM_CHUB_2 70 +#define INTREQ__PWM_CHUB_3 71 +#define INTREQ__TIMER_CHUB 72 +#define INTREQ__WDT_CHUB 73 +#define INTREQ__CPUCL0_CLUSTERPMUIRQ 74 +#define INTREQ__CPUCL0_COMMIRQ_0 75 +#define INTREQ__CPUCL0_COMMIRQ_1 76 +#define INTREQ__CPUCL0_COMMIRQ_2 77 +#define INTREQ__CPUCL0_COMMIRQ_3 78 +#define INTREQ__CPUCL0_ERRIRQ_0 79 +#define INTREQ__CPUCL0_ERRIRQ_1 80 +#define INTREQ__CPUCL0_ERRIRQ_2 81 +#define INTREQ__CPUCL0_ERRIRQ_3 82 +#define INTREQ__CPUCL0_ERRIRQ_4 83 +#define INTREQ__CPUCL0_FAULTIRQ_0 84 +#define INTREQ__CPUCL0_FAULTIRQ_1 85 +#define INTREQ__CPUCL0_FAULTIRQ_2 86 +#define INTREQ__CPUCL0_FAULTIRQ_3 87 +#define INTREQ__CPUCL0_FAULTIRQ_4 88 +#define INTREQ__CPUCL0_PMUIRQ_0 89 +#define INTREQ__CPUCL0_PMUIRQ_1 90 +#define INTREQ__CPUCL0_PMUIRQ_2 91 +#define INTREQ__CPUCL0_PMUIRQ_3 92 +#define INTREQ__CPUCL1_CLUSTERPMUIRQ 93 +#define INTREQ__CPUCL1_COMMIRQ_0 94 +#define INTREQ__CPUCL1_COMMIRQ_1 95 +#define INTREQ__CPUCL1_COMMIRQ_2 96 +#define INTREQ__CPUCL1_COMMIRQ_3 97 +#define INTREQ__CPUCL1_ERRIRQ_0 98 +#define INTREQ__CPUCL1_ERRIRQ_1 99 +#define INTREQ__CPUCL1_ERRIRQ_2 100 +#define INTREQ__CPUCL1_ERRIRQ_3 101 +#define INTREQ__CPUCL1_ERRIRQ_4 102 +#define INTREQ__CPUCL1_FAULTIRQ_0 103 +#define INTREQ__CPUCL1_FAULTIRQ_1 104 +#define INTREQ__CPUCL1_FAULTIRQ_2 105 +#define INTREQ__CPUCL1_FAULTIRQ_3 106 +#define INTREQ__CPUCL1_FAULTIRQ_4 107 +#define INTREQ__CPUCL1_PMUIRQ_0 108 +#define INTREQ__CPUCL1_PMUIRQ_1 109 +#define INTREQ__CPUCL1_PMUIRQ_2 110 +#define INTREQ__CPUCL1_PMUIRQ_3 111 +#define INTREQ__DECON0_EXTRA 112 +#define INTREQ__DECON0_FRAME_DONE 113 +#define INTREQ__DECON0_FRAME_START 114 +#define INTREQ__DECON0_UNDER_FLOW 115 +#define INTREQ__DPP_VG0 116 +#define INTREQ__DPU_DMA_G0 117 +#define INTREQ__DPU_DMA_G1 118 +#define INTREQ__DPU_DMA_GF 119 +#define INTREQ__DPU_DMA_VG0 120 +#define INTREQ__DSIM0 121 +#define INTREQ__SMMU_DPU_NS 122 +#define INTREQ__SMMU_DPU_S 123 +#define INTREQ__G3D_IRQEVENT 124 +#define INTREQ__G3D_IRQGPU 125 +#define INTREQ__G3D_IRQJOB 126 +#define INTREQ__G3D_IRQMMU 127 +#define INTREQ__GNSS_SW_INT 128 +#define INTREQ__GNSS_WAKEUP_INT 129 +#define INTREQ__GNSS_WDOG_RESET 130 +#define INTREQ__GPIO_HSI 131 +#define INTREQ__MMC_CARD 132 +#define INTREQ__PPMU_HSI_UPPER 133 +#define INTREQ__USB2_REMOTE_CONNECT 134 +#define INTREQ__USB2_REMOTE_TIMER 135 +#define INTREQ__USB2_REMOTE_WAKEUP 136 +#define INTREQ__USB20DRD_0 137 +#define INTREQ__USB20DRD_1 138 +#define INTREQ__USB20_PHY_FSVMINUS 139 +#define INTREQ__USB20_PHY_FSVPLUS 140 +#define INTREQ__CSIS0 141 +#define INTREQ__CSIS1 142 +#define INTREQ__CSIS2 143 +#define INTREQ__CSIS_DMA_0 144 +#define INTREQ__CSIS_DMA_1 145 +#define INTREQ__GDC 146 +#define INTREQ__IPP0_0 147 +#define INTREQ__CPUCL0_CTIIRQ_0 148 +#define INTREQ__CPUCL0_CTIIRQ_1 149 +#define INTREQ__CPUCL0_CTIIRQ_2 150 +#define INTREQ__CPUCL0_CTIIRQ_3 151 +#define INTREQ__CPUCL1_CTIIRQ_0 152 +#define INTREQ__CPUCL1_CTIIRQ_1 153 +#define INTREQ__CPUCL1_CTIIRQ_2 154 +#define INTREQ__CPUCL1_CTIIRQ_3 155 +#define INTREQ__IPP0_1 156 +#define INTREQ__IPP1_0 157 +#define INTREQ__IPP1_1 158 +#define INTREQ__ITP_0 159 +#define INTREQ__ITP_1 160 +#define INTREQ__MCSC_IS 161 +#define INTREQ__PPMU_IS0_UPPER_OR_NORMAL 162 +#define INTREQ__PPMU_IS1_UPPER_OR_NORMAL 163 +#define INTREQ__SYSMMU_IS0_S1_NS 164 +#define INTREQ__SYSMMU_IS0_S1_S 165 +#define INTREQ__SYSMMU_IS1_S1_NS 166 +#define INTREQ__SYSMMU_IS1_S1_S 167 +#define INTREQ__VRA 168 +#define INTREQ__JPEG 169 +#define INTREQ__M2M 170 +#define INTREQ__MCSC_MFC 171 +#define INTREQ__MFC 172 +#define INTREQ__PPMU_MFCMSCL_interrupt_upper_or_normal 173 +#define INTREQ__SYSMMU_MFCMSCL_S1_NS 174 +#define INTREQ__SYSMMU_MFCMSCL_S1_S 175 +#define INTREQ__DERATE_INTR_MIF0 176 +#define INTREQ__DMC_INTR_MIF0 177 +#define INTREQ__DMC_PEREV_INTR_MIF0 178 +#define INTREQ__HIGHTEMP_INTR_MIF0 179 +#define INTREQ__NORMTEMP_INTR_MIF0 180 +#define INTREQ__PPMU_UPPER_OR_NORMAL_MIF0 181 +#define INTREQ__TEMPERR_INTR_MIF0 182 +#define INTREQ__DERATE_INTR_MIF1 183 +#define INTREQ__DMC_INTR_MIF1 184 +#define INTREQ__DMC_PEREV_INTR_MIF1 185 +#define INTREQ__HIGHTEMP_INTR_MIF1 186 +#define INTREQ__NORMTEMP_INTR_MIF1 187 +#define INTREQ__PPMU_UPPER_OR_NORMAL_MIF1 188 +#define INTREQ__TEMPERR_INTR_MIF1 189 +#define INTREQ__RESET_REQ 190 +#define INTREQ__SFR_BUS_RDY 191 +#define INTREQ__GPIO_PERI 192 +#define INTREQ__HSI2C_0 193 +#define INTREQ__HSI2C_1 194 +#define INTREQ__HSI2C_2 195 +#define INTREQ__I2C_0 196 +#define INTREQ__I2C_1 197 +#define INTREQ__I2C_2 198 +#define INTREQ__I2C_3 199 +#define INTREQ__I2C_4 200 +#define INTREQ__I2C_5 201 +#define INTREQ__I2C_6 202 +#define INTREQ__MCT_G0 203 +#define INTREQ__MCT_G1 204 +#define INTREQ__MCT_G2 205 +#define INTREQ__MCT_G3 206 +#define INTREQ__MCT_L0 207 +#define INTREQ__MCT_L1 208 +#define INTREQ__MCT_L2 209 +#define INTREQ__MCT_L3 210 +#define INTREQ__MCT_L4 211 +#define INTREQ__MCT_L5 212 +#define INTREQ__MCT_L6 213 +#define INTREQ__MCT_L7 214 +#define INTREQ__OTP_CON 215 +#define INTREQ__PWM0 216 +#define INTREQ__PWM1 217 +#define INTREQ__PWM2 218 +#define INTREQ__PWM3 219 +#define INTREQ__PWM4 220 +#define INTREQ__SPI_0 221 + +#define INTREQ__SECURE_LOG 224 +#define INTREQ__TBASE 223 +#define INTREQ__RPMB 225 + +#define INTREQ__TMU 226 +#define INTREQ__UART 227 +#define INTREQ__WDT_0 228 +#define INTREQ__WDT_1 229 +#define INTREQ__WB2AP_CFG_REQ 230 +#define INTREQ__WB2AP_WDOG_RESET_REQ_IRQ 231 +#define INTREQ__CCI_NEVNTCNTOVERFLOW_7 438 +#define INTREQ__CCI_NEVNTCNTOVERFLOW_6 439 +#define INTREQ__CCI_NEVNTCNTOVERFLOW_5 440 +#define INTREQ__CCI_NEVNTCNTOVERFLOW_4 441 +#define INTREQ__CCI_NEVNTCNTOVERFLOW_3 442 +#define INTREQ__CCI_NEVNTCNTOVERFLOW_2 443 +#define INTREQ__CCI_NEVNTCNTOVERFLOW_1 444 +#define INTREQ__CCI_NEVNTCNTOVERFLOW_0 445 +#define INTREQ__CCI_NERR 446 +#define INTREQ__PPMU_ACE_CPUCL1_LOW 447 +#define INTREQ__PPMU_ACE_CPUCL1_UPN 448 +#define INTREQ__PPMU_ACE_CPUCL0_LOW 449 +#define INTREQ__PPMU_ACE_CPUCL0_UPN 450 +#define INTREQ__GPIO_CORE 451 +#define INTREQ__MMC_EMBD_CORE 452 +#define INTREQ__RTIC 453 +#define INTREQ__SSS_WDT2 454 +#define INTREQ__SSS_WDT1 455 +#define INTREQ__SSS_KM 456 +#define INTREQ__SSS_MAILBOX 457 +#define INTREQ__SSS 458 +#define INTREQ__TREX_P_CORE_PPMU_M_PERI 459 +#define INTREQ__TREX_P_CORE_PPMU_M_CPU 460 +#define INTREQ__TREX_P_CORE_DEBUG_INT 461 +#define INTREQ__TREX_D_CORE_DEBUG_INT 462 +#define INTREQ__TREX_D_CORE_PPMU_S_PERI 463 +#define INTREQ__TREX_D_CORE_PPMU_NRT_MEM1 464 +#define INTREQ__TREX_D_CORE_PPMU_NRT_MEM0 465 +#define INTREQ__TREX_D_CORE_PPMU_RT_MEM1 466 +#define INTREQ__TREX_D_CORE_PPMU_RT_MEM0 467 +#define INTREQ__TREX_D_CORE_PPMU_CP_MEM1 468 +#define INTREQ__TREX_D_CORE_PPMU_CP_MEM0 469 +#define INTREQ__TREX_D_CORE_PPMU_WLBT 470 +#define INTREQ__TREX_D_CORE_PPMU_MODEM1 471 +#define INTREQ__TREX_D_CORE_PPMU_MODEM0 472 +#define INTREQ__TREX_D_CORE_PPMU_GNSS 473 +#define INTREQ__TREX_D_CORE_PPMU_G3D 474 +#define INTREQ__TREX_D_CORE_PPMU_COREX 475 +#define INTREQ__TREX_D_CORE_PPMU_CHUB 476 +#define INTREQ__TREX_D_CORE_PPMU_APM 477 +#define INTREQ__SPDMA0 478 +#define INTREQ__PDMA0 479 + +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_850_H */