From patchwork Fri Jan 26 11:16:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vnktux X-Patchwork-Id: 866255 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=protonmail.com header.i=@protonmail.com header.b="YU94fBoc"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zSbvc4dZcz9s8J for ; Fri, 26 Jan 2018 22:16:44 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 36B39C222AC; Fri, 26 Jan 2018 11:16:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4C6E8C21F3A; Fri, 26 Jan 2018 11:16:36 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 86938C21F3A; Fri, 26 Jan 2018 11:16:35 +0000 (UTC) Received: from mail1.protonmail.ch (mail1.protonmail.ch [185.70.40.18]) by lists.denx.de (Postfix) with ESMTPS id 4927EC21F2B for ; Fri, 26 Jan 2018 11:16:34 +0000 (UTC) Date: Fri, 26 Jan 2018 06:16:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=default; t=1516965389; bh=Fp5HO5GGRTegnEk6rqmjj983T0csE4YWsp4LyYxqJ4A=; h=Date:To:From:Reply-To:Subject:Feedback-ID:From; b=YU94fBocpHhanKZeojuNsGELkhzKOSEoa5sHzVjPv24AO2O8F8vWCF3f4C9EXuqXa 0SHHRMuT2ObHuGS/FM+/VJKapWl3L2ADxVFroDPo9zeFqSn6yZ0dLGHBrVgVED885E wzZfpQksKkMdWhYyAcAQRXNtFtSDsOW8VsqeY2J8= To: U-Boot Mailing List , Bin Meng , Simon Glass From: vnktux Message-ID: Feedback-ID: fQAv8VbfcH8vKw3iZs6YphjgEQJ-aaYuxqlUNJIYnTNWJaksoUfwxN0WBNzHStAL5v1BIFRDUajzM6hlODYqkw==:Ext:ProtonMail MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.18 Subject: [U-Boot] [PATCH 1/6] Add Broadwell-DE architecture cpu files X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: vnktux Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch contain all the cpu files for Broadwell-DE architecture, including ACPI and FSP settings. Signed-off-by: Vincenzo Bove --- arch/x86/cpu/broadwell-de/Kconfig | 66 +++++++ arch/x86/cpu/broadwell-de/Makefile | 10 ++ arch/x86/cpu/broadwell-de/acpi.c | 234 +++++++++++++++++++++++++ arch/x86/cpu/broadwell-de/broadwell_de.c | 38 ++++ arch/x86/cpu/broadwell-de/cpu.c | 98 +++++++++++ arch/x86/cpu/broadwell-de/fsp_configs.c | 292 +++++++++++++++++++++++++++++++ 6 files changed, 738 insertions(+) create mode 100644 arch/x86/cpu/broadwell-de/Kconfig create mode 100644 arch/x86/cpu/broadwell-de/Makefile create mode 100644 arch/x86/cpu/broadwell-de/acpi.c create mode 100644 arch/x86/cpu/broadwell-de/broadwell_de.c create mode 100644 arch/x86/cpu/broadwell-de/cpu.c create mode 100644 arch/x86/cpu/broadwell-de/fsp_configs.c -- 2.11.0 diff --git a/arch/x86/cpu/broadwell-de/Kconfig b/arch/x86/cpu/broadwell-de/Kconfig new file mode 100644 index 0000000000..4e7b72c81c --- /dev/null +++ b/arch/x86/cpu/broadwell-de/Kconfig @@ -0,0 +1,66 @@ +# +# Copyright (C) 2017, Vincenzo Bove +# +# SPDX-License-Identifier: GPL-2.0+ +# + +config INTEL_BROADWELL_DE + bool + select HAVE_FSP + select ARCH_MISC_INIT + select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED + imply HAVE_INTEL_ME + imply ENABLE_MRC_CACHE + imply AHCI_PCI + imply ICH_SPI + imply INTEL_ICH6_GPIO + imply SCSI + imply SPI_FLASH + imply SYS_NS16550 + imply USB + imply USB_EHCI_HCD + imply USB_XHCI_HCD + #imply VIDEO_VESA + +if INTEL_BROADWELL_DE + +config FSP_ADDR + hex + default 0xffeb0000 + +#config DCACHE_RAM_BASE +# default 0xfef00000 + +#config DCACHE_RAM_SIZE +# default 0x4000 + +config CPU_SPECIFIC_OPTIONS + def_bool y + select SMM_TSEG + #select X86_RAMTEST + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config INTERNAL_UART + bool + default y + +config MAX_CPUS + int + default 16 + +config MAX_PIRQ_LINKS + int + default 4 + +config IRQ_SLOT_COUNT + int + default 18 + +config XIP_ROM_SIZE + hex + default 0x10000 + +endif diff --git a/arch/x86/cpu/broadwell-de/Makefile b/arch/x86/cpu/broadwell-de/Makefile new file mode 100644 index 0000000000..0fa427e1bf --- /dev/null +++ b/arch/x86/cpu/broadwell-de/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2017, Vincenzo Bove +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o +obj-y += fsp_configs.o +obj-y += broadwell_de.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o diff --git a/arch/x86/cpu/broadwell-de/acpi.c b/arch/x86/cpu/broadwell-de/acpi.c new file mode 100644 index 0000000000..2e005623de --- /dev/null +++ b/arch/x86/cpu/broadwell-de/acpi.c @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PM1_STS 0x00 +#define PM1_CNT 0x04 +#define GEN_PMCON1 0xA0 +#define WAK_STS (1 << 15) +#define PWR_FLR (1 << 1) +#define SUS_PWR_FLR (1 << 14) + +#define PMC_BASE_ADDRESS 0xfed03000 +#define PMC_BASE_SIZE 0x400 + +void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, + void *dsdt) +{ + struct acpi_table_header *header = &(fadt->header); + u16 pmbase = ACPI_BASE_ADDRESS; + + memset((void *)fadt, 0, sizeof(struct acpi_fadt)); + + /* + * Reference section 5.2.9 Fixed ACPI Description Table (FADT) + * in the ACPI 3.0b specification. + */ + + /* FADT Header Structure */ + acpi_fill_header(header, "FACP"); + header->length = sizeof(struct acpi_fadt); + header->revision = 4; + + /* ACPI Pointers */ + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; + + fadt->preferred_pm_profile = ACPI_PM_MOBILE; + fadt->sci_int = 9; + + /* System Management */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + + /* Power Control */ + fadt->s4bios_req = 0; + fadt->pstate_cnt = 0; + + /* Control Registers - Base Address */ + fadt->pm1a_evt_blk = pmbase + 0x00; //PM1_STS + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x04; //PM1_CNT + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; //PM2A_CNT_BLK + fadt->pm_tmr_blk = pmbase + 0x8; //PM1_TMR + fadt->gpe0_blk = pmbase + 0x20; //GPE0_STS + fadt->gpe1_blk = 0; + + /* Control Registers - Length */ + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 0; + + /* RTC Registers */ + fadt->day_alrm = 0x0d; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PLATFORM_CLOCK; + + /* Reset Register */ + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = IO_PORT_RESET; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 6; //SYS_RST | RST_CPU | FULL_RST + + /* Extended ACPI Pointers */ + fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_h = 0; + + /* PM1 Status & PM1 Enable */ + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + /* PM1 Control Registers */ + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + /* PM2 Control Registers */ + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + /* PM1 Timer Register */ + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x0; + + /* General-Purpose Event Registers */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = table_compute_checksum(fadt, header->length); +} + +void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +{ + struct udevice *dev; + int ret; + + /* at least we have one processor */ + gnvs->pcnt = 1; + /* override the processor count with actual number */ + ret = uclass_find_first_device(UCLASS_CPU, &dev); + if (ret == 0 && dev != NULL) { + ret = cpu_get_count(dev); + if (ret > 0) + gnvs->pcnt = ret; + } + + /* determine whether internal uart is on */ + if (IS_ENABLED(CONFIG_INTERNAL_UART)) + gnvs->iuart_en = 1; + else + gnvs->iuart_en = 0; +} + +#ifdef CONFIG_HAVE_ACPI_RESUME + +enum acpi_sleep_state chipset_prev_sleep_state(void) +{ + u32 pm1_sts; + u32 pm1_cnt; + u32 gen_pmcon1; + enum acpi_sleep_state prev_sleep_state = ACPI_S0; + + /* Read Power State */ + pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + gen_pmcon1 = readl(PMC_BASE_ADDRESS + GEN_PMCON1); + + debug("PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n", + pm1_sts, pm1_cnt, gen_pmcon1); + + if (pm1_sts & WAK_STS) + prev_sleep_state = acpi_sleep_from_pm1(pm1_cnt); + + if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = ACPI_S5; + + return prev_sleep_state; +} + +void chipset_clear_sleep_state(void) +{ + u32 pm1_cnt; + + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); +} + +#endif diff --git a/arch/x86/cpu/broadwell-de/broadwell_de.c b/arch/x86/cpu/broadwell-de/broadwell_de.c new file mode 100644 index 0000000000..54afde7db9 --- /dev/null +++ b/arch/x86/cpu/broadwell-de/broadwell_de.c @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int arch_cpu_init(void) +{ + post_code(POST_CPU_INIT); + + return x86_cpu_init_f(); +} + +int arch_misc_init(void) +{ +#ifdef CONFIG_ENABLE_MRC_CACHE + /* + * We intend not to check any return value here, as even MRC cache + * is not saved successfully, it is not a severe error that will + * prevent system from continuing to boot. + */ + mrccache_save(); +#endif + + return 0; +} + + + +void reset_cpu(ulong addr) +{ + /* cold reset */ + x86_full_reset(); +} diff --git a/arch/x86/cpu/broadwell-de/cpu.c b/arch/x86/cpu/broadwell-de/cpu.c new file mode 100644 index 0000000000..71377fad1c --- /dev/null +++ b/arch/x86/cpu/broadwell-de/cpu.c @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MSR_CORE_THREAD_COUNT 0x35 + +static void configure_mca(void) +{ + msr_t msr; + const unsigned int mcg_cap_msr = 0x179; + int i; + int num_banks; + + msr = msr_read(mcg_cap_msr); + num_banks = msr.lo & 0xff; + msr.lo = 0; + msr.hi = 0; + /* + * TODO(adurbin): This should only be done on a cold boot. Also, some + * of these banks are core vs package scope. For now every CPU clears + * every bank + */ + for (i = 0; i < num_banks; i++) { + msr_write(MSR_IA32_MC0_STATUS + (i * 4) + 1, msr); + msr_write(MSR_IA32_MC0_STATUS + (i * 4) + 2, msr); + msr_write(MSR_IA32_MC0_STATUS + (i * 4) + 3, msr); + + } + + msr.lo = 0xffffffff; + msr.hi = 0xffffffff; + + for (i = 0; i < num_banks; i++) { + msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr); + } +} + +static int cpu_x86_broadwell_de_probe(struct udevice *dev) +{ + debug("Init Broadwell-DE core\n"); + + /* Clear out pending MCEs */ + configure_mca(); + + return 0; +} + + +static int broadwell_de_get_info(struct udevice *dev, struct cpu_info *info) +{ + //TBD + + return 0; +} + +static int broadwell_de_get_count(struct udevice *dev) +{ + msr_t core_thread_count = msr_read(MSR_CORE_THREAD_COUNT); + return core_thread_count.lo & 0xffff; +} + +static const struct cpu_ops cpu_x86_broadwell_de_ops = { + .get_desc = cpu_x86_get_desc, + .get_info = broadwell_de_get_info, + .get_count = broadwell_de_get_count, + .get_vendor = cpu_x86_get_vendor, +}; + +static const struct udevice_id cpu_x86_broadwell_de_ids[] = { + { .compatible = "intel,broadwell-de-cpu" }, + { } +}; + +U_BOOT_DRIVER(cpu_x86_broadwell_de_drv) = { + .name = "cpu_x86_broadwell_de", + .id = UCLASS_CPU, + .of_match = cpu_x86_broadwell_de_ids, + .bind = cpu_x86_bind, + .probe = cpu_x86_broadwell_de_probe, + .ops = &cpu_x86_broadwell_de_ops, +}; diff --git a/arch/x86/cpu/broadwell-de/fsp_configs.c b/arch/x86/cpu/broadwell-de/fsp_configs.c new file mode 100644 index 0000000000..b2ccbdbd55 --- /dev/null +++ b/arch/x86/cpu/broadwell-de/fsp_configs.c @@ -0,0 +1,292 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/** + * Override the FSP's configuration data. + * If the device tree does not specify an integer setting, use the default + * provided by Prodrive BroadwellDE.rom + */ +void update_fsp_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf) +{ + struct upd_region *fsp_upd = &config->fsp_upd; + const void *blob = gd->fdt_blob; + int node; + + /* Initialize runtime buffer for fsp_init() */ + rt_buf->common.stack_top = config->common.stack_top - 32; + rt_buf->common.boot_mode = config->common.boot_mode; + rt_buf->common.upd_data = &config->fsp_upd; + + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BROADWELL_DE_FSP); + if (node < 0) { + debug("%s: Cannot find FSP node\n", __func__); + return; + } + + fsp_upd->memEccSupport = fdtdec_get_int(blob, node, + "fsp,memEccSupport", + MEM_ECC_SUPPORT_AUTO); + + fsp_upd->memDdrMemoryType = fdtdec_get_int(blob, node, + "fsp,memDdrMemoryType", + MEM_DDR_MEMORY_TYPE_UDIMM_AND_RDIMM); + + fsp_upd->memRankMultiplication = fdtdec_get_int(blob, node, + "fsp,memRankMultiplication", + MEM_RANK_MULTIPLICATION_AUTO); + + fsp_upd->memRankMarginTool = fdtdec_get_int(blob, node, + "fsp,memRankMarginTool", + MEM_RANK_MARGIN_TOOL_AUTO); + + fsp_upd->memScrambling = fdtdec_get_int(blob, node, + "fsp,memScrambling", + MEM_SCRAMBLING_AUTO); + + fsp_upd->memRefreshMode = fdtdec_get_int(blob, node, + "fsp,memRefreshMode", + MEM_REFRESH_MODE_ACC_SELF_REFRESH); + + fsp_upd->memMcOdtOverride = fdtdec_get_int(blob, node, + "fsp,memMcOdtOverride", + MEM_MC0DT_OVERRIDE_AUTO); + + fsp_upd->memCAParity = fdtdec_get_int(blob, node, + "fsp,memCAParity", + MEM_CA_PARITY_AUTO); + + fsp_upd->memThermalThrottling = fdtdec_get_int(blob, node, + "fsp,memThermalThrottling", + MEM_THERMAL_THROTTLING_CLOSEDLOOP); + + fsp_upd->memPowerSavingsMode = fdtdec_get_int(blob, node, + "fsp,memPowerSavingsMode", + MEM_POWER_SAVINGS_MODE_AUTO); + + fsp_upd->memElectricalThrottling = fdtdec_get_int(blob, node, + "fsp,memElectricalThrottling", + MEM_ELECTRICAL_THROTTLING_DISABLED); + + fsp_upd->memPagePolicy = fdtdec_get_int(blob, node, + "fsp,memPagePolicy", + MEM_PAGE_POLICY_AUTO); + + fsp_upd->memSocketInterleaveBelow4G = fdtdec_get_int(blob, node, + "fsp,memSocketInterleaveBelow4G", + MEM_SOCKET_INTERLEAVE_BELOW_4G_DISABLED); + + fsp_upd->memChannelInterleave = fdtdec_get_int(blob, node, + "fsp,memChannelInterleave", + MEM_CHANNEL_INTERLEAVE_AUTO); + + fsp_upd->memRankInterleave = fdtdec_get_int(blob, node, + "fsp,memRankInterleave", + MEM_RANK_INTERLEAVE_AUTO); + + #ifdef CONFIG_FSP_MEMORY_DOWN + fsp_upd->memDownEnable = fdtdec_get_bool(blob, node, "fsp,memDownEnable"); + + fsp_upd->memDownCh0Dimm0SpdPtr = fdtdec_get_int(blob, node, + "fsp,memDownCh0Dimm0SpdPtr", + CONFIG_SPD_ADDR); + + fsp_upd->memDownCh0Dimm1SpdPtr = fdtdec_get_int(blob, node, + "fsp,memDownCh0Dimm1SpdPtr", + 0x0); + + fsp_upd->memDownCh1Dimm0SpdPtr = fdtdec_get_int(blob, node, + "fsp,memDownCh1Dimm0SpdPtr", + 0x0); + + fsp_upd->memDownCh1Dimm1SpdPtr = fdtdec_get_int(blob, node, + "fsp,memDownCh1Dimm1SpdPtr", + 0x0); + #endif + + //#ifdef CONFIG_ENABLE_MRC_CACHE + //fsp_upd->memFastBoot = fdtdec_get_int(blob, node, "fsp,mem-fast-boot", MEM_FAST_BOOT_ENABLE); + //#else + //fsp_upd->memFastBoot = fdtdec_get_int(blob, node, "fsp,mem-fast-boot", MEM_FAST_BOOT_DISABLE); + //#endif + fsp_upd->memFastBoot = fdtdec_get_int(blob, node, "fsp,mem-fast-boot", MEM_FAST_BOOT_DISABLE); + + fsp_upd->pam0_hienable = fdtdec_get_int(blob, node, + "fsp,pam0-hienable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam1_loenable = fdtdec_get_int(blob, node, + "fsp,pam1-loenable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam1_hienable = fdtdec_get_int(blob, node, + "fsp,pam1-hienable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam2_loenable = fdtdec_get_int(blob, node, + "fsp,pam2-loenable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam2_hienable = fdtdec_get_int(blob, node, + "fsp,pam2-hienable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam3_loenable = fdtdec_get_int(blob, node, + "fsp,pam3-loenable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam3_hienable = fdtdec_get_int(blob, node, + "fsp,pam3-hienable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam4_loenable = fdtdec_get_int(blob, node, + "fsp,pam4-loenable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam4_hienable = fdtdec_get_int(blob, node, + "fsp,pam4-hienable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam5_loenable = fdtdec_get_int(blob, node, + "fsp,pam5-loenable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam5_hienable = fdtdec_get_int(blob, node, + "fsp,pam5-hienable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam6_loenable = fdtdec_get_int(blob, node, + "fsp,pam6-loenable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam6_hienable = fdtdec_get_int(blob, node, + "fsp,pam6-hienable", + PAM_RW_DRAM_ONLY); + + fsp_upd->memAdr = fdtdec_get_int(blob, node, + "fsp,memAdr", + MEM_ADR_DISABLED); + + fsp_upd->serialPortType = fdtdec_get_int(blob, node, + "fsp,serial-port-type", + SERIAL_PORT_TYPE_IO); + + fsp_upd->serialPortAddress = fdtdec_get_int(blob, node, + "fsp,serial-port-address", + 0x3f8); + + fsp_upd->serialPortConfigure = fdtdec_get_bool(blob, node, "fsp,serial-port-configure"); + + fsp_upd->serialPortBaudRate = fdtdec_get_int(blob, node, + "fsp,serial-port-baudrate", + SERIAL_PORT_BAUDRATE_115200); + + fsp_upd->serialPortControllerInit0 = fdtdec_get_bool(blob, node, "fsp,serial-port-controller-init0"); + + fsp_upd->serialPortControllerInit1 = fdtdec_get_bool(blob, node, "fsp,serial-port-controller-init1"); + + fsp_upd->configIOU1_PciPort3 = fdtdec_get_int(blob, node, + "fsp,config-iou1-pci-port3", + CONFIG_IOU1_PCI_PORT3_X4X4X4X4); + + fsp_upd->configIOU2_PciPort1 = fdtdec_get_int(blob, node, + "fsp,config-iou2-pci-port1", + CONFIG_IOU2_PCI_PORT1_XXX8); + + fsp_upd->pchPciPort1 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port1"); + + fsp_upd->pchPciPort2 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port2"); + + fsp_upd->pchPciPort3 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port3"); + + fsp_upd->pchPciPort4 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port4"); + + fsp_upd->pchPciPort5 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port5"); + + fsp_upd->pchPciPort6 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port6"); + + fsp_upd->pchPciPort7 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port7"); + + fsp_upd->pchPciPort8 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port8"); + + fsp_upd->ehci1Enable = fdtdec_get_bool(blob, node, "fsp,ehci1-enable"); + + fsp_upd->hyperThreading = fdtdec_get_bool(blob, node, "fsp,hyper-threading"); + + fsp_upd->debugOutputLevel = fdtdec_get_int(blob, node, + "fsp,debug-output-level", + DEBUG_OUTPUT_LEVEL_NORMAL); + + fsp_upd->tcoTimerHaltLock = fdtdec_get_bool(blob, node, "fsp,tco-timer-halt-lock"); + + fsp_upd->turboMode = fdtdec_get_bool(blob, node, "fsp,turbo-mode"); + + fsp_upd->bootPerfMode = fdtdec_get_bool(blob, node, "fsp,boot-perf-mode"); + + fsp_upd->pciePort1aAspm = fdtdec_get_int(blob, node, + "fsp,pcie-port1a-aspm", + PCIE_ASPM_DISABLED); + + fsp_upd->pciePort1bAspm = fdtdec_get_int(blob, node, + "fsp,pcie-port1b-aspm", + PCIE_ASPM_DISABLED); + + fsp_upd->pciePort3aAspm = fdtdec_get_int(blob, node, + "fsp,pcie-port3a-aspm", + PCIE_ASPM_DISABLED); + + fsp_upd->pciePort3bAspm = fdtdec_get_int(blob, node, + "fsp,pcie-port3b-aspm", + PCIE_ASPM_DISABLED); + + fsp_upd->pciePort3cAspm = fdtdec_get_int(blob, node, + "fsp,pcie-port3c-aspm", + PCIE_ASPM_DISABLED); + + fsp_upd->pciePort3dAspm = fdtdec_get_int(blob, node, + "fsp,pcie-port3d-aspm", + PCIE_ASPM_DISABLED); + + fsp_upd->pchPciePort1Aspm = fdtdec_get_int(blob, node, + "fsp,pch-pcie-port1-aspm", + PCH_PCI_ASPM_DISABLED); + + fsp_upd->pchPciePort2Aspm = fdtdec_get_int(blob, node, + "fsp,pch-pcie-port2-aspm", + PCH_PCI_ASPM_DISABLED); + + fsp_upd->pchPciePort3Aspm = fdtdec_get_int(blob, node, + "fsp,pch-pcie-port3-aspm", + PCH_PCI_ASPM_DISABLED); + + fsp_upd->pchPciePort4Aspm = fdtdec_get_int(blob, node, + "fsp,pch-pcie-port4-aspm", + PCH_PCI_ASPM_DISABLED); + + fsp_upd->pchPciePort5Aspm = fdtdec_get_int(blob, node, + "fsp,pch-pcie-port5-aspm", + PCH_PCI_ASPM_DISABLED); + + fsp_upd->pchPciePort6Aspm = fdtdec_get_int(blob, node, + "fsp,pch-pcie-port6-aspm", + PCH_PCI_ASPM_DISABLED); + + fsp_upd->pchPciePort7Aspm = fdtdec_get_int(blob, node, + "fsp,pch-pcie-port7-aspm", + PCH_PCI_ASPM_DISABLED); + + fsp_upd->pchPciePort8Aspm = fdtdec_get_int(blob, node, + "fsp,pch-pcie-port8-aspm", + PCH_PCI_ASPM_DISABLED); + + fsp_upd->thermalDeviceEnable = fdtdec_get_bool(blob, node, "fsp,thermal-device-enable"); +} From patchwork Fri Jan 26 11:17:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vnktux X-Patchwork-Id: 866361 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=protonmail.com header.i=@protonmail.com header.b="vIrZ6AKM"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zSggD53HDz9s75 for ; Sat, 27 Jan 2018 01:06:16 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5F058C225BE; Fri, 26 Jan 2018 13:59:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D87FBC22427; Fri, 26 Jan 2018 13:54:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DF356C21F3A; Fri, 26 Jan 2018 11:17:58 +0000 (UTC) Received: from mail1.protonmail.ch (mail1.protonmail.ch [185.70.40.18]) by lists.denx.de (Postfix) with ESMTPS id E7EECC21F2B for ; Fri, 26 Jan 2018 11:17:56 +0000 (UTC) Date: Fri, 26 Jan 2018 06:17:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=default; t=1516965468; bh=h7aZ/cE4C516u+V0gcBGCOeu89+zW2qgtSvGRsSiqgM=; h=Date:To:From:Reply-To:Subject:Feedback-ID:From; b=vIrZ6AKMED81OZWB+TsV0KsYhaxVR+LsvgLh34n6VwH7Cmj8F6uRAQXgzqTjUvMzh JOS6PuYSN0s1HSCVuOBnlmBTVXt86q9wBx0LsbLv2IbmkH1iWzyE9JXqNxVO8ffRtO XpeICAb2zb2wYXl98Ifmwr5TxBURdCYD5BPYtJi0= To: U-Boot Mailing List , Bin Meng , Simon Glass From: vnktux Message-ID: <6syLIzwLvo8QsmZEqeWcuIELAGSSG5Rwcg6o0Bi68xpQipChGL5zzjtC362n8pivkf121c-1g16PUiZSGnR_IM5fuae8alNmWOj5FfukDkg=@protonmail.com> Feedback-ID: fQAv8VbfcH8vKw3iZs6YphjgEQJ-aaYuxqlUNJIYnTNWJaksoUfwxN0WBNzHStAL5v1BIFRDUajzM6hlODYqkw==:Ext:ProtonMail MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 26 Jan 2018 13:54:39 +0000 X-Content-Filtered-By: Mailman/MimeDel 2.1.18 Subject: [U-Boot] [PATCH 2/6] Add Broadwell-DE include header files X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: vnktux Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch contain all the include headers for Broadwell-DE architecture. Signed-off-by: Vincenzo Bove --- .../asm/arch-broadwell-de/acpi/global_nvs.asl | 15 + .../asm/arch-broadwell-de/acpi/irq_helper.h | 36 ++ .../asm/arch-broadwell-de/acpi/irqlinks.asl | 454 ++++++++++++++++++++ .../asm/arch-broadwell-de/acpi/irqroute.asl | 29 ++ .../include/asm/arch-broadwell-de/acpi/irqroute.h | 31 ++ .../x86/include/asm/arch-broadwell-de/acpi/lpc.asl | 81 ++++ .../include/asm/arch-broadwell-de/acpi/pcie1.asl | 455 +++++++++++++++++++++ .../asm/arch-broadwell-de/acpi/platform.asl | 61 +++ .../asm/arch-broadwell-de/acpi/southcluster.asl | 339 +++++++++++++++ arch/x86/include/asm/arch-broadwell-de/device.h | 116 ++++++ .../asm/arch-broadwell-de/fsp/fsp_configs.h | 134 ++++++ .../include/asm/arch-broadwell-de/fsp/fsp_vpd.h | 116 ++++++ .../x86/include/asm/arch-broadwell-de/global_nvs.h | 21 + arch/x86/include/asm/arch-broadwell-de/iomap.h | 58 +++ arch/x86/include/asm/arch-broadwell-de/irq.h | 88 ++++ 15 files changed, 2034 insertions(+) create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/global_nvs.asl create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/irq_helper.h create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/irqlinks.asl create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.asl create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.h create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/lpc.asl create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/pcie1.asl create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/platform.asl create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/southcluster.asl create mode 100644 arch/x86/include/asm/arch-broadwell-de/device.h create mode 100644 arch/x86/include/asm/arch-broadwell-de/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-broadwell-de/fsp/fsp_vpd.h create mode 100644 arch/x86/include/asm/arch-broadwell-de/global_nvs.h create mode 100644 arch/x86/include/asm/arch-broadwell-de/iomap.h create mode 100644 arch/x86/include/asm/arch-broadwell-de/irq.h -- 2.11.0 diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/global_nvs.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/global_nvs.asl new file mode 100644 index 0000000000..a28d4dfade --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/global_nvs.asl @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2016 Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE) +Field(GNVS, ByteAcc, NoLock, Preserve) +{ + Offset (0x00), + PCNT, 8, /* processor count */ + IURE, 8, /* internal UART enabled */ +} diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/irq_helper.h b/arch/x86/include/asm/arch-broadwell-de/acpi/irq_helper.h new file mode 100644 index 0000000000..5bdddd7d9c --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/irq_helper.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#undef PCI_DEV_PIRQ_ROUTES +#undef ACPI_DEV_IRQ +#undef PCI_DEV_PIRQ_ROUTE +#undef PIRQ_PIC_ROUTES +#undef PIRQ_PIC +#undef IRQROUTE_H + +#if defined(PIC_MODE) + +#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ + { Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 } } + +#else /* defined(PIC_MODE) */ + +#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ + { Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } } + +#endif + +#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ + { ACPI_DEV_IRQ(dev_, 0, a_), \ + ACPI_DEV_IRQ(dev_, 1, b_), \ + ACPI_DEV_IRQ(dev_, 2, c_), \ + ACPI_DEV_IRQ(dev_, 3, d_) } + +/* Empty PIRQ_PIC definition. */ +#define PIRQ_PIC(pirq_, pic_irq_) + +///* Include the mainboard irq route definition */ +#include "irqroute.h" diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/irqlinks.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/irqlinks.asl new file mode 100644 index 0000000000..36942982c8 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/irqlinks.asl @@ -0,0 +1,454 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OperationRegion (PRR0, PCI_Config, 0x00, 0x100) +Field (PRR0, AnyAcc, NoLock, Preserve) { + Offset(0x60), + PIRA, 8, + PIRB, 8, + PIRC, 8, + PIRD, 8, + Offset(0x68), + PIRE, 8, + PIRF, 8, + PIRG, 8, + PIRH, 8 +} + +Device (LNKA) { // PCI IRQ link A + Name (_HID,EISAID("PNP0C0F")) + //Name(_UID, 1) + Method (_STA,0,NotSerialized) { + If(And(PIRA, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRA, 0x80, PIRA) + } + + Method (_CRS,0,Serialized) { + Name (BUF0, ResourceTemplate() {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And(PIRA, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And (PIRA,0x0F),IRQW) // Save in buffer + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)){ + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRA) + } // End of _SRS Method +} + +Device(LNKB) { // PCI IRQ link B + Name (_HID,EISAID("PNP0C0F")) + //Name(_UID, 2) + Method (_STA,0,NotSerialized) { + If (And (PIRB, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRB, 0x80,PIRB) + } + + Method (_CRS,0,Serialized) { + Name(BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRB, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And (PIRB,0x0F),IRQW) // Save in buffer + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name (_PRS, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual(IRQW,Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store (Local0, PIRB) + } // End of _SRS Method +} + +Device(LNKC) { // PCI IRQ link C + Name(_HID, EISAID("PNP0C0F")) + //Name(_UID, 3) + + Method (_STA,0,NotSerialized) { + If (And (PIRC, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS, 0, NotSerialized) { + Or (PIRC, 0x80, PIRC) + } + + Method (_CRS, 0, Serialized) { + Name (BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRC, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And (PIRC,0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRC) + } // End of _SRS Method +} + +Device (LNKD) { // PCI IRQ link D + Name (_HID,EISAID ("PNP0C0F")) + + //Name(_UID, 4) + + Method (_STA, 0, NotSerialized) { + If (And (PIRD, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS, 0, NotSerialized) { + Or(PIRD, 0x80,PIRD) + } + + Method (_CRS,0,Serialized) { + Name (BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRD, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0, And (PIRD,0x0F), IRQW) + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW, Local0)// Set IRQ + If (LNotEqual (IRQW, Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store(Local0, PIRD) + } // End of _SRS Method +} + +Device(LNKE) { // PCI IRQ link E + Name(_HID,EISAID("PNP0C0F")) + + //Name(_UID, 5) + + Method (_STA,0,NotSerialized) { + If (And (PIRE, 0x80)) { + Return(0x9) + } Else { + Return(0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRE, 0x80, PIRE) + } + + Method (_CRS, 0, Serialized) { + Name (BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRE, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One, Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0, And (PIRE,0x0F), IRQW) + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name(_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW, Local0) // Set IRQ + If (LNotEqual (IRQW, Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store (Local0, PIRE) + } // End of _SRS Method +} + +Device(LNKF) { // PCI IRQ link F + Name (_HID,EISAID("PNP0C0F")) + + //Name(_UID, 6) + + Method (_STA,0,NotSerialized) { + If (And (PIRF, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRB, 0x80, PIRF) + } + + Method (_CRS,0,Serialized) { + Name(BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRF, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One, Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0, And (PIRF, 0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name(_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store (Local0, PIRF) + } // End of _SRS Method +} + +Device(LNKG) { // PCI IRQ link G + Name(_HID,EISAID("PNP0C0F")) + //Name(_UID, 7) + Method(_STA,0,NotSerialized) { + If (And (PIRG, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS, 0, NotSerialized) { + Or(PIRG, 0x80,PIRG) + } + + Method (_CRS,0,Serialized){ + Name(BUF0,ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And(PIRG, 0x80)) { + Store(Zero, Local0) + } Else { + Store(One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And(PIRG,0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRG) + } // End of _SRS Method +} + +Device(LNKH) { // PCI IRQ link H + Name (_HID,EISAID("PNP0C0F")) + + //Name(_UID, 8) + + Method (_STA,0,NotSerialized) { + If (And(PIRH, 0x80)) { + Return(0x9) + } Else { + Return(0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or(PIRH, 0x80,PIRH) + } + + Method (_CRS,0,Serialized) { + Name(BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRH, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And(PIRH,0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name(_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW,Local0)// Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRH) + } +} diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.asl new file mode 100644 index 0000000000..39c7a19349 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.asl @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* PCI Interrupt Routing */ +Method(_PRT) +{ + /* + * PICM comes from _PIC, which returns the following: + * 0 - PIC mode + * 1 - APIC mode + * 2 - SAPIC mode + */ + If (PICM) { + Return (Package() { + #undef PIC_MODE + #include "irq_helper.h" + PCI_DEV_PIRQ_ROUTES + }) + } Else { + Return (Package() { + #define PIC_MODE + #include "irq_helper.h" + PCI_DEV_PIRQ_ROUTES + }) + } +} diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.h b/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.h new file mode 100644 index 0000000000..27701db790 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(ME_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(GBE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI1_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D) + +/* +* Route each PIRQ[A-H] to a PIC IRQ[0-15] +* Reserved: 0, 1, 2, 8, 13 +* ACPI/SCI: 9 +*/ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 5), \ + PIRQ_PIC(B, 6), \ + PIRQ_PIC(C, 7), \ + PIRQ_PIC(D, 10), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 12), \ + PIRQ_PIC(G, 14), \ + PIRQ_PIC(H, 15) diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/lpc.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/lpc.asl new file mode 100644 index 0000000000..c1a9e2fb7d --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/lpc.asl @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Intel LPC Bus Device - 0:1f.0 */ + +Device (LPC0) +{ + Name(_ADR, 0x001f0000) + + #include "irqlinks.asl" + + Device (FWH) // Firmware Hub + { + Name (_HID, EISAID("INT0800")) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + }) + } + + Device (HPET) + { + Name (_HID, EISAID("PNP0103")) + Name (_CID, 0x010CD041) + + Method (_STA, 0) // Device Status + { + Return (0xf) // Enable and show device + } + + Name(_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + }) + } + + Device(LDRC) // LPC device: Resource consumption + { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 2) + + Name (RBUF, ResourceTemplate() + { + IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status + IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post + IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI + }) + + Method (_CRS, 0, NotSerialized) + { + Return (RBUF) + } + } + + Device (RTC) // Real Time Clock + { + Name (_HID, EISAID("PNP0B00")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x70, 0x70, 1, 8) + }) + } + + Device (TIMR) // Intel 8254 timer + { + Name(_HID, EISAID("PNP0100")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x40, 0x40, 0x01, 0x04) + IO (Decode16, 0x50, 0x50, 0x10, 0x04) + IRQNoFlags() {0} + }) + } +} diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/pcie1.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/pcie1.asl new file mode 100644 index 0000000000..4c0cd37f50 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/pcie1.asl @@ -0,0 +1,455 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +Name (PR01, Package() { + // [SL01]: PCI Express Slot 1 on 1A on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR01, Package() { + // [SL01]: PCI Express Slot 1 on 1A on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH01, Package() { + // [SL01]: PCI Express Slot 1 on 1A on PCI0 + Package() { 0x0000FFFF, 0, 0, 26 }, + Package() { 0x0000FFFF, 1, 0, 28 }, + Package() { 0x0000FFFF, 2, 0, 29 }, + Package() { 0x0000FFFF, 3, 0, 30 }, +}) + +Name (PR02, Package() { + // [SL02]: PCI Express Slot 2 on 1B on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR02, Package() { + // [SL02]: PCI Express Slot 2 on 1B on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH02, Package() { + // [SL02]: PCI Express Slot 2 on 1B on PCI0 + Package() { 0x0000FFFF, 0, 0, 27 }, + Package() { 0x0000FFFF, 1, 0, 30 }, + Package() { 0x0000FFFF, 2, 0, 28 }, + Package() { 0x0000FFFF, 3, 0, 29 }, +}) + +Name (PR03, Package() { + // [CB0I]: CB3DMA on IOSF + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [CB0J]: CB3DMA on IOSF + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + // [CB0K]: CB3DMA on IOSF + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + // [CB0L]: CB3DMA on IOSF + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR03, Package() { + // [CB0I]: CB3DMA on IOSF + Package() { 0x0000FFFF, 0, 0, 16 }, + // [CB0J]: CB3DMA on IOSF + Package() { 0x0000FFFF, 1, 0, 17 }, + // [CB0K]: CB3DMA on IOSF + Package() { 0x0000FFFF, 2, 0, 18 }, + // [CB0L]: CB3DMA on IOSF + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH03, Package() { + // [CB0I]: CB3DMA on IOSF + Package() { 0x0000FFFF, 0, 0, 32 }, + // [CB0J]: CB3DMA on IOSF + Package() { 0x0000FFFF, 1, 0, 36 }, + // [CB0K]: CB3DMA on IOSF + Package() { 0x0000FFFF, 2, 0, 37 }, + // [CB0L]: CB3DMA on IOSF + Package() { 0x0000FFFF, 3, 0, 38 }, +}) + +Name (PR04, Package() { + // [SL04]: PCI Express Slot 4 on 2B on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR04, Package() { + // [SL04]: PCI Express Slot 4 on 2B on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH04, Package() { + // [SL04]: PCI Express Slot 4 on 2B on PCI0 + Package() { 0x0000FFFF, 0, 0, 33 }, + Package() { 0x0000FFFF, 1, 0, 37 }, + Package() { 0x0000FFFF, 2, 0, 38 }, + Package() { 0x0000FFFF, 3, 0, 36 }, +}) + +Name (PR05, Package() { + // [SL05]: PCI Express Slot 5 on 2C on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR05, Package() { + // [SL05]: PCI Express Slot 5 on 2C on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH05, Package() { + // [SL05]: PCI Express Slot 5 on 2C on PCI0 + Package() { 0x0000FFFF, 0, 0, 34 }, + Package() { 0x0000FFFF, 1, 0, 37 }, + Package() { 0x0000FFFF, 2, 0, 36 }, + Package() { 0x0000FFFF, 3, 0, 38 }, +}) + +Name (PR06, Package() { + // [SL06]: PCI Express Slot 6 on 2D on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR06, Package() { + // [SL06]: PCI Express Slot 6 on 2D on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH06, Package() { + // [SL06]: PCI Express Slot 6 on 2D on PCI0 + Package() { 0x0000FFFF, 0, 0, 35 }, + Package() { 0x0000FFFF, 1, 0, 36 }, + Package() { 0x0000FFFF, 2, 0, 38 }, + Package() { 0x0000FFFF, 3, 0, 37 }, +}) + +Name (PR07, Package() { + // [SL07]: PCI Express Slot 7 on 3A on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR07, Package() { + // [SL07]: PCI Express Slot 7 on 3A on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH07, Package() { + // [SL07]: PCI Express Slot 7 on 3A on PCI0 + Package() { 0x0000FFFF, 0, 0, 40 }, + Package() { 0x0000FFFF, 1, 0, 44 }, + Package() { 0x0000FFFF, 2, 0, 45 }, + Package() { 0x0000FFFF, 3, 0, 46 }, +}) + +Name (PR08, Package() { + // [SL08]: PCI Express Slot 8 on 3B on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR08, Package() { + // [SL08]: PCI Express Slot 8 on 3B on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH08, Package() { + // [SL08]: PCI Express Slot 8 on 3B on PCI0 + Package() { 0x0000FFFF, 0, 0, 41 }, + Package() { 0x0000FFFF, 1, 0, 45 }, + Package() { 0x0000FFFF, 2, 0, 46 }, + Package() { 0x0000FFFF, 3, 0, 44 }, +}) + +Name (PR09, Package() { + // [SL09]: PCI Express Slot 9 on 3C on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR09, Package() { + // [SL09]: PCI Express Slot 9 on 3C on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH09, Package() { + // [SL09]: PCI Express Slot 9 on 3C on PCI0 + Package() { 0x0000FFFF, 0, 0, 42 }, + Package() { 0x0000FFFF, 1, 0, 45 }, + Package() { 0x0000FFFF, 2, 0, 44 }, + Package() { 0x0000FFFF, 3, 0, 46 }, +}) + +Name (PR0A, Package() { + // [SL0A]: PCI Express Slot 10 on 3D on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR0A, Package() { + // [SL0A]: PCI Express Slot 10 on 3D on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH0A, Package() { + // [SL0A]: PCI Express Slot 10 on 3D on PCI0 + Package() { 0x0000FFFF, 0, 0, 43 }, + Package() { 0x0000FFFF, 1, 0, 44 }, + Package() { 0x0000FFFF, 2, 0, 46 }, + Package() { 0x0000FFFF, 3, 0, 45 }, +}) + + + // PCI Express Port 1A on PCI0 +Device (BR1A) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR01) + } + If (LEqual(APC1, One)) { + Return (AH01) + } + Return (AR01) + } + +} + +// PCI Express Port 1B on PCI0 +Device (BR1B) { + Name (_ADR, 0x00010001) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR02) + } + If (LEqual(APC1, One)) { + Return (AH02) + } + Return (AR02) + } + +} + +// PCI Express Port 2A on PCI0 +Device (BR2A) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR03) + } + If (LEqual(APC1, One)) { + Return (AH03) + } + Return (AR03) + } + + + // CB3DMA on IOSF + Device (CB0I) { + Name (_ADR, 0x00000000) + } + + // CB3DMA on IOSF + Device (CB0J) { + Name (_ADR, 0x00000001) + } + + // CB3DMA on IOSF + Device (CB0K) { + Name (_ADR, 0x00000002) + } + + // CB3DMA on IOSF + Device (CB0L) { + Name (_ADR, 0x00000003) + } +} + +// PCI Express Port 2B on PCI0 +Device (BR2B) { + Name (_ADR, 0x00020001) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR04) + } + If (LEqual(APC1, One)) { + Return (AH04) + } + Return (AR04) + } + +} + +// PCI Express Port 2C on PCI0 +Device (BR2C) { + Name (_ADR, 0x00020002) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR05) + } + If (LEqual(APC1, One)) { + Return (AH05) + } + Return (AR05) + } + +} + +// PCI Express Port 2D on PCI0 +Device (BR2D) { + Name (_ADR, 0x00020003) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR06) + } + If (LEqual(APC1, One)) { + Return (AH06) + } + Return (AR06) + } + +} + +// PCI Express Port 3A on PCI0 +Device (BR3A) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR07) + } + If (LEqual(APC1, One)) { + Return (AH07) + } + Return (AR07) + } + +} + +// PCI Express Port 3B on PCI0 +Device (BR3B) { + Name (_ADR, 0x00030001) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR08) + } + If (LEqual(APC1, One)) { + Return (AH08) + } + Return (AR08) + } + +} + +// PCI Express Port 3C on PCI0 +Device (BR3C) { + Name (_ADR, 0x00030002) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR09) + } + If (LEqual(APC1, One)) { + Return (AH09) + } + Return (AR09) + } + +} + +// PCI Express Port 3D on PCI0 +Device (BR3D) { + Name (_ADR, 0x00030003) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR0A) + } + If (LEqual(APC1, One)) { + Return (AH0A) + } + Return (AR0A) + } + +} diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/platform.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/platform.asl new file mode 100644 index 0000000000..cefe4f72d5 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/platform.asl @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2016, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +Name(\APC1, Zero) // IIO IOAPIC + +Name(\PICM, Zero) // IOAPIC/8259 + +Method(_PIC, 1) +{ + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +/* ACPI global NVS */ +//#include "irqlinks.asl" + +Scope (\_SB) +{ + #include "southcluster.asl" + + #include "pcie1.asl" +} diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/southcluster.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/southcluster.asl new file mode 100644 index 0000000000..d2b0ba9879 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/southcluster.asl @@ -0,0 +1,339 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +Name(_HID,EISAID("PNP0A08")) // PCIe +Name(_CID,EISAID("PNP0A03")) // PCI + +Name(_ADR, 0) +Name(_BBN, 0) + +Name (MCRS, ResourceTemplate() { + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00fe, 0x0000, 0xff,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xefff, 0x0000, 0xE300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-0xfeafffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x90000000, 0xFEAFFFFF, 0x00000000, + 0x6EB00000,,, PMEM) + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfec00000, 0xfecfffff, 0x00000000, + 0x00100000,,, APIC) + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed00000, 0xfedfffff, 0x00000000, + 0x00100000,,, PCHR) + + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000380000000000, // Range Minimum + 0x0000383FFFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000004000000000, // Length + ,,, AddressRangeMemory, TypeStatic) +}) + +Method (_CRS, 0, Serialized) { + Return (MCRS) +} + +/* Device Resource Consumption */ +Device (PDRC) { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 1) + + Name (PDRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) + Memory32Fixed(ReadWrite, PSEG_BASE_ADDRESS, PSEG_BASE_SIZE) + Memory32Fixed(ReadWrite, IOXAPIC1_BASE_ADDRESS, IOXAPIC1_BASE_SIZE) + Memory32Fixed(ReadWrite, IOXAPIC2_BASE_ADDRESS, IOXAPIC2_BASE_SIZE) + Memory32Fixed(ReadWrite, PCH_BASE_ADDRESS, PCH_BASE_SIZE) + Memory32Fixed(ReadWrite, LXAPIC_BASE_ADDRESS, LXAPIC_BASE_SIZE) + Memory32Fixed(ReadWrite, FIRMWARE_BASE_ADDRESS, FIRMWARE_BASE_SIZE) + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) + { + Return(PDRS) + } +} + +Method (_OSC, 4) { + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + Else + { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } +} + +Name (PR00, Package() { + // [DMI0]: Legacy PCI Express Port 0 on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [BR1A]: PCI Express Port 1A on PCI0 + // [BR1B]: PCI Express Port 1B on PCI0 + Package() { 0x0001FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [BR2A]: PCI Express Port 2A on PCI0 + // [BR2B]: PCI Express Port 2B on PCI0 + // [BR2C]: PCI Express Port 2C on PCI0 + // [BR2D]: PCI Express Port 2D on PCI0 + Package() { 0x0002FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [BR3A]: PCI Express Port 3A on PCI0 + // [BR3B]: PCI Express Port 3B on PCI0 + // [BR3C]: PCI Express Port 3C on PCI0 + // [BR3D]: PCI Express Port 3D on PCI0 + Package() { 0x0003FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [CB0A]: CB3DMA on PCI0 + // [CB0E]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [CB0B]: CB3DMA on PCI0 + // [CB0F]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + // [CB0C]: CB3DMA on PCI0 + // [CB0G]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + // [CB0D]: CB3DMA on PCI0 + // [CB0H]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + // [IIM0]: IIOMISC on PCI0 + Package() { 0x0005FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0005FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0005FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0005FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + // [IID0]: IIODFX0 on PCI0 + Package() { 0x0006FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0006FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0006FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0006FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + // [XHCI]: xHCI controller 1 on PCH + Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + // [HECI]: ME HECI on PCH + // [IDER]: ME IDE redirect on PCH + Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [HEC2]: ME HECI2 on PCH + // [MEKT]: MEKT on PCH + Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + // [GBEM]: GbE Controller VPRO + Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKE, 0 }, + // [EHC2]: EHCI controller #2 on PCH + Package() { 0x001AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + // [ALZA]: High definition Audio Controller + Package() { 0x001BFFFF, 0, \_SB.PCI0.LPC0.LNKG, 0 }, + // [RP01]: Pci Express Port 1 on PCH + // [RP05]: Pci Express Port 5 on PCH + Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [RP02]: Pci Express Port 2 on PCH + // [RP06]: Pci Express Port 6 on PCH + Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + // [RP03]: Pci Express Port 3 on PCH + // [RP07]: Pci Express Port 7 on PCH + Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + // [RP04]: Pci Express Port 4 on PCH + // [RP08]: Pci Express Port 8 on ICH + Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + // [EHC1]: EHCI controller #1 on PCH + Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + // [SAT1]: SATA controller 1 on PCH + // [SAT2]: SATA Host controller 2 on PCH + Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [SMBS]: SMBus controller on PCH + // [TERM]: Thermal Subsystem on ICH + Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, +}) + +Name (AR00, Package() { + // [DMI0]: Legacy PCI Express Port 0 on PCI0 + Package() { 0x0000FFFF, 0, 0, 47 }, + // [BR1A]: PCI Express Port 1A on PCI0 + // [BR1B]: PCI Express Port 1B on PCI0 + Package() { 0x0001FFFF, 0, 0, 47 }, + // [BR2A]: PCI Express Port 2A on PCI0 + // [BR2B]: PCI Express Port 2B on PCI0 + // [BR2C]: PCI Express Port 2C on PCI0 + // [BR2D]: PCI Express Port 2D on PCI0 + Package() { 0x0002FFFF, 0, 0, 47 }, + // [BR3A]: PCI Express Port 3A on PCI0 + // [BR3B]: PCI Express Port 3B on PCI0 + // [BR3C]: PCI Express Port 3C on PCI0 + // [BR3D]: PCI Express Port 3D on PCI0 + Package() { 0x0003FFFF, 0, 0, 47 }, + // [CB0A]: CB3DMA on PCI0 + // [CB0E]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 0, 0, 31 }, + // [CB0B]: CB3DMA on PCI0 + // [CB0F]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 1, 0, 39 }, + // [CB0C]: CB3DMA on PCI0 + // [CB0G]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 2, 0, 31 }, + // [CB0D]: CB3DMA on PCI0 + // [CB0H]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 3, 0, 39 }, + // [IIM0]: IIOMISC on PCI0 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [IID0]: IIODFX0 on PCI0 + Package() { 0x0006FFFF, 0, 0, 16 }, + Package() { 0x0006FFFF, 1, 0, 17 }, + Package() { 0x0006FFFF, 2, 0, 18 }, + Package() { 0x0006FFFF, 3, 0, 19 }, + // [XHCI]: xHCI controller 1 on PCH + Package() { 0x0014FFFF, 3, 0, 19 }, + // [HECI]: ME HECI on PCH + // [IDER]: ME IDE redirect on PCH + Package() { 0x0016FFFF, 0, 0, 16 }, + // [HEC2]: ME HECI2 on PCH + // [MEKT]: MEKT on PCH + Package() { 0x0016FFFF, 1, 0, 17 }, + // [GBEM]: GbE Controller VPRO + Package() { 0x0019FFFF, 0, 0, 20 }, + // [EHC2]: EHCI controller #2 on PCH + Package() { 0x001AFFFF, 2, 0, 18 }, + // [ALZA]: High definition Audio Controller + Package() { 0x001BFFFF, 0, 0, 22 }, + // [RP01]: Pci Express Port 1 on PCH + // [RP05]: Pci Express Port 5 on PCH + Package() { 0x001CFFFF, 0, 0, 16 }, + // [RP02]: Pci Express Port 2 on PCH + // [RP06]: Pci Express Port 6 on PCH + Package() { 0x001CFFFF, 1, 0, 17 }, + // [RP03]: Pci Express Port 3 on PCH + // [RP07]: Pci Express Port 7 on PCH + Package() { 0x001CFFFF, 2, 0, 18 }, + // [RP04]: Pci Express Port 4 on PCH + // [RP08]: Pci Express Port 8 on ICH + Package() { 0x001CFFFF, 3, 0, 19 }, + // [EHC1]: EHCI controller #1 on PCH + Package() { 0x001DFFFF, 2, 0, 18 }, + // [SAT1]: SATA controller 1 on PCH + // [SAT2]: SATA Host controller 2 on PCH + Package() { 0x001FFFFF, 0, 0, 16 }, + // [SMBS]: SMBus controller on PCH + // [TERM]: Thermal Subsystem on ICH + Package() { 0x001FFFFF, 2, 0, 18 }, +}) + +// Socket 0 Root bridge +Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR00) + } + Return (AR00) // If you disable the IOxAPIC in IIO, you should return AR00 +} + +#include "lpc.asl" diff --git a/arch/x86/include/asm/arch-broadwell-de/device.h b/arch/x86/include/asm/arch-broadwell-de/device.h new file mode 100644 index 0000000000..be6df7c018 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/device.h @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BROADWELL_DE_DEVICE_H_ +#define _BROADWELL_DE_DEVICE_H_ + +#define BUS0 0 + +#define SOC_DEV 0 +#define SOC_FUNC 0 +#define SOC_DEVID 0x2F00 +#define SOC_DEVID_ES2 0x6F00 +#define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV, SOC_FUNC) + +#define VTD_DEV 5 +#define VTD_FUNC 0 +#define VTD_DEVID 0x6f28 +#define VTD_DEV_FUNC PCI_DEVFN(VTD_DEV, VTD_FUNC) + +#define LPC_DEV 31 +#define LPC_FUNC 0 +#define LPC_DEVID 0x8C42 +#define LPC_DEVID_ES2 0x8C54 +#define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV, LPC_FUNC) + +#define SATA_DEV 31 +#define SATA_FUNC 2 +#define AHCI_DEVID 0x8C02 +#define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV, SATA_FUNC) + +#define SMBUS_DEV 31 +#define SMBUS_FUNC 3 +#define SMBUS_DEVID 0x8C22 +#define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) + +#define SATA2_DEV 31 +#define SATA2_FUNC 5 +#define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV, SATA2_FUNC) + +#define EHCI1_DEV 29 +#define EHCI1_FUNC 0 +#define EHCI1_DEVID 0x8C26 +#define EHCI1_DEV_FUNC PCI_DEVFN(EHCI_DEV1, EHCI_FUNC1) + +#define EHCI2_DEV 26 +#define EHCI2_FUNC 0 +#define EHCI2_DEVID 0x8C2D +#define EHCI2_DEV_FUNC PCI_DEVFN(EHCI_DEV2, EHCI_FUNC2) + +#define XHCI_DEV 20 +#define XHCI_FUNC 0 +#define XHCI_DEVID 0x8C31 +#define XHCI_FUS_REG 0xE0 +#define XHCI_FUNC_DISABLE (1 << 0) +#define XHCI_USB2PR_REG 0xD0 +#define XHCI_DEV_FUNC PCI_DEVFN(XHCI_DEV, XHCI_FUNC) + +#define GBE_DEV 25 +#define GBE_FUNC 0 +#define GBE_DEVID 0x8C33 +#define GBE_DEV_FUNC PCI_DEVFN(GBE_DEV, GBE_FUNC) + +#define ME_DEV 22 +#define ME_FUNC 0 +#define ME_DEVID 0x8C3A +#define ME_DEV_FUNC PCI_DEVFN(ME_DEV, ME_FUNC) + +#define HDA_DEV 27 +#define HDA_FUNC 0 +#define HDA_DEVID 0x8C20 +#define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV, HDA_FUNC) + +#define PCIE_DEV 28 +#define PCIE_PORT1_DEV PCIE_DEV +#define PCIE_PORT1_FUNC 0 +#define PCIE_PORT1_DEVID 0x8C10 +#define PCIE_PORT2_DEV PCIE_DEV +#define PCIE_PORT2_FUNC 1 +#define PCIE_PORT2_DEVID 0x8C12 +#define PCIE_PORT3_DEV PCIE_DEV +#define PCIE_PORT3_FUNC 2 +#define PCIE_PORT3_DEVID 0x8C14 +#define PCIE_PORT4_DEV PCIE_DEV +#define PCIE_PORT4_FUNC 3 +#define PCIE_PORT4_DEVID 0x8C16 +#define PCIE_PORT5_DEV PCIE_DEV +#define PCIE_PORT5_FUNC 4 +#define PCIE_PORT5_DEVID 0x8C18 +#define PCIE_PORT6_DEV PCIE_DEV +#define PCIE_PORT6_FUNC 5 +#define PCIE_PORT6_DEVID 0x8C1A +#define PCIE_PORT7_DEV PCIE_DEV +#define PCIE_PORT7_FUNC 6 +#define PCIE_PORT7_DEVID 0x8C1C +#define PCIE_PORT8_DEV PCIE_DEV +#define PCIE_PORT8_FUNC 7 +#define PCIE_PORT8_DEVID 0x8C1E +#define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT1_FUNC) +#define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT2_FUNC) +#define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT3_FUNC) +#define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT4_FUNC) +#define PCIE_PORT5_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT5_FUNC) +#define PCIE_PORT6_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT6_FUNC) +#define PCIE_PORT7_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT7_FUNC) +#define PCIE_PORT8_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT8_FUNC) + +/* The SMM device is located on bus 0xff (QPI) */ +#define QPI_BUS 0xff +#define SMM_DEV 0x10 +#define SMM_FUNC 0x06 +#define SMM_DEV_FUNC PCI_DEVFN(SMM_DEV, SMM_FUNC) + +#endif /* _BROADWELL_DE_DEVICE_H_ */ diff --git a/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_configs.h b/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_configs.h new file mode 100644 index 0000000000..139f8b5db4 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_configs.h @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSP_CONFIGS_H__ +#define __FSP_CONFIGS_H__ + +#ifndef __ASSEMBLY__ +struct fsp_config_data { + struct fsp_cfg_common common; + struct upd_region fsp_upd; +}; + +struct fspinit_rtbuf { + struct common_buf common; /* FSP common runtime data structure */ +}; +#endif + +/* FSP user configuration settings */ + +#define PAM_RW_DMI_ONLY 0 +#define PAM_R_DRAM_W_DMI 1 +#define PAM_R_DMI_W_DRAM 2 +#define PAM_RW_DRAM_ONLY 3 + +#define PCH_PCI_ASPM_DISABLED 0 +#define PCH_PCI_ASPM_L0S 1 +#define PCH_PCI_ASPM_L1_ONLY 2 +#define PCH_PCI_ASPM_L0SL1 3 +#define PCH_PCI_ASPM_AUTO 4 + +#define PCIE_ASPM_DISABLED 0 +#define PCIE_ASPM_L1ONLY 2 +#define PCIE_ASPM_AUTO 7 + +#define MEM_CHANNEL_INTERLEAVE_AUTO 0 +#define MEM_CHANNEL_INTERLEAVE_1WAY 1 +#define MEM_CHANNEL_INTERLEAVE_2WAY 2 +#define MEM_CHANNEL_INTERLEAVE_3WAY 3 +#define MEM_CHANNEL_INTERLEAVE_4WAY 4 + +#define MEM_SCRAMBLING_DISABLED 0 +#define MEM_SCRAMBLING_ENABLED 1 +#define MEM_SCRAMBLING_AUTO 2 + +#define MEM_ECC_SUPPORT_DISABLED 0 +#define MEM_ECC_SUPPORT_ENABLED 1 +#define MEM_ECC_SUPPORT_AUTO 2 + +#define MEM_CA_PARITY_DISABLED 0 +#define MEM_CA_PARITY_ENABLED 1 +#define MEM_CA_PARITY_AUTO 2 + +#define MEM_POWER_SAVINGS_MODE_DISABLED 0 +#define MEM_POWER_SAVINGS_MODE_SLOW 1 +#define MEM_POWER_SAVINGS_MODE_FAST 2 +#define MEM_POWER_SAVINGS_MODE_APD 3 +#define MEM_POWER_SAVINGS_MODE_USER 4 +#define MEM_POWER_SAVINGS_MODE_AUTO 5 + +#define MEM_RANK_MARGIN_TOOL_DISABLED 0 +#define MEM_RANK_MARGIN_TOOL_ENABLED 1 +#define MEM_RANK_MARGIN_TOOL_AUTO 2 + +#define MEM_RANK_MULTIPLICATION_AUTO 0 +#define MEM_RANK_MULTIPLICATION_ENABLED 1 + +#define MEM_THERMAL_THROTTLING_DISABLED 0 +#define MEM_THERMAL_THROTTLING_OPENLOOP 1 +#define MEM_THERMAL_THROTTLING_CLOSEDLOOP 2 + +#define MEM_ELECTRICAL_THROTTLING_DISABLED 0 +#define MEM_ELECTRICAL_THROTTLING_ENABLED 1 +#define MEM_ELECTRICAL_THROTTLING_AUTO 2 + +#define MEM_DDR_MEMORY_TYPE_RDIMM_ONLY 0 +#define MEM_DDR_MEMORY_TYPE_UDIMM_ONLY 1 +#define MEM_DDR_MEMORY_TYPE_UDIMM_AND_RDIMM 2 + +#define MEM_MC0DT_OVERRIDE_50OHM 0 +#define MEM_MC0DT_OVERRIDE_100OHM 1 +#define MEM_MC0DT_OVERRIDE_AUTO 2 + +#define MEM_ADR_DISABLED 0 +#define MEM_ADR_ENABLED 1 +#define MEM_ADR_ENABLED_NVDIMM 2 + +#define MEM_RANK_INTERLEAVE_AUTO 0 +#define MEM_RANK_INTERLEAVE_1WAY 1 +#define MEM_RANK_INTERLEAVE_2WAY 2 +#define MEM_RANK_INTERLEAVE_4WAY 4 +#define MEM_RANK_INTERLEAVE_8WAY 8 + +#define MEM_PAGE_POLICY_OPEN 0 +#define MEM_PAGE_POLICY_CLOSED 1 +#define MEM_PAGE_POLICY_ADAPTIVE 2 +#define MEM_PAGE_POLICY_AUTO 3 + +#define MEM_REFRESH_MODE_ACC_SELF_REFRESH 0 +#define MEM_REFRESH_MODE_2X_REFRESH 1 + +#define MEM_SOCKET_INTERLEAVE_BELOW_4G_DISABLED 0 +#define MEM_SOCKET_INTERLEAVE_BELOW_4G_ENABLED 1 + +#define CONFIG_IOU1_PCI_PORT3_X4X4X4X4 0 +#define CONFIG_IOU1_PCI_PORT3_X4X4XXX8 1 +#define CONFIG_IOU1_PCI_PORT3_XXX8X4X4 2 +#define CONFIG_IOU1_PCI_PORT3_XXX8XXX8 3 +#define CONFIG_IOU1_PCI_PORT3_XXXXXX16 4 + +#define CONFIG_IOU2_PCI_PORT1_X4X4 0 +#define CONFIG_IOU2_PCI_PORT1_XXX8 1 + +#define SERIAL_PORT_BAUDRATE_9600 8 +#define SERIAL_PORT_BAUDRATE_19200 9 +#define SERIAL_PORT_BAUDRATE_38400 10 +#define SERIAL_PORT_BAUDRATE_57600 11 +#define SERIAL_PORT_BAUDRATE_115200 12 + +#define SERIAL_PORT_TYPE_NONE 0 +#define SERIAL_PORT_TYPE_IO 1 +#define SERIAL_PORT_TYPE_MMIO 2 + +#define DEBUG_OUTPUT_LEVEL_DISABLED 0 +#define DEBUG_OUTPUT_LEVEL_MINIMUM 1 +#define DEBUG_OUTPUT_LEVEL_NORMAL 2 +#define DEBUG_OUTPUT_LEVEL_MAXIMUM 3 + +#define MEM_FAST_BOOT_DISABLE 0 +#define MEM_FAST_BOOT_ENABLE 1 + +#endif /* __FSP_CONFIGS_H__ */ diff --git a/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_vpd.h new file mode 100644 index 0000000000..048c528710 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_vpd.h @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSP_VPD_H +#define __FSP_VPD_H + +struct __packed upd_region { + uint64_t signature; /**Offset 0x0000 **/ + uint64_t reserved; /**Offset 0x0008 **/ + uint8_t unusedUpdSpace0[16]; /**Offset 0x0010 **/ + uint8_t serialPortType; /**Offset 0x0020 **/ + uint32_t serialPortAddress; /**Offset 0x0021 **/ + uint8_t serialPortConfigure; /**Offset 0x0025 **/ + uint8_t serialPortBaudRate; /**Offset 0x0026 **/ + uint8_t serialPortControllerInit0; /**Offset 0x0027 **/ + uint8_t serialPortControllerInit1; /**Offset 0x0028 **/ + uint8_t configIOU1_PciPort3; /**Offset 0x0029 **/ + uint8_t configIOU2_PciPort1; /**Offset 0x002A **/ + uint8_t powerStateAfterG3; /**Offset 0x002B **/ + uint8_t pchPciPort1; /**Offset 0x002C **/ + uint8_t pchPciPort2; /**Offset 0x002D **/ + uint8_t pchPciPort3; /**Offset 0x002E **/ + uint8_t pchPciPort4; /**Offset 0x002F **/ + uint8_t pchPciPort5; /**Offset 0x0030 **/ + uint8_t pchPciPort6; /**Offset 0x0031 **/ + uint8_t pchPciPort7; /**Offset 0x0032 **/ + uint8_t pchPciPort8; /**Offset 0x0033 **/ + uint8_t hotPlug_PchPciPort1; /**Offset 0x0034 **/ + uint8_t hotPlug_PchPciPort2; /**Offset 0x0035 **/ + uint8_t hotPlug_PchPciPort3; /**Offset 0x0036 **/ + uint8_t hotPlug_PchPciPort4; /**Offset 0x0037 **/ + uint8_t hotPlug_PchPciPort5; /**Offset 0x0038 **/ + uint8_t hotPlug_PchPciPort6; /**Offset 0x0039 **/ + uint8_t hotPlug_PchPciPort7; /**Offset 0x003A **/ + uint8_t hotPlug_PchPciPort8; /**Offset 0x003B **/ + uint8_t ehci1Enable; /**Offset 0x003C **/ + uint8_t ehci2Enable; /**Offset 0x003D **/ + uint8_t hyperThreading; /**Offset 0x003E **/ + uint8_t debugOutputLevel; /**Offset 0x003F **/ + uint8_t tcoTimerHaltLock; /**Offset 0x0040 **/ + uint8_t turboMode; /**Offset 0x0041 **/ + uint8_t bootPerfMode; /**Offset 0x0042 **/ + uint8_t pciePort1aAspm; /**Offset 0x0043 **/ + uint8_t pciePort1bAspm; /**Offset 0x0044 **/ + uint8_t pciePort3aAspm; /**Offset 0x0045 **/ + uint8_t pciePort3bAspm; /**Offset 0x0046 **/ + uint8_t pciePort3cAspm; /**Offset 0x0047 **/ + uint8_t pciePort3dAspm; /**Offset 0x0048 **/ + uint8_t pchPciePort1Aspm; /**Offset 0x0049 **/ + uint8_t pchPciePort2Aspm; /**Offset 0x004A **/ + uint8_t pchPciePort3Aspm; /**Offset 0x004B **/ + uint8_t pchPciePort4Aspm; /**Offset 0x004C **/ + uint8_t pchPciePort5Aspm; /**Offset 0x004D **/ + uint8_t pchPciePort6Aspm; /**Offset 0x004E **/ + uint8_t pchPciePort7Aspm; /**Offset 0x004F **/ + uint8_t pchPciePort8Aspm; /**Offset 0x0050 **/ + uint8_t dFXEnable; /**Offset 0x0051 **/ + uint8_t thermalDeviceEnable; /**Offset 0x0052 **/ + uint8_t unusedUpdSpace1[88]; /**Offset 0x0053 **/ + uint8_t memEccSupport; /**Offset 0x00AB **/ + uint8_t memDdrMemoryType; /**Offset 0x00AC **/ + uint8_t memRankMultiplication; /**Offset 0x00AD **/ + uint8_t memRankMarginTool; /**Offset 0x00AE **/ + uint8_t memScrambling; /**Offset 0x00AF **/ + uint8_t memRefreshMode; /**Offset 0x00B0 **/ + uint8_t memMcOdtOverride; /**Offset 0x00B1 **/ + uint8_t memCAParity; /**Offset 0x00B2 **/ + uint8_t memThermalThrottling; /**Offset 0x00B3 **/ + uint8_t memPowerSavingsMode; /**Offset 0x00B4 **/ + uint8_t memElectricalThrottling; /**Offset 0x00B5 **/ + uint8_t memPagePolicy; /**Offset 0x00B6 **/ + uint8_t memSocketInterleaveBelow4G; /**Offset 0x00B7 **/ + uint8_t memChannelInterleave; /**Offset 0x00B8 **/ + uint8_t memRankInterleave; /**Offset 0x00B9 **/ + uint8_t memDownEnable; /**Offset 0x00BA **/ + uint32_t memDownCh0Dimm0SpdPtr; /**Offset 0x00BB **/ + uint32_t memDownCh0Dimm1SpdPtr; /**Offset 0x00BF **/ + uint32_t memDownCh1Dimm0SpdPtr; /**Offset 0x00C3 **/ + uint32_t memDownCh1Dimm1SpdPtr; /**Offset 0x00C7 **/ + uint8_t memFastBoot; /**Offset 0x00CB **/ + uint8_t pam0_hienable; /**Offset 0x00CC **/ + uint8_t pam1_loenable; /**Offset 0x00CD **/ + uint8_t pam1_hienable; /**Offset 0x00CE **/ + uint8_t pam2_loenable; /**Offset 0x00CF **/ + uint8_t pam2_hienable; /**Offset 0x00D0 **/ + uint8_t pam3_loenable; /**Offset 0x00D1 **/ + uint8_t pam3_hienable; /**Offset 0x00D2 **/ + uint8_t pam4_loenable; /**Offset 0x00D3 **/ + uint8_t pam4_hienable; /**Offset 0x00D4 **/ + uint8_t pam5_loenable; /**Offset 0x00D5 **/ + uint8_t pam5_hienable; /**Offset 0x00D6 **/ + uint8_t pam6_loenable; /**Offset 0x00D7 **/ + uint8_t pam6_hienable; /**Offset 0x00D8 **/ + uint8_t memAdr; /**Offset 0x00D9 **/ + uint8_t memAdrResumePath; /**Offset 0x00DA **/ + uint8_t memBlockScTrafficOnAdr; /**Offset 0x00DB **/ + uint16_t memPlatformReleaseAdrClampsPort;/**Offset 0x00DC **/ + uint32_t memPlatformReleaseAdrClampsAnd; /**Offset 0x00DE **/ + uint32_t memPlatformReleaseAdrClampsOr; /**Offset 0x00E2 **/ + uint8_t unusedUpdSpace2[24]; /**Offset 0x00E6 **/ + uint16_t terminator; /**Offset 0x00FE **/ +}; + +#define VPD_IMAGE_ID 0x5F45442D5844425F /* '_BDX-DE_' */ + +struct __packed vpd_region { + uint64_t sign; /* Offset 0x0000 */ + uint32_t img_rev; /* Offset 0x0008 */ + uint32_t upd_offset; /* Offset 0x000c */ + uint8_t unused[16]; /* Offset 0x0010 */ + uint32_t fsp_res_memlen; /* Offset 0x0020 */ +}; +#endif diff --git a/arch/x86/include/asm/arch-broadwell-de/global_nvs.h b/arch/x86/include/asm/arch-broadwell-de/global_nvs.h new file mode 100644 index 0000000000..5097cc1282 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/global_nvs.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BROADWELL_DE_GLOBAL_NVS_H_ +#define _BROADWELL_DE_GLOBAL_NVS_H_ + +struct __packed acpi_global_nvs { + u8 pcnt; /* processor count */ + u8 iuart_en; /* internal UART enabled */ + + /* + * Add padding so sizeof(struct acpi_global_nvs) == 0x100. + * This must match the size defined in the global_nvs.asl. + */ + u8 rsvd[254]; +}; + +#endif /* _BROADWELL_DE_GLOBAL_NVS_H_ */ diff --git a/arch/x86/include/asm/arch-broadwell-de/iomap.h b/arch/x86/include/asm/arch-broadwell-de/iomap.h new file mode 100644 index 0000000000..80f2b9d937 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/iomap.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BROADWELL_DE_IOMAP_H_ +#define _BROADWELL_DE_IOMAP_H_ + +/* Memory Mapped IO bases */ + +/* PCI Configuration Space */ +#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE //CONFIG_MMCONF_BASE_ADDRESS in Coreboot +#define MCFG_BASE_SIZE 0x10000000 + +/* Transactions in this range will abort */ +#define ABORT_BASE_ADDRESS 0xfeb00000 +#define ABORT_BASE_SIZE 0x00010000 + +/* PSEG */ +#define PSEG_BASE_ADDRESS 0xfeb80000 +#define PSEG_BASE_SIZE 0x00080000 + +/* IOxAPIC */ +#define IOXAPIC1_BASE_ADDRESS 0xfec00000 +#define IOXAPIC1_BASE_SIZE 0x00100000 +#define IOXAPIC2_BASE_ADDRESS 0xfec01000 +#define IOXAPIC2_BASE_SIZE 0x00100000 + +/* PCH (HPET/LT/TPM/Others) */ +#define PCH_BASE_ADDRESS 0xfed00000 +#define PCH_BASE_SIZE 0x00100000 + +/* Local XAPIC */ +#define LXAPIC_BASE_ADDRESS 0xfee00000 +#define LXAPIC_BASE_SIZE 0x00100000 + +/* High Performance Event Timer */ +#define HPET_BASE_ADDRESS 0xfed00000 +#define HPET_BASE_SIZE 0x400 + +/* Firmware */ +#define FIRMWARE_BASE_ADDRESS 0xff000000 +#define FIRMWARE_BASE_SIZE 0x01000000 + +/* + * IO Port bases. + */ + +/* ACPI Base Address */ +#define ACPI_BASE_ADDRESS 0x400 +#define ACPI_BASE_SIZE 0x80 + +/* GPIO Base Address */ +#define GPIO_BASE_ADDRESS 0x500 +#define GPIO_BASE_SIZE 0x80 + +#endif /* _BROADWELL_DE_IOMAP_H_ */ diff --git a/arch/x86/include/asm/arch-broadwell-de/irq.h b/arch/x86/include/asm/arch-broadwell-de/irq.h new file mode 100644 index 0000000000..ac6f689479 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/irq.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BROADWELL_DE_IRQ_H_ +#define _BROADWELL_DE_IRQ_H_ + +#define PIRQA_APIC_IRQ 16 +#define PIRQB_APIC_IRQ 17 +#define PIRQC_APIC_IRQ 18 +#define PIRQD_APIC_IRQ 19 +#define PIRQE_APIC_IRQ 20 +#define PIRQF_APIC_IRQ 21 +#define PIRQG_APIC_IRQ 22 +#define PIRQH_APIC_IRQ 23 + +/* PIC IRQ settings. */ +#define PIRQ_PIC_IRQ3 0x3 +#define PIRQ_PIC_IRQ4 0x4 +#define PIRQ_PIC_IRQ5 0x5 +#define PIRQ_PIC_IRQ6 0x6 +#define PIRQ_PIC_IRQ7 0x7 +#define PIRQ_PIC_IRQ9 0x9 +#define PIRQ_PIC_IRQ10 0xa +#define PIRQ_PIC_IRQ11 0xb +#define PIRQ_PIC_IRQ12 0xc +#define PIRQ_PIC_IRQ14 0xe +#define PIRQ_PIC_IRQ15 0xf +#define PIRQ_PIC_IRQDISABLE 0x80 +#define PIRQ_PIC_UNKNOWN_UNUSED 0xff + +/* Overloaded term, but these values determine the per device route. */ +#define PIRQA 0 +#define PIRQB 1 +#define PIRQC 2 +#define PIRQD 3 +#define PIRQE 4 +#define PIRQF 5 +#define PIRQG 6 +#define PIRQH 7 + +#define ACPI_CNTL_OFFSET 0x44 +#define SCIS_MASK 0x07 +#define SCIS_IRQ9 0x00 +#define SCIS_IRQ10 0x01 +#define SCIS_IRQ11 0x02 +#define SCIS_IRQ20 0x04 +#define SCIS_IRQ21 0x05 +#define SCIS_IRQ22 0x06 +#define SCIS_IRQ23 0x07 + +/* In each mainboard directory there should exist a header file irqroute.h that + * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which + * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ + +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) +#include + +#define NUM_OF_PCI_DEVS 32 +#define NUM_PIRQS 8 + +struct broadwell_de_irq_route { + /* Per device configuration. */ + uint16_t pcidev[NUM_OF_PCI_DEVS]; + /* Route path for each internal PIRQx in PIC mode. */ + uint8_t pic[NUM_PIRQS]; +}; + +extern const struct broadwell_de_irq_route global_broadwell_de_irq_route; + +#define DEFINE_IRQ_ROUTES \ + const struct broadwell_de_irq_route global_broadwell_de_irq_route = { \ + .pcidev = { PCI_DEV_PIRQ_ROUTES, }, \ + .pic = { PIRQ_PIC_ROUTES, }, \ + } + +#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ + [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ + ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) + +#define PIRQ_PIC(pirq_, pic_irq_) \ + [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ + +#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ + +#endif /* _BROADWELL_DE_IRQ_H_ */ From patchwork Fri Jan 26 11:19:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vnktux X-Patchwork-Id: 866257 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=protonmail.com header.i=@protonmail.com header.b="Z+77owHM"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zSbyk1R5vz9s7n for ; Fri, 26 Jan 2018 22:19:26 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D4BFBC22465; Fri, 26 Jan 2018 11:19:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0D5E8C21F3A; Fri, 26 Jan 2018 11:19:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EEA8DC21F3A; Fri, 26 Jan 2018 11:19:15 +0000 (UTC) Received: from mail1.protonmail.ch (mail1.protonmail.ch [185.70.40.18]) by lists.denx.de (Postfix) with ESMTPS id 99183C21F2B for ; Fri, 26 Jan 2018 11:19:15 +0000 (UTC) Date: Fri, 26 Jan 2018 06:19:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=default; t=1516965554; bh=cIVwf693fSvy3meI9k73ZaA6JSCJn9OtDWbXdS05mjw=; h=Date:To:From:Reply-To:Subject:Feedback-ID:From; b=Z+77owHMlqigYGs7Nh90Ynljub0cfmLZJcu6f+rVLqLyigQthpgnkru0+mKl2O0rT 4CS1R6DcN+YjFTH3Ea5JTwmapNV7nScGR1lIGYi6MR88KWJQVqlyuphuww+Tu1MF9O anxN/QRCvWi4R7qBSlVNhlbJAUY/ABD4drBm/Ihk= To: U-Boot Mailing List , Bin Meng , Simon Glass From: vnktux Message-ID: Feedback-ID: fQAv8VbfcH8vKw3iZs6YphjgEQJ-aaYuxqlUNJIYnTNWJaksoUfwxN0WBNzHStAL5v1BIFRDUajzM6hlODYqkw==:Ext:ProtonMail MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.18 Subject: [U-Boot] [PATCH 3/6] Implemented support for SPD memory file required by BDE FSP X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: vnktux Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch include the support for SPD binary required by Broadwell-DE FSP in case the platform has memory down enabled. Signed-off-by: Vincenzo Bove --- arch/x86/Kconfig | 24 ++++++++++++++++++++++++ arch/x86/dts/u-boot.dtsi | 6 ++++++ 2 files changed, 30 insertions(+) -- 2.11.0 diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5c23b2cb57..9d78c80d9f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -766,6 +766,30 @@ config HIGH_TABLE_SIZE Increse it if the default size does not fit the board's needs. This is most likely due to a large ACPI DSDT table is used. +config FSP_MEMORY_DOWN + bool "Platform has memory down" + help + Select this option if your platform has memory soldered on the motherboard and FSP need SPD file. + +config HAVE_SPD + bool "Add SPD file" + help + Select this option if you have a SPD binary file for your memorydown. + +config SPD_FILE + string "SPD image filename" + depends on HAVE_SPD + default "spd_ch0_dimm0.bin" + help + The filename of the ram SPD binary. + +config SPD_ADDR + hex "SPD image location" + depends on HAVE_SPD + default 0xffcb0000 + help + The location of the SPD binary file. + source "arch/x86/lib/efi/Kconfig" endmenu diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 7e37d4f394..486abe31bf 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -67,6 +67,12 @@ pos = ; }; #endif +#ifdef CONFIG_HAVE_SPD + intel-spd { + filename = CONFIG_SPD_FILE; + pos = ; + }; +#endif #ifdef CONFIG_HAVE_VBT intel-vbt { filename = CONFIG_VBT_FILE; From patchwork Fri Jan 26 11:21:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vnktux X-Patchwork-Id: 866259 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=protonmail.com header.i=@protonmail.com header.b="a39Ix4T5"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zSc1G3Cvqz9ryr for ; Fri, 26 Jan 2018 22:21:37 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 45E27C2246D; Fri, 26 Jan 2018 11:21:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 625C1C21ECC; Fri, 26 Jan 2018 11:21:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DF796C21ECC; Fri, 26 Jan 2018 11:21:28 +0000 (UTC) Received: from mail1.protonmail.ch (mail1.protonmail.ch [185.70.40.18]) by lists.denx.de (Postfix) with ESMTPS id 6E9B1C21DA1 for ; Fri, 26 Jan 2018 11:21:28 +0000 (UTC) Date: Fri, 26 Jan 2018 06:21:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=default; t=1516965686; bh=fp37fCYDSv8iiuA3Z4H60tQWeODW9QvlebKxFGWimbE=; h=Date:To:From:Reply-To:Subject:Feedback-ID:From; b=a39Ix4T5D7/cA5DN2A/RHH5IxnRXMaa5QkNlzPsLKl8m/YOoJWIyho+OoTm9GDoPN OiAfBiNO1PH3qhKp1m2k9AdyS/f6g6AfF0+ktr8S3y7b1sJMgaSFFTxDxQSW2xQtm9 xE78LtU7rLrnmU1m7aYcNW8F8+dVSp3z0KZuW2ss= To: U-Boot Mailing List , Bin Meng , Simon Glass From: vnktux Message-ID: Feedback-ID: fQAv8VbfcH8vKw3iZs6YphjgEQJ-aaYuxqlUNJIYnTNWJaksoUfwxN0WBNzHStAL5v1BIFRDUajzM6hlODYqkw==:Ext:ProtonMail MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.18 Subject: [U-Boot] [PATCH 4/6] Add DTS for Broadwell-DE platform board X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: vnktux Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch include a DTS file for a Broadwell-de platform used for developing called Poseidon. I did not include the 3 microcodes to keep the patch small, do I have to submit them as well? Signed-off-by: Vincenzo Bove --- arch/x86/dts/Makefile | 1 + arch/x86/dts/poseidon.dts | 177 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 178 insertions(+) create mode 100644 arch/x86/dts/poseidon.dts -- 2.11.0 diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 6d0c4b65ec..e59f192b6e 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -15,6 +15,7 @@ dtb-y += bayleybay.dtb \ efi.dtb \ galileo.dtb \ minnowmax.dtb \ + poseidon.dtb \ qemu-x86_i440fx.dtb \ qemu-x86_q35.dtb \ theadorable-x86-dfi-bt700.dtb \ diff --git a/arch/x86/dts/poseidon.dts b/arch/x86/dts/poseidon.dts new file mode 100644 index 0000000000..3a08dc76df --- /dev/null +++ b/arch/x86/dts/poseidon.dts @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include +#include +#include + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" +/include/ "coreboot_fb.dtsi" + +/ { + model = "Intel Broadwell-DE"; + compatible = "x86", "intel,poseidon", "intel,broadwell-de"; + + chosen { + stdout-path = "/serial"; + }; + + tsc-timer { + clock-frequency = <1000000000>; + }; + + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 + 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + pch@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,pch9"; + #address-cells = <1>; + #size-cells = <1>; + + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "ibase"; + intel,ibase-offset = <0x50>; + intel,pirq-link = <8 8>; + intel,pirq-mask = <0xdee0>; + intel,pirq-routing = < + /*PCI_BDF(0, 31, 0) LPC Controller does not generate an interrupt */ + PCI_BDF(0, 31, 2) INTB PIRQB /* SATA Controller #1 */ + PCI_BDF(0, 31, 3) INTC PIRQC /* SMBus Controller */ + PCI_BDF(0, 31, 5) INTB PIRQB /* SATA Controller #2 */ + PCI_BDF(0, 31, 6) INTC PIRQC /* Thermal Subsystem */ + PCI_BDF(0, 29, 0) INTA PIRQA /* USB EHCI Controller #1 */ + PCI_BDF(0, 28, 0) INTA PIRQA /* PCI Express Port 1 */ + PCI_BDF(0, 28, 1) INTB PIRQB /* PCI Express Port 2 */ + PCI_BDF(0, 28, 2) INTC PIRQC /* PCI Express Port 3 */ + PCI_BDF(0, 28, 3) INTD PIRQD /* PCI Express Port 4 */ + PCI_BDF(0, 28, 4) INTA PIRQA /* PCI Express Port 5 */ + PCI_BDF(0, 28, 5) INTB PIRQB /* PCI Express Port 6 */ + PCI_BDF(0, 28, 6) INTC PIRQC /* PCI Express Port 7 */ + PCI_BDF(0, 28, 7) INTD PIRQD /* PCI Express Port 8 */ + PCI_BDF(0, 25, 0) INTA PIRQA /* Gigabit Ethernet Controller*/ + PCI_BDF(0, 22, 0) INTA PIRQA /* Intel Management Engine Interface #1 */ + PCI_BDF(0, 22, 1) INTB PIRQB /* Intel Management Engine Interface #2*/ + PCI_BDF(0, 22, 2) INTC PIRQC /* IDE-R*/ + PCI_BDF(0, 22, 3) INTD PIRQD /* KT*/ + PCI_BDF(0, 20, 0) INTA PIRQA /* xHCI Controller */ + >; + }; + + }; + }; + + fsp { + compatible = "intel,broadwell-de-fsp"; + fsp,memEccSupport = ; + fsp,memDdrMemoryType = ; + fsp,memRankMultiplication = ; + fsp,memRankMarginTool = ; + fsp,memScrambling = ; + fsp,memRefreshMode = ; + fsp,memMcOdtOverride = ; + fsp,memCAParity = ; + fsp,memThermalThrottling = ; + fsp,memPowerSavingsMode = ; + fsp,memElectricalThrottling = ; + fsp,memPagePolicy = ; + fsp,memSocketInterleaveBelow4G = ; + fsp,memChannelInterleave = ; + fsp,memRankInterleave = ; + + #ifdef CONFIG_FSP_MEMORY_DOWN + fsp,memDownEnable; + fsp,memDownCh0Dimm0SpdPtr = ; + fsp,memDownCh0Dimm1SpdPtr = <0x0>; + fsp,memDownCh1Dimm0SpdPtr = <0x0>; + fsp,memDownCh1Dimm1SpdPtr = <0x0>; + #endif + + /*#ifdef CONFIG_ENABLE_MRC_CACHE + fsp,mem-fast-boot = ; + #else + fsp,mem-fast-boot = ; + #endif*/ + fsp,mem-fast-boot = ; + + fsp,pam0-hienable = ; + fsp,pam1-loenable = ; + fsp,pam1-hienable = ; + fsp,pam2-loenable = ; + fsp,pam2-hienable = ; + fsp,pam3-loenable = ; + fsp,pam3-hienable = ; + fsp,pam4-loenable = ; + fsp,pam4-hienable = ; + fsp,pam5-loenable = ; + fsp,pam5-hienable = ; + fsp,pam6-loenable = ; + fsp,pam6-hienable = ; + fsp,memAdr = ; + fsp,serial-port-type = ; + fsp,serial-port-address = <0x3f8>; + fsp,serial-port-configure; + fsp,serial-port-baudrate = ; + fsp,serial-port-controller-init0; + fsp,serial-port-controller-init1; + fsp,config-iou1-pci-port3 = ; + fsp,config-iou2-pci-port1 = ; + fsp,pch-pci-port1; + fsp,pch-pci-port2; + fsp,pch-pci-port3; + fsp,pch-pci-port4; + fsp,pch-pci-port5; + fsp,pch-pci-port6; + fsp,pch-pci-port7; + fsp,pch-pci-port8; + fsp,ehci1-enable; + fsp,hyper-threading; + fsp,debug-output-level = ; + fsp,tco-timer-halt-lock; + fsp,turbo-mode; + fsp,boot-perf-mode; + fsp,pcie-port1a-aspm = ; + fsp,pcie-port1b-aspm = ; + fsp,pcie-port3a-aspm = ; + fsp,pcie-port3b-aspm = ; + fsp,pcie-port3c-aspm = ; + fsp,pcie-port3d-aspm = ; + fsp,pch-pcie-port1-aspm = ; + fsp,pch-pcie-port2-aspm = ; + fsp,pch-pcie-port3-aspm = ; + fsp,pch-pcie-port4-aspm = ; + fsp,pch-pcie-port5-aspm = ; + fsp,pch-pcie-port6-aspm = ; + fsp,pch-pcie-port7-aspm = ; + fsp,pch-pcie-port8-aspm = ; + fsp,thermal-device-enable; + }; + + microcode { + update@0 { +#include "microcode/broadwell_de_microcode/m1050663_0700000e.dtsi" + }; + update@1 { +#include "microcode/broadwell_de_microcode/m1050662_00000011.dtsi" + }; + update@2 { +#include "microcode/broadwell_de_microcode/mff50661_f1000008.dtsi" + }; + }; + +}; From patchwork Fri Jan 26 11:22:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vnktux X-Patchwork-Id: 866260 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=protonmail.com header.i=@protonmail.com header.b="FzKhVt2E"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zSc356Vqhz9ryr for ; Fri, 26 Jan 2018 22:23:13 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 47836C22465; Fri, 26 Jan 2018 11:23:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 45F2FC21F3A; Fri, 26 Jan 2018 11:23:05 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 79F80C21F3A; Fri, 26 Jan 2018 11:23:04 +0000 (UTC) Received: from mail1.protonmail.ch (mail1.protonmail.ch [185.70.40.18]) by lists.denx.de (Postfix) with ESMTPS id D6974C21DA1 for ; Fri, 26 Jan 2018 11:23:03 +0000 (UTC) Date: Fri, 26 Jan 2018 06:22:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=default; t=1516965781; bh=hA+DfL73WCMF3uKTvQXY0WzgMVGlEfzYOrrGIqNwYQ0=; h=Date:To:From:Reply-To:Subject:Feedback-ID:From; b=FzKhVt2E/nRUXnXZKEnrWX2b5lj7DeAyKt3VJ4efk1mBvtxak4HzdjC0AjRGR9mZE Kw4BIfWU+Ss0k7viiIj6cfGiP+cNremNHepJ1kblKhLICbriMzVxXQe9tuj9UHCDoP cBtPi34osCIM44znkGLYxlFpDRdM831BfN4MzsNw= To: U-Boot Mailing List , Bin Meng , Simon Glass From: vnktux Message-ID: <8-L6bHrRj2ajmxMCpFp8kZZzQpF7cSYpaEaAUL2d-ljj9cASqCgtMs610-dhJR5KlLe9_wzDKpK6UKQbqtmzSKe3_FzNLu3PDXzgN0phse8=@protonmail.com> Feedback-ID: fQAv8VbfcH8vKw3iZs6YphjgEQJ-aaYuxqlUNJIYnTNWJaksoUfwxN0WBNzHStAL5v1BIFRDUajzM6hlODYqkw==:Ext:ProtonMail MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.18 Subject: [U-Boot] [PATCH 5/6] Add Poseidon platform, based on BDE with memory down X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: vnktux Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch include a board called Poseidon. That is a platform based on Broadwell-DE with memory down enabled on channel 0 dimm 0. This platform was used to implement the architecture in U-Boot. Signed-off-by: Vincenzo Bove --- board/prodrive/Kconfig | 23 ++++ board/prodrive/poseidon/.gitignore | 5 + board/prodrive/poseidon/Kconfig | 45 +++++++ board/prodrive/poseidon/MAINTAINERS | 6 + board/prodrive/poseidon/Makefile | 8 ++ board/prodrive/poseidon/acpi/mainboard.asl | 11 ++ board/prodrive/poseidon/dsdt.asl | 187 +++++++++++++++++++++++++++++ board/prodrive/poseidon/poseidon.c | 18 +++ board/prodrive/poseidon/start.S | 9 ++ configs/poseidon_defconfig | 70 +++++++++++ include/configs/poseidon.h | 29 +++++ 11 files changed, 411 insertions(+) create mode 100644 board/prodrive/Kconfig create mode 100644 board/prodrive/poseidon/.gitignore create mode 100644 board/prodrive/poseidon/Kconfig create mode 100644 board/prodrive/poseidon/MAINTAINERS create mode 100644 board/prodrive/poseidon/Makefile create mode 100644 board/prodrive/poseidon/acpi/mainboard.asl create mode 100644 board/prodrive/poseidon/dsdt.asl create mode 100644 board/prodrive/poseidon/poseidon.c create mode 100644 board/prodrive/poseidon/start.S create mode 100644 configs/poseidon_defconfig create mode 100644 include/configs/poseidon.h -- 2.11.0 diff --git a/board/prodrive/Kconfig b/board/prodrive/Kconfig new file mode 100644 index 0000000000..4828b65b2b --- /dev/null +++ b/board/prodrive/Kconfig @@ -0,0 +1,23 @@ +# +# Copyright (C) 2017, Vincenzo Bove +# +# SPDX-License-Identifier: GPL-2.0+ +# + +if VENDOR_PRODRIVE + +choice + prompt "Mainboard model" + optional + +config TARGET_POSEIDON + bool "Poseidon" + help + This target is for Prodrive Poseidon. + Embedded board hosting x86 Broadwell-DE Xeon processor. + +endchoice + +source "board/prodrive/poseidon/Kconfig" + +endif diff --git a/board/prodrive/poseidon/.gitignore b/board/prodrive/poseidon/.gitignore new file mode 100644 index 0000000000..c782010f5b --- /dev/null +++ b/board/prodrive/poseidon/.gitignore @@ -0,0 +1,5 @@ +dsdt.aml +dsdt.asl.tmp +dsdt.c + +!*.bin \ No newline at end of file diff --git a/board/prodrive/poseidon/Kconfig b/board/prodrive/poseidon/Kconfig new file mode 100644 index 0000000000..4fa9feff6e --- /dev/null +++ b/board/prodrive/poseidon/Kconfig @@ -0,0 +1,45 @@ +# +# Copyright (C) 2017, Vincenzo Bove +# +# SPDX-License-Identifier: GPL-2.0+ + +if TARGET_POSEIDON + +config SYS_BOARD + default "poseidon" + +config SYS_VENDOR + default "prodrive" + +config SYS_SOC + default "broadwell-de" + +config SYS_CONFIG_NAME + default "poseidon" + +config SYS_TEXT_BASE + default 0xffdb0000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_BROADWELL_DE + select BOARD_ROMSIZE_KB_16384 + select SPI_FLASH_MACRONIX + +config PCIE_ECAM_BASE + default 0x80000000 + +config SYS_CAR_ADDR + hex + default 0xfef00000 + +config SYS_CAR_SIZE + hex + default 0x40000 + +config SYS_PROMPT + string + default "Poseidon => " + +endif diff --git a/board/prodrive/poseidon/MAINTAINERS b/board/prodrive/poseidon/MAINTAINERS new file mode 100644 index 0000000000..c21f2e6374 --- /dev/null +++ b/board/prodrive/poseidon/MAINTAINERS @@ -0,0 +1,6 @@ +Prodrive Poseidon x86 Broadwell-DE +M: Vincenzo Bove +S: Maintained +F: board/prodrive/poseidon +F: include/configs/poseidon.h +F: configs/poseidon_defconfig diff --git a/board/prodrive/poseidon/Makefile b/board/prodrive/poseidon/Makefile new file mode 100644 index 0000000000..83fd499814 --- /dev/null +++ b/board/prodrive/poseidon/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017, Vincenzo Bove +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += poseidon.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/prodrive/poseidon/acpi/mainboard.asl b/board/prodrive/poseidon/acpi/mainboard.asl new file mode 100644 index 0000000000..4cc8ad376d --- /dev/null +++ b/board/prodrive/poseidon/acpi/mainboard.asl @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} diff --git a/board/prodrive/poseidon/dsdt.asl b/board/prodrive/poseidon/dsdt.asl new file mode 100644 index 0000000000..951f320b74 --- /dev/null +++ b/board/prodrive/poseidon/dsdt.asl @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x20110725) +{ + /* platform specific */ + #include + + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) + Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) + + Scope (\_SB) + { + Device (PCI0) + { + #include + #include + } + + Name (PRUN, Package() { + Package() { 0x0008FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0009FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000AFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000BFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0010FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0011FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0011FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0011FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0011FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0012FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0012FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0012FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0012FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0013FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0013FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0013FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0013FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + }) + + Name (ARUN, Package() { + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + + Package() { 0x000CFFFF, 0, 0, 16 }, + Package() { 0x000CFFFF, 1, 0, 17 }, + Package() { 0x000CFFFF, 2, 0, 18 }, + Package() { 0x000CFFFF, 3, 0, 19 }, + + Package() { 0x000DFFFF, 0, 0, 16 }, + Package() { 0x000DFFFF, 1, 0, 17 }, + Package() { 0x000DFFFF, 2, 0, 18 }, + Package() { 0x000DFFFF, 3, 0, 19 }, + + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + + Package() { 0x0011FFFF, 0, 0, 16 }, + Package() { 0x0011FFFF, 1, 0, 17 }, + Package() { 0x0011FFFF, 2, 0, 18 }, + Package() { 0x0011FFFF, 3, 0, 19 }, + + Package() { 0x0012FFFF, 0, 0, 16 }, + Package() { 0x0012FFFF, 1, 0, 17 }, + Package() { 0x0012FFFF, 2, 0, 18 }, + Package() { 0x0012FFFF, 3, 0, 19 }, + + Package() { 0x0013FFFF, 0, 0, 16 }, + Package() { 0x0013FFFF, 1, 0, 17 }, + Package() { 0x0013FFFF, 2, 0, 18 }, + Package() { 0x0013FFFF, 3, 0, 19 }, + }) + + Device (UNC0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_UID, 0x3F) + Method (_BBN, 0, NotSerialized) + { + Return (0xff) + } + + Name (_ADR, 0x00) + Method (_STA, 0, NotSerialized) + { + Return (0xf) + } + + Name (_CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x00FF, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + + Method (_PRT, 0, NotSerialized) + { + If (LEqual (PICM, Zero)) + { + Return (PRUN) + } + + Return (ARUN) + } + } + } + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/board/prodrive/poseidon/poseidon.c b/board/prodrive/poseidon/poseidon.c new file mode 100644 index 0000000000..9323b3c669 --- /dev/null +++ b/board/prodrive/poseidon/poseidon.c @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + + +int misc_init_r(void) +{ + + return 0; +} diff --git a/board/prodrive/poseidon/start.S b/board/prodrive/poseidon/start.S new file mode 100644 index 0000000000..bf9374b8f7 --- /dev/null +++ b/board/prodrive/poseidon/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/configs/poseidon_defconfig b/configs/poseidon_defconfig new file mode 100644 index 0000000000..accf0a1b80 --- /dev/null +++ b/configs/poseidon_defconfig @@ -0,0 +1,70 @@ +CONFIG_X86=y +CONFIG_SYS_CONFIG_NAME="poseidon" +CONFIG_VENDOR_PRODRIVE=y +CONFIG_DEFAULT_DEVICE_TREE="poseidon" +CONFIG_TARGET_POSEIDON=y +CONFIG_FSP_MEMORY_DOWN=y +CONFIG_HAVE_SPD=y +CONFIG_INTERNAL_UART=y +CONFIG_SMP=y +#CONFIG_HAVE_VGA_BIOS=y +#CONFIG_VGA_BIOS_ADDR=0xfffd0001 +#CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +#CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_GENERATE_PIRQ_TABLE=y +#CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_SEABIOS=y +CONFIG_FIT=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +#CONFIG_USE_BOOTARGS=y +#CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/sdb3 init=/sbin/init rootwait ro" +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_PART=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CPU=y +CONFIG_USB_STORAGE=y +CONFIG_USB_KEYBOARD=y +CONFIG_CONSOLE_SCROLL_LINES=5 +#CONFIG_CMD_IMLS=n +CONFIG_SYS_NS16550=y +#CONFIG_CMD_TPM=y +#CONFIG_CMD_TPM_TEST=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_DM_PCI=y +#CONFIG_DM_RTC=y +CONFIG_TIMER=y +#CONFIG_TPM_TIS_LPC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_UHCI_HCD=y +#CONFIG_DM_VIDEO=y +CONFIG_USE_PRIVATE_LIBGCC=y +#CONFIG_TPM=y +CONFIG_OF_CONTROL=y +CONFIG_I8259_PIC=y +CONFIG_I8254_TIMER=y diff --git a/include/configs/poseidon.h b/include/configs/poseidon.h new file mode 100644 index 0000000000..739ca8ec50 --- /dev/null +++ b/include/configs/poseidon.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2017, Vincenzo Bove + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#define CONFIG_USB_ETHER_ASIX88179 + +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, 0x8c02} + +#undef CONFIG_ENV_IS_IN_SPI_FLASH + +#define DEBUG + +#endif /* __CONFIG_H */ From patchwork Fri Jan 26 11:24:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vnktux X-Patchwork-Id: 866261 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=protonmail.com header.i=@protonmail.com header.b="TdFiluUG"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zSc4m262Dz9ryr for ; Fri, 26 Jan 2018 22:24:40 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B6CBFC21FCD; Fri, 26 Jan 2018 11:24:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3C530C21E90; Fri, 26 Jan 2018 11:24:32 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 85AF5C21E90; Fri, 26 Jan 2018 11:24:31 +0000 (UTC) Received: from mail1.protonmail.ch (mail1.protonmail.ch [185.70.40.18]) by lists.denx.de (Postfix) with ESMTPS id 0C8F0C21DA1 for ; Fri, 26 Jan 2018 11:24:31 +0000 (UTC) Date: Fri, 26 Jan 2018 06:24:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=default; t=1516965869; bh=k3V3GDwJthVRmU2+gphSdosaYuXL914VkMHFgkJG+pE=; h=Date:To:From:Reply-To:Subject:Feedback-ID:From; b=TdFiluUGL8K8Hxfug3rVhsnpnJ4biMYa+k8bQ4YZa/bugvZTKyR5p9FZVS/NX2oh8 avRbT2rm4IkX+bjRGnOUAuOciOE1UQF48aq2hCv/bBqiVAbqijO+4/BP5/Y+qS2kZu X6fROgyarZQBwYGLiEOg56uWjCcJFghyzQ9F4V6o= To: U-Boot Mailing List , Bin Meng , Simon Glass From: vnktux Message-ID: Feedback-ID: fQAv8VbfcH8vKw3iZs6YphjgEQJ-aaYuxqlUNJIYnTNWJaksoUfwxN0WBNzHStAL5v1BIFRDUajzM6hlODYqkw==:Ext:ProtonMail MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.18 Subject: [U-Boot] [PATCH 6/6] Updated Makefile and Kconfig in order to build BDE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: vnktux Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch modify Makefile and Kconfig file in order to build Broadwell-de platforms. Signed-off-by: Vincenzo Bove --- arch/x86/Kconfig | 5 +++++ arch/x86/cpu/Makefile | 1 + include/fdtdec.h | 1 + lib/fdtdec.c | 1 + tools/binman/etype/intel_spd.py | 14 ++++++++++++++ 5 files changed, 22 insertions(+) create mode 100644 tools/binman/etype/intel_spd.py -- 2.11.0 diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 9d78c80d9f..57fdcd780b 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -78,6 +78,9 @@ config VENDOR_GOOGLE config VENDOR_INTEL bool "Intel" +config VENDOR_PRODRIVE + bool "Prodrive" + endchoice # subarchitectures-specific options below @@ -105,11 +108,13 @@ source "board/efi/Kconfig" source "board/emulation/Kconfig" source "board/google/Kconfig" source "board/intel/Kconfig" +source "board/prodrive/Kconfig" # platform-specific options below source "arch/x86/cpu/baytrail/Kconfig" source "arch/x86/cpu/braswell/Kconfig" source "arch/x86/cpu/broadwell/Kconfig" +source "arch/x86/cpu/broadwell-de/Kconfig" source "arch/x86/cpu/coreboot/Kconfig" source "arch/x86/cpu/ivybridge/Kconfig" source "arch/x86/cpu/qemu/Kconfig" diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 94cdff18cc..1fb1c40095 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -29,6 +29,7 @@ obj-y += intel_common/ obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/ obj-$(CONFIG_INTEL_BRASWELL) += braswell/ obj-$(CONFIG_INTEL_BROADWELL) += broadwell/ +obj-$(CONFIG_INTEL_BROADWELL_DE) += broadwell-de/ obj-$(CONFIG_SYS_COREBOOT) += coreboot/ obj-$(CONFIG_EFI_APP) += efi/ obj-$(CONFIG_QEMU) += qemu/ diff --git a/include/fdtdec.h b/include/fdtdec.h index 4afb9ac501..ea8bff43a1 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -150,6 +150,7 @@ enum fdt_compat_id { COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ + COMPAT_INTEL_BROADWELL_DE_FSP, /* Intel Broadwell-DE FSP */ COMPAT_SUNXI_NAND, /* SUNXI NAND controller */ COMPAT_ALTERA_SOCFPGA_CLK, /* SoCFPGA Clock initialization */ COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE, /* SoCFPGA pinctrl-single */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index df9d9ae433..e1a2f176e3 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -62,6 +62,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"), COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"), COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"), + COMPAT(INTEL_BROADWELL_DE_FSP, "intel,broadwell-de-fsp"), COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"), COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"), COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"), diff --git a/tools/binman/etype/intel_spd.py b/tools/binman/etype/intel_spd.py new file mode 100644 index 0000000000..028c98f0c8 --- /dev/null +++ b/tools/binman/etype/intel_spd.py @@ -0,0 +1,14 @@ +# Copyright (c) 2016 Google, Inc +# Written by Simon Glass +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Entry-type module for Intel Management Engine binary blob +# + +from entry import Entry +from blob import Entry_blob + +class Entry_intel_spd(Entry_blob): + def __init__(self, image, etype, node): + Entry_blob.__init__(self, image, etype, node) \ No newline at end of file