From patchwork Mon Jul 12 14:04:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Hoyes X-Patchwork-Id: 1504022 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GNlrc3bqkz9sWc for ; Tue, 13 Jul 2021 00:04:48 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8A30A82D95; Mon, 12 Jul 2021 16:04:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 8555D82D7E; Mon, 12 Jul 2021 16:04:41 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id B949E82D7E for ; Mon, 12 Jul 2021 16:04:38 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=peter.hoyes@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D4BB81FB; Mon, 12 Jul 2021 07:04:37 -0700 (PDT) Received: from e125920.arm.com (unknown [10.57.90.135]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4CEB43F774; Mon, 12 Jul 2021 07:04:36 -0700 (PDT) From: Peter Hoyes To: u-boot@lists.denx.de Cc: Stephen Warren , Michal Simek , "Edgar E . Iglesias" , Andre Przywara , Diego Sueiro , Peter Hoyes Subject: [PATCH] armv8: Initialize CNTFRQ if at highest exception level Date: Mon, 12 Jul 2021 15:04:21 +0100 Message-Id: <20210712140421.3532104-1-peter.hoyes@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Peter Hoyes CNTFRQ_EL0 is only writable from the highest supported exception level on the platform. For Armv8-A, this is typically EL3, but technically EL2 and EL3 are optional so it may need to be initialized at EL2 or EL1. For Armv8-R, the highest exception level is always EL2. This patch moves the initialization outside of the switch_el block and uses a new macro branch_if_not_highest_el which dynamically detects whether it is at the highest supported exception level. Linux's docs state that CNTFRQ_EL0 should be initialized by the bootloader. If not set, the the U-Boot prompt countdown hangs. Signed-off-by: Peter Hoyes --- arch/arm/cpu/armv8/start.S | 13 ++++++++----- arch/arm/include/asm/macro.h | 18 ++++++++++++++++++ arch/arm/include/asm/system.h | 6 ++++++ 3 files changed, 32 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 662449156b..8d7cfd7a87 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -127,10 +127,6 @@ pie_fixup_done: orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ msr scr_el3, x0 msr cptr_el3, xzr /* Enable FP/SIMD */ -#ifdef COUNTER_FREQUENCY - ldr x0, =COUNTER_FREQUENCY - msr cntfrq_el0, x0 /* Initialize CNTFRQ */ -#endif b 0f 2: set_vbar vbar_el2, x0 mov x0, #0x33ff @@ -140,7 +136,14 @@ pie_fixup_done: mov x0, #3 << 20 msr cpacr_el1, x0 /* Enable FP/SIMD */ 0: - isb + +#ifdef COUNTER_FREQUENCY + branch_if_not_highest_el x0, 4f + ldr x0, =COUNTER_FREQUENCY + msr cntfrq_el0, x0 /* Initialize CNTFRQ */ +#endif + +4: isb /* * Enable SMPEN bit for coherency. diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index bb33b4bc89..485310d660 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -77,6 +77,24 @@ lr .req x30 b.eq \el1_label .endm +/* + * Branch if we are not in the highest exception level + */ +.macro branch_if_not_highest_el, xreg, label + switch_el \xreg, 3f, 2f, 1f + +2: mrs \xreg, ID_AA64PFR0_EL1 + and \xreg, \xreg, #(ID_AA64PFR0_EL1_EL3) + cbnz \xreg, \label + b 3f + +1: mrs \xreg, ID_AA64PFR0_EL1 + and \xreg, \xreg, #(ID_AA64PFR0_EL1_EL3 | ID_AA64PFR0_EL1_EL2) + cbnz \xreg, \label + +3: +.endm + /* * Branch if current processor is a Cortex-A57 core. */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 11fceec4d2..8b3a54e64c 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -79,6 +79,12 @@ #define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */ #define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */ +/* + * ID_AA64PFR0_EL1 bits definitions + */ +#define ID_AA64PFR0_EL1_EL3 (0xF << 12) /* EL3 implemented */ +#define ID_AA64PFR0_EL1_EL2 (0xF << 8) /* EL2 implemented */ + /* * CPACR_EL1 bits definitions */