From patchwork Thu Jul 8 00:54:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502048 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKycc0Rlmz9sWS for ; Thu, 8 Jul 2021 10:59:44 +1000 (AEST) Received: from localhost ([::1]:46496 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IOD-0000KX-Op for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 20:59:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37956) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKl-0001rA-Oo for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:07 -0400 Received: from mga03.intel.com ([134.134.136.65]:19084) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKk-0007Kl-2H for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:07 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="209461992" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="209461992" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:52 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423769979" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:51 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 01/44] target/i386: Expose x86_cpu_get_supported_feature_word() for TDX Date: Wed, 7 Jul 2021 17:54:31 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.65; envelope-from=isaku.yamahata@intel.com; helo=mga03.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Sean Christopherson Expose x86_cpu_get_supported_feature_word() outside of cpu.c so that it can be used by TDX to setup the VM-wide CPUID configuration. Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata Reviewed-by: Connor Kuehl --- target/i386/cpu.c | 4 ++-- target/i386/cpu.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d8f3ab3192..45b81a63df 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4894,8 +4894,8 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) return cpu_list; } -static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, - bool migratable_only) +uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, + bool migratable_only) { FeatureWordInfo *wi = &feature_word_info[w]; uint64_t r = 0; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index f7fa5870b1..ff8f9532b9 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1838,6 +1838,9 @@ void cpu_clear_ignne(void); /* mpx_helper.c */ void cpu_sync_bndcs_hflags(CPUX86State *env); +uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, + bool migratable_only); + /* this function must always be used to load data in the segment cache: it synchronizes the hflags with the segment cache values */ static inline void cpu_x86_load_seg_cache(CPUX86State *env, From patchwork Thu Jul 8 00:54:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502044 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyYp2L6gz9sWS for ; Thu, 8 Jul 2021 10:57:18 +1000 (AEST) Received: from localhost ([::1]:37846 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1ILs-0001ly-2b for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 20:57:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37906) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKg-0001lk-Ey for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:02 -0400 Received: from mga03.intel.com ([134.134.136.65]:19084) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKd-0007Kl-FC for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:02 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="209461993" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="209461993" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:53 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423769985" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:52 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 02/44] kvm: Switch KVM_CAP_READONLY_MEM to a per-VM ioctl() Date: Wed, 7 Jul 2021 17:54:32 -0700 Message-Id: <20f5a78e8c704adcf4e96dac4aa160b9b6a7c17c.1625704980.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.65; envelope-from=isaku.yamahata@intel.com; helo=mga03.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Switch to making a VM ioctl() call for KVM_CAP_READONLY_MEM, which may be conditional on VM type in recent versions of KVM, e.g. when TDX is supported. kvm_vm_check_extension() has fallback from kvm_vm_ioctl() to kvm_check_extension(). fallback from VM ioctl to System ioctl for compatibility for old kernel. Signed-off-by: Isaku Yamahata Reviewed-by: Connor Kuehl --- accel/kvm/kvm-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index e5b10dd129..fdbe24bf59 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -2531,7 +2531,7 @@ static int kvm_init(MachineState *ms) } kvm_readonly_mem_allowed = - (kvm_check_extension(s, KVM_CAP_READONLY_MEM) > 0); + (kvm_vm_check_extension(s, KVM_CAP_READONLY_MEM) > 0); kvm_eventfds_allowed = (kvm_check_extension(s, KVM_CAP_IOEVENTFD) > 0); From patchwork Thu Jul 8 00:54:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502047 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKybH0wxvz9sW8 for ; Thu, 8 Jul 2021 10:58:35 +1000 (AEST) Received: from localhost ([::1]:41072 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IN6-0004XN-QU for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 20:58:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37970) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKm-0001st-6g for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:08 -0400 Received: from mga03.intel.com ([134.134.136.65]:19093) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKk-0007Lp-2J for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:07 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="209461994" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="209461994" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:53 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423769989" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:52 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 03/44] i386/kvm: Move architectural CPUID leaf generation to separarte helper Date: Wed, 7 Jul 2021 17:54:33 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.65; envelope-from=isaku.yamahata@intel.com; helo=mga03.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Sean Christopherson Move the architectural (for lack of a better term) CPUID leaf generation to a separate helper so that the generation code can be reused by TDX, which needs to generate a canonical VM-scoped configuration. Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- target/i386/kvm/kvm.c | 186 +++++++++++++++++++------------------ target/i386/kvm/kvm_i386.h | 4 + 2 files changed, 102 insertions(+), 88 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 04e4ec063f..0558e4b506 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1507,90 +1507,12 @@ static int hyperv_init_vcpu(X86CPU *cpu) static Error *invtsc_mig_blocker; -#define KVM_MAX_CPUID_ENTRIES 100 - -int kvm_arch_init_vcpu(CPUState *cs) +uint32_t kvm_x86_arch_cpuid(CPUX86State *env, struct kvm_cpuid_entry2 *entries, + uint32_t cpuid_i) { - struct { - struct kvm_cpuid2 cpuid; - struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES]; - } cpuid_data; - /* - * The kernel defines these structs with padding fields so there - * should be no extra padding in our cpuid_data struct. - */ - QEMU_BUILD_BUG_ON(sizeof(cpuid_data) != - sizeof(struct kvm_cpuid2) + - sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES); - - X86CPU *cpu = X86_CPU(cs); - CPUX86State *env = &cpu->env; - uint32_t limit, i, j, cpuid_i; + uint32_t limit, i, j; uint32_t unused; struct kvm_cpuid_entry2 *c; - uint32_t signature[3]; - int kvm_base = KVM_CPUID_SIGNATURE; - int max_nested_state_len; - int r; - Error *local_err = NULL; - - memset(&cpuid_data, 0, sizeof(cpuid_data)); - - cpuid_i = 0; - - r = kvm_arch_set_tsc_khz(cs); - if (r < 0) { - return r; - } - - /* vcpu's TSC frequency is either specified by user, or following - * the value used by KVM if the former is not present. In the - * latter case, we query it from KVM and record in env->tsc_khz, - * so that vcpu's TSC frequency can be migrated later via this field. - */ - if (!env->tsc_khz) { - r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ? - kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : - -ENOTSUP; - if (r > 0) { - env->tsc_khz = r; - } - } - - env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY; - - /* Paravirtualization CPUIDs */ - hyperv_expand_features(cs, &local_err); - if (local_err) { - error_report_err(local_err); - return -ENOSYS; - } - - if (hyperv_enabled(cpu)) { - r = hyperv_init_vcpu(cpu); - if (r) { - return r; - } - - cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries); - kvm_base = KVM_CPUID_SIGNATURE_NEXT; - has_msr_hv_hypercall = true; - } - - if (cpu->expose_kvm) { - memcpy(signature, "KVMKVMKVM\0\0\0", 12); - c = &cpuid_data.entries[cpuid_i++]; - c->function = KVM_CPUID_SIGNATURE | kvm_base; - c->eax = KVM_CPUID_FEATURES | kvm_base; - c->ebx = signature[0]; - c->ecx = signature[1]; - c->edx = signature[2]; - - c = &cpuid_data.entries[cpuid_i++]; - c->function = KVM_CPUID_FEATURES | kvm_base; - c->eax = env->features[FEAT_KVM]; - c->edx = env->features[FEAT_KVM_HINTS]; - } cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); @@ -1599,7 +1521,7 @@ int kvm_arch_init_vcpu(CPUState *cs) fprintf(stderr, "unsupported level value: 0x%x\n", limit); abort(); } - c = &cpuid_data.entries[cpuid_i++]; + c = &entries[cpuid_i++]; switch (i) { case 2: { @@ -1618,7 +1540,7 @@ int kvm_arch_init_vcpu(CPUState *cs) "cpuid(eax:2):eax & 0xf = 0x%x\n", times); abort(); } - c = &cpuid_data.entries[cpuid_i++]; + c = &entries[cpuid_i++]; c->function = i; c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); @@ -1664,7 +1586,7 @@ int kvm_arch_init_vcpu(CPUState *cs) "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); abort(); } - c = &cpuid_data.entries[cpuid_i++]; + c = &entries[cpuid_i++]; } break; case 0x7: @@ -1683,7 +1605,7 @@ int kvm_arch_init_vcpu(CPUState *cs) "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); abort(); } - c = &cpuid_data.entries[cpuid_i++]; + c = &entries[cpuid_i++]; c->function = i; c->index = j; c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; @@ -1740,7 +1662,7 @@ int kvm_arch_init_vcpu(CPUState *cs) fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit); abort(); } - c = &cpuid_data.entries[cpuid_i++]; + c = &entries[cpuid_i++]; switch (i) { case 0x8000001d: @@ -1759,7 +1681,7 @@ int kvm_arch_init_vcpu(CPUState *cs) "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); abort(); } - c = &cpuid_data.entries[cpuid_i++]; + c = &entries[cpuid_i++]; } break; default: @@ -1786,7 +1708,7 @@ int kvm_arch_init_vcpu(CPUState *cs) fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit); abort(); } - c = &cpuid_data.entries[cpuid_i++]; + c = &entries[cpuid_i++]; c->function = i; c->flags = 0; @@ -1794,6 +1716,94 @@ int kvm_arch_init_vcpu(CPUState *cs) } } + return cpuid_i; +} + +#define KVM_MAX_CPUID_ENTRIES 100 + +int kvm_arch_init_vcpu(CPUState *cs) +{ + struct { + struct kvm_cpuid2 cpuid; + struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES]; + } cpuid_data; + /* + * The kernel defines these structs with padding fields so there + * should be no extra padding in our cpuid_data struct. + */ + QEMU_BUILD_BUG_ON(sizeof(cpuid_data) != + sizeof(struct kvm_cpuid2) + + sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES); + + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + uint32_t cpuid_i; + struct kvm_cpuid_entry2 *c; + uint32_t signature[3]; + int kvm_base = KVM_CPUID_SIGNATURE; + int max_nested_state_len; + int r; + Error *local_err = NULL; + + memset(&cpuid_data, 0, sizeof(cpuid_data)); + + cpuid_i = 0; + + r = kvm_arch_set_tsc_khz(cs); + if (r < 0) { + return r; + } + + /* vcpu's TSC frequency is either specified by user, or following + * the value used by KVM if the former is not present. In the + * latter case, we query it from KVM and record in env->tsc_khz, + * so that vcpu's TSC frequency can be migrated later via this field. + */ + if (!env->tsc_khz) { + r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ? + kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : + -ENOTSUP; + if (r > 0) { + env->tsc_khz = r; + } + } + + env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY; + + /* Paravirtualization CPUIDs */ + hyperv_expand_features(cs, &local_err); + if (local_err) { + error_report_err(local_err); + return -ENOSYS; + } + + if (hyperv_enabled(cpu)) { + r = hyperv_init_vcpu(cpu); + if (r) { + return r; + } + + cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries); + kvm_base = KVM_CPUID_SIGNATURE_NEXT; + has_msr_hv_hypercall = true; + } + + if (cpu->expose_kvm) { + memcpy(signature, "KVMKVMKVM\0\0\0", 12); + c = &cpuid_data.entries[cpuid_i++]; + c->function = KVM_CPUID_SIGNATURE | kvm_base; + c->eax = KVM_CPUID_FEATURES | kvm_base; + c->ebx = signature[0]; + c->ecx = signature[1]; + c->edx = signature[2]; + + c = &cpuid_data.entries[cpuid_i++]; + c->function = KVM_CPUID_FEATURES | kvm_base; + c->eax = env->features[FEAT_KVM]; + c->edx = env->features[FEAT_KVM_HINTS]; + } + + cpuid_i = kvm_x86_arch_cpuid(env, cpuid_data.entries, cpuid_i); cpuid_data.cpuid.nent = cpuid_i; if (((env->cpuid_version >> 8)&0xF) >= 6 diff --git a/target/i386/kvm/kvm_i386.h b/target/i386/kvm/kvm_i386.h index dc72508389..c9a92578b1 100644 --- a/target/i386/kvm/kvm_i386.h +++ b/target/i386/kvm/kvm_i386.h @@ -24,6 +24,10 @@ #define kvm_ioapic_in_kernel() \ (kvm_irqchip_in_kernel() && !kvm_irqchip_is_split()) +#define KVM_MAX_CPUID_ENTRIES 100 +uint32_t kvm_x86_arch_cpuid(CPUX86State *env, struct kvm_cpuid_entry2 *entries, + uint32_t cpuid_i); + #else #define kvm_pit_in_kernel() 0 From patchwork Thu Jul 8 00:54:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502076 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyyK5NSfz9sWS for ; Thu, 8 Jul 2021 11:15:05 +1000 (AEST) Received: from localhost ([::1]:41488 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1Id5-00012i-CO for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:15:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38048) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKp-0001zG-9r for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:11 -0400 Received: from mga03.intel.com ([134.134.136.65]:19084) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKm-0007Kl-7z for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:10 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="209461995" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="209461995" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:53 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423769995" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:52 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 04/44] vl: Introduce machine_init_done_late notifier Date: Wed, 7 Jul 2021 17:54:34 -0700 Message-Id: <80ac3e382a248bac13662d4052d17c41f1c21e3a.1625704980.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.65; envelope-from=isaku.yamahata@intel.com; helo=mga03.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Introduce a new notifier, machine_init_done_late, that is notified after machine_init_done. This will be used by TDX to generate the HOB for its virtual firmware, which needs to be done after all guest memory has been added, i.e. after machine_init_done notifiers have run. Some code registers memory by machine_init_done(). Signed-off-by: Isaku Yamahata --- hw/core/machine.c | 26 ++++++++++++++++++++++++++ include/sysemu/sysemu.h | 2 ++ 2 files changed, 28 insertions(+) diff --git a/hw/core/machine.c b/hw/core/machine.c index ffc076ae84..66c39cf72a 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1278,6 +1278,31 @@ void qemu_remove_machine_init_done_notifier(Notifier *notify) notifier_remove(notify); } +static NotifierList machine_init_done_late_notifiers = + NOTIFIER_LIST_INITIALIZER(machine_init_done_late_notifiers); + +static bool machine_init_done_late; + +void qemu_add_machine_init_done_late_notifier(Notifier *notify) +{ + notifier_list_add(&machine_init_done_late_notifiers, notify); + if (machine_init_done_late) { + notify->notify(notify, NULL); + } +} + +void qemu_remove_machine_init_done_late_notifier(Notifier *notify) +{ + notifier_remove(notify); +} + + +static void qemu_run_machine_init_done_late_notifiers(void) +{ + machine_init_done_late = true; + notifier_list_notify(&machine_init_done_late_notifiers, NULL); +} + void qdev_machine_creation_done(void) { cpu_synchronize_all_post_init(); @@ -1311,6 +1336,7 @@ void qdev_machine_creation_done(void) if (rom_check_and_register_reset() != 0) { exit(1); } + qemu_run_machine_init_done_late_notifiers(); replay_start(); diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h index 8fae667172..d44f8cf778 100644 --- a/include/sysemu/sysemu.h +++ b/include/sysemu/sysemu.h @@ -19,6 +19,8 @@ void qemu_remove_exit_notifier(Notifier *notify); void qemu_run_machine_init_done_notifiers(void); void qemu_add_machine_init_done_notifier(Notifier *notify); void qemu_remove_machine_init_done_notifier(Notifier *notify); +void qemu_add_machine_init_done_late_notifier(Notifier *notify); +void qemu_remove_machine_init_done_late_notifier(Notifier *notify); void configure_rtc(QemuOpts *opts); From patchwork Thu Jul 8 00:54:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502055 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyjz3RNbz9sW8 for ; Thu, 8 Jul 2021 11:04:23 +1000 (AEST) Received: from localhost ([::1]:58444 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1ISj-0008MJ-6c for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:04:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38088) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKq-00024A-HI for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:12 -0400 Received: from mga03.intel.com ([134.134.136.65]:19093) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKm-0007Lp-MA for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:12 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="209461996" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="209461996" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:53 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423769999" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:53 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 05/44] linux-headers: Update headers to pull in TDX API changes Date: Wed, 7 Jul 2021 17:54:35 -0700 Message-Id: <6aee1a3a4d57cf4856fc0733eb01ba8176706773.1625704980.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.65; envelope-from=isaku.yamahata@intel.com; helo=mga03.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Xiaoyao Li Pull in recent TDX updates, which are not backwards compatible. Signed-off-by: Xiaoyao Li Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- linux-headers/asm-x86/kvm.h | 60 +++++++++++++++++++++++++++++++++++++ linux-headers/linux/kvm.h | 2 ++ 2 files changed, 62 insertions(+) diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h index 0662f644aa..dbcb590fb8 100644 --- a/linux-headers/asm-x86/kvm.h +++ b/linux-headers/asm-x86/kvm.h @@ -490,4 +490,64 @@ struct kvm_pmu_event_filter { #define KVM_PMU_EVENT_ALLOW 0 #define KVM_PMU_EVENT_DENY 1 +#define KVM_X86_LEGACY_VM 0 +#define KVM_X86_SW_PROTECTED_VM 1 +#define KVM_X86_TDX_VM 2 + +/* Trust Domain eXtension command*/ +enum kvm_tdx_cmd_id { + KVM_TDX_CAPABILITIES = 0, + KVM_TDX_INIT_VM, + KVM_TDX_INIT_VCPU, + KVM_TDX_INIT_MEM_REGION, + KVM_TDX_FINALIZE_VM, + + KVM_TDX_CMD_NR_MAX, +}; + +struct kvm_tdx_cmd { + __u32 id; + __u32 metadata; + __u64 data; +}; + +struct kvm_tdx_cpuid_config { + __u32 leaf; + __u32 sub_leaf; + __u32 eax; + __u32 ebx; + __u32 ecx; + __u32 edx; +}; + +struct kvm_tdx_capabilities { + __u64 attrs_fixed0; + __u64 attrs_fixed1; + __u64 xfam_fixed0; + __u64 xfam_fixed1; + + __u32 nr_cpuid_configs; + __u32 padding; + struct kvm_tdx_cpuid_config cpuid_configs[0]; +}; + +struct kvm_tdx_init_vm { + __u32 max_vcpus; + __u32 tsc_khz; + __u64 attributes; + __u64 cpuid; + __u64 mrconfigid[6]; /* sha384 digest */ + __u64 mrowner[6]; /* sha384 digest */ + __u64 mrownerconfig[6]; /* sha348 digest */ + __u64 reserved[43]; /* must be zero for future extensibility */ +}; + +#define KVM_TDX_MEASURE_MEMORY_REGION (1UL << 0) + +struct kvm_tdx_init_mem_region { + __u64 source_addr; + __u64 gpa; + __u64 nr_pages; +}; + #endif /* _ASM_X86_KVM_H */ diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 20d6a263bb..65ac70d6fd 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1084,6 +1084,8 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_VM_COPY_ENC_CONTEXT_FROM 197 #define KVM_CAP_PTP_KVM 198 +#define KVM_CAP_VM_TYPES 1000 + #ifdef KVM_CAP_IRQ_ROUTING struct kvm_irq_routing_irqchip { From patchwork Thu Jul 8 00:54:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502051 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKygL0bqtz9sWS for ; Thu, 8 Jul 2021 11:02:06 +1000 (AEST) Received: from localhost ([::1]:49792 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IQV-0002WD-At for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:02:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38054) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKp-0001zN-Cg for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:11 -0400 Received: from mga03.intel.com ([134.134.136.65]:19099) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKm-0007Mo-QX for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:11 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="209461998" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="209461998" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:54 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770006" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:53 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 06/44] hw/i386: Introduce kvm-type for TDX guest Date: Wed, 7 Jul 2021 17:54:36 -0700 Message-Id: <04c08d0770736cfa2e3148489602bc42492c78f3.1625704980.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.65; envelope-from=isaku.yamahata@intel.com; helo=mga03.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Xiaoyao Li Introduce a machine property, kvm-type, to allow the user to create a Trusted Domain eXtensions (TDX) VM, a.k.a. a Trusted Domain (TD), e.g.: # $QEMU \ -machine ...,kvm-type=tdx \ ... Only two types are supported: "legacy" and "tdx", with "legacy" being the default. Signed-off-by: Xiaoyao Li Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- default-configs/devices/i386-softmmu.mak | 1 + hw/i386/Kconfig | 5 +++ hw/i386/x86.c | 44 ++++++++++++++++++++++++ include/hw/i386/x86.h | 1 + include/sysemu/tdx.h | 10 ++++++ target/i386/kvm/kvm-stub.c | 5 +++ target/i386/kvm/kvm.c | 16 +++++++++ target/i386/kvm/kvm_i386.h | 1 + target/i386/kvm/meson.build | 1 + target/i386/kvm/tdx-stub.c | 10 ++++++ target/i386/kvm/tdx.c | 30 ++++++++++++++++ 11 files changed, 124 insertions(+) create mode 100644 include/sysemu/tdx.h create mode 100644 target/i386/kvm/tdx-stub.c create mode 100644 target/i386/kvm/tdx.c diff --git a/default-configs/devices/i386-softmmu.mak b/default-configs/devices/i386-softmmu.mak index 84d1a2487c..6e805407b8 100644 --- a/default-configs/devices/i386-softmmu.mak +++ b/default-configs/devices/i386-softmmu.mak @@ -18,6 +18,7 @@ #CONFIG_QXL=n #CONFIG_SEV=n #CONFIG_SGA=n +#CONFIG_TDX=n #CONFIG_TEST_DEVICES=n #CONFIG_TPM_CRB=n #CONFIG_TPM_TIS_ISA=n diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index aacb6f6d96..01633123e0 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -2,6 +2,10 @@ config SEV bool depends on KVM +config TDX + bool + depends on KVM + config PC bool imply APPLESMC @@ -17,6 +21,7 @@ config PC imply PVPANIC_ISA imply QXL imply SEV + imply TDX imply SGA imply TEST_DEVICES imply TPM_CRB diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 00448ed55a..ed15f6f2cf 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -21,6 +21,7 @@ * THE SOFTWARE. */ #include "qemu/osdep.h" +#include #include "qemu/error-report.h" #include "qemu/option.h" #include "qemu/cutils.h" @@ -31,6 +32,7 @@ #include "qapi/qmp/qerror.h" #include "qapi/qapi-visit-common.h" #include "qapi/visitor.h" +#include "sysemu/kvm_int.h" #include "sysemu/qtest.h" #include "sysemu/whpx.h" #include "sysemu/numa.h" @@ -1263,6 +1265,42 @@ static void x86_machine_set_bus_lock_ratelimit(Object *obj, Visitor *v, visit_type_uint64(v, name, &x86ms->bus_lock_ratelimit, errp); } +static char *x86_get_kvm_type(Object *obj, Error **errp) +{ + X86MachineState *x86ms = X86_MACHINE(obj); + + return g_strdup(x86ms->kvm_type); +} + +static void x86_set_kvm_type(Object *obj, const char *value, Error **errp) +{ + X86MachineState *x86ms = X86_MACHINE(obj); + + g_free(x86ms->kvm_type); + x86ms->kvm_type = g_strdup(value); +} + +static int x86_kvm_type(MachineState *ms, const char *vm_type) +{ + int kvm_type; + + if (!vm_type || !strcmp(vm_type, "") || + !g_ascii_strcasecmp(vm_type, "legacy")) { + kvm_type = KVM_X86_LEGACY_VM; + } else if (!g_ascii_strcasecmp(vm_type, "tdx")) { + kvm_type = KVM_X86_TDX_VM; + } else { + error_report("Unknown kvm-type specified '%s'", vm_type); + exit(1); + } + if (kvm_set_vm_type(ms, kvm_type)) { + error_report("kvm-type '%s' not supported by KVM", vm_type); + exit(1); + } + + return kvm_type; +} + static void x86_machine_initfn(Object *obj) { X86MachineState *x86ms = X86_MACHINE(obj); @@ -1273,6 +1311,11 @@ static void x86_machine_initfn(Object *obj) x86ms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); x86ms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); x86ms->bus_lock_ratelimit = 0; + + object_property_add_str(obj, "kvm-type", + x86_get_kvm_type, x86_set_kvm_type); + object_property_set_description(obj, "kvm-type", + "KVM guest type (legacy, tdx)"); } static void x86_machine_class_init(ObjectClass *oc, void *data) @@ -1284,6 +1327,7 @@ static void x86_machine_class_init(ObjectClass *oc, void *data) mc->cpu_index_to_instance_props = x86_cpu_index_to_props; mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; + mc->kvm_type = x86_kvm_type; x86mc->compat_apic_id_mode = false; x86mc->save_tsc_khz = true; nc->nmi_monitor_handler = x86_nmi; diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index 6e9244a82c..a450b5e226 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -56,6 +56,7 @@ struct X86MachineState { /* RAM information (sizes, addresses, configuration): */ ram_addr_t below_4g_mem_size, above_4g_mem_size; + char *kvm_type; /* CPU and apic information: */ bool apic_xrupt_override; diff --git a/include/sysemu/tdx.h b/include/sysemu/tdx.h new file mode 100644 index 0000000000..60ebded851 --- /dev/null +++ b/include/sysemu/tdx.h @@ -0,0 +1,10 @@ +#ifndef QEMU_TDX_H +#define QEMU_TDX_H + +#ifndef CONFIG_USER_ONLY +#include "sysemu/kvm.h" + +bool kvm_has_tdx(KVMState *s); +#endif + +#endif diff --git a/target/i386/kvm/kvm-stub.c b/target/i386/kvm/kvm-stub.c index 92f49121b8..e9221de76f 100644 --- a/target/i386/kvm/kvm-stub.c +++ b/target/i386/kvm/kvm-stub.c @@ -39,3 +39,8 @@ bool kvm_hv_vpindex_settable(void) { return false; } + +int kvm_set_vm_type(MachineState *ms, int kvm_type) +{ + return 0; +} diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 0558e4b506..a3d5b334d1 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -27,6 +27,7 @@ #include "sysemu/hw_accel.h" #include "sysemu/kvm_int.h" #include "sysemu/runstate.h" +#include "sysemu/tdx.h" #include "kvm_i386.h" #include "sev_i386.h" #include "hyperv.h" @@ -132,9 +133,24 @@ static struct kvm_cpuid2 *cpuid_cache; static struct kvm_cpuid2 *hv_cpuid_cache; static struct kvm_msr_list *kvm_feature_msrs; + #define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */ static RateLimit bus_lock_ratelimit_ctrl; +static int vm_type; + +int kvm_set_vm_type(MachineState *ms, int kvm_type) +{ + if (kvm_type == KVM_X86_LEGACY_VM || + (kvm_type == KVM_X86_TDX_VM && + kvm_has_tdx(KVM_STATE(ms->accelerator)))) { + vm_type = kvm_type; + return 0; + } + + return -ENOTSUP; +} + int kvm_has_pit_state2(void) { return has_pit_state2; diff --git a/target/i386/kvm/kvm_i386.h b/target/i386/kvm/kvm_i386.h index c9a92578b1..8e63365162 100644 --- a/target/i386/kvm/kvm_i386.h +++ b/target/i386/kvm/kvm_i386.h @@ -41,6 +41,7 @@ bool kvm_has_adjust_clock(void); bool kvm_has_adjust_clock_stable(void); bool kvm_has_exception_payload(void); void kvm_synchronize_all_tsc(void); +int kvm_set_vm_type(MachineState *ms, int kvm_type); void kvm_arch_reset_vcpu(X86CPU *cs); void kvm_arch_do_init_vcpu(X86CPU *cs); diff --git a/target/i386/kvm/meson.build b/target/i386/kvm/meson.build index 0a533411ca..3c143a3c93 100644 --- a/target/i386/kvm/meson.build +++ b/target/i386/kvm/meson.build @@ -6,3 +6,4 @@ i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files( )) i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_false: files('hyperv-stub.c')) +i386_ss.add(when: 'CONFIG_TDX', if_true: files('tdx.c'), if_false: files('tdx-stub.c')) diff --git a/target/i386/kvm/tdx-stub.c b/target/i386/kvm/tdx-stub.c new file mode 100644 index 0000000000..e1eb09cae1 --- /dev/null +++ b/target/i386/kvm/tdx-stub.c @@ -0,0 +1,10 @@ +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "sysemu/tdx.h" + +#ifndef CONFIG_USER_ONLY +bool kvm_has_tdx(KVMState *s) +{ + return false; +} +#endif diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c new file mode 100644 index 0000000000..e62a570f75 --- /dev/null +++ b/target/i386/kvm/tdx.c @@ -0,0 +1,30 @@ +/* + * QEMU TDX support + * + * Copyright Intel + * + * Author: + * Xiaoyao Li + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory + * + */ + +#include "qemu/osdep.h" + +#include + +#include "cpu.h" +#include "hw/boards.h" +#include "qapi/error.h" +#include "qom/object_interfaces.h" +#include "sysemu/sysemu.h" +#include "sysemu/kvm.h" +#include "sysemu/kvm_int.h" +#include "sysemu/tdx.h" + +bool kvm_has_tdx(KVMState *s) +{ + return !!(kvm_check_extension(s, KVM_CAP_VM_TYPES) & BIT(KVM_X86_TDX_VM)); +} From patchwork Thu Jul 8 00:54:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502067 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyt21hhKz9sXM for ; Thu, 8 Jul 2021 11:11:22 +1000 (AEST) Received: from localhost ([::1]:52534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IZT-0006MB-W1 for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:11:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38166) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKt-0002B3-0X for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:17 -0400 Received: from mga03.intel.com ([134.134.136.65]:19099) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKq-0007Mo-II for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:14 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="209461999" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="209461999" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:54 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770010" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:54 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 07/44] i386/kvm: Squash getting/putting guest state for TDX VMs Date: Wed, 7 Jul 2021 17:54:37 -0700 Message-Id: <7194a76cfb8541d4f7a5b6a04fb3496bc14eab15.1625704980.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.65; envelope-from=isaku.yamahata@intel.com; helo=mga03.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Sean Christopherson Ignore get/put state of TDX VMs as accessing/mutating guest state of producation TDs is not supported. Allow kvm_arch_get_registers() to run as normal, except for MSRs, for debug TDs, and silently ignores attempts to read guest state for non-debug TDs. Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- target/i386/kvm/kvm.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index a3d5b334d1..27b64dedc2 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2641,6 +2641,11 @@ void kvm_put_apicbase(X86CPU *cpu, uint64_t value) { int ret; + /* TODO: Allow accessing guest state for debug TDs. */ + if (vm_type == KVM_X86_TDX_VM) { + return; + } + ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value); assert(ret == 1); } @@ -4099,6 +4104,11 @@ int kvm_arch_put_registers(CPUState *cpu, int level) assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); + /* TODO: Allow accessing guest state for debug TDs. */ + if (vm_type == KVM_X86_TDX_VM) { + return 0; + } + /* must be before kvm_put_nested_state so that EFER.SVME is set */ ret = kvm_put_sregs(x86_cpu); if (ret < 0) { @@ -4209,9 +4219,11 @@ int kvm_arch_get_registers(CPUState *cs) if (ret < 0) { goto out; } - ret = kvm_get_msrs(cpu); - if (ret < 0) { - goto out; + if (vm_type != KVM_X86_TDX_VM) { + ret = kvm_get_msrs(cpu); + if (ret < 0) { + goto out; + } } ret = kvm_get_apic(cpu); if (ret < 0) { From patchwork Thu Jul 8 00:54:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502084 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKz3z40xpz9sWS for ; Thu, 8 Jul 2021 11:19:59 +1000 (AEST) Received: from localhost ([::1]:58606 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1Ihp-0003zB-A0 for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:19:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38148) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKs-0002B1-84 for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:17 -0400 Received: from mga03.intel.com ([134.134.136.65]:19084) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKq-0007Kl-HI for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:14 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="209462000" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="209462000" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:54 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770015" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:54 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 08/44] i386/kvm: Skip KVM_X86_SETUP_MCE for TDX guests Date: Wed, 7 Jul 2021 17:54:38 -0700 Message-Id: <50d3b2d8d652fccc49a6235aea77857713874bd9.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.65; envelope-from=isaku.yamahata@intel.com; helo=mga03.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Despite advertising MCE support to the guest, TDX-SEAM doesn't support injecting #MCs into the guest. All of the associated setup is thus rejected by KVM. Signed-off-by: Isaku Yamahata --- target/i386/kvm/kvm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 27b64dedc2..c29cb420a1 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1825,7 +1825,8 @@ int kvm_arch_init_vcpu(CPUState *cs) if (((env->cpuid_version >> 8)&0xF) >= 6 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == (CPUID_MCE | CPUID_MCA) - && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) { + && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0 + && vm_type != KVM_X86_TDX_VM) { uint64_t mcg_cap, unsupported_caps; int banks; int ret; From patchwork Thu Jul 8 00:54:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502046 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyYq5W3Dz9sW8 for ; Thu, 8 Jul 2021 10:57:19 +1000 (AEST) Received: from localhost ([::1]:37972 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1ILt-0001rM-Fm for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 20:57:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37924) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKk-0001mR-8s for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:06 -0400 Received: from mga06.intel.com ([134.134.136.31]:36375) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKe-0007Kq-2D for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:02 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534892" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534892" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:54 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770018" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:54 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 09/44] target/i386: kvm: don't synchronize guest tsc for TD guest Date: Wed, 7 Jul 2021 17:54:39 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Make kvm_synchronize_all_tsc() nop for TD-guest. TDX module specification, 9.11.1 TSC Virtualization "Virtual TSC values are consistent among all the TD;s VCPUs at the level suppored by the CPU". There is no need for qemu to synchronize tsc and VMM can't access to guest TSC. Actually do_kvm_synchronize_tsc() hits assert due to failure to write to guest tsc. > qemu/target/i386/kvm.c:235: kvm_get_tsc: Assertion `ret == 1' failed. Signed-off-by: Isaku Yamahata Reviewed-by: Connor Kuehl --- target/i386/kvm/kvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index c29cb420a1..ecb1714920 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -254,7 +254,7 @@ void kvm_synchronize_all_tsc(void) { CPUState *cpu; - if (kvm_enabled()) { + if (kvm_enabled() && vm_type != KVM_X86_TDX_VM) { CPU_FOREACH(cpu) { run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL); } From patchwork Thu Jul 8 00:54:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502052 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyj05yg8z9sW8 for ; Thu, 8 Jul 2021 11:03:32 +1000 (AEST) Received: from localhost ([::1]:55058 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IRu-000691-Ik for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:03:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37922) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKk-0001mQ-94 for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:06 -0400 Received: from mga06.intel.com ([134.134.136.31]:36379) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKd-0007L4-FI for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:02 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534893" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534893" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:55 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770021" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:54 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 10/44] hw/i386: Initialize TDX via KVM ioctl() when kvm_type is TDX Date: Wed, 7 Jul 2021 17:54:40 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Xiaoyao Li Introduce tdx_ioctl() to invoke TDX specific sub-ioctls of KVM_MEMORY_ENCRYPT_OP. Use tdx_ioctl() to invoke KVM_TDX_INIT, by way of tdx_init(), during kvm_arch_init(). KVM_TDX_INIT configures global TD state, e.g. the canonical CPUID config, and must be executed prior to creating vCPUs. Note, this doesn't address the fact that Qemu may change the CPUID configuration when creating vCPUs, i.e. punts on refactoring Qemu to provide a stable CPUID config prior to kvm_arch_init(). Explicitly set subleaf index and flags when adding CPUID Set the index and flags when adding a CPUID entry to avoid propagating stale state from a removed entry, e.g. when the CPUID 0x4 loop bails, it can leave non-zero index and flags in the array. Signed-off-by: Xiaoyao Li Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- accel/kvm/kvm-all.c | 2 + include/sysemu/tdx.h | 2 + qapi/qom.json | 14 +++++ target/i386/kvm/tdx-stub.c | 4 ++ target/i386/kvm/tdx.c | 126 +++++++++++++++++++++++++++++++++++++ target/i386/kvm/tdx.h | 24 +++++++ 6 files changed, 172 insertions(+) create mode 100644 target/i386/kvm/tdx.h diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index fdbe24bf59..6475f15d5f 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -38,6 +38,7 @@ #include "qemu/main-loop.h" #include "trace.h" #include "hw/irq.h" +#include "sysemu/tdx.h" #include "qapi/visitor.h" #include "qapi/qapi-types-common.h" #include "qapi/qapi-visit-common.h" @@ -459,6 +460,7 @@ int kvm_init_vcpu(CPUState *cpu, Error **errp) trace_kvm_init_vcpu(cpu->cpu_index, kvm_arch_vcpu_id(cpu)); + tdx_pre_create_vcpu(cpu); ret = kvm_get_vcpu(s, kvm_arch_vcpu_id(cpu)); if (ret < 0) { error_setg_errno(errp, -ret, "kvm_init_vcpu: kvm_get_vcpu failed (%lu)", diff --git a/include/sysemu/tdx.h b/include/sysemu/tdx.h index 60ebded851..36a901e723 100644 --- a/include/sysemu/tdx.h +++ b/include/sysemu/tdx.h @@ -7,4 +7,6 @@ bool kvm_has_tdx(KVMState *s); #endif +void tdx_pre_create_vcpu(CPUState *cpu); + #endif diff --git a/qapi/qom.json b/qapi/qom.json index 652be317b8..70c70e3efe 100644 --- a/qapi/qom.json +++ b/qapi/qom.json @@ -760,6 +760,18 @@ '*cbitpos': 'uint32', 'reduced-phys-bits': 'uint32' } } +## +# @TdxGuestProperties: +# +# Properties for tdx-guest objects. +# +# @debug: enable debug mode (default: off) +# +# Since: 6.0 +## +{ 'struct': 'TdxGuestProperties', + 'data': { '*debug': 'bool' } } + ## # @ObjectType: # @@ -802,6 +814,7 @@ 'secret_keyring', 'sev-guest', 's390-pv-guest', + 'tdx-guest', 'throttle-group', 'tls-creds-anon', 'tls-creds-psk', @@ -858,6 +871,7 @@ 'secret': 'SecretProperties', 'secret_keyring': 'SecretKeyringProperties', 'sev-guest': 'SevGuestProperties', + 'tdx-guest': 'TdxGuestProperties', 'throttle-group': 'ThrottleGroupProperties', 'tls-creds-anon': 'TlsCredsAnonProperties', 'tls-creds-psk': 'TlsCredsPskProperties', diff --git a/target/i386/kvm/tdx-stub.c b/target/i386/kvm/tdx-stub.c index e1eb09cae1..93d5913c89 100644 --- a/target/i386/kvm/tdx-stub.c +++ b/target/i386/kvm/tdx-stub.c @@ -8,3 +8,7 @@ bool kvm_has_tdx(KVMState *s) return false; } #endif + +void tdx_pre_create_vcpu(CPUState *cpu) +{ +} diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index e62a570f75..e8c70f241d 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -14,8 +14,10 @@ #include "qemu/osdep.h" #include +#include #include "cpu.h" +#include "kvm_i386.h" #include "hw/boards.h" #include "qapi/error.h" #include "qom/object_interfaces.h" @@ -23,8 +25,132 @@ #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" #include "sysemu/tdx.h" +#include "tdx.h" + +#define TDX1_TD_ATTRIBUTE_DEBUG BIT_ULL(0) +#define TDX1_TD_ATTRIBUTE_PERFMON BIT_ULL(63) bool kvm_has_tdx(KVMState *s) { return !!(kvm_check_extension(s, KVM_CAP_VM_TYPES) & BIT(KVM_X86_TDX_VM)); } + +static void __tdx_ioctl(int ioctl_no, const char *ioctl_name, + __u32 metadata, void *data) +{ + struct kvm_tdx_cmd tdx_cmd; + int r; + + memset(&tdx_cmd, 0x0, sizeof(tdx_cmd)); + + tdx_cmd.id = ioctl_no; + tdx_cmd.metadata = metadata; + tdx_cmd.data = (__u64)(unsigned long)data; + + r = kvm_vm_ioctl(kvm_state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd); + if (r) { + error_report("%s failed: %s", ioctl_name, strerror(-r)); + exit(1); + } +} +#define tdx_ioctl(ioctl_no, metadata, data) \ + __tdx_ioctl(ioctl_no, stringify(ioctl_no), metadata, data) + +void tdx_pre_create_vcpu(CPUState *cpu) +{ + struct { + struct kvm_cpuid2 cpuid; + struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES]; + } cpuid_data; + + /* + * The kernel defines these structs with padding fields so there + * should be no extra padding in our cpuid_data struct. + */ + QEMU_BUILD_BUG_ON(sizeof(cpuid_data) != + sizeof(struct kvm_cpuid2) + + sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES); + + MachineState *ms = MACHINE(qdev_get_machine()); + X86CPU *x86cpu = X86_CPU(cpu); + CPUX86State *env = &x86cpu->env; + TdxGuest *tdx = (TdxGuest *)object_dynamic_cast(OBJECT(ms->cgs), + TYPE_TDX_GUEST); + struct kvm_tdx_init_vm init_vm; + + if (!tdx) { + return; + } + + /* HACK: Remove MPX support, which is not allowed by TDX. */ + env->features[FEAT_XSAVE_COMP_LO] &= ~(XSTATE_BNDREGS_MASK | + XSTATE_BNDCSR_MASK); + + if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { + error_report("TDX VM must support XSAVE features"); + exit(1); + } + + qemu_mutex_lock(&tdx->lock); + if (tdx->initialized) { + goto out; + } + tdx->initialized = true; + + memset(&cpuid_data, 0, sizeof(cpuid_data)); + + cpuid_data.cpuid.nent = kvm_x86_arch_cpuid(env, cpuid_data.entries, 0); + cpuid_data.cpuid.padding = 0; + + init_vm.max_vcpus = ms->smp.cpus; + init_vm.attributes = 0; + init_vm.attributes |= tdx->debug ? TDX1_TD_ATTRIBUTE_DEBUG : 0; + init_vm.attributes |= x86cpu->enable_pmu ? TDX1_TD_ATTRIBUTE_PERFMON : 0; + + init_vm.cpuid = (__u64)(&cpuid_data); + tdx_ioctl(KVM_TDX_INIT_VM, 0, &init_vm); +out: + qemu_mutex_unlock(&tdx->lock); +} + +static bool tdx_guest_get_debug(Object *obj, Error **errp) +{ + TdxGuest *tdx = TDX_GUEST(obj); + + return tdx->debug; +} + +static void tdx_guest_set_debug(Object *obj, bool value, Error **errp) +{ + TdxGuest *tdx = TDX_GUEST(obj); + + tdx->debug = value; +} + +/* tdx guest */ +OBJECT_DEFINE_TYPE_WITH_INTERFACES(TdxGuest, + tdx_guest, + TDX_GUEST, + CONFIDENTIAL_GUEST_SUPPORT, + { TYPE_USER_CREATABLE }, + { NULL }) + +static void tdx_guest_init(Object *obj) +{ + TdxGuest *tdx = TDX_GUEST(obj); + + tdx->parent_obj.ready = true; + qemu_mutex_init(&tdx->lock); + + tdx->debug = false; + object_property_add_bool(obj, "debug", tdx_guest_get_debug, + tdx_guest_set_debug); +} + +static void tdx_guest_finalize(Object *obj) +{ +} + +static void tdx_guest_class_init(ObjectClass *oc, void *data) +{ +} diff --git a/target/i386/kvm/tdx.h b/target/i386/kvm/tdx.h new file mode 100644 index 0000000000..6ad6c9a313 --- /dev/null +++ b/target/i386/kvm/tdx.h @@ -0,0 +1,24 @@ +#ifndef QEMU_I386_TDX_H +#define QEMU_I386_TDX_H + +#include "qom/object.h" +#include "exec/confidential-guest-support.h" + +#define TYPE_TDX_GUEST "tdx-guest" +#define TDX_GUEST(obj) \ + OBJECT_CHECK(TdxGuest, (obj), TYPE_TDX_GUEST) + +typedef struct TdxGuestClass { + ConfidentialGuestSupportClass parent_class; +} TdxGuestClass; + +typedef struct TdxGuest { + ConfidentialGuestSupport parent_obj; + + QemuMutex lock; + + bool initialized; + bool debug; +} TdxGuest; + +#endif From patchwork Thu Jul 8 00:54:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502053 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyj116s0z9sWS for ; Thu, 8 Jul 2021 11:03:33 +1000 (AEST) Received: from localhost ([::1]:55056 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IRu-000690-U1 for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:03:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38042) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKp-0001zD-82 for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:11 -0400 Received: from mga06.intel.com ([134.134.136.31]:36375) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKk-0007Kq-OC for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:09 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534894" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534894" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:55 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770024" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:54 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 11/44] i386/tdx: Implement user specified tsc frequency Date: Wed, 7 Jul 2021 17:54:41 -0700 Message-Id: <564e6ae089c30aaba9443294ecca72da9ee7b7c4.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Xiaoyao Li Reuse -cpu,tsc-frequency= to get user wanted tsc frequency and pass it to KVM_TDX_INIT_VM. Besides, sanity check the tsc frequency to be in the legal range and legal granularity (required by SEAM module). Signed-off-by: Xiaoyao Li Signed-off-by: Isaku Yamahata --- target/i386/kvm/kvm.c | 8 ++++++++ target/i386/kvm/tdx.c | 16 ++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index ecb1714920..be0b96b120 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -763,6 +763,14 @@ static int kvm_arch_set_tsc_khz(CPUState *cs) int r, cur_freq; bool set_ioctl = false; + /* + * TD guest's TSC is immutable, it cannot be set/changed via + * KVM_SET_TSC_KHZ, but only be initialized via KVM_TDX_INIT_VM + */ + if (vm_type == KVM_X86_TDX_VM) { + return 0; + } + if (!env->tsc_khz) { return 0; } diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index e8c70f241d..c50a0dcf11 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -29,6 +29,8 @@ #define TDX1_TD_ATTRIBUTE_DEBUG BIT_ULL(0) #define TDX1_TD_ATTRIBUTE_PERFMON BIT_ULL(63) +#define TDX1_MIN_TSC_FREQUENCY_KHZ (100 * 1000) +#define TDX1_MAX_TSC_FREQUENCY_KHZ (10 * 1000 * 1000) bool kvm_has_tdx(KVMState *s) { @@ -91,6 +93,19 @@ void tdx_pre_create_vcpu(CPUState *cpu) exit(1); } + if (env->tsc_khz && (env->tsc_khz < TDX1_MIN_TSC_FREQUENCY_KHZ || + env->tsc_khz > TDX1_MAX_TSC_FREQUENCY_KHZ)) { + error_report("Invalid TSC %ld KHz, must specify cpu_frequecy between [%d, %d] kHz\n", + env->tsc_khz, TDX1_MIN_TSC_FREQUENCY_KHZ, + TDX1_MAX_TSC_FREQUENCY_KHZ); + exit(1); + } + + if (env->tsc_khz % (25 * 1000)) { + error_report("Invalid TSC %ld KHz, it must be multiple of 25MHz\n", env->tsc_khz); + exit(1); + } + qemu_mutex_lock(&tdx->lock); if (tdx->initialized) { goto out; @@ -103,6 +118,7 @@ void tdx_pre_create_vcpu(CPUState *cpu) cpuid_data.cpuid.padding = 0; init_vm.max_vcpus = ms->smp.cpus; + init_vm.tsc_khz = env->tsc_khz; init_vm.attributes = 0; init_vm.attributes |= tdx->debug ? TDX1_TD_ATTRIBUTE_DEBUG : 0; init_vm.attributes |= x86cpu->enable_pmu ? TDX1_TD_ATTRIBUTE_PERFMON : 0; From patchwork Thu Jul 8 00:54:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502054 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyj16KVYz9sW8 for ; Thu, 8 Jul 2021 11:03:33 +1000 (AEST) Received: from localhost ([::1]:55186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IRv-0006E6-Jd for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:03:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKp-0001zE-8d for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:11 -0400 Received: from mga06.intel.com ([134.134.136.31]:36379) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKk-0007L4-OD for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:09 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534895" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534895" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:55 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770027" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:55 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 12/44] target/i386/tdx: Finalize the TD's measurement when machine is done Date: Wed, 7 Jul 2021 17:54:42 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Xiaoyao Li Invoke KVM_TDX_FINALIZEMR to finalize the TD's measurement and make the TD vCPUs runnable once machine initialization is complete. Signed-off-by: Xiaoyao Li Signed-off-by: Isaku Yamahata Reviewed-by: Connor Kuehl --- target/i386/kvm/kvm.c | 7 +++++++ target/i386/kvm/tdx.c | 21 +++++++++++++++++++++ target/i386/kvm/tdx.h | 3 +++ 3 files changed, 31 insertions(+) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index be0b96b120..5742fa4806 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -53,6 +53,7 @@ #include "migration/blocker.h" #include "exec/memattrs.h" #include "trace.h" +#include "tdx.h" //#define DEBUG_KVM @@ -2246,6 +2247,12 @@ int kvm_arch_init(MachineState *ms, KVMState *s) return ret; } + ret = tdx_kvm_init(ms->cgs, &local_err); + if (ret < 0) { + error_report_err(local_err); + return ret; + } + if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) { error_report("kvm: KVM_CAP_IRQ_ROUTING not supported by KVM"); return -ENOTSUP; diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index c50a0dcf11..f8c7560fc8 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -58,6 +58,27 @@ static void __tdx_ioctl(int ioctl_no, const char *ioctl_name, #define tdx_ioctl(ioctl_no, metadata, data) \ __tdx_ioctl(ioctl_no, stringify(ioctl_no), metadata, data) +static void tdx_finalize_vm(Notifier *notifier, void *unused) +{ + tdx_ioctl(KVM_TDX_FINALIZE_VM, 0, NULL); +} + +static Notifier tdx_machine_done_late_notify = { + .notify = tdx_finalize_vm, +}; + +int tdx_kvm_init(ConfidentialGuestSupport *cgs, Error **errp) +{ + TdxGuest *tdx = (TdxGuest *)object_dynamic_cast(OBJECT(cgs), + TYPE_TDX_GUEST); + if (!tdx) { + return 0; + } + + qemu_add_machine_init_done_late_notifier(&tdx_machine_done_late_notify); + return 0; +} + void tdx_pre_create_vcpu(CPUState *cpu) { struct { diff --git a/target/i386/kvm/tdx.h b/target/i386/kvm/tdx.h index 6ad6c9a313..e15657d272 100644 --- a/target/i386/kvm/tdx.h +++ b/target/i386/kvm/tdx.h @@ -2,6 +2,7 @@ #define QEMU_I386_TDX_H #include "qom/object.h" +#include "qapi/error.h" #include "exec/confidential-guest-support.h" #define TYPE_TDX_GUEST "tdx-guest" @@ -21,4 +22,6 @@ typedef struct TdxGuest { bool debug; } TdxGuest; +int tdx_kvm_init(ConfidentialGuestSupport *cgs, Error **errp); + #endif From patchwork Thu Jul 8 00:54:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502072 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKywL0Mpzz9sWS for ; Thu, 8 Jul 2021 11:13:22 +1000 (AEST) Received: from localhost ([::1]:33102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IbP-0003qt-Px for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:13:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38050) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKp-0001zH-9r for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:11 -0400 Received: from mga06.intel.com ([134.134.136.31]:36390) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKm-0007ML-3s for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:10 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534896" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534896" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:55 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770031" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:55 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 13/44] i386/tdx: Frame in tdx_get_supported_cpuid with KVM_TDX_CAPABILITIES Date: Wed, 7 Jul 2021 17:54:43 -0700 Message-Id: <64a6aff39a1f5d96fcddff8923bfba5728fcfa8c.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Sean Christopherson Add support for grabbing KVM_TDX_CAPABILITIES and use the new kvm_get_supported_cpuid() hook to adjust the supported XCR0 bits. Add TODOs for the remaining work. Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- target/i386/kvm/kvm.c | 2 ++ target/i386/kvm/tdx.c | 79 ++++++++++++++++++++++++++++++++++++++++--- target/i386/kvm/tdx.h | 2 ++ 3 files changed, 78 insertions(+), 5 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 5742fa4806..25dcecd60c 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -448,6 +448,8 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, ret |= 1U << KVM_HINTS_REALTIME; } + tdx_get_supported_cpuid(s, function, index, reg, &ret); + return ret; } diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index f8c7560fc8..b1e4f27c9a 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -21,6 +21,7 @@ #include "hw/boards.h" #include "qapi/error.h" #include "qom/object_interfaces.h" +#include "standard-headers/asm-x86/kvm_para.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" @@ -49,7 +50,11 @@ static void __tdx_ioctl(int ioctl_no, const char *ioctl_name, tdx_cmd.metadata = metadata; tdx_cmd.data = (__u64)(unsigned long)data; - r = kvm_vm_ioctl(kvm_state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd); + if (ioctl_no == KVM_TDX_CAPABILITIES) { + r = kvm_ioctl(kvm_state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd); + } else { + r = kvm_vm_ioctl(kvm_state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd); + } if (r) { error_report("%s failed: %s", ioctl_name, strerror(-r)); exit(1); @@ -67,6 +72,18 @@ static Notifier tdx_machine_done_late_notify = { .notify = tdx_finalize_vm, }; +#define TDX1_MAX_NR_CPUID_CONFIGS 6 + +static struct { + struct kvm_tdx_capabilities __caps; + struct kvm_tdx_cpuid_config __cpuid_configs[TDX1_MAX_NR_CPUID_CONFIGS]; +} __tdx_caps; + +static struct kvm_tdx_capabilities *tdx_caps = (void *)&__tdx_caps; + +#define XCR0_MASK (MAKE_64BIT_MASK(0, 8) | BIT_ULL(9)) +#define XSS_MASK (~XCR0_MASK) + int tdx_kvm_init(ConfidentialGuestSupport *cgs, Error **errp) { TdxGuest *tdx = (TdxGuest *)object_dynamic_cast(OBJECT(cgs), @@ -75,10 +92,65 @@ int tdx_kvm_init(ConfidentialGuestSupport *cgs, Error **errp) return 0; } + QEMU_BUILD_BUG_ON(sizeof(__tdx_caps) != + sizeof(struct kvm_tdx_capabilities) + + sizeof(struct kvm_tdx_cpuid_config) * + TDX1_MAX_NR_CPUID_CONFIGS); + + tdx_caps->nr_cpuid_configs = TDX1_MAX_NR_CPUID_CONFIGS; + tdx_ioctl(KVM_TDX_CAPABILITIES, 0, tdx_caps); + qemu_add_machine_init_done_late_notifier(&tdx_machine_done_late_notify); + return 0; } +void tdx_get_supported_cpuid(KVMState *s, uint32_t function, + uint32_t index, int reg, uint32_t *ret) +{ + MachineState *ms = MACHINE(qdev_get_machine()); + TdxGuest *tdx = (TdxGuest *)object_dynamic_cast(OBJECT(ms->cgs), + TYPE_TDX_GUEST); + + if (!tdx) { + return; + } + + switch (function) { + case 1: + if (reg == R_ECX) { + *ret &= ~CPUID_EXT_VMX; + } + break; + case 0xd: + if (index == 0) { + if (reg == R_EAX) { + *ret &= (uint32_t)tdx_caps->xfam_fixed0 & XCR0_MASK; + *ret |= (uint32_t)tdx_caps->xfam_fixed1 & XCR0_MASK; + } else if (reg == R_EDX) { + *ret &= (tdx_caps->xfam_fixed0 & XCR0_MASK) >> 32; + *ret |= (tdx_caps->xfam_fixed1 & XCR0_MASK) >> 32; + } + } else if (index == 1) { + /* TODO: Adjust XSS when it's supported. */ + } + break; + case KVM_CPUID_FEATURES: + if (reg == R_EAX) { + *ret &= ~((1ULL << KVM_FEATURE_CLOCKSOURCE) | + (1ULL << KVM_FEATURE_CLOCKSOURCE2) | + (1ULL << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | + (1ULL << KVM_FEATURE_ASYNC_PF) | + (1ULL << KVM_FEATURE_ASYNC_PF_VMEXIT) | + (1ULL << KVM_FEATURE_ASYNC_PF_INT)); + } + break; + default: + /* TODO: Use tdx_caps to adjust CPUID leafs. */ + break; + } +} + void tdx_pre_create_vcpu(CPUState *cpu) { struct { @@ -105,10 +177,7 @@ void tdx_pre_create_vcpu(CPUState *cpu) return; } - /* HACK: Remove MPX support, which is not allowed by TDX. */ - env->features[FEAT_XSAVE_COMP_LO] &= ~(XSTATE_BNDREGS_MASK | - XSTATE_BNDCSR_MASK); - + /* TODO: Use tdx_caps to validate the config. */ if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { error_report("TDX VM must support XSAVE features"); exit(1); diff --git a/target/i386/kvm/tdx.h b/target/i386/kvm/tdx.h index e15657d272..844d24aade 100644 --- a/target/i386/kvm/tdx.h +++ b/target/i386/kvm/tdx.h @@ -23,5 +23,7 @@ typedef struct TdxGuest { } TdxGuest; int tdx_kvm_init(ConfidentialGuestSupport *cgs, Error **errp); +void tdx_get_supported_cpuid(KVMState *s, uint32_t function, + uint32_t index, int reg, uint32_t *ret); #endif From patchwork Thu Jul 8 00:54:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502080 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKz193gHgz9sWS for ; Thu, 8 Jul 2021 11:17:33 +1000 (AEST) Received: from localhost ([::1]:50002 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IfT-0006lc-83 for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:17:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38132) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKr-0002AS-Sg for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:17 -0400 Received: from mga06.intel.com ([134.134.136.31]:36375) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKp-0007Kq-MU for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:13 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534897" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534897" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:55 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770034" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:55 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 14/44] i386/tdx: Frame in the call for KVM_TDX_INIT_VCPU Date: Wed, 7 Jul 2021 17:54:44 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- include/sysemu/tdx.h | 1 + target/i386/kvm/kvm.c | 8 ++++++++ target/i386/kvm/tdx-stub.c | 4 ++++ target/i386/kvm/tdx.c | 20 ++++++++++++++++---- 4 files changed, 29 insertions(+), 4 deletions(-) diff --git a/include/sysemu/tdx.h b/include/sysemu/tdx.h index 36a901e723..03461b6ae8 100644 --- a/include/sysemu/tdx.h +++ b/include/sysemu/tdx.h @@ -8,5 +8,6 @@ bool kvm_has_tdx(KVMState *s); #endif void tdx_pre_create_vcpu(CPUState *cpu); +void tdx_post_init_vcpu(CPUState *cpu); #endif diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 25dcecd60c..af6b5f350e 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4122,6 +4122,14 @@ int kvm_arch_put_registers(CPUState *cpu, int level) assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); + /* + * level == KVM_PUT_FULL_STATE is only set by + * kvm_cpu_synchronize_post_init() after initialization + */ + if (vm_type == KVM_X86_TDX_VM && level == KVM_PUT_FULL_STATE) { + tdx_post_init_vcpu(cpu); + } + /* TODO: Allow accessing guest state for debug TDs. */ if (vm_type == KVM_X86_TDX_VM) { return 0; diff --git a/target/i386/kvm/tdx-stub.c b/target/i386/kvm/tdx-stub.c index 93d5913c89..93afe07ddb 100644 --- a/target/i386/kvm/tdx-stub.c +++ b/target/i386/kvm/tdx-stub.c @@ -12,3 +12,7 @@ bool kvm_has_tdx(KVMState *s) void tdx_pre_create_vcpu(CPUState *cpu) { } + +void tdx_post_init_vcpu(CPUState *cpu) +{ +} diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index b1e4f27c9a..67fb03b4b5 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -38,7 +38,7 @@ bool kvm_has_tdx(KVMState *s) return !!(kvm_check_extension(s, KVM_CAP_VM_TYPES) & BIT(KVM_X86_TDX_VM)); } -static void __tdx_ioctl(int ioctl_no, const char *ioctl_name, +static void __tdx_ioctl(void *state, int ioctl_no, const char *ioctl_name, __u32 metadata, void *data) { struct kvm_tdx_cmd tdx_cmd; @@ -51,17 +51,21 @@ static void __tdx_ioctl(int ioctl_no, const char *ioctl_name, tdx_cmd.data = (__u64)(unsigned long)data; if (ioctl_no == KVM_TDX_CAPABILITIES) { - r = kvm_ioctl(kvm_state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd); + r = kvm_ioctl(state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd); + } else if (ioctl_no == KVM_TDX_INIT_VCPU) { + r = kvm_vcpu_ioctl(state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd); } else { - r = kvm_vm_ioctl(kvm_state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd); + r = kvm_vm_ioctl(state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd); } if (r) { error_report("%s failed: %s", ioctl_name, strerror(-r)); exit(1); } } +#define _tdx_ioctl(cpu, ioctl_no, metadata, data) \ + __tdx_ioctl(cpu, ioctl_no, stringify(ioctl_no), metadata, data) #define tdx_ioctl(ioctl_no, metadata, data) \ - __tdx_ioctl(ioctl_no, stringify(ioctl_no), metadata, data) + _tdx_ioctl(kvm_state, ioctl_no, metadata, data) static void tdx_finalize_vm(Notifier *notifier, void *unused) { @@ -219,6 +223,14 @@ out: qemu_mutex_unlock(&tdx->lock); } +void tdx_post_init_vcpu(CPUState *cpu) +{ + CPUX86State *env = &X86_CPU(cpu)->env; + + _tdx_ioctl(cpu, KVM_TDX_INIT_VCPU, 0, + (void *)(unsigned long)env->regs[R_ECX]); +} + static bool tdx_guest_get_debug(Object *obj, Error **errp) { TdxGuest *tdx = TDX_GUEST(obj); From patchwork Thu Jul 8 00:54:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502065 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyqL33qJz9shx for ; Thu, 8 Jul 2021 11:09:01 +1000 (AEST) Received: from localhost ([::1]:47608 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IXC-000379-QR for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:08:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38140) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKs-0002Az-2C for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:17 -0400 Received: from mga06.intel.com ([134.134.136.31]:36379) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKp-0007L4-MS for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:13 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534898" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534898" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:55 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770037" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:55 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 15/44] i386/tdx: Add hook to require generic device loader Date: Wed, 7 Jul 2021 17:54:45 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Sean Christopherson Add a hook for TDX to denote that the TD Virtual Firmware must be provided via the "generic" device loader. Error out if pflash is used in conjuction with TDX. Suggested-by: Isaku Yamahata Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- hw/i386/pc_sysfw.c | 6 ++++++ include/sysemu/tdx.h | 2 ++ target/i386/kvm/tdx-stub.c | 5 +++++ target/i386/kvm/tdx.c | 25 +++++++++++++++++++++++++ 4 files changed, 38 insertions(+) diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c index 6ce37a2b05..5ff571af36 100644 --- a/hw/i386/pc_sysfw.c +++ b/hw/i386/pc_sysfw.c @@ -38,6 +38,7 @@ #include "hw/block/flash.h" #include "sysemu/kvm.h" #include "sysemu/sev.h" +#include "sysemu/tdx.h" #define FLASH_SECTOR_SIZE 4096 @@ -328,6 +329,11 @@ void pc_system_firmware_init(PCMachineState *pcms, int i; BlockBackend *pflash_blk[ARRAY_SIZE(pcms->flash)]; + if (!tdx_system_firmware_init(pcms, rom_memory)) { + pc_system_flash_cleanup_unused(pcms); + return; + } + if (!pcmc->pci_enabled) { x86_bios_rom_init(MACHINE(pcms), "bios.bin", rom_memory, true); return; diff --git a/include/sysemu/tdx.h b/include/sysemu/tdx.h index 03461b6ae8..70eb01348f 100644 --- a/include/sysemu/tdx.h +++ b/include/sysemu/tdx.h @@ -3,8 +3,10 @@ #ifndef CONFIG_USER_ONLY #include "sysemu/kvm.h" +#include "hw/i386/pc.h" bool kvm_has_tdx(KVMState *s); +int tdx_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); #endif void tdx_pre_create_vcpu(CPUState *cpu); diff --git a/target/i386/kvm/tdx-stub.c b/target/i386/kvm/tdx-stub.c index 93afe07ddb..4e1a0a4280 100644 --- a/target/i386/kvm/tdx-stub.c +++ b/target/i386/kvm/tdx-stub.c @@ -7,6 +7,11 @@ bool kvm_has_tdx(KVMState *s) { return false; } + +int tdx_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory) +{ + return -ENOSYS; +} #endif void tdx_pre_create_vcpu(CPUState *cpu) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 67fb03b4b5..48c04d344d 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -109,6 +109,31 @@ int tdx_kvm_init(ConfidentialGuestSupport *cgs, Error **errp) return 0; } +int tdx_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory) +{ + MachineState *ms = MACHINE(pcms); + TdxGuest *tdx = (TdxGuest *)object_dynamic_cast(OBJECT(ms->cgs), + TYPE_TDX_GUEST); + int i; + + if (!tdx) { + return -ENOSYS; + } + + /* + * Sanitiy check for tdx: + * TDX uses generic loader to load bios instead of pflash. + */ + for (i = 0; i < ARRAY_SIZE(pcms->flash); i++) { + if (drive_get(IF_PFLASH, 0, i)) { + error_report("pflash not supported by VM type, " + "use -device loader,file="); + exit(1); + } + } + return 0; +} + void tdx_get_supported_cpuid(KVMState *s, uint32_t function, uint32_t index, int reg, uint32_t *ret) { From patchwork Thu Jul 8 00:54:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502059 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKymj4lkpz9sW8 for ; Thu, 8 Jul 2021 11:06:45 +1000 (AEST) Received: from localhost ([::1]:38754 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IV1-0005gd-C6 for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:06:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38170) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKt-0002B4-2i for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:17 -0400 Received: from mga06.intel.com ([134.134.136.31]:36390) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKp-0007ML-MT for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:14 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534899" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534899" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:55 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770041" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:55 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 16/44] hw/i386: Add definitions from UEFI spec for volumes, resources, etc... Date: Wed, 7 Jul 2021 17:54:46 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Add definitions for literals, enums, structs, GUIDs, etc... that will be used by TDX to build the UEFI Hand-Off Block (HOB) that is passed to the Trusted Domain Virtual Firmware (TDVF). All values come from the UEFI specification and TDVF design guide. [1] Note: EFI_RESOURCE_ATTRIBUTE_{ENCRYPTED, UNACCEPTED}, will be added in future UEFI spec. [1] https://software.intel.com/content/dam/develop/external/us/en/documents/tdx-virtual-firmware-design-guide-rev-1.pdf Signed-off-by: Isaku Yamahata --- hw/i386/uefi.h | 496 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 496 insertions(+) create mode 100644 hw/i386/uefi.h diff --git a/hw/i386/uefi.h b/hw/i386/uefi.h new file mode 100644 index 0000000000..72bfc2f6a9 --- /dev/null +++ b/hw/i386/uefi.h @@ -0,0 +1,496 @@ +/* + * Copyright (C) 2020 Intel Corporation + * + * Author: Isaku Yamahata + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + * + */ + +#ifndef HW_I386_UEFI_H +#define HW_I386_UEFI_H + +/***************************************************************************/ +/* + * basic EFI definitions + * supplemented with UEFI Specification Version 2.8 (Errata A) + * released February 2020 + */ +/* UEFI integer is little endian */ + +typedef struct { + uint32_t Data1; + uint16_t Data2; + uint16_t Data3; + uint8_t Data4[8]; +} EFI_GUID; + +typedef uint64_t EFI_PHYSICAL_ADDRESS; +typedef uint32_t EFI_BOOT_MODE; + +typedef enum { + EfiReservedMemoryType, + EfiLoaderCode, + EfiLoaderData, + EfiBootServicesCode, + EfiBootServicesData, + EfiRuntimeServicesCode, + EfiRuntimeServicesData, + EfiConventionalMemory, + EfiUnusableMemory, + EfiACPIReclaimMemory, + EfiACPIMemoryNVS, + EfiMemoryMappedIO, + EfiMemoryMappedIOPortSpace, + EfiPalCode, + EfiPersistentMemory, + EfiMaxMemoryType +} EFI_MEMORY_TYPE; + + +/* + * data structure firmware volume/file + * based on + * UEFI Platform Initialization Specification Version 1.7. vol 3, 3.2.1 + */ + +#define SIGNATURE_16(A, B) (((A) | (B << 8))) +#define SIGNATURE_32(A, B, C, D) (((A) | (B << 8) | (C << 16) | (D << 24))) +#define SIGNATURE_64(A, B, C, D, E, F, G, H) \ + (SIGNATURE_32(A, B, C, D) | ((uint64_t)(SIGNATURE_32(E, F, G, H)) << 32)) + +/***************************************************************************/ +/* Firmware Volume format */ + +typedef uint32_t EFI_FV_FILE_ATTRIBUTES; + + +#define EFI_FV_FILE_ATTRIB_ALIGNMENT 0x0000001F +#define EFI_FV_FILE_ATTRIB_FIXED 0x00000100 +#define EFI_FV_FILE_ATTRIB_MEMORY_MAPPED 0x00000200 + +typedef uint32_t EFI_FVB_ATTRIBUTES_2; + + +#define EFI_FVB2_READ_DISABLED_CAP 0x00000001 +#define EFI_FVB2_READ_ENABLED_CAP 0x00000002 +#define EFI_FVB2_READ_STATUS 0x00000004 +#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008 +#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010 +#define EFI_FVB2_WRITE_STATUS 0x00000020 +#define EFI_FVB2_LOCK_CAP 0x00000040 +#define EFI_FVB2_LOCK_STATUS 0x00000080 +#define EFI_FVB2_STICKY_WRITE 0x00000200 +#define EFI_FVB2_MEMORY_MAPPED 0x00000400 +#define EFI_FVB2_ERASE_POLARITY 0x00000800 +#define EFI_FVB2_READ_LOCK_CAP 0x00001000 +#define EFI_FVB2_READ_LOCK_STATUS 0x00002000 +#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000 +#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000 +#define EFI_FVB2_ALIGNMENT 0x001F0000 +#define EFI_FVB2_WEAK_ALIGNMENT 0x80000000 +#define EFI_FVB2_ALIGNMENT_1 0x00000000 +#define EFI_FVB2_ALIGNMENT_2 0x00010000 +#define EFI_FVB2_ALIGNMENT_4 0x00020000 +#define EFI_FVB2_ALIGNMENT_8 0x00030000 +#define EFI_FVB2_ALIGNMENT_16 0x00040000 +#define EFI_FVB2_ALIGNMENT_32 0x00050000 +#define EFI_FVB2_ALIGNMENT_64 0x00060000 +#define EFI_FVB2_ALIGNMENT_128 0x00070000 +#define EFI_FVB2_ALIGNMENT_256 0x00080000 +#define EFI_FVB2_ALIGNMENT_512 0x00090000 +#define EFI_FVB2_ALIGNMENT_1K 0x000A0000 +#define EFI_FVB2_ALIGNMENT_2K 0x000B0000 +#define EFI_FVB2_ALIGNMENT_4K 0x000C0000 +#define EFI_FVB2_ALIGNMENT_8K 0x000D0000 +#define EFI_FVB2_ALIGNMENT_16K 0x000E0000 +#define EFI_FVB2_ALIGNMENT_32K 0x000F0000 +#define EFI_FVB2_ALIGNMENT_64K 0x00100000 +#define EFI_FVB2_ALIGNMENT_128K 0x00110000 +#define EFI_FVB2_ALIGNMENT_256K 0x00120000 +#define EFI_FVB2_ALIGNMENT_512K 0x00130000 +#define EFI_FVB2_ALIGNMENT_1M 0x00140000 +#define EFI_FVB2_ALIGNMENT_2M 0x00150000 +#define EFI_FVB2_ALIGNMENT_4M 0x00160000 +#define EFI_FVB2_ALIGNMENT_8M 0x00170000 +#define EFI_FVB2_ALIGNMENT_16M 0x00180000 +#define EFI_FVB2_ALIGNMENT_32M 0x00190000 +#define EFI_FVB2_ALIGNMENT_64M 0x001A0000 +#define EFI_FVB2_ALIGNMENT_128M 0x001B0000 +#define EFI_FVB2_ALIGNMENT_256M 0x001C0000 +#define EFI_FVB2_ALIGNMENT_512M 0x001D0000 +#define EFI_FVB2_ALIGNMENT_1G 0x001E0000 +#define EFI_FVB2_ALIGNMENT_2G 0x001F0000 + +typedef struct { + uint32_t NumBlocks; + uint32_t Length; +} EFI_FV_BLOCK_MAP_ENTRY; + +typedef struct { + uint8_t ZeroVector[16]; + EFI_GUID FileSystemGuid; + uint64_t FvLength; + uint32_t Signature; + EFI_FVB_ATTRIBUTES_2 Attributes; + uint16_t HeaderLength; + uint16_t Checksum; + uint16_t ExtHeaderOffset; + uint8_t Reserved[1]; + uint8_t Revision; + EFI_FV_BLOCK_MAP_ENTRY BlockMap[1]; +} EFI_FIRMWARE_VOLUME_HEADER; + +#define EFI_FVH_SIGNATURE SIGNATURE_32('_', 'F', 'V', 'H') + +#define EFI_FVH_REVISION 0x02 + +typedef struct { + EFI_GUID FvName; + uint32_t ExtHeaderSize; +} EFI_FIRMWARE_VOLUME_EXT_HEADER; + +typedef struct { + uint16_t ExtEntrySize; + uint16_t ExtEntryType; +} EFI_FIRMWARE_VOLUME_EXT_ENTRY; + +#define EFI_FV_EXT_TYPE_OEM_TYPE 0x01 +typedef struct { + EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr; + uint32_t TypeMask; + + EFI_GUID Types[]; +} EFI_FIRMWARE_VOLUME_EXT_ENTRY_OEM_TYPE; + +#define EFI_FV_EXT_TYPE_GUID_TYPE 0x0002 +typedef struct { + EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr; + EFI_GUID FormatType; + + uint8_t Data[]; +} EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE; + +#define EFI_FV_EXT_TYPE_USED_SIZE_TYPE 0x03 +typedef struct { + EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr; + uint32_t UsedSize; +} EFI_FIRMWARE_VOLUME_EXT_ENTRY_USED_SIZE_TYPE; + +/***************************************************************************/ +/* Firmware File */ + +#pragma pack(push, 1) + +typedef union { + struct { + uint8_t Header; + uint8_t File; + } Checksum; + uint16_t Checksum16; +} EFI_FFS_INTEGRITY_CHECK; + +typedef uint8_t EFI_FV_FILETYPE; +typedef uint8_t EFI_FFS_FILE_ATTRIBUTES; +typedef uint8_t EFI_FFS_FILE_STATE; + + +#define EFI_FV_FILETYPE_ALL 0x00 +#define EFI_FV_FILETYPE_RAW 0x01 +#define EFI_FV_FILETYPE_FREEFORM 0x02 +#define EFI_FV_FILETYPE_SECURITY_CORE 0x03 +#define EFI_FV_FILETYPE_PEI_CORE 0x04 +#define EFI_FV_FILETYPE_DXE_CORE 0x05 +#define EFI_FV_FILETYPE_PEIM 0x06 +#define EFI_FV_FILETYPE_DRIVER 0x07 +#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08 +#define EFI_FV_FILETYPE_APPLICATION 0x09 +#define EFI_FV_FILETYPE_SMM 0x0A +#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B +#define EFI_FV_FILETYPE_COMBINED_SMM_DXE 0x0C +#define EFI_FV_FILETYPE_SMM_CORE 0x0D +#define EFI_FV_FILETYPE_MM_STANDALONE 0x0E +#define EFI_FV_FILETYPE_MM_CORE_STANDALONE 0x0F +#define EFI_FV_FILETYPE_OEM_MIN 0xc0 +#define EFI_FV_FILETYPE_OEM_MAX 0xdf +#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0 +#define EFI_FV_FILETYPE_DEBUG_MAX 0xef +#define EFI_FV_FILETYPE_FFS_MIN 0xf0 +#define EFI_FV_FILETYPE_FFS_MAX 0xff +#define EFI_FV_FILETYPE_FFS_PAD 0xf0 + + +#define FFS_ATTRIB_LARGE_FILE 0x01 +#define FFS_ATTRIB_DATA_ALIGNMENT2 0x02 +#define FFS_ATTRIB_FIXED 0x04 +#define FFS_ATTRIB_DATA_ALIGNMENT 0x38 +#define FFS_ATTRIB_CHECKSUM 0x40 + + +#define EFI_FILE_HEADER_CONSTRUCTION 0x01 +#define EFI_FILE_HEADER_VALID 0x02 +#define EFI_FILE_DATA_VALID 0x04 +#define EFI_FILE_MARKED_FOR_UPDATE 0x08 +#define EFI_FILE_DELETED 0x10 +#define EFI_FILE_HEADER_INVALID 0x20 + + +#define EFI_FILE_ALL_STATE_BITS \ + (EFI_FILE_HEADER_CONSTRUCTION | \ + EFI_FILE_HEADER_VALID | \ + EFI_FILE_DATA_VALID | \ + EFI_FILE_MARKED_FOR_UPDATE | \ + EFI_FILE_DELETED | \ + EFI_FILE_HEADER_INVALID) + + +typedef struct { + EFI_GUID Name; + EFI_FFS_INTEGRITY_CHECK IntegrityCheck; + EFI_FV_FILETYPE Type; + EFI_FFS_FILE_ATTRIBUTES Attributes; + uint8_t Size[3]; + EFI_FFS_FILE_STATE State; +} EFI_FFS_FILE_HEADER; + + +typedef struct { + EFI_GUID Name; + EFI_FFS_INTEGRITY_CHECK IntegrityCheck; + EFI_FV_FILETYPE Type; + EFI_FFS_FILE_ATTRIBUTES Attributes; + uint8_t Size[3]; + EFI_FFS_FILE_STATE State; + uint64_t ExtendedSize; +} EFI_FFS_FILE_HEADER2; + +#define MAX_FFS_SIZE 0x1000000 + +#pragma pack(pop) + + +/***************************************************************************/ +/* GUIDs */ +#define EFI_FIRMWARE_FILE_SYSTEM2_GUID \ + ((EFI_GUID){ 0x8c8ce578, 0x8a3d, 0x4f1c, \ + { 0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2d, 0xd3 } }) + +#define EFI_FIRMWARE_FILE_SYSTEM3_GUID \ + ((EFI_GUID){ 0x5473c07a, 0x3dcb, 0x4dca, \ + { 0xbd, 0x6f, 0x1e, 0x96, 0x89, 0xe7, 0x34, 0x9a } }) + +#define EFI_SYSTEM_NV_DATA_FV_GUID \ + ((EFI_GUID){ 0xfff12b8d, 0x7696, 0x4c8b, \ + { 0xa9, 0x85, 0x27, 0x47, 0x7, 0x5b, 0x4f, 0x50 } }) + +#define EFI_FFS_VOLUME_TOP_FILE_GUID \ + ((EFI_GUID){ 0x1BA0062E, 0xC779, 0x4582, \ + { 0x85, 0x66, 0x33, 0x6A, 0xE8, 0xF7, 0x8F, 0x09 } }) + +/* + * data structure for hob(Hand-Off block) + * based on + * UEFI Platform Initialization Specification Version 1.7. vol 3, chap 4 and 5 + */ + +#define EFI_HOB_TYPE_HANDOFF 0x0001 +#define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002 +#define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003 +#define EFI_HOB_TYPE_GUID_EXTENSION 0x0004 +#define EFI_HOB_TYPE_FV 0x0005 +#define EFI_HOB_TYPE_CPU 0x0006 +#define EFI_HOB_TYPE_MEMORY_POOL 0x0007 +#define EFI_HOB_TYPE_FV2 0x0009 +#define EFI_HOB_TYPE_LOAD_PEIM_UNUSED 0x000A +#define EFI_HOB_TYPE_UEFI_CAPSULE 0x000B +#define EFI_HOB_TYPE_FV3 0x000C +#define EFI_HOB_TYPE_UNUSED 0xFFFE +#define EFI_HOB_TYPE_END_OF_HOB_LIST 0xFFFF + +typedef struct { + uint16_t HobType; + uint16_t HobLength; + uint32_t Reserved; +} EFI_HOB_GENERIC_HEADER; + + +#define EFI_HOB_HANDOFF_TABLE_VERSION 0x0009 + +typedef struct { + EFI_HOB_GENERIC_HEADER Header; + uint32_t Version; + EFI_BOOT_MODE BootMode; + EFI_PHYSICAL_ADDRESS EfiMemoryTop; + EFI_PHYSICAL_ADDRESS EfiMemoryBottom; + EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop; + EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom; + EFI_PHYSICAL_ADDRESS EfiEndOfHobList; +} EFI_HOB_HANDOFF_INFO_TABLE; + +typedef struct { + EFI_GUID Name; + EFI_PHYSICAL_ADDRESS MemoryBaseAddress; + uint64_t MemoryLength; + EFI_MEMORY_TYPE MemoryType; + uint8_t Reserved[4]; +} EFI_HOB_MEMORY_ALLOCATION_HEADER; + +typedef struct { + EFI_HOB_GENERIC_HEADER Header; + EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor; +} EFI_HOB_MEMORY_ALLOCATION; + +typedef struct { + EFI_HOB_GENERIC_HEADER Header; + EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor; +} EFI_HOB_MEMORY_ALLOCATION_STACK; + +typedef struct { + EFI_HOB_GENERIC_HEADER Header; + EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor; +} EFI_HOB_MEMORY_ALLOCATION_BSP_STORE; + +typedef struct { + EFI_HOB_GENERIC_HEADER Header; + EFI_HOB_MEMORY_ALLOCATION_HEADER MemoryAllocationHeader; + EFI_GUID ModuleName; + EFI_PHYSICAL_ADDRESS EntryPoint; +} EFI_HOB_MEMORY_ALLOCATION_MODULE; + +#define EFI_HOB_MEMORY_ALLOC_STACK_GUID \ + ((EFI_GUID){ 0x4ed4bf27, 0x4092, 0x42e9, \ + { 0x80, 0x7d, 0x52, 0x7b, 0x1d, 0x0, 0xc9, 0xbd } }) + +#define EFI_HOB_MEMORY_ALLOC_BSP_STORE_GUID \ + ((EFI_GUID){ 0x564b33cd, 0xc92a, 0x4593, \ + { 0x90, 0xbf, 0x24, 0x73, 0xe4, 0x3c, 0x63, 0x22 } }) + +#define EFI_HOB_MEMORY_ALLOC_MODULE_GUID \ + ((EFI_GUID){ 0xf8e21975, 0x899, 0x4f58, \ + { 0xa4, 0xbe, 0x55, 0x25, 0xa9, 0xc6, 0xd7, 0x7a } }) + + +typedef uint32_t EFI_RESOURCE_TYPE; + +#define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000 +#define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001 +#define EFI_RESOURCE_IO 0x00000002 +#define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003 +#define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004 +#define EFI_RESOURCE_MEMORY_RESERVED 0x00000005 +#define EFI_RESOURCE_IO_RESERVED 0x00000006 +#define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000007 + +typedef uint32_t EFI_RESOURCE_ATTRIBUTE_TYPE; + +#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001 +#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002 +#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004 +#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080 + +#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100 +#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200 +#define EFI_RESOURCE_ATTRIBUTE_PERSISTENT 0x00800000 + +#define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC 0x00000008 +#define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC 0x00000010 +#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 0x00000020 +#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 0x00000040 +#define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400 +#define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800 +#define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000 +#define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000 +#define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO 0x00004000 +#define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO 0x00008000 +#define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO 0x00010000 +#define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED 0x00020000 +#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTABLE 0x00100000 + +#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE 0x00200000 +#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTABLE 0x00400000 +#define EFI_RESOURCE_ATTRIBUTE_PERSISTABLE 0x01000000 + +#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED 0x00040000 +#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE 0x00080000 + +#define EFI_RESOURCE_ATTRIBUTE_MORE_RELIABLE 0x02000000 +#define EFI_RESOURCE_ATTRIBUTE_ENCRYPTED 0x04000000 + +/* FIXME: place holder for now */ +#define EFI_RESOURCE_ATTRIBUTE_UNACCEPTED 0x00000000 + +typedef struct { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Owner; + EFI_RESOURCE_TYPE ResourceType; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; + EFI_PHYSICAL_ADDRESS PhysicalStart; + uint64_t ResourceLength; +} EFI_HOB_RESOURCE_DESCRIPTOR; + +typedef struct { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + + /* guid specific data follows */ +} EFI_HOB_GUID_TYPE; + +typedef struct { + EFI_HOB_GENERIC_HEADER Header; + EFI_PHYSICAL_ADDRESS BaseAddress; + uint64_t Length; +} EFI_HOB_FIRMWARE_VOLUME; + +typedef struct { + EFI_HOB_GENERIC_HEADER Header; + EFI_PHYSICAL_ADDRESS BaseAddress; + uint64_t Length; + EFI_GUID FvName; + EFI_GUID FileName; +} EFI_HOB_FIRMWARE_VOLUME2; + +typedef struct { + EFI_HOB_GENERIC_HEADER Header; + EFI_PHYSICAL_ADDRESS BaseAddress; + uint64_t Length; + uint32_t AuthenticationStatus; + bool ExtractedFv; + EFI_GUID FvName; + EFI_GUID FileName; +} EFI_HOB_FIRMWARE_VOLUME3; + +typedef struct { + EFI_HOB_GENERIC_HEADER Header; + uint8_t SizeOfMemorySpace; + uint8_t SizeOfIoSpace; + uint8_t Reserved[6]; +} EFI_HOB_CPU; + +typedef struct { + EFI_HOB_GENERIC_HEADER Header; +} EFI_HOB_MEMORY_POOL; + +typedef struct { + EFI_HOB_GENERIC_HEADER Header; + + EFI_PHYSICAL_ADDRESS BaseAddress; + uint64_t Length; +} EFI_HOB_UEFI_CAPSULE; + +#define EFI_HOB_OWNER_ZERO \ + ((EFI_GUID){ 0x00000000, 0x0000, 0x0000, \ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }) + +#endif From patchwork Thu Jul 8 00:54:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502068 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyt526Yhz9sWS for ; Thu, 8 Jul 2021 11:11:25 +1000 (AEST) Received: from localhost ([::1]:52746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IZW-0006VU-UH for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:11:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38182) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKv-0002C3-U7 for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:17 -0400 Received: from mga06.intel.com ([134.134.136.31]:36375) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKs-0007Kq-BO for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:15 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534900" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534900" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:56 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770044" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:55 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 17/44] i386/tdx: Add definitions for TDVF metadata Date: Wed, 7 Jul 2021 17:54:47 -0700 Message-Id: <7a06bbaff6b399811b7a2c17a2e9b1d7f4e84a2d.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Add constants and structs for the TD Virtual Firmware metadata, which describes how the TDVF must be built to ensure correct functionality and measurement. They are defined in TDVF Design Guide [1]. [1] TDVF Design Guide https://software.intel.com/content/dam/develop/external/us/en/documents/tdx-virtual-firmware-design-guide-rev-1.pdf Signed-off-by: Isaku Yamahata Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson --- include/hw/i386/tdvf.h | 55 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 include/hw/i386/tdvf.h diff --git a/include/hw/i386/tdvf.h b/include/hw/i386/tdvf.h new file mode 100644 index 0000000000..5c78e2affb --- /dev/null +++ b/include/hw/i386/tdvf.h @@ -0,0 +1,55 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + + * Copyright (c) 2020 Intel Corporation + * Author: Isaku Yamahata + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef HW_I386_TDVF_H +#define HW_I386_TDVF_H + +#include "qemu/osdep.h" + +#define TDVF_METDATA_OFFSET_FROM_END 0x20 + +#define TDVF_SECTION_TYPE_BFV 0 +#define TDVF_SECTION_TYPE_CFV 1 +#define TDVF_SECTION_TYPE_TD_HOB 2 +#define TDVF_SECTION_TYPE_TEMP_MEM 3 + +#define TDVF_SECTION_ATTRIBUTES_EXTENDMR (1U << 0) + +typedef struct { + uint32_t DataOffset; + uint32_t RawDataSize; + uint64_t MemoryAddress; + uint64_t MemoryDataSize; + uint32_t Type; + uint32_t Attributes; +} TdvfSectionEntry; + +#define TDVF_SIGNATURE_LE32 0x46564454 /* TDVF as little endian */ + +typedef struct { + uint8_t Signature[4]; + uint32_t Length; + uint32_t Version; + uint32_t NumberOfSectionEntries; + TdvfSectionEntry SectionEntries[]; +} TdvfMetadata; + +#endif /* HW_I386_TDVF_H */ From patchwork Thu Jul 8 00:54:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502074 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKywy6bd9z9sWS for ; Thu, 8 Jul 2021 11:13:54 +1000 (AEST) Received: from localhost ([::1]:36460 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1Ibw-00066h-Hi for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:13:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38202) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKx-0002HY-4t for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:19 -0400 Received: from mga06.intel.com ([134.134.136.31]:36379) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKt-0007L4-5C for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:18 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534901" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534901" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:56 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770047" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:55 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 18/44] hw/i386: refactor e820_add_entry() Date: Wed, 7 Jul 2021 17:54:48 -0700 Message-Id: <876d3849f5293e7902df6e6f1dc8e89662b42a6b.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata The following patch will utilize this refactoring. Signed-off-by: Isaku Yamahata --- hw/i386/e820_memory_layout.c | 42 ++++++++++++++++++++++++------------ 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/hw/i386/e820_memory_layout.c b/hw/i386/e820_memory_layout.c index bcf9eaf837..d9bb11c02a 100644 --- a/hw/i386/e820_memory_layout.c +++ b/hw/i386/e820_memory_layout.c @@ -14,31 +14,45 @@ static size_t e820_entries; struct e820_table e820_reserve; struct e820_entry *e820_table; -int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) +static int e820_append_reserve(uint64_t address, uint64_t length, uint32_t type) { int index = le32_to_cpu(e820_reserve.count); struct e820_entry *entry; - if (type != E820_RAM) { - /* old FW_CFG_E820_TABLE entry -- reservations only */ - if (index >= E820_NR_ENTRIES) { - return -EBUSY; - } - entry = &e820_reserve.entry[index++]; + /* old FW_CFG_E820_TABLE entry -- reservations only */ + if (index >= E820_NR_ENTRIES) { + return -EBUSY; + } + entry = &e820_reserve.entry[index++]; - entry->address = cpu_to_le64(address); - entry->length = cpu_to_le64(length); - entry->type = cpu_to_le32(type); + entry->address = cpu_to_le64(address); + entry->length = cpu_to_le64(length); + entry->type = cpu_to_le32(type); - e820_reserve.count = cpu_to_le32(index); - } + e820_reserve.count = cpu_to_le32(index); + return 0; +} - /* new "etc/e820" file -- include ram too */ - e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); +static void e820_append_entry(uint64_t address, uint64_t length, uint32_t type) +{ e820_table[e820_entries].address = cpu_to_le64(address); e820_table[e820_entries].length = cpu_to_le64(length); e820_table[e820_entries].type = cpu_to_le32(type); e820_entries++; +} + +int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) +{ + if (type != E820_RAM) { + int ret = e820_append_reserve(address, length, type); + if (ret) { + return ret; + } + } + + /* new "etc/e820" file -- include ram too */ + e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); + e820_append_entry(address, length, type); return e820_entries; } From patchwork Thu Jul 8 00:54:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502071 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKywH5sDhz9sWS for ; Thu, 8 Jul 2021 11:13:19 +1000 (AEST) Received: from localhost ([::1]:32868 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IbN-0003h6-HN for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:13:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38204) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKx-0002JD-IO for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:19 -0400 Received: from mga06.intel.com ([134.134.136.31]:36390) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKv-0007ML-OW for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:19 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534902" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534902" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:56 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770050" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:56 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 19/44] hw/i386/e820: introduce a helper function to change type of e820 Date: Wed, 7 Jul 2021 17:54:49 -0700 Message-Id: <57f1c8c44405aadc421bc1fd5b6cb41f55b10e20.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Introduce a helper function, e820_change_type(), that change the type of subregion of e820 entry. The following patch uses it. Signed-off-by: Isaku Yamahata --- hw/i386/e820_memory_layout.c | 72 ++++++++++++++++++++++++++++++++++++ hw/i386/e820_memory_layout.h | 1 + 2 files changed, 73 insertions(+) diff --git a/hw/i386/e820_memory_layout.c b/hw/i386/e820_memory_layout.c index d9bb11c02a..109c4f715a 100644 --- a/hw/i386/e820_memory_layout.c +++ b/hw/i386/e820_memory_layout.c @@ -57,6 +57,78 @@ int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) return e820_entries; } +int e820_change_type(uint64_t address, uint64_t length, uint32_t type) +{ + size_t i; + + if (type != E820_RAM) { + int ret = e820_append_reserve(address, length, type); + if (ret) { + return ret; + } + } + + /* new "etc/e820" file -- include ram too */ + for (i = 0; i < e820_entries; i++) { + struct e820_entry *e = &e820_table[i]; + struct e820_entry tmp = { + .address = le64_to_cpu(e->address), + .length = le64_to_cpu(e->length), + .type = le32_to_cpu(e->type), + }; + /* overlap? */ + if (address + length < tmp.address || + tmp.address + tmp.length < address) { + continue; + } + /* + * partial-overlap is not allowed. + * It is assumed that the region is completely contained within + * other region. + */ + if (address < tmp.address || + tmp.address + tmp.length < address + length) { + return -EINVAL; + } + /* only real type change is allowed. */ + if (tmp.type == type) { + return -EINVAL; + } + + if (tmp.address == address && + tmp.address + tmp.length == address + length) { + e->type = cpu_to_le32(type); + return e820_entries; + } else if (tmp.address == address) { + e820_table = g_renew(struct e820_entry, + e820_table, e820_entries + 1); + e = &e820_table[i]; + e->address = cpu_to_le64(tmp.address + length); + e820_append_entry(address, length, type); + return e820_entries; + } else if (tmp.address + tmp.length == address + length) { + e820_table = g_renew(struct e820_entry, + e820_table, e820_entries + 1); + e = &e820_table[i]; + e->length = cpu_to_le64(tmp.length - length); + e820_append_entry(address, length, type); + return e820_entries; + } else { + e820_table = g_renew(struct e820_entry, + e820_table, e820_entries + 2); + e = &e820_table[i]; + e->length = cpu_to_le64(address - tmp.address); + e820_append_entry(address, length, type); + e820_append_entry(address + length, + tmp.address + tmp.length - (address + length), + tmp.type); + return e820_entries; + } + } + + return -EINVAL; +} + int e820_get_num_entries(void) { return e820_entries; diff --git a/hw/i386/e820_memory_layout.h b/hw/i386/e820_memory_layout.h index 2a0ceb8b9c..5f27cee476 100644 --- a/hw/i386/e820_memory_layout.h +++ b/hw/i386/e820_memory_layout.h @@ -33,6 +33,7 @@ extern struct e820_table e820_reserve; extern struct e820_entry *e820_table; int e820_add_entry(uint64_t address, uint64_t length, uint32_t type); +int e820_change_type(uint64_t address, uint64_t length, uint32_t type); int e820_get_num_entries(void); bool e820_get_entry(int index, uint32_t type, uint64_t *address, uint64_t *length); From patchwork Thu Jul 8 00:54:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502078 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyzj681Xz9sWS for ; Thu, 8 Jul 2021 11:16:17 +1000 (AEST) Received: from localhost ([::1]:44878 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IeF-0003LS-Jw for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:16:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38272) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILB-0002qt-0U for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:34 -0400 Received: from mga06.intel.com ([134.134.136.31]:36375) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IL6-0007Kq-A5 for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:32 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534903" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534903" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:56 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770053" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:56 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 20/44] i386/tdx: Parse tdx metadata and store the result into TdxGuestState Date: Wed, 7 Jul 2021 17:54:50 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org, "Min M . Xu" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Add support for loading TDX's Trusted Domain Virtual Firmware (TDVF) via the generic loader. Prioritize the TDVF above plain hex to avoid false positives with hex (TDVF has explicit metadata to confirm it's a TDVF). Enumerate TempMem as added, private memory, i.e. E820_RESERVED, otherwise TDVF will interpret the whole shebang as MMIO and complain that the aperture overlaps other MMIO regions. Signed-off-by: Isaku Yamahata Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson Reported-by: Min M. Xu --- hw/core/generic-loader.c | 5 + hw/core/meson.build | 3 + hw/core/tdvf-stub.c | 6 + hw/i386/meson.build | 1 + hw/i386/tdvf.c | 312 +++++++++++++++++++++++++++++++++++++++ include/sysemu/tdvf.h | 6 + target/i386/kvm/tdx.h | 26 ++++ 7 files changed, 359 insertions(+) create mode 100644 hw/core/tdvf-stub.c create mode 100644 hw/i386/tdvf.c create mode 100644 include/sysemu/tdvf.h diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index d14f932eea..ee2f49b47a 100644 --- a/hw/core/generic-loader.c +++ b/hw/core/generic-loader.c @@ -34,6 +34,7 @@ #include "hw/core/cpu.h" #include "sysemu/dma.h" #include "sysemu/reset.h" +#include "sysemu/tdvf.h" #include "hw/boards.h" #include "hw/loader.h" #include "hw/qdev-properties.h" @@ -147,6 +148,10 @@ static void generic_loader_realize(DeviceState *dev, Error **errp) as); } + if (size < 0) { + size = load_tdvf(s->file); + } + if (size < 0) { size = load_targphys_hex_as(s->file, &entry, as); } diff --git a/hw/core/meson.build b/hw/core/meson.build index 18f44fb7c2..ec943debf1 100644 --- a/hw/core/meson.build +++ b/hw/core/meson.build @@ -24,6 +24,9 @@ common_ss.add(when: 'CONFIG_REGISTER', if_true: files('register.c')) common_ss.add(when: 'CONFIG_SPLIT_IRQ', if_true: files('split-irq.c')) common_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('stream.c')) +common_ss.add(when: 'CONFIG_TDX', if_false: files('tdvf-stub.c')) +common_ss.add(when: 'CONFIG_ALL', if_true: files('tdvf-stub.c')) + softmmu_ss.add(files( 'cpu-sysemu.c', 'fw-path-provider.c', diff --git a/hw/core/tdvf-stub.c b/hw/core/tdvf-stub.c new file mode 100644 index 0000000000..5f2586dd70 --- /dev/null +++ b/hw/core/tdvf-stub.c @@ -0,0 +1,6 @@ +#include "sysemu/tdvf.h" + +int load_tdvf(const char *filename) +{ + return -1; +} diff --git a/hw/i386/meson.build b/hw/i386/meson.build index e5d109f5c6..945e805525 100644 --- a/hw/i386/meson.build +++ b/hw/i386/meson.build @@ -24,6 +24,7 @@ i386_ss.add(when: 'CONFIG_PC', if_true: files( 'pc_sysfw.c', 'acpi-build.c', 'port92.c')) +i386_ss.add(when: 'CONFIG_TDX', if_true: files('tdvf.c')) subdir('kvm') subdir('xen') diff --git a/hw/i386/tdvf.c b/hw/i386/tdvf.c new file mode 100644 index 0000000000..9b0065d656 --- /dev/null +++ b/hw/i386/tdvf.c @@ -0,0 +1,312 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + + * Copyright (c) 2020 Intel Corporation + * Author: Isaku Yamahata + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/units.h" +#include "cpu.h" +#include "exec/hwaddr.h" +#include "hw/boards.h" +#include "hw/i386/e820_memory_layout.h" +#include "hw/i386/tdvf.h" +#include "hw/i386/x86.h" +#include "hw/loader.h" +#include "sysemu/tdx.h" +#include "sysemu/tdvf.h" +#include "target/i386/kvm/tdx.h" + +static void tdvf_init_ram_memory(MachineState *ms, TdxFirmwareEntry *entry) +{ + void *ram_ptr = memory_region_get_ram_ptr(ms->ram); + X86MachineState *x86ms = X86_MACHINE(ms); + + if (entry->type == TDVF_SECTION_TYPE_BFV || + entry->type == TDVF_SECTION_TYPE_CFV) { + error_report("TDVF type %u addr 0x%" PRIx64 " in RAM (disallowed)", + entry->type, entry->address); + exit(1); + } + + if (entry->address < 4 * GiB) { + entry->mem_ptr = ram_ptr + entry->address; + } else { + /* + * If TDVF temp memory describe in TDVF metadata lays in RAM, reserve + * the region property. + */ + if (entry->address >= 4 * GiB + x86ms->above_4g_mem_size || + entry->address + entry->size >= 4 * GiB + x86ms->above_4g_mem_size) { + error_report("TDVF type %u address 0x%" PRIx64 " size 0x%" PRIx64 + " above high memory", + entry->type, entry->address, entry->size); + exit(1); + } + entry->mem_ptr = ram_ptr + x86ms->below_4g_mem_size + + entry->address - 4 * GiB; + } + e820_change_type(entry->address, entry->size, E820_RESERVED); +} + +static void tdvf_init_bios_memory(int fd, const char *filename, + TdxFirmwareEntry *entry) +{ + static unsigned int nr_cfv; + static unsigned int nr_tmp; + + MemoryRegion *system_memory = get_system_memory(); + Error *err = NULL; + const char *name; + + /* Error out if the section might overlap other structures. */ + if (entry->address < 4 * GiB - 16 * MiB) { + error_report("TDVF type %u address 0x%" PRIx64 " in PCI hole", + entry->type, entry->address); + exit(1); + } + + if (entry->type == TDVF_SECTION_TYPE_BFV) { + name = g_strdup("tdvf.bfv"); + } else if (entry->type == TDVF_SECTION_TYPE_CFV) { + name = g_strdup_printf("tdvf.cfv%u", nr_cfv++); + } else if (entry->type == TDVF_SECTION_TYPE_TD_HOB) { + name = g_strdup("tdvf.hob"); + } else if (entry->type == TDVF_SECTION_TYPE_TEMP_MEM) { + name = g_strdup_printf("tdvf.tmp%u", nr_tmp++); + } else { + error_report("TDVF type %u unknown/unsupported", entry->type); + exit(1); + } + entry->mr = g_malloc(sizeof(*entry->mr)); + + memory_region_init_ram(entry->mr, NULL, name, entry->size, &err); + if (err) { + error_report_err(err); + exit(1); + } + + entry->mem_ptr = memory_region_get_ram_ptr(entry->mr); + if (entry->data_len) { + /* + * The memory_region api doesn't allow partial file mapping, create + * ram and copy the contents + */ + if (lseek(fd, entry->data_offset, SEEK_SET) != entry->data_offset) { + error_report("can't seek to 0x%x %s", entry->data_offset, filename); + exit(1); + } + if (read(fd, entry->mem_ptr, entry->data_len) != entry->data_len) { + error_report("can't read 0x%x %s", entry->data_len, filename); + exit(1); + } + } + + memory_region_add_subregion(system_memory, entry->address, entry->mr); + + if (entry->type == TDVF_SECTION_TYPE_TEMP_MEM) { + e820_add_entry(entry->address, entry->size, E820_RESERVED); + } +} + +static void tdvf_parse_section_entry(TdxFirmwareEntry *entry, + const TdvfSectionEntry *src, + uint64_t file_size) +{ + entry->data_offset = le32_to_cpu(src->DataOffset); + entry->data_len = le32_to_cpu(src->RawDataSize); + entry->address = le64_to_cpu(src->MemoryAddress); + entry->size = le64_to_cpu(src->MemoryDataSize); + entry->type = le32_to_cpu(src->Type); + entry->attributes = le32_to_cpu(src->Attributes); + + /* sanity check */ + if (entry->data_offset + entry->data_len > file_size) { + error_report("too large section: DataOffset 0x%x RawDataSize 0x%x", + entry->data_offset, entry->data_len); + exit(1); + } + if (entry->size < entry->data_len) { + error_report("broken metadata RawDataSize 0x%x MemoryDataSize 0x%lx", + entry->data_len, entry->size); + exit(1); + } + if (!QEMU_IS_ALIGNED(entry->address, TARGET_PAGE_SIZE)) { + error_report("MemoryAddress 0x%lx not page aligned", entry->address); + exit(1); + } + if (!QEMU_IS_ALIGNED(entry->size, TARGET_PAGE_SIZE)) { + error_report("MemoryDataSize 0x%lx not page aligned", entry->size); + exit(1); + } + if (entry->type == TDVF_SECTION_TYPE_TD_HOB || + entry->type == TDVF_SECTION_TYPE_TEMP_MEM) { + if (entry->data_len > 0) { + error_report("%d section with RawDataSize 0x%x > 0", + entry->type, entry->data_len); + exit(1); + } + } +} + +static void tdvf_parse_metadata_entries(int fd, TdxFirmware *fw, + TdvfMetadata *metadata) +{ + + TdvfSectionEntry *sections; + ssize_t entries_size; + uint32_t len, i; + + fw->nr_entries = le32_to_cpu(metadata->NumberOfSectionEntries); + if (fw->nr_entries < 2) { + error_report("Invalid number of entries (%u) in TDVF", fw->nr_entries); + exit(1); + } + + len = le32_to_cpu(metadata->Length); + entries_size = fw->nr_entries * sizeof(TdvfSectionEntry); + if (len != sizeof(*metadata) + entries_size) { + error_report("TDVF metadata len (0x%x) mismatch, expected (0x%x)", + len, (uint32_t)(sizeof(*metadata) + entries_size)); + exit(1); + } + + fw->entries = g_new(TdxFirmwareEntry, fw->nr_entries); + sections = g_new(TdvfSectionEntry, fw->nr_entries); + + if (read(fd, sections, entries_size) != entries_size) { + error_report("Failed to read TDVF section entries"); + exit(1); + } + + for (i = 0; i < fw->nr_entries; i++) { + tdvf_parse_section_entry(&fw->entries[i], §ions[i], fw->file_size); + } + g_free(sections); +} + +static int tdvf_parse_metadata_header(int fd, TdvfMetadata *metadata) +{ + uint32_t offset; + int64_t size; + + size = lseek(fd, 0, SEEK_END); + if (size < TDVF_METDATA_OFFSET_FROM_END || (uint32_t)size != size) { + return -1; + } + + /* Chase the metadata pointer to get to the actual metadata. */ + offset = size - TDVF_METDATA_OFFSET_FROM_END; + if (lseek(fd, offset, SEEK_SET) != offset) { + return -1; + } + if (read(fd, &offset, sizeof(offset)) != sizeof(offset)) { + return -1; + } + + offset = le32_to_cpu(offset); + if (offset > size - sizeof(*metadata)) { + return -1; + } + + /* Pointer to the metadata has been resolved, read the actual metadata. */ + if (lseek(fd, offset, SEEK_SET) != offset) { + return -1; + } + if (read(fd, metadata, sizeof(*metadata)) != sizeof(*metadata)) { + return -1; + } + + /* Finally, verify the signature to determine if this is a TDVF image. */ + if (metadata->Signature[0] != 'T' || metadata->Signature[1] != 'D' || + metadata->Signature[2] != 'V' || metadata->Signature[3] != 'F') { + return -1; + } + + /* Sanity check that the TDVF doesn't overlap its own metadata. */ + metadata->Length = le32_to_cpu(metadata->Length); + if (metadata->Length > size - offset) { + return -1; + } + + /* Only version 1 is supported/defined. */ + metadata->Version = le32_to_cpu(metadata->Version); + if (metadata->Version != 1) { + return -1; + } + + return size; +} + +int load_tdvf(const char *filename) +{ + MachineState *ms = MACHINE(qdev_get_machine()); + X86MachineState *x86ms = X86_MACHINE(ms); + TdxFirmwareEntry *entry; + TdvfMetadata metadata; + TdxGuest *tdx; + TdxFirmware *fw; + int64_t size; + int fd; + + if (!kvm_enabled()) { + return -1; + } + + tdx = (void *)object_dynamic_cast(OBJECT(ms->cgs), TYPE_TDX_GUEST); + if (!tdx) { + return -1; + } + + fd = open(filename, O_RDONLY | O_BINARY); + if (fd < 0) { + return -1; + } + + size = tdvf_parse_metadata_header(fd, &metadata); + if (size < 0) { + close(fd); + return -1; + } + + /* Error out if the user is attempting to load multiple TDVFs. */ + fw = &tdx->fw; + if (fw->file_name) { + error_report("tdvf can only be specified once."); + exit(1); + } + + fw->file_size = size; + fw->file_name = g_strdup(filename); + + tdvf_parse_metadata_entries(fd, fw, &metadata); + + for_each_fw_entry(fw, entry) { + if (entry->address < x86ms->below_4g_mem_size || + entry->address > 4 * GiB) { + tdvf_init_ram_memory(ms, entry); + } else { + tdvf_init_bios_memory(fd, filename, entry); + } + } + + close(fd); + return 0; +} diff --git a/include/sysemu/tdvf.h b/include/sysemu/tdvf.h new file mode 100644 index 0000000000..0cf085e3ae --- /dev/null +++ b/include/sysemu/tdvf.h @@ -0,0 +1,6 @@ +#ifndef QEMU_TDVF_H +#define QEMU_TDVF_H + +int load_tdvf(const char *filename); + +#endif diff --git a/target/i386/kvm/tdx.h b/target/i386/kvm/tdx.h index 844d24aade..2fed27b3fb 100644 --- a/target/i386/kvm/tdx.h +++ b/target/i386/kvm/tdx.h @@ -5,6 +5,30 @@ #include "qapi/error.h" #include "exec/confidential-guest-support.h" +typedef struct TdxFirmwareEntry { + uint32_t data_offset; + uint32_t data_len; + uint64_t address; + uint64_t size; + uint32_t type; + uint32_t attributes; + + MemoryRegion *mr; + void *mem_ptr; +} TdxFirmwareEntry; + +typedef struct TdxFirmware { + const char *file_name; + uint64_t file_size; + + /* metadata */ + uint32_t nr_entries; + TdxFirmwareEntry *entries; +} TdxFirmware; + +#define for_each_fw_entry(fw, e) \ + for (e = (fw)->entries; e != (fw)->entries + (fw)->nr_entries; e++) + #define TYPE_TDX_GUEST "tdx-guest" #define TDX_GUEST(obj) \ OBJECT_CHECK(TdxGuest, (obj), TYPE_TDX_GUEST) @@ -20,6 +44,8 @@ typedef struct TdxGuest { bool initialized; bool debug; + + TdxFirmware fw; } TdxGuest; int tdx_kvm_init(ConfidentialGuestSupport *cgs, Error **errp); From patchwork Thu Jul 8 00:54:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502083 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKz3h08Zzz9sWS for ; Thu, 8 Jul 2021 11:19:44 +1000 (AEST) Received: from localhost ([::1]:58172 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IhX-0003h2-V7 for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:19:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38282) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILC-0002ro-RF for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:36 -0400 Received: from mga06.intel.com ([134.134.136.31]:36379) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IL7-0007L4-Uf for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:33 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534904" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534904" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:56 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770056" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:56 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 21/44] i386/tdx: Create the TD HOB list upon machine init done Date: Wed, 7 Jul 2021 17:54:51 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Build the TD HOB during machine late initialization, i.e. once guest memory is fully defined. Signed-off-by: Isaku Yamahata Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson --- hw/i386/meson.build | 2 +- hw/i386/tdvf-hob.c | 166 ++++++++++++++++++++++++++++++++++++++++++ hw/i386/tdvf-hob.h | 20 +++++ target/i386/kvm/tdx.c | 19 +++++ 4 files changed, 206 insertions(+), 1 deletion(-) create mode 100644 hw/i386/tdvf-hob.c create mode 100644 hw/i386/tdvf-hob.h diff --git a/hw/i386/meson.build b/hw/i386/meson.build index 945e805525..8175c3c638 100644 --- a/hw/i386/meson.build +++ b/hw/i386/meson.build @@ -24,7 +24,7 @@ i386_ss.add(when: 'CONFIG_PC', if_true: files( 'pc_sysfw.c', 'acpi-build.c', 'port92.c')) -i386_ss.add(when: 'CONFIG_TDX', if_true: files('tdvf.c')) +i386_ss.add(when: 'CONFIG_TDX', if_true: files('tdvf.c', 'tdvf-hob.c')) subdir('kvm') subdir('xen') diff --git a/hw/i386/tdvf-hob.c b/hw/i386/tdvf-hob.c new file mode 100644 index 0000000000..5e0bf807f7 --- /dev/null +++ b/hw/i386/tdvf-hob.c @@ -0,0 +1,166 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + + * Copyright (c) 2020 Intel Corporation + * Author: Isaku Yamahata + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "e820_memory_layout.h" +#include "hw/i386/x86.h" +#include "sysemu/tdx.h" +#include "tdvf-hob.h" +#include "uefi.h" + +typedef struct TdvfHob { + hwaddr hob_addr; + void *ptr; + int size; + + /* working area */ + void *current; + void *end; +} TdvfHob; + +static uint64_t tdvf_current_guest_addr(const TdvfHob *hob) +{ + return hob->hob_addr + (hob->current - hob->ptr); +} + +static void tdvf_align(TdvfHob *hob, size_t align) +{ + hob->current = QEMU_ALIGN_PTR_UP(hob->current, align); +} + +static void *tdvf_get_area(TdvfHob *hob, uint64_t size) +{ + void *ret; + + if (hob->current + size > hob->end) { + error_report("TD_HOB overrun, size = 0x%" PRIx64, size); + exit(1); + } + + ret = hob->current; + hob->current += size; + tdvf_align(hob, 8); + return ret; +} + +static int tdvf_e820_compare(const void *lhs_, const void* rhs_) +{ + const struct e820_entry *lhs = lhs_; + const struct e820_entry *rhs = rhs_; + + if (lhs->address == rhs->address) { + return 0; + } + if (le64_to_cpu(lhs->address) > le64_to_cpu(rhs->address)) { + return 1; + } + return -1; +} + +static void tdvf_hob_add_memory_resources(TdvfHob *hob) +{ + EFI_HOB_RESOURCE_DESCRIPTOR *region; + EFI_RESOURCE_ATTRIBUTE_TYPE attr; + EFI_RESOURCE_TYPE resource_type; + + struct e820_entry *e820_entries, *e820_entry; + int nr_e820_entries, i; + + nr_e820_entries = e820_get_num_entries(); + e820_entries = g_new(struct e820_entry, nr_e820_entries); + + /* Copy and sort the e820 tables to add them to the HOB. */ + memcpy(e820_entries, e820_table, + nr_e820_entries * sizeof(struct e820_entry)); + qsort(e820_entries, nr_e820_entries, sizeof(struct e820_entry), + &tdvf_e820_compare); + + for (i = 0; i < nr_e820_entries; i++) { + e820_entry = &e820_entries[i]; + + if (le32_to_cpu(e820_entry->type) == E820_RAM) { + resource_type = EFI_RESOURCE_SYSTEM_MEMORY; + attr = EFI_RESOURCE_ATTRIBUTE_TDVF_UNACCEPTED; + } else { + resource_type = EFI_RESOURCE_MEMORY_RESERVED; + attr = EFI_RESOURCE_ATTRIBUTE_TDVF_PRIVATE; + } + + region = tdvf_get_area(hob, sizeof(*region)); + *region = (EFI_HOB_RESOURCE_DESCRIPTOR) { + .Header = { + .HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, + .HobLength = cpu_to_le16(sizeof(*region)), + .Reserved = cpu_to_le32(0), + }, + .Owner = EFI_HOB_OWNER_ZERO, + .ResourceType = cpu_to_le32(resource_type), + .ResourceAttribute = cpu_to_le32(attr), + .PhysicalStart = e820_entry->address, + .ResourceLength = e820_entry->length, + }; + } + + g_free(e820_entries); +} + +void tdvf_hob_create(TdxGuest *tdx, TdxFirmwareEntry *hob_entry) +{ + TdvfHob hob = { + .hob_addr = hob_entry->address, + .ptr = hob_entry->mem_ptr, + .size = hob_entry->size, + + .current = hob_entry->mem_ptr, + .end = hob_entry->mem_ptr + hob_entry->size, + }; + + EFI_HOB_GENERIC_HEADER *last_hob; + EFI_HOB_HANDOFF_INFO_TABLE *hit; + + /* Note, Efi{Free}Memory{Bottom,Top} are ignored, leave 'em zeroed. */ + hit = tdvf_get_area(&hob, sizeof(*hit)); + *hit = (EFI_HOB_HANDOFF_INFO_TABLE) { + .Header = { + .HobType = EFI_HOB_TYPE_HANDOFF, + .HobLength = cpu_to_le16(sizeof(*hit)), + .Reserved = cpu_to_le32(0), + }, + .Version = cpu_to_le32(EFI_HOB_HANDOFF_TABLE_VERSION), + .BootMode = cpu_to_le32(0), + .EfiMemoryTop = cpu_to_le64(0), + .EfiMemoryBottom = cpu_to_le64(0), + .EfiFreeMemoryTop = cpu_to_le64(0), + .EfiFreeMemoryBottom = cpu_to_le64(0), + .EfiEndOfHobList = cpu_to_le64(0), /* initialized later */ + }; + + tdvf_hob_add_memory_resources(&hob); + + last_hob = tdvf_get_area(&hob, sizeof(*last_hob)); + *last_hob = (EFI_HOB_GENERIC_HEADER) { + .HobType = EFI_HOB_TYPE_END_OF_HOB_LIST, + .HobLength = cpu_to_le16(sizeof(*last_hob)), + .Reserved = cpu_to_le32(0), + }; + hit->EfiEndOfHobList = tdvf_current_guest_addr(&hob); +} diff --git a/hw/i386/tdvf-hob.h b/hw/i386/tdvf-hob.h new file mode 100644 index 0000000000..c6c5c1d564 --- /dev/null +++ b/hw/i386/tdvf-hob.h @@ -0,0 +1,20 @@ +#ifndef HW_I386_TD_HOB_H +#define HW_I386_TD_HOB_H + +#include "hw/i386/tdvf.h" +#include "target/i386/kvm/tdx.h" + +void tdvf_hob_create(TdxGuest *tdx, TdxFirmwareEntry *hob_entry); + +#define EFI_RESOURCE_ATTRIBUTE_TDVF_PRIVATE \ + (EFI_RESOURCE_ATTRIBUTE_PRESENT | \ + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | \ + EFI_RESOURCE_ATTRIBUTE_ENCRYPTED | \ + EFI_RESOURCE_ATTRIBUTE_TESTED) + +#define EFI_RESOURCE_ATTRIBUTE_TDVF_UNACCEPTED \ + (EFI_RESOURCE_ATTRIBUTE_PRESENT | \ + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | \ + EFI_RESOURCE_ATTRIBUTE_UNACCEPTED) + +#endif diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 48c04d344d..12b2e02fa2 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -19,6 +19,7 @@ #include "cpu.h" #include "kvm_i386.h" #include "hw/boards.h" +#include "hw/i386/tdvf-hob.h" #include "qapi/error.h" #include "qom/object_interfaces.h" #include "standard-headers/asm-x86/kvm_para.h" @@ -67,8 +68,26 @@ static void __tdx_ioctl(void *state, int ioctl_no, const char *ioctl_name, #define tdx_ioctl(ioctl_no, metadata, data) \ _tdx_ioctl(kvm_state, ioctl_no, metadata, data) +static TdxFirmwareEntry *tdx_get_hob_entry(TdxGuest *tdx) +{ + TdxFirmwareEntry *entry; + + for_each_fw_entry(&tdx->fw, entry) { + if (entry->type == TDVF_SECTION_TYPE_TD_HOB) { + return entry; + } + } + error_report("TDVF metadata doesn't specify TD_HOB location."); + exit(1); +} + static void tdx_finalize_vm(Notifier *notifier, void *unused) { + MachineState *ms = MACHINE(qdev_get_machine()); + TdxGuest *tdx = TDX_GUEST(ms->cgs); + + tdvf_hob_create(tdx, tdx_get_hob_entry(tdx)); + tdx_ioctl(KVM_TDX_FINALIZE_VM, 0, NULL); } From patchwork Thu Jul 8 00:54:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502082 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKz2S2xVgz9sXM for ; Thu, 8 Jul 2021 11:18:40 +1000 (AEST) Received: from localhost ([::1]:53710 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IgY-0000lb-4T for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:18:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38284) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILC-0002rq-RE for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:36 -0400 Received: from mga06.intel.com ([134.134.136.31]:36390) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IL7-0007ML-VA for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:33 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534905" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534905" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:56 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770059" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:56 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 22/44] i386/tdx: Add TDVF memory via INIT_MEM_REGION Date: Wed, 7 Jul 2021 17:54:52 -0700 Message-Id: <8abb2018fbaafaa12f9d4b9f225ec7de481f39db.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Add, and optionally measure, TDVF memory via KVM_TDX_INIT_MEM_REGION as part of finalizing the TD. Signed-off-by: Isaku Yamahata Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson --- target/i386/kvm/tdx.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 12b2e02fa2..0cd649dd01 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -85,10 +85,26 @@ static void tdx_finalize_vm(Notifier *notifier, void *unused) { MachineState *ms = MACHINE(qdev_get_machine()); TdxGuest *tdx = TDX_GUEST(ms->cgs); + TdxFirmwareEntry *entry; tdvf_hob_create(tdx, tdx_get_hob_entry(tdx)); + for_each_fw_entry(&tdx->fw, entry) { + struct kvm_tdx_init_mem_region mem_region = { + .source_addr = (__u64)entry->mem_ptr, + .gpa = entry->address, + .nr_pages = entry->size / 4096, + }; + + __u32 metadata = entry->attributes & TDVF_SECTION_ATTRIBUTES_EXTENDMR ? + KVM_TDX_MEASURE_MEMORY_REGION : 0; + + tdx_ioctl(KVM_TDX_INIT_MEM_REGION, metadata, &mem_region); + } + tdx_ioctl(KVM_TDX_FINALIZE_VM, 0, NULL); + + tdx->parent_obj.ready = true; } static Notifier tdx_machine_done_late_notify = { @@ -301,7 +317,6 @@ static void tdx_guest_init(Object *obj) { TdxGuest *tdx = TDX_GUEST(obj); - tdx->parent_obj.ready = true; qemu_mutex_init(&tdx->lock); tdx->debug = false; From patchwork Thu Jul 8 00:54:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502090 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKzBQ1NZqz9sWc for ; Thu, 8 Jul 2021 11:25:34 +1000 (AEST) Received: from localhost ([::1]:51564 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1InD-00016O-VU for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:25:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38342) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILN-0002zO-Hf for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:45 -0400 Received: from mga06.intel.com ([134.134.136.31]:36375) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILL-0007Kq-CL for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:45 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534907" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534907" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:56 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770062" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:56 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 23/44] i386/tdx: Use KVM_TDX_INIT_VCPU to pass HOB to TDVF Date: Wed, 7 Jul 2021 17:54:53 -0700 Message-Id: <3b5827e8f4004c332d679eb55c98e23cbe53dfeb.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Specify the initial value for RCX/R8 to be the address of the HOB. Don't propagate the value to Qemu's cache of the registers so as to avoid implying that the register state is valid, e.g. Qemu doesn't model TDX-SEAM behavior for initializing other GPRs. Signed-off-by: Isaku Yamahata --- target/i386/kvm/tdx.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 0cd649dd01..c348626dbf 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -285,10 +285,17 @@ out: void tdx_post_init_vcpu(CPUState *cpu) { - CPUX86State *env = &X86_CPU(cpu)->env; + MachineState *ms = MACHINE(qdev_get_machine()); + TdxGuest *tdx = (TdxGuest *)object_dynamic_cast(OBJECT(ms->cgs), + TYPE_TDX_GUEST); + TdxFirmwareEntry *hob; + + if (!tdx) { + return; + } - _tdx_ioctl(cpu, KVM_TDX_INIT_VCPU, 0, - (void *)(unsigned long)env->regs[R_ECX]); + hob = tdx_get_hob_entry(tdx); + _tdx_ioctl(cpu, KVM_TDX_INIT_VCPU, 0, (void *)hob->address); } static bool tdx_guest_get_debug(Object *obj, Error **errp) From patchwork Thu Jul 8 00:54:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502081 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKz2G3B97z9sXM for ; Thu, 8 Jul 2021 11:18:30 +1000 (AEST) Received: from localhost ([::1]:53604 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IgO-0000hj-73 for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:18:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38366) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILP-00034S-1D for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:47 -0400 Received: from mga06.intel.com ([134.134.136.31]:36390) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILN-0007ML-5L for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:46 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534908" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534908" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:57 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770065" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:56 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 24/44] i386/tdx: Add MMIO HOB entries Date: Wed, 7 Jul 2021 17:54:54 -0700 Message-Id: <3cf3b4e1ccbddd08bb4695930b6ebee9678f9454.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Sean Christopherson Add MMIO HOB entries, which are needed to enumerate legal MMIO ranges to early TDVF. Note, the attribute absolutely must include UNCACHEABLE, else TDVF will effectively consider it a bad HOB entry and ignore it. Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- hw/i386/tdvf-hob.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++ hw/i386/tdvf-hob.h | 5 ++++ 2 files changed, 74 insertions(+) diff --git a/hw/i386/tdvf-hob.c b/hw/i386/tdvf-hob.c index 5e0bf807f7..60c5ed0e03 100644 --- a/hw/i386/tdvf-hob.c +++ b/hw/i386/tdvf-hob.c @@ -22,7 +22,10 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "e820_memory_layout.h" +#include "hw/i386/pc.h" #include "hw/i386/x86.h" +#include "hw/pci/pci_host.h" +#include "hw/pci/pcie_host.h" #include "sysemu/tdx.h" #include "tdvf-hob.h" #include "uefi.h" @@ -62,6 +65,70 @@ static void *tdvf_get_area(TdvfHob *hob, uint64_t size) return ret; } +static void tdvf_hob_add_mmio_resource(TdvfHob *hob, uint64_t start, + uint64_t end) +{ + EFI_HOB_RESOURCE_DESCRIPTOR *region; + + if (!start) { + return; + } + + region = tdvf_get_area(hob, sizeof(*region)); + *region = (EFI_HOB_RESOURCE_DESCRIPTOR) { + .Header = { + .HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, + .HobLength = cpu_to_le16(sizeof(*region)), + .Reserved = cpu_to_le32(0), + }, + .Owner = EFI_HOB_OWNER_ZERO, + .ResourceType = cpu_to_le32(EFI_RESOURCE_MEMORY_MAPPED_IO), + .ResourceAttribute = cpu_to_le32(EFI_RESOURCE_ATTRIBUTE_TDVF_MMIO), + .PhysicalStart = cpu_to_le64(start), + .ResourceLength = cpu_to_le64(end - start), + }; +} + +static void tdvf_hob_add_mmio_resources(TdvfHob *hob) +{ + MachineState *ms = MACHINE(qdev_get_machine()); + X86MachineState *x86ms = X86_MACHINE(ms); + PCIHostState *pci_host; + uint64_t start, end; + uint64_t mcfg_base, mcfg_size; + Object *host; + + /* Effectively PCI hole + other MMIO devices. */ + tdvf_hob_add_mmio_resource(hob, x86ms->below_4g_mem_size, + APIC_DEFAULT_ADDRESS); + + /* Stolen from acpi_get_i386_pci_host(), there's gotta be an easier way. */ + pci_host = OBJECT_CHECK(PCIHostState, + object_resolve_path("/machine/i440fx", NULL), + TYPE_PCI_HOST_BRIDGE); + if (!pci_host) { + pci_host = OBJECT_CHECK(PCIHostState, + object_resolve_path("/machine/q35", NULL), + TYPE_PCI_HOST_BRIDGE); + } + g_assert(pci_host); + + host = OBJECT(pci_host); + + /* PCI hole above 4gb. */ + start = object_property_get_uint(host, PCI_HOST_PROP_PCI_HOLE64_START, + NULL); + end = object_property_get_uint(host, PCI_HOST_PROP_PCI_HOLE64_END, NULL); + tdvf_hob_add_mmio_resource(hob, start, end); + + /* MMCFG region */ + mcfg_base = object_property_get_uint(host, PCIE_HOST_MCFG_BASE, NULL); + mcfg_size = object_property_get_uint(host, PCIE_HOST_MCFG_SIZE, NULL); + if (mcfg_base && mcfg_base != PCIE_BASE_ADDR_UNMAPPED && mcfg_size) { + tdvf_hob_add_mmio_resource(hob, mcfg_base, mcfg_base + mcfg_size); + } +} + static int tdvf_e820_compare(const void *lhs_, const void* rhs_) { const struct e820_entry *lhs = lhs_; @@ -156,6 +223,8 @@ void tdvf_hob_create(TdxGuest *tdx, TdxFirmwareEntry *hob_entry) tdvf_hob_add_memory_resources(&hob); + tdvf_hob_add_mmio_resources(&hob); + last_hob = tdvf_get_area(&hob, sizeof(*last_hob)); *last_hob = (EFI_HOB_GENERIC_HEADER) { .HobType = EFI_HOB_TYPE_END_OF_HOB_LIST, diff --git a/hw/i386/tdvf-hob.h b/hw/i386/tdvf-hob.h index c6c5c1d564..9967dbfe5a 100644 --- a/hw/i386/tdvf-hob.h +++ b/hw/i386/tdvf-hob.h @@ -17,4 +17,9 @@ void tdvf_hob_create(TdxGuest *tdx, TdxFirmwareEntry *hob_entry); EFI_RESOURCE_ATTRIBUTE_INITIALIZED | \ EFI_RESOURCE_ATTRIBUTE_UNACCEPTED) +#define EFI_RESOURCE_ATTRIBUTE_TDVF_MMIO \ + (EFI_RESOURCE_ATTRIBUTE_PRESENT | \ + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | \ + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE) + #endif From patchwork Thu Jul 8 00:54:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502085 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKz5l0c9fz9sXM for ; Thu, 8 Jul 2021 11:21:31 +1000 (AEST) Received: from localhost ([::1]:34098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IjI-0006WH-Ov for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:21:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38364) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILO-00033s-TI for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:46 -0400 Received: from mga06.intel.com ([134.134.136.31]:36379) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILN-0007L4-8l for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:46 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534909" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534909" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:57 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770069" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:57 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 25/44] q35: Move PCIe BAR check above PAM check in mch_write_config() Date: Wed, 7 Jul 2021 17:54:55 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Sean Christopherson Process PCIe BAR before PAM so that a future patch can skip all the SMM related crud with a single check-and-return. Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- hw/pci-host/q35.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 2eb729dff5..9a2be237d7 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -468,16 +468,16 @@ static void mch_write_config(PCIDevice *d, pci_default_write_config(d, address, val, len); - if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, - MCH_HOST_BRIDGE_PAM_SIZE)) { - mch_update_pam(mch); - } - if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { mch_update_pciexbar(mch); } + if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, + MCH_HOST_BRIDGE_PAM_SIZE)) { + mch_update_pam(mch); + } + if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, MCH_HOST_BRIDGE_SMRAM_SIZE)) { mch_update_smram(mch); From patchwork Thu Jul 8 00:54:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502091 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKzCr3Pq6z9sWq for ; Thu, 8 Jul 2021 11:26:48 +1000 (AEST) Received: from localhost ([::1]:56698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IoQ-0004az-6s for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:26:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38422) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILb-0003OD-Bo for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:57:03 -0400 Received: from mga06.intel.com ([134.134.136.31]:36375) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILX-0007Kq-UE for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:58 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534910" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534910" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:57 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770073" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:57 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 26/44] pci-host/q35: Move PAM initialization above SMRAM initialization Date: Wed, 7 Jul 2021 17:54:56 -0700 Message-Id: <2e1b8cadf4176c2f0d80c53a20f7c774c7d39a69.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata In mch_realize(), process PAM initialization before SMRAM initialization so that later patch can skill all the SMRAM related with a single check. Signed-off-by: Isaku Yamahata --- hw/pci-host/q35.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 9a2be237d7..68234d209c 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -571,6 +571,16 @@ static void mch_realize(PCIDevice *d, Error **errp) pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, mch->pci_address_space); + /* PAM */ + init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, + mch->pci_address_space, &mch->pam_regions[0], + PAM_BIOS_BASE, PAM_BIOS_SIZE); + for (i = 0; i < ARRAY_SIZE(mch->pam_regions) - 1; ++i) { + init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, + mch->pci_address_space, &mch->pam_regions[i+1], + PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); + } + /* if *disabled* show SMRAM to all CPUs */ memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, @@ -637,15 +647,6 @@ static void mch_realize(PCIDevice *d, Error **errp) object_property_add_const_link(qdev_get_machine(), "smram", OBJECT(&mch->smram)); - - init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, - mch->pci_address_space, &mch->pam_regions[0], - PAM_BIOS_BASE, PAM_BIOS_SIZE); - for (i = 0; i < ARRAY_SIZE(mch->pam_regions) - 1; ++i) { - init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, - mch->pci_address_space, &mch->pam_regions[i+1], - PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); - } } uint64_t mch_mcfg_base(void) From patchwork Thu Jul 8 00:54:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502086 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKz5k6ffcz9sWS for ; Thu, 8 Jul 2021 11:21:30 +1000 (AEST) Received: from localhost ([::1]:34102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IjI-0006WX-JZ for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:21:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38424) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILb-0003OE-BF for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:57:03 -0400 Received: from mga06.intel.com ([134.134.136.31]:36379) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILZ-0007L4-9d for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:58 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534911" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534911" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:57 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770076" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:57 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 27/44] q35: Introduce smm_ranges property for q35-pci-host Date: Wed, 7 Jul 2021 17:54:57 -0700 Message-Id: <32a79698d8c585cbf34e92d558ef9250ebba85ab.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , Isaku Yamahata , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Add a q35 property to check whether or not SMM ranges, e.g. SMRAM, TSEG, etc... exist for the target platform. TDX doesn't support SMM and doesn't play nice with QEMU modifying related guest memory ranges. Signed-off-by: Isaku Yamahata Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- hw/i386/pc_q35.c | 2 ++ hw/pci-host/q35.c | 42 +++++++++++++++++++++++++++------------ include/hw/i386/pc.h | 1 + include/hw/pci-host/q35.h | 1 + 4 files changed, 33 insertions(+), 13 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 46a0f196f4..1718aa94d9 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -219,6 +219,8 @@ static void pc_q35_init(MachineState *machine) x86ms->below_4g_mem_size, NULL); object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE, x86ms->above_4g_mem_size, NULL); + object_property_set_bool(OBJECT(q35_host), PCI_HOST_PROP_SMM_RANGES, + x86_machine_is_smm_enabled(x86ms), NULL); /* pci */ sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal); phb = PCI_HOST_BRIDGE(q35_host); diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 68234d209c..ba28d969ba 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -183,6 +183,8 @@ static Property q35_host_props[] = { mch.below_4g_mem_size, 0), DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, mch.above_4g_mem_size, 0), + DEFINE_PROP_BOOL(PCI_HOST_PROP_SMM_RANGES, Q35PCIHost, + mch.has_smm_ranges, true), DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), DEFINE_PROP_END_OF_LIST(), }; @@ -218,6 +220,7 @@ static void q35_host_initfn(Object *obj) /* mch's object_initialize resets the default value, set it again */ qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); + object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", q35_host_get_pci_hole_start, NULL, NULL, NULL); @@ -478,6 +481,10 @@ static void mch_write_config(PCIDevice *d, mch_update_pam(mch); } + if (!mch->has_smm_ranges) { + return; + } + if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, MCH_HOST_BRIDGE_SMRAM_SIZE)) { mch_update_smram(mch); @@ -496,10 +503,13 @@ static void mch_write_config(PCIDevice *d, static void mch_update(MCHPCIState *mch) { mch_update_pciexbar(mch); + mch_update_pam(mch); - mch_update_smram(mch); - mch_update_ext_tseg_mbytes(mch); - mch_update_smbase_smram(mch); + if (mch->has_smm_ranges) { + mch_update_smram(mch); + mch_update_ext_tseg_mbytes(mch); + mch_update_smbase_smram(mch); + } /* * pci hole goes from end-of-low-ram to io-apic. @@ -540,18 +550,20 @@ static void mch_reset(DeviceState *qdev) pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); - d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; - d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; - d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; - d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; + if (mch->has_smm_ranges) { + d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; + d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; + d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; + d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; - if (mch->ext_tseg_mbytes > 0) { - pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, - MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); - } + if (mch->ext_tseg_mbytes > 0) { + pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); + } - d->config[MCH_HOST_BRIDGE_F_SMBASE] = 0; - d->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 0xff; + d->config[MCH_HOST_BRIDGE_F_SMBASE] = 0; + d->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 0xff; + } mch_update(mch); } @@ -581,6 +593,10 @@ static void mch_realize(PCIDevice *d, Error **errp) PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); } + if (!mch->has_smm_ranges) { + return; + } + /* if *disabled* show SMRAM to all CPUs */ memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 87294f2632..cd2113c763 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -147,6 +147,7 @@ void pc_guest_info_init(PCMachineState *pcms); #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size" #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size" +#define PCI_HOST_PROP_SMM_RANGES "smm-ranges" void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index ab989698ef..ce634e708a 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -50,6 +50,7 @@ struct MCHPCIState { MemoryRegion tseg_blackhole, tseg_window; MemoryRegion smbase_blackhole, smbase_window; bool has_smram_at_smbase; + bool has_smm_ranges; Range pci_hole; uint64_t below_4g_mem_size; uint64_t above_4g_mem_size; From patchwork Thu Jul 8 00:54:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502088 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKz7v08vsz9sWc for ; Thu, 8 Jul 2021 11:23:23 +1000 (AEST) Received: from localhost ([::1]:42110 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1Il6-0003LO-NU for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:23:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38426) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILb-0003OM-QU for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:57:03 -0400 Received: from mga06.intel.com ([134.134.136.31]:36390) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILZ-0007ML-CE for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:59 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="270534912" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="270534912" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:57 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770079" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:57 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 28/44] i386/tdx: Force x2apic mode and routing for TDs Date: Wed, 7 Jul 2021 17:54:58 -0700 Message-Id: <5524acbf0b403fea046978456129d4c59a06f8a0.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=isaku.yamahata@intel.com; helo=mga06.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Sean Christopherson TDX requires x2apic and "resets" vCPUs to have x2apic enabled. Model this in QEMU and unconditionally enable x2apic interrupt routing. This fixes issues where interrupts from IRQFD would not get forwarded to the guest due to KVM silently dropping the invalid routing entry. Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- hw/intc/apic_common.c | 12 ++++++++++++ include/hw/i386/apic.h | 1 + include/hw/i386/apic_internal.h | 1 + target/i386/kvm/tdx.c | 7 +++++++ 4 files changed, 21 insertions(+) diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 2a20982066..b95fed95da 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -262,6 +262,15 @@ void apic_designate_bsp(DeviceState *dev, bool bsp) } } +void apic_force_x2apic(DeviceState *dev) +{ + if (dev == NULL) { + return; + } + + APIC_COMMON(dev)->force_x2apic = true; +} + static void apic_reset_common(DeviceState *dev) { APICCommonState *s = APIC_COMMON(dev); @@ -270,6 +279,9 @@ static void apic_reset_common(DeviceState *dev) bsp = s->apicbase & MSR_IA32_APICBASE_BSP; s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE; + if (s->force_x2apic) { + s->apicbase |= MSR_IA32_APICBASE_EXTD; + } s->id = s->initial_apic_id; apic_reset_irq_delivered(); diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h index da1d2fe155..7d05abd7e0 100644 --- a/include/hw/i386/apic.h +++ b/include/hw/i386/apic.h @@ -19,6 +19,7 @@ void apic_init_reset(DeviceState *s); void apic_sipi(DeviceState *s); void apic_poll_irq(DeviceState *d); void apic_designate_bsp(DeviceState *d, bool bsp); +void apic_force_x2apic(DeviceState *d); int apic_get_highest_priority_irr(DeviceState *dev); /* pc.c */ diff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_internal.h index c175e7e718..eda0b5a587 100644 --- a/include/hw/i386/apic_internal.h +++ b/include/hw/i386/apic_internal.h @@ -187,6 +187,7 @@ struct APICCommonState { DeviceState *vapic; hwaddr vapic_paddr; /* note: persistence via kvmvapic */ bool legacy_instance_id; + bool force_x2apic; }; typedef struct VAPICState { diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index c348626dbf..47a502051c 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -139,6 +139,11 @@ int tdx_kvm_init(ConfidentialGuestSupport *cgs, Error **errp) tdx_caps->nr_cpuid_configs = TDX1_MAX_NR_CPUID_CONFIGS; tdx_ioctl(KVM_TDX_CAPABILITIES, 0, tdx_caps); + if (!kvm_enable_x2apic()) { + error_report("Failed to enable x2apic in KVM"); + exit(1); + } + qemu_add_machine_init_done_late_notifier(&tdx_machine_done_late_notify); return 0; @@ -296,6 +301,8 @@ void tdx_post_init_vcpu(CPUState *cpu) hob = tdx_get_hob_entry(tdx); _tdx_ioctl(cpu, KVM_TDX_INIT_VCPU, 0, (void *)hob->address); + + apic_force_x2apic(X86_CPU(cpu)->apic_state); } static bool tdx_guest_get_debug(Object *obj, Error **errp) From patchwork Thu Jul 8 00:54:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502049 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKycb6YtSz9sW8 for ; Thu, 8 Jul 2021 10:59:43 +1000 (AEST) Received: from localhost ([::1]:46466 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IOD-0000JC-KO for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 20:59:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37916) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKk-0001mK-7y for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:06 -0400 Received: from mga12.intel.com ([192.55.52.136]:57606) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKd-0007L7-Hf for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:02 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101718" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101718" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:57 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770082" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:57 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 29/44] target/i386: Add machine option to disable PIC/8259 Date: Wed, 7 Jul 2021 17:54:59 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Sean Christopherson , isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Sean Christopherson Add a machine option to disable the legacy PIC (8259), which cannot be supported for TDX guests as TDX-SEAM doesn't allow directly interrupt injection. Using posted interrupts for the PIC is not a viable option as the guest BIOS/kernel will not do EOI for PIC IRQs, i.e. will leave the vIRR bit set. Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- hw/i386/pc.c | 18 ++++++++++++++++++ hw/i386/pc_piix.c | 4 +++- hw/i386/pc_q35.c | 4 +++- include/hw/i386/pc.h | 2 ++ 4 files changed, 26 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 8e1220db72..f4590df231 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1522,6 +1522,20 @@ static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) pcms->hpet_enabled = value; } +static bool pc_machine_get_pic(Object *obj, Error **errp) +{ + PCMachineState *pcms = PC_MACHINE(obj); + + return pcms->pic_enabled; +} + +static void pc_machine_set_pic(Object *obj, bool value, Error **errp) +{ + PCMachineState *pcms = PC_MACHINE(obj); + + pcms->pic_enabled = value; +} + static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) @@ -1617,6 +1631,7 @@ static void pc_machine_initfn(Object *obj) pcms->smbus_enabled = true; pcms->sata_enabled = true; pcms->pit_enabled = true; + pcms->pic_enabled = true; pcms->max_fw_size = 8 * MiB; #ifdef CONFIG_HPET pcms->hpet_enabled = true; @@ -1742,6 +1757,9 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) object_class_property_add_bool(oc, PC_MACHINE_PIT, pc_machine_get_pit, pc_machine_set_pit); + object_class_property_add_bool(oc, PC_MACHINE_PIC, + pc_machine_get_pic, pc_machine_set_pic); + object_class_property_add_bool(oc, "hpet", pc_machine_get_hpet, pc_machine_set_hpet); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 30b8bd6ea9..4c1e31f180 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -218,7 +218,9 @@ static void pc_init1(MachineState *machine, } isa_bus_irqs(isa_bus, x86ms->gsi); - pc_i8259_create(isa_bus, gsi_state->i8259_irq); + if (pcms->pic_enabled) { + pc_i8259_create(isa_bus, gsi_state->i8259_irq); + } if (pcmc->pci_enabled) { ioapic_init_gsi(gsi_state, "i440fx"); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 1718aa94d9..106f5726cc 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -251,7 +251,9 @@ static void pc_q35_init(MachineState *machine) pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); isa_bus = ich9_lpc->isa_bus; - pc_i8259_create(isa_bus, gsi_state->i8259_irq); + if (pcms->pic_enabled) { + pc_i8259_create(isa_bus, gsi_state->i8259_irq); + } if (pcmc->pci_enabled) { ioapic_init_gsi(gsi_state, "q35"); diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index cd2113c763..9cede7a260 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -44,6 +44,7 @@ typedef struct PCMachineState { bool sata_enabled; bool pit_enabled; bool hpet_enabled; + bool pic_enabled; uint64_t max_fw_size; /* NUMA information: */ @@ -61,6 +62,7 @@ typedef struct PCMachineState { #define PC_MACHINE_SMBUS "smbus" #define PC_MACHINE_SATA "sata" #define PC_MACHINE_PIT "pit" +#define PC_MACHINE_PIC "pic" #define PC_MACHINE_MAX_FW_SIZE "max-fw-size" /** * PCMachineClass: From patchwork Thu Jul 8 00:55:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502050 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKycf293Lz9sW8 for ; Thu, 8 Jul 2021 10:59:46 +1000 (AEST) Received: from localhost ([::1]:46548 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IOF-0000Mb-RP for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 20:59:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37918) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKk-0001mM-9k for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:06 -0400 Received: from mga12.intel.com ([192.55.52.136]:57610) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKe-0007LH-7p for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:02 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101719" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101719" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:58 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770085" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:57 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 30/44] qom: implement property helper for sha384 Date: Wed, 7 Jul 2021 17:55:00 -0700 Message-Id: <398d321c9c74c43bf0fa137c04932b1b7a89efab.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Implement property_add_sha384() which converts hex string <-> uint8_t[48] It will be used for TDX which uses sha384 for measurement. Signed-off-by: Isaku Yamahata --- include/qom/object.h | 17 ++++++++++ qom/object.c | 76 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 93 insertions(+) diff --git a/include/qom/object.h b/include/qom/object.h index 6721cd312e..594d0ec52c 100644 --- a/include/qom/object.h +++ b/include/qom/object.h @@ -1853,6 +1853,23 @@ ObjectProperty *object_property_add_alias(Object *obj, const char *name, ObjectProperty *object_property_add_const_link(Object *obj, const char *name, Object *target); + +/** + * object_property_add_sha384: + * @obj: the object to add a property to + * @name: the name of the property + * @v: pointer to value + * @flags: bitwise-or'd ObjectPropertyFlags + * + * Add an sha384 property in memory. This function will add a + * property of type 'sha384'. + * + * Returns: The newly added property on success, or %NULL on failure. + */ +ObjectProperty * object_property_add_sha384(Object *obj, const char *name, + const uint8_t *v, + ObjectPropertyFlags flags); + /** * object_property_set_description: * @obj: the object owning the property diff --git a/qom/object.c b/qom/object.c index 6a01d56546..e33a0b8c5d 100644 --- a/qom/object.c +++ b/qom/object.c @@ -15,6 +15,7 @@ #include "qapi/error.h" #include "qom/object.h" #include "qom/object_interfaces.h" +#include "qemu/ctype.h" #include "qemu/cutils.h" #include "qapi/visitor.h" #include "qapi/string-input-visitor.h" @@ -2749,6 +2750,81 @@ object_property_add_alias(Object *obj, const char *name, return op; } +#define SHA384_DIGEST_SIZE 48 +static void property_get_sha384(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint8_t *value = (uint8_t *)opaque; + char str[SHA384_DIGEST_SIZE * 2 + 1]; + char *str_ = (char*)str; + size_t i; + + for (i = 0; i < SHA384_DIGEST_SIZE; i++) { + char *buf; + buf = &str[i * 2]; + + sprintf(buf, "%02hhx", value[i]); + } + str[SHA384_DIGEST_SIZE * 2] = '\0'; + + visit_type_str(v, name, &str_, errp); +} + +static void property_set_sha384(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint8_t *value = (uint8_t *)opaque; + char* str; + size_t len; + size_t i; + + if (!visit_type_str(v, name, &str, errp)) { + goto err; + } + + len = strlen(str); + if (len != SHA384_DIGEST_SIZE * 2) { + error_setg(errp, "invalid length for sha348 hex string %s. " + "it must be 48 * 2 hex", name); + goto err; + } + + for (i = 0; i < SHA384_DIGEST_SIZE; i++) { + if (!qemu_isxdigit(str[i * 2]) || !qemu_isxdigit(str[i * 2 + 1])) { + error_setg(errp, "invalid char for sha318 hex string %s at %c%c", + name, str[i * 2], str[i * 2 + 1]); + goto err; + } + + if (sscanf(str + i * 2, "%02hhx", &value[i]) != 1) { + error_setg(errp, "invalid format for sha318 hex string %s", name); + goto err; + } + } + +err: + g_free(str); +} + +ObjectProperty * +object_property_add_sha384(Object *obj, const char *name, + const uint8_t *v, ObjectPropertyFlags flags) +{ + ObjectPropertyAccessor *getter = NULL; + ObjectPropertyAccessor *setter = NULL; + + if ((flags & OBJ_PROP_FLAG_READ) == OBJ_PROP_FLAG_READ) { + getter = property_get_sha384; + } + + if ((flags & OBJ_PROP_FLAG_WRITE) == OBJ_PROP_FLAG_WRITE) { + setter = property_set_sha384; + } + + return object_property_add(obj, name, "sha384", + getter, setter, NULL, (void *)v); +} + void object_property_set_description(Object *obj, const char *name, const char *description) { From patchwork Thu Jul 8 00:55:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502056 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyln1nKXz9sWS for ; Thu, 8 Jul 2021 11:05:57 +1000 (AEST) Received: from localhost ([::1]:35448 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IUE-0003O0-TT for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:05:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37920) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKk-0001mP-9X for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:06 -0400 Received: from mga12.intel.com ([192.55.52.136]:57600) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKg-0007Kk-06 for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:03 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101721" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101721" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:58 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770089" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:57 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 31/44] target/i386/tdx: Allows mrconfigid/mrowner/mrownerconfig for TDX_INIT_VM Date: Wed, 7 Jul 2021 17:55:01 -0700 Message-Id: <9f1e7fd7678900791d2094d2f0def53fe0afc658.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata When creating VM with TDX_INIT_VM, three sha384 hash values are accepted for TDX attestation. So far they were hard coded as 0. Now allow user to specify those values via property mrconfigid, mrowner and mrownerconfig. string for those property are hex string of 48 * 2 length. example -device tdx-guest, \ mrconfigid=0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef, \ mrowner=fedcba9876543210fedcba9876543210fedcba9876543210fedcba9876543210fedcba9876543210fedcba9876543210, \ mrownerconfig=0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef Signed-off-by: Isaku Yamahata --- qapi/qom.json | 11 ++++++++++- target/i386/kvm/tdx.c | 17 +++++++++++++++++ target/i386/kvm/tdx.h | 3 +++ 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/qapi/qom.json b/qapi/qom.json index 70c70e3efe..8f8b7828b3 100644 --- a/qapi/qom.json +++ b/qapi/qom.json @@ -767,10 +767,19 @@ # # @debug: enable debug mode (default: off) # +# @mrconfigid: MRCONFIGID SHA384 hex string of 48 * 2 length (default: 0) +# +# @mrowner: MROWNER SHA384 hex string of 48 * 2 length (default: 0) +# +# @mrownerconfig: MROWNERCONFIG SHA384 hex string of 48 * 2 length (default: 0) +# # Since: 6.0 ## { 'struct': 'TdxGuestProperties', - 'data': { '*debug': 'bool' } } + 'data': { '*debug': 'bool', + '*mrconfigid': 'str', + '*mrowner': 'str', + '*mrownerconfig': 'str' } } ## # @ObjectType: diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 47a502051c..6b560c1c0b 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -282,6 +282,17 @@ void tdx_pre_create_vcpu(CPUState *cpu) init_vm.attributes |= tdx->debug ? TDX1_TD_ATTRIBUTE_DEBUG : 0; init_vm.attributes |= x86cpu->enable_pmu ? TDX1_TD_ATTRIBUTE_PERFMON : 0; + QEMU_BUILD_BUG_ON(sizeof(init_vm.mrconfigid) != sizeof(tdx->mrconfigid)); + memcpy(init_vm.mrconfigid, tdx->mrconfigid, sizeof(init_vm.mrconfigid)); + QEMU_BUILD_BUG_ON(sizeof(init_vm.mrowner) != sizeof(tdx->mrowner)); + memcpy(init_vm.mrowner, tdx->mrowner, sizeof(init_vm.mrowner)); + QEMU_BUILD_BUG_ON(sizeof(init_vm.mrownerconfig) != + sizeof(tdx->mrownerconfig)); + memcpy(init_vm.mrownerconfig, tdx->mrownerconfig, + sizeof(init_vm.mrownerconfig)); + + memset(init_vm.reserved, 0, sizeof(init_vm.reserved)); + init_vm.cpuid = (__u64)(&cpuid_data); tdx_ioctl(KVM_TDX_INIT_VM, 0, &init_vm); out: @@ -336,6 +347,12 @@ static void tdx_guest_init(Object *obj) tdx->debug = false; object_property_add_bool(obj, "debug", tdx_guest_get_debug, tdx_guest_set_debug); + object_property_add_sha384(obj, "mrconfigid", tdx->mrconfigid, + OBJ_PROP_FLAG_READWRITE); + object_property_add_sha384(obj, "mrowner", tdx->mrowner, + OBJ_PROP_FLAG_READWRITE); + object_property_add_sha384(obj, "mrownerconfig", tdx->mrownerconfig, + OBJ_PROP_FLAG_READWRITE); } static void tdx_guest_finalize(Object *obj) diff --git a/target/i386/kvm/tdx.h b/target/i386/kvm/tdx.h index 2fed27b3fb..4132d1be30 100644 --- a/target/i386/kvm/tdx.h +++ b/target/i386/kvm/tdx.h @@ -44,6 +44,9 @@ typedef struct TdxGuest { bool initialized; bool debug; + uint8_t mrconfigid[48]; /* sha348 digest */ + uint8_t mrowner[48]; /* sha348 digest */ + uint8_t mrownerconfig[48]; /* sha348 digest */ TdxFirmware fw; } TdxGuest; From patchwork Thu Jul 8 00:55:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502061 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyp452Nkz9sW8 for ; Thu, 8 Jul 2021 11:07:56 +1000 (AEST) Received: from localhost ([::1]:44082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IWA-0000ma-E3 for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:07:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKm-0001wX-Tw for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:08 -0400 Received: from mga12.intel.com ([192.55.52.136]:57606) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKk-0007L7-JB for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:08 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101723" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101723" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:58 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770092" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:58 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 32/44] tdx: add kvm_tdx_enabled() accessor for later use Date: Wed, 7 Jul 2021 17:55:02 -0700 Message-Id: <26d88e7618038c1fed501352a04144745abd12ae.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Signed-off-by: Isaku Yamahata --- include/sysemu/tdx.h | 1 + target/i386/kvm/kvm.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/include/sysemu/tdx.h b/include/sysemu/tdx.h index 70eb01348f..f3eced10f9 100644 --- a/include/sysemu/tdx.h +++ b/include/sysemu/tdx.h @@ -6,6 +6,7 @@ #include "hw/i386/pc.h" bool kvm_has_tdx(KVMState *s); +bool kvm_tdx_enabled(void); int tdx_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); #endif diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index af6b5f350e..76c3ea9fac 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -152,6 +152,11 @@ int kvm_set_vm_type(MachineState *ms, int kvm_type) return -ENOTSUP; } +bool kvm_tdx_enabled(void) +{ + return vm_type == KVM_X86_TDX_VM; +} + int kvm_has_pit_state2(void) { return has_pit_state2; From patchwork Thu Jul 8 00:55:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502057 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyln1gwWz9sW8 for ; Thu, 8 Jul 2021 11:05:57 +1000 (AEST) Received: from localhost ([::1]:35436 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IUE-0003NW-V9 for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:05:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38046) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKp-0001zF-84 for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:11 -0400 Received: from mga12.intel.com ([192.55.52.136]:57610) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKk-0007LH-JN for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:09 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101725" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101725" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:58 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770096" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:58 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 33/44] qmp: add query-tdx-capabilities query-tdx command Date: Wed, 7 Jul 2021 17:55:03 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org, Chenyi Qiang Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Chenyi Qiang Add QMP commands that can be used by libvirt to query the TDX capabilities and TDX info. The set of capabilities that needs to be reported is only enabled at the moment, which means TDX is enabled. Signed-off-by: Chenyi Qiang Co-developed-by: Isaku Yamahata Signed-off-by: Isaku Yamahata --- include/sysemu/tdx.h | 6 ++++ qapi/misc-target.json | 59 ++++++++++++++++++++++++++++++++++++++ target/i386/kvm/tdx-stub.c | 10 +++++++ target/i386/kvm/tdx.c | 19 ++++++++++++ target/i386/monitor.c | 23 +++++++++++++++ 5 files changed, 117 insertions(+) diff --git a/include/sysemu/tdx.h b/include/sysemu/tdx.h index f3eced10f9..756f46d2de 100644 --- a/include/sysemu/tdx.h +++ b/include/sysemu/tdx.h @@ -13,4 +13,10 @@ int tdx_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); void tdx_pre_create_vcpu(CPUState *cpu); void tdx_post_init_vcpu(CPUState *cpu); +struct TDXInfo; +struct TDXInfo *tdx_get_info(void); + +struct TDXCapability; +struct TDXCapability *tdx_get_capabilities(void); + #endif diff --git a/qapi/misc-target.json b/qapi/misc-target.json index 5573dcf8f0..c1de95c082 100644 --- a/qapi/misc-target.json +++ b/qapi/misc-target.json @@ -323,3 +323,62 @@ { 'command': 'query-sev-attestation-report', 'data': { 'mnonce': 'str' }, 'returns': 'SevAttestationReport', 'if': 'defined(TARGET_I386)' } + +## +# @TDXInfo: +# +# Information about Trust Domain Extensions (TDX) support +# +# @enabled: true if TDX is active +# +## +{ 'struct': 'TDXInfo', + 'data': { 'enabled': 'bool' }, + 'if': 'defined(TARGET_I386)' +} + +## +# @query-tdx: +# +# Returns information about TDX +# +# Returns: @TdxInfo +# +# +# Example: +# +# -> { "execute": "query-tdx" } +# <- { "return": { "enabled": true } } +# +## +{ 'command': 'query-tdx', 'returns': 'TDXInfo', + 'if': 'defined(TARGET_I386)' } + +## +# @TDXCapability: +# +# The struct describes capability for a TDX +# feature. +# +## +{ 'struct': 'TDXCapability', + 'data': { 'enabled': 'bool' }, + 'if': 'defined(TARGET_I386)' } + +## +# @query-tdx-capabilities: +# +# This command is used to get the TDX capabilities, and is supported on Intel +# X86 platforms only. +# +# Returns: @TDXCapability. +# +# +# Example: +# +# -> { "execute": "query-tdx-capabilities" } +# <- { "return": { 'enabled': 'bool' }} +# +## +{ 'command': 'query-tdx-capabilities', 'returns': 'TDXCapability', + 'if': 'defined(TARGET_I386)' } diff --git a/target/i386/kvm/tdx-stub.c b/target/i386/kvm/tdx-stub.c index 4e1a0a4280..5d8faf0716 100644 --- a/target/i386/kvm/tdx-stub.c +++ b/target/i386/kvm/tdx-stub.c @@ -21,3 +21,13 @@ void tdx_pre_create_vcpu(CPUState *cpu) void tdx_post_init_vcpu(CPUState *cpu) { } + +struct TDXInfo *tdx_get_info(void) +{ + return NULL; +} + +struct TDXCapability *tdx_get_capabilities(void) +{ + return NULL; +} diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 6b560c1c0b..1316d95209 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -22,6 +22,7 @@ #include "hw/i386/tdvf-hob.h" #include "qapi/error.h" #include "qom/object_interfaces.h" +#include "qapi/qapi-types-misc-target.h" #include "standard-headers/asm-x86/kvm_para.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" @@ -39,6 +40,24 @@ bool kvm_has_tdx(KVMState *s) return !!(kvm_check_extension(s, KVM_CAP_VM_TYPES) & BIT(KVM_X86_TDX_VM)); } +TDXInfo *tdx_get_info(void) +{ + TDXInfo *info; + + info = g_new0(TDXInfo, 1); + info->enabled = kvm_enabled() && kvm_tdx_enabled(); + return info; +} + +TDXCapability *tdx_get_capabilities(void) +{ + TDXCapability *cap; + + cap = g_new0(TDXCapability, 1); + cap->enabled = kvm_enabled() && kvm_has_tdx(kvm_state); + return cap; +} + static void __tdx_ioctl(void *state, int ioctl_no, const char *ioctl_name, __u32 metadata, void *data) { diff --git a/target/i386/monitor.c b/target/i386/monitor.c index 119211f0b0..c0be99d13d 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -30,6 +30,7 @@ #include "qapi/qmp/qdict.h" #include "sysemu/kvm.h" #include "sysemu/sev.h" +#include "sysemu/tdx.h" #include "qapi/error.h" #include "sev_i386.h" #include "qapi/qapi-commands-misc-target.h" @@ -763,3 +764,25 @@ qmp_query_sev_attestation_report(const char *mnonce, Error **errp) { return sev_get_attestation_report(mnonce, errp); } + +TDXInfo *qmp_query_tdx(Error **errp) +{ + TDXInfo *info; + + info = tdx_get_info(); + if (!info) { + error_setg(errp, "TDX is not available."); + } + return info; +} + +TDXCapability *qmp_query_tdx_capabilities(Error **errp) +{ + TDXCapability *cap; + + cap = tdx_get_capabilities(); + if (!cap) { + error_setg(errp, "TDX is not available."); + } + return cap; +} From patchwork Thu Jul 8 00:55:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502069 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyt53N9Rz9sXM for ; Thu, 8 Jul 2021 11:11:25 +1000 (AEST) Received: from localhost ([::1]:52756 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IZX-0006Vl-6Q for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:11:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38012) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKn-0001xj-5l for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:09 -0400 Received: from mga12.intel.com ([192.55.52.136]:57600) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKk-0007Kk-KI for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:08 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101727" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101727" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:58 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770101" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:58 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 34/44] target/i386/tdx: set reboot action to shutdown when tdx Date: Wed, 7 Jul 2021 17:55:04 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata In TDX CPU state is also protected, thus vcpu state can't be reset by VMM. It assumes -action reboot=shutdown instead of silently ignoring vcpu reset. TDX module spec version 344425-002US doesn't support vcpu reset by VMM. VM needs to be destroyed and created again to emulate REBOOT_ACTION_RESET. For simplicity, put its responsibility to management system like libvirt because it's difficult for the current qemu implementation to destroy and re-create KVM VM resources with keeping other resources. If management system wants reboot behavior for its users, it needs to - set reboot_action to REBOOT_ACTION_SHUTDOWN, - set shutdown_action to SHUTDOWN_ACTION_PAUSE optionally and, - subscribe VM state change and on reboot, (destroy qemu if SHUTDOWN_ACTION_PAUSE and) start new qemu. Signed-off-by: Isaku Yamahata --- target/i386/kvm/tdx.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 1316d95209..0621317b0a 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -25,6 +25,7 @@ #include "qapi/qapi-types-misc-target.h" #include "standard-headers/asm-x86/kvm_para.h" #include "sysemu/sysemu.h" +#include "sysemu/runstate-action.h" #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" #include "sysemu/tdx.h" @@ -363,6 +364,19 @@ static void tdx_guest_init(Object *obj) qemu_mutex_init(&tdx->lock); + /* + * TDX module spec version 344425-002US doesn't support reset of vcpu by + * VMM. VM needs to be destroyed and created again to emulate + * REBOOT_ACTION_RESET. For simplicity, put its responsibility to + * management system like libvirt. + * + * Management system should + * - set reboot_action to REBOOT_ACTION_SHUTDOWN + * - set shutdown_action to SHUTDOWN_ACTION_PAUSE + * - subscribe VM state and on reboot, destroy qemu and start new qemu + */ + reboot_action = REBOOT_ACTION_SHUTDOWN; + tdx->debug = false; object_property_add_bool(obj, "debug", tdx_guest_get_debug, tdx_guest_set_debug); From patchwork Thu Jul 8 00:55:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502058 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKylp2cPyz9sWS for ; Thu, 8 Jul 2021 11:05:58 +1000 (AEST) Received: from localhost ([::1]:35552 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IUF-0003Rd-VC for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:05:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38096) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKq-00026E-TP for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:12 -0400 Received: from mga12.intel.com ([192.55.52.136]:57606) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKn-0007L7-Ls for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:12 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101729" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101729" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:58 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770104" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:58 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 35/44] ioapic: add property to disable level interrupt Date: Wed, 7 Jul 2021 17:55:05 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata According to TDX module spec version 344425-002US [1], VMM can inject virtual interrupt only via posted interrupt and VMM can't get TDEXIT on guest EOI to virtual x2APIC. Because posted interrupt is edge-trigger and VMM needs to hook guest EOI to re-inject level-triggered interrupt if the level still active, level-trigger isn't supported for TD Guest VM. Prevent trigger mode from setting to be level trigger with warning. Without this guard, qemu can result in unexpected behavior later. [1] https://software.intel.com/content/dam/develop/external/us/en/documents/tdx-module-1eas-v0.85.039.pdf Signed-off-by: Isaku Yamahata --- hw/intc/ioapic.c | 20 ++++++++++++++++++++ hw/intc/ioapic_common.c | 27 +++++++++++++++++++++++++++ include/hw/i386/ioapic_internal.h | 1 + 3 files changed, 48 insertions(+) diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index 264262959d..6d61744961 100644 --- a/hw/intc/ioapic.c +++ b/hw/intc/ioapic.c @@ -364,6 +364,23 @@ ioapic_fix_edge_remote_irr(uint64_t *entry) } } +static inline void +ioapic_fix_level_trigger_unsupported(uint64_t *entry) +{ + if ((*entry & IOAPIC_LVT_TRIGGER_MODE) != + IOAPIC_TRIGGER_EDGE << IOAPIC_LVT_TRIGGER_MODE_SHIFT) { + /* + * ignore a request for level trigger because + * level trigger requires eoi intercept to re-inject + * interrupt when the level is still active. + */ + warn_report_once("attempting to set level-trigger mode " + "while eoi intercept isn't supported"); + *entry &= ~IOAPIC_LVT_TRIGGER_MODE; + *entry |= IOAPIC_TRIGGER_EDGE << IOAPIC_LVT_TRIGGER_MODE_SHIFT; + } +} + static void ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size) @@ -404,6 +421,9 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, s->ioredtbl[index] &= IOAPIC_RW_BITS; s->ioredtbl[index] |= ro_bits; s->irq_eoi[index] = 0; + if (s->level_trigger_unsupported) { + ioapic_fix_level_trigger_unsupported(&s->ioredtbl[index]); + } ioapic_fix_edge_remote_irr(&s->ioredtbl[index]); ioapic_service(s); } diff --git a/hw/intc/ioapic_common.c b/hw/intc/ioapic_common.c index 3cccfc1556..07ee142470 100644 --- a/hw/intc/ioapic_common.c +++ b/hw/intc/ioapic_common.c @@ -150,6 +150,32 @@ static int ioapic_dispatch_post_load(void *opaque, int version_id) return 0; } +static bool ioapic_common_get_level_trigger_unsupported(Object *obj, + Error **errp) +{ + IOAPICCommonState *s = IOAPIC_COMMON(obj); + return s->level_trigger_unsupported; +} + +static void ioapic_common_set_level_trigger_unsupported(Object *obj, bool value, + Error **errp) +{ + DeviceState *dev = DEVICE(obj); + IOAPICCommonState *s = IOAPIC_COMMON(obj); + /* only disabling before realize is allowed */ + assert(!dev->realized); + assert(!s->level_trigger_unsupported); + s->level_trigger_unsupported = value; +} + +static void ioapic_common_init(Object *obj) +{ + object_property_add_bool(obj, "level_trigger_unsupported", + ioapic_common_get_level_trigger_unsupported, + ioapic_common_set_level_trigger_unsupported); + +} + static void ioapic_common_realize(DeviceState *dev, Error **errp) { IOAPICCommonState *s = IOAPIC_COMMON(dev); @@ -207,6 +233,7 @@ static const TypeInfo ioapic_common_type = { .name = TYPE_IOAPIC_COMMON, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(IOAPICCommonState), + .instance_init = ioapic_common_init, .class_size = sizeof(IOAPICCommonClass), .class_init = ioapic_common_class_init, .abstract = true, diff --git a/include/hw/i386/ioapic_internal.h b/include/hw/i386/ioapic_internal.h index 021e715f11..20f2fc7897 100644 --- a/include/hw/i386/ioapic_internal.h +++ b/include/hw/i386/ioapic_internal.h @@ -103,6 +103,7 @@ struct IOAPICCommonState { uint32_t irr; uint64_t ioredtbl[IOAPIC_NUM_PINS]; Notifier machine_done; + bool level_trigger_unsupported; uint8_t version; uint64_t irq_count[IOAPIC_NUM_PINS]; int irq_level[IOAPIC_NUM_PINS]; From patchwork Thu Jul 8 00:55:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502060 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyp34YDGz9sW8 for ; Thu, 8 Jul 2021 11:07:55 +1000 (AEST) Received: from localhost ([::1]:44006 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IW9-0000jJ-Ax for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:07:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38090) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKq-00025s-S8 for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:12 -0400 Received: from mga12.intel.com ([192.55.52.136]:57600) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKp-0007Kk-2Q for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:12 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101731" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101731" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:59 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770108" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:58 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 36/44] hw/i386: add eoi_intercept_unsupported member to X86MachineState Date: Wed, 7 Jul 2021 17:55:06 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Add a new bool member, eoi_intercept_unsupported, to X86MachineState with default value false. Set true when tdx kvm type. Inability to intercept eoi causes impossibility to emulate level triggered interrupt to be re-injected when level is still kept active. which affects interrupt controller emulation. Such new behavior will be introduced later. Signed-off-by: Isaku Yamahata --- hw/i386/x86.c | 1 + include/hw/i386/x86.h | 1 + 2 files changed, 2 insertions(+) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index ed15f6f2cf..9862fe5bc9 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -1311,6 +1311,7 @@ static void x86_machine_initfn(Object *obj) x86ms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); x86ms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); x86ms->bus_lock_ratelimit = 0; + x86ms->eoi_intercept_unsupported = false; object_property_add_str(obj, "kvm-type", x86_get_kvm_type, x86_set_kvm_type); diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index a450b5e226..6eff42550f 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -63,6 +63,7 @@ struct X86MachineState { unsigned pci_irq_mask; unsigned apic_id_limit; uint16_t boot_cpus; + bool eoi_intercept_unsupported; OnOffAuto smm; OnOffAuto acpi; From patchwork Thu Jul 8 00:55:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502070 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKytt70Drz9sXM for ; Thu, 8 Jul 2021 11:12:06 +1000 (AEST) Received: from localhost ([::1]:56184 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IaC-0000Kn-Ey for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:12:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38136) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKs-0002Aw-08 for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:17 -0400 Received: from mga12.intel.com ([192.55.52.136]:57610) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKp-0007LH-Iy for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:13 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101734" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101734" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:59 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770111" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:58 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 37/44] hw/i386: add option to forcibly report edge trigger in acpi tables Date: Wed, 7 Jul 2021 17:55:07 -0700 Message-Id: <7348b3dd8450923bba9b52e6705bdce477197bef.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata When level trigger isn't supported on x86 platform, forcibly report edge trigger in acpi tables. Signed-off-by: Isaku Yamahata --- hw/i386/acpi-build.c | 103 ++++++++++++++++++++++++++++-------------- hw/i386/acpi-common.c | 74 ++++++++++++++++++++++-------- 2 files changed, 124 insertions(+), 53 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 796ffc6f5c..d0d52258b9 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -866,7 +866,8 @@ static void build_dbg_aml(Aml *table) aml_append(table, scope); } -static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) +static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg, + bool level_trigger_unsupported) { Aml *dev; Aml *crs; @@ -878,7 +879,10 @@ static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) aml_append(dev, aml_name_decl("_UID", aml_int(uid))); crs = aml_resource_template(); - aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, + aml_append(crs, aml_interrupt(AML_CONSUMER, + level_trigger_unsupported ? + AML_EDGE : AML_LEVEL, + AML_ACTIVE_HIGH, AML_SHARED, irqs, ARRAY_SIZE(irqs))); aml_append(dev, aml_name_decl("_PRS", crs)); @@ -902,7 +906,8 @@ static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) return dev; } -static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) +static Aml *build_gsi_link_dev(const char *name, uint8_t uid, + uint8_t gsi, bool level_trigger_unsupported) { Aml *dev; Aml *crs; @@ -915,7 +920,10 @@ static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) crs = aml_resource_template(); irqs = gsi; - aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, + aml_append(crs, aml_interrupt(AML_CONSUMER, + level_trigger_unsupported ? + AML_EDGE : AML_LEVEL, + AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); aml_append(dev, aml_name_decl("_PRS", crs)); @@ -934,7 +942,7 @@ static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) } /* _CRS method - get current settings */ -static Aml *build_iqcr_method(bool is_piix4) +static Aml *build_iqcr_method(bool is_piix4, bool level_trigger_unsupported) { Aml *if_ctx; uint32_t irqs; @@ -942,7 +950,9 @@ static Aml *build_iqcr_method(bool is_piix4) Aml *crs = aml_resource_template(); irqs = 0; - aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, + aml_append(crs, aml_interrupt(AML_CONSUMER, + level_trigger_unsupported ? + AML_EDGE : AML_LEVEL, AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); aml_append(method, aml_name_decl("PRR0", crs)); @@ -976,7 +986,7 @@ static Aml *build_irq_status_method(void) return method; } -static void build_piix4_pci0_int(Aml *table) +static void build_piix4_pci0_int(Aml *table, bool level_trigger_unsupported) { Aml *dev; Aml *crs; @@ -997,12 +1007,16 @@ static void build_piix4_pci0_int(Aml *table) aml_append(sb_scope, field); aml_append(sb_scope, build_irq_status_method()); - aml_append(sb_scope, build_iqcr_method(true)); + aml_append(sb_scope, build_iqcr_method(true, level_trigger_unsupported)); - aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); - aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); - aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); - aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); + aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"), + level_trigger_unsupported)); dev = aml_device("LNKS"); { @@ -1011,7 +1025,9 @@ static void build_piix4_pci0_int(Aml *table) crs = aml_resource_template(); irqs = 9; - aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, + aml_append(crs, aml_interrupt(AML_CONSUMER, + level_trigger_unsupported ? + AML_EDGE : AML_LEVEL, AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); aml_append(dev, aml_name_decl("_PRS", crs)); @@ -1097,7 +1113,7 @@ static Aml *build_q35_routing_table(const char *str) return pkg; } -static void build_q35_pci0_int(Aml *table) +static void build_q35_pci0_int(Aml *table, bool level_trigger_unsupported) { Aml *field; Aml *method; @@ -1149,25 +1165,41 @@ static void build_q35_pci0_int(Aml *table) aml_append(sb_scope, field); aml_append(sb_scope, build_irq_status_method()); - aml_append(sb_scope, build_iqcr_method(false)); - - aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); - aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); - aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); - aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); - aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); - aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); - aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); - aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); - - aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); - aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); - aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); - aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); - aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); - aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); - aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); - aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); + aml_append(sb_scope, build_iqcr_method(false, level_trigger_unsupported)); + + aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"), + level_trigger_unsupported)); + + aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10, + level_trigger_unsupported)); + aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11, + level_trigger_unsupported)); + aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12, + level_trigger_unsupported)); + aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13, + level_trigger_unsupported)); + aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14, + level_trigger_unsupported)); + aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15, + level_trigger_unsupported)); + aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16, + level_trigger_unsupported)); + aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17, + level_trigger_unsupported)); aml_append(table, sb_scope); } @@ -1370,6 +1402,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms = PC_MACHINE(machine); PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); X86MachineState *x86ms = X86_MACHINE(machine); + bool level_trigger_unsupported = x86ms->eoi_intercept_unsupported; AcpiMcfgInfo mcfg; bool mcfg_valid = !!acpi_get_mcfg(&mcfg); uint32_t nr_mem = machine->ram_slots; @@ -1404,7 +1437,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, if (pm->pcihp_bridge_en || pm->pcihp_root_en) { build_piix4_pci_hotplug(dsdt); } - build_piix4_pci0_int(dsdt); + build_piix4_pci0_int(dsdt, level_trigger_unsupported); } else { sb_scope = aml_scope("_SB"); dev = aml_device("PCI0"); @@ -1450,7 +1483,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } build_q35_isa_bridge(dsdt); build_isa_devices_aml(dsdt); - build_q35_pci0_int(dsdt); + build_q35_pci0_int(dsdt, level_trigger_unsupported); if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); } diff --git a/hw/i386/acpi-common.c b/hw/i386/acpi-common.c index 1f5947fcf9..90cb05a46d 100644 --- a/hw/i386/acpi-common.c +++ b/hw/i386/acpi-common.c @@ -80,6 +80,7 @@ void acpi_build_madt(GArray *table_data, BIOSLinker *linker, int madt_start = table_data->len; AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(adev); bool x2apic_mode = false; + bool level_trigger_unsupported = x86ms->eoi_intercept_unsupported; AcpiMultipleApicTable *madt; AcpiMadtIoApic *io_apic; @@ -114,26 +115,63 @@ void acpi_build_madt(GArray *table_data, BIOSLinker *linker, io_apic2->interrupt = cpu_to_le32(IO_APIC_SECONDARY_IRQBASE); } - if (x86ms->apic_xrupt_override) { - intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); - intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; - intsrcovr->length = sizeof(*intsrcovr); - intsrcovr->source = 0; - intsrcovr->gsi = cpu_to_le32(2); - intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ - } + if (level_trigger_unsupported) { + /* Force edge trigger */ + if (x86ms->apic_xrupt_override) { + intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); + intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; + intsrcovr->length = sizeof(*intsrcovr); + intsrcovr->source = 0; + intsrcovr->gsi = cpu_to_le32(2); + /* active high, edge triggered */ + intsrcovr->flags = cpu_to_le16(1 | (1 << 2)); + } + + for (i = x86ms->apic_xrupt_override ? 1 : 0; i < 16; i++) { + intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); + intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; + intsrcovr->length = sizeof(*intsrcovr); + intsrcovr->source = i; + intsrcovr->gsi = cpu_to_le32(i); + /* active high, edge triggered */ + intsrcovr->flags = cpu_to_le16(1 | (1 << 2)); + } + + if (x86ms->ioapic2) { + for (i = 0; i < 16; i++) { + intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); + intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; + intsrcovr->length = sizeof(*intsrcovr); + intsrcovr->source = IO_APIC_SECONDARY_IRQBASE + i; + intsrcovr->gsi = cpu_to_le32(IO_APIC_SECONDARY_IRQBASE + i); + /* active high, edge triggered */ + intsrcovr->flags = cpu_to_le16(1 | (1 << 2)); + } + } + } else { + if (x86ms->apic_xrupt_override) { + intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); + intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; + intsrcovr->length = sizeof(*intsrcovr); + intsrcovr->source = 0; + intsrcovr->gsi = cpu_to_le32(2); + /* conforms to bus specifications */ + intsrcovr->flags = cpu_to_le16(0); + } - for (i = 1; i < 16; i++) { - if (!(x86ms->pci_irq_mask & (1 << i))) { - /* No need for a INT source override structure. */ - continue; + for (i = 1; i < 16; i++) { + if (!(x86ms->pci_irq_mask & (1 << i))) { + /* No need for a INT source override structure. */ + continue; + } + intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); + intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; + intsrcovr->length = sizeof(*intsrcovr); + intsrcovr->source = i; + intsrcovr->gsi = cpu_to_le32(i); + /* active high, level triggered */ + intsrcovr->flags = cpu_to_le16(0xd); } - intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); - intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; - intsrcovr->length = sizeof(*intsrcovr); - intsrcovr->source = i; - intsrcovr->gsi = cpu_to_le32(i); - intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ } if (x2apic_mode) { From patchwork Thu Jul 8 00:55:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502062 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyp50j1Bz9sXM for ; Thu, 8 Jul 2021 11:07:57 +1000 (AEST) Received: from localhost ([::1]:44162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IWA-0000pf-Pi for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:07:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38176) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKt-0002B6-9n for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:17 -0400 Received: from mga12.intel.com ([192.55.52.136]:57600) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKr-0007Kk-BC for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:15 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101736" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101736" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:59 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770114" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:59 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 38/44] hw/i386: plug eoi_intercept_unsupported to ioapic Date: Wed, 7 Jul 2021 17:55:08 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata When x86machine doesn't support eoi intercept, set level_trigger_unsupported property of ioapic to true so that ioapic doesn't accept configuration to use level trigger. Signed-off-by: Isaku Yamahata --- hw/i386/microvm.c | 5 +++-- hw/i386/pc_piix.c | 2 +- hw/i386/pc_q35.c | 2 +- hw/i386/x86.c | 10 ++++++++-- include/hw/i386/x86.h | 6 ++++-- 5 files changed, 17 insertions(+), 8 deletions(-) diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index aba0c83219..9b03d051ca 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -175,9 +175,10 @@ static void microvm_devices_init(MicrovmMachineState *mms) &error_abort); isa_bus_irqs(isa_bus, x86ms->gsi); - ioapic_init_gsi(gsi_state, "machine"); + ioapic_init_gsi(gsi_state, "machine", x86ms->eoi_intercept_unsupported); if (ioapics > 1) { - x86ms->ioapic2 = ioapic_init_secondary(gsi_state); + x86ms->ioapic2 = ioapic_init_secondary( + gsi_state, x86ms->eoi_intercept_unsupported); } kvmclock_create(true); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 4c1e31f180..a601c4a916 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -223,7 +223,7 @@ static void pc_init1(MachineState *machine, } if (pcmc->pci_enabled) { - ioapic_init_gsi(gsi_state, "i440fx"); + ioapic_init_gsi(gsi_state, "i440fx", x86ms->eoi_intercept_unsupported); } if (tcg_enabled()) { diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 106f5726cc..464463766c 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -256,7 +256,7 @@ static void pc_q35_init(MachineState *machine) } if (pcmc->pci_enabled) { - ioapic_init_gsi(gsi_state, "q35"); + ioapic_init_gsi(gsi_state, "q35", x86ms->eoi_intercept_unsupported); } if (tcg_enabled()) { diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 9862fe5bc9..88c365b72d 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -608,7 +608,8 @@ void gsi_handler(void *opaque, int n, int level) } } -void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) +void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name, + bool level_trigger_unsupported) { DeviceState *dev; SysBusDevice *d; @@ -622,6 +623,8 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) } object_property_add_child(object_resolve_path(parent_name, NULL), "ioapic", OBJECT(dev)); + object_property_set_bool(OBJECT(dev), "level_trigger_unsupported", + level_trigger_unsupported, NULL); d = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(d, &error_fatal); sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); @@ -631,13 +634,16 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) } } -DeviceState *ioapic_init_secondary(GSIState *gsi_state) +DeviceState *ioapic_init_secondary(GSIState *gsi_state, + bool level_trigger_unsupported) { DeviceState *dev; SysBusDevice *d; unsigned int i; dev = qdev_new(TYPE_IOAPIC); + object_property_set_bool(OBJECT(dev), "level_trigger_unsupported", + level_trigger_unsupported, NULL); d = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(d, &error_fatal); sysbus_mmio_map(d, 0, IO_APIC_SECONDARY_ADDRESS); diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index 6eff42550f..7536e5fb8c 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -140,7 +140,9 @@ typedef struct GSIState { qemu_irq x86_allocate_cpu_irq(void); void gsi_handler(void *opaque, int n, int level); -void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name); -DeviceState *ioapic_init_secondary(GSIState *gsi_state); +void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name, + bool eoi_intercept_unsupported); +DeviceState *ioapic_init_secondary(GSIState *gsi_state, + bool eoi_intercept_unsupported); #endif From patchwork Thu Jul 8 00:55:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502075 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyyF6RJkz9sWS for ; Thu, 8 Jul 2021 11:15:01 +1000 (AEST) Received: from localhost ([::1]:41070 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1Id0-0000ln-Gt for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:14:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38218) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IL2-0002fC-TT for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:24 -0400 Received: from mga12.intel.com ([192.55.52.136]:57606) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IL1-0007L7-8A for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:24 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101738" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101738" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:59 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770117" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:59 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 39/44] ioapic: add property to disallow SMI delivery mode Date: Wed, 7 Jul 2021 17:55:09 -0700 Message-Id: <0855fc584f8ffe862760bc7ef076984b1f2c48a2.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Add a property to prevent ioapic from setting SMI delivery mode. Without this guard, qemu can result in unexpected behavior. Signed-off-by: Isaku Yamahata --- hw/intc/ioapic.c | 18 ++++++++++++++++++ hw/intc/ioapic_common.c | 20 ++++++++++++++++++++ include/hw/i386/ioapic_internal.h | 1 + 3 files changed, 39 insertions(+) diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index 6d61744961..1815fbd282 100644 --- a/hw/intc/ioapic.c +++ b/hw/intc/ioapic.c @@ -381,6 +381,21 @@ ioapic_fix_level_trigger_unsupported(uint64_t *entry) } } +static inline void +ioapic_fix_smi_unsupported(uint64_t *entry) +{ + if ((*entry & IOAPIC_LVT_DELIV_MODE) == + IOAPIC_DM_PMI << IOAPIC_LVT_DELIV_MODE_SHIFT) { + /* + * ignore a request for delivery mode of lowest SMI + */ + warn_report_once("attempting to set delivery mode to SMI" + "which is not supported"); + *entry &= ~IOAPIC_LVT_DELIV_MODE; + *entry |= IOAPIC_DM_FIXED << IOAPIC_LVT_DELIV_MODE_SHIFT; + } +} + static void ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size) @@ -424,6 +439,9 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, if (s->level_trigger_unsupported) { ioapic_fix_level_trigger_unsupported(&s->ioredtbl[index]); } + if (s->smi_unsupported) { + ioapic_fix_smi_unsupported(&s->ioredtbl[index]); + } ioapic_fix_edge_remote_irr(&s->ioredtbl[index]); ioapic_service(s); } diff --git a/hw/intc/ioapic_common.c b/hw/intc/ioapic_common.c index 07ee142470..b8ef7efbad 100644 --- a/hw/intc/ioapic_common.c +++ b/hw/intc/ioapic_common.c @@ -168,12 +168,32 @@ static void ioapic_common_set_level_trigger_unsupported(Object *obj, bool value, s->level_trigger_unsupported = value; } +static bool ioapic_common_get_smi_unsupported(Object *obj, Error **errp) +{ + IOAPICCommonState *s = IOAPIC_COMMON(obj); + return s->smi_unsupported; +} + +static void ioapic_common_set_smi_unsupported(Object *obj, bool value, + Error **errp) +{ + DeviceState *dev = DEVICE(obj); + IOAPICCommonState *s = IOAPIC_COMMON(obj); + /* only disabling before realize is allowed */ + assert(!dev->realized); + assert(!s->smi_unsupported); + s->smi_unsupported = value; +} + static void ioapic_common_init(Object *obj) { object_property_add_bool(obj, "level_trigger_unsupported", ioapic_common_get_level_trigger_unsupported, ioapic_common_set_level_trigger_unsupported); + object_property_add_bool(obj, "smi_unsupported", + ioapic_common_get_smi_unsupported, + ioapic_common_set_smi_unsupported); } static void ioapic_common_realize(DeviceState *dev, Error **errp) diff --git a/include/hw/i386/ioapic_internal.h b/include/hw/i386/ioapic_internal.h index 20f2fc7897..46f22a4f85 100644 --- a/include/hw/i386/ioapic_internal.h +++ b/include/hw/i386/ioapic_internal.h @@ -104,6 +104,7 @@ struct IOAPICCommonState { uint64_t ioredtbl[IOAPIC_NUM_PINS]; Notifier machine_done; bool level_trigger_unsupported; + bool smi_unsupported; uint8_t version; uint64_t irq_count[IOAPIC_NUM_PINS]; int irq_level[IOAPIC_NUM_PINS]; From patchwork Thu Jul 8 00:55:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502073 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKywx6LxHz9s24 for ; Thu, 8 Jul 2021 11:13:53 +1000 (AEST) Received: from localhost ([::1]:36358 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1Ibv-00062p-KJ for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:13:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38230) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IL4-0002iv-2Q for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:27 -0400 Received: from mga12.intel.com ([192.55.52.136]:57610) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IL2-0007LH-AK for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:25 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101740" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101740" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:59 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770120" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:59 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 40/44] hw/i386: add a flag to disallow SMI Date: Wed, 7 Jul 2021 17:55:10 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Add a new flag to X86Machine to disallow SMI and pass it to ioapic creation so that ioapic disallows delivery mode of SMI. Signed-off-by: Isaku Yamahata --- hw/i386/microvm.c | 6 ++++-- hw/i386/pc_piix.c | 3 ++- hw/i386/pc_q35.c | 3 ++- hw/i386/x86.c | 11 +++++++++-- include/hw/i386/x86.h | 7 +++++-- 5 files changed, 22 insertions(+), 8 deletions(-) diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 9b03d051ca..7504324891 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -175,10 +175,12 @@ static void microvm_devices_init(MicrovmMachineState *mms) &error_abort); isa_bus_irqs(isa_bus, x86ms->gsi); - ioapic_init_gsi(gsi_state, "machine", x86ms->eoi_intercept_unsupported); + ioapic_init_gsi(gsi_state, "machine", x86ms->eoi_intercept_unsupported, + x86ms->smi_unsupported); if (ioapics > 1) { x86ms->ioapic2 = ioapic_init_secondary( - gsi_state, x86ms->eoi_intercept_unsupported); + gsi_state, x86ms->eoi_intercept_unsupported, + x86ms->smi_unsupported); } kvmclock_create(true); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index a601c4a916..0958035bf8 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -223,7 +223,8 @@ static void pc_init1(MachineState *machine, } if (pcmc->pci_enabled) { - ioapic_init_gsi(gsi_state, "i440fx", x86ms->eoi_intercept_unsupported); + ioapic_init_gsi(gsi_state, "i440fx", x86ms->eoi_intercept_unsupported, + x86ms->smi_unsupported); } if (tcg_enabled()) { diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 464463766c..1ab8a6a78b 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -256,7 +256,8 @@ static void pc_q35_init(MachineState *machine) } if (pcmc->pci_enabled) { - ioapic_init_gsi(gsi_state, "q35", x86ms->eoi_intercept_unsupported); + ioapic_init_gsi(gsi_state, "q35", x86ms->eoi_intercept_unsupported, + x86ms->smi_unsupported); } if (tcg_enabled()) { diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 88c365b72d..3dc36e3590 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -609,7 +609,8 @@ void gsi_handler(void *opaque, int n, int level) } void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name, - bool level_trigger_unsupported) + bool level_trigger_unsupported, + bool smi_unsupported) { DeviceState *dev; SysBusDevice *d; @@ -625,6 +626,8 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name, "ioapic", OBJECT(dev)); object_property_set_bool(OBJECT(dev), "level_trigger_unsupported", level_trigger_unsupported, NULL); + object_property_set_bool(OBJECT(dev), "smi_unsupported", + smi_unsupported, NULL); d = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(d, &error_fatal); sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); @@ -635,7 +638,8 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name, } DeviceState *ioapic_init_secondary(GSIState *gsi_state, - bool level_trigger_unsupported) + bool level_trigger_unsupported, + bool smi_unsupported) { DeviceState *dev; SysBusDevice *d; @@ -644,6 +648,8 @@ DeviceState *ioapic_init_secondary(GSIState *gsi_state, dev = qdev_new(TYPE_IOAPIC); object_property_set_bool(OBJECT(dev), "level_trigger_unsupported", level_trigger_unsupported, NULL); + object_property_set_bool(OBJECT(dev), "smi_unsupported", + smi_unsupported, NULL); d = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(d, &error_fatal); sysbus_mmio_map(d, 0, IO_APIC_SECONDARY_ADDRESS); @@ -1318,6 +1324,7 @@ static void x86_machine_initfn(Object *obj) x86ms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); x86ms->bus_lock_ratelimit = 0; x86ms->eoi_intercept_unsupported = false; + x86ms->smi_unsupported = false; object_property_add_str(obj, "kvm-type", x86_get_kvm_type, x86_set_kvm_type); diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index 7536e5fb8c..3d1d74d171 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -64,6 +64,7 @@ struct X86MachineState { unsigned apic_id_limit; uint16_t boot_cpus; bool eoi_intercept_unsupported; + bool smi_unsupported; OnOffAuto smm; OnOffAuto acpi; @@ -141,8 +142,10 @@ typedef struct GSIState { qemu_irq x86_allocate_cpu_irq(void); void gsi_handler(void *opaque, int n, int level); void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name, - bool eoi_intercept_unsupported); + bool eoi_intercept_unsupported, + bool smi_unsupported); DeviceState *ioapic_init_secondary(GSIState *gsi_state, - bool eoi_intercept_unsupported); + bool eoi_intercept_unsupported, + bool smi_unsupported); #endif From patchwork Thu Jul 8 00:55:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502079 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKz111P0Jz9sWS for ; Thu, 8 Jul 2021 11:17:25 +1000 (AEST) Received: from localhost ([::1]:49438 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IfK-0006Od-Kj for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:17:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38258) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILA-0002nk-9U for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:32 -0400 Received: from mga12.intel.com ([192.55.52.136]:57600) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IL5-0007Kk-Ol for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:31 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101742" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101742" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:59 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770123" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:59 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 41/44] ioapic: add property to disallow INIT/SIPI delivery mode Date: Wed, 7 Jul 2021 17:55:11 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Add a property to prevent ioapic from setting INIT/SIPI delivery mode. Without this guard, qemu can result in unexpected behavior. Signed-off-by: Isaku Yamahata --- hw/intc/ioapic.c | 19 +++++++++++++++++++ hw/intc/ioapic_common.c | 21 +++++++++++++++++++++ include/hw/i386/ioapic_internal.h | 1 + 3 files changed, 41 insertions(+) diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index 1815fbd282..f7eb9f7146 100644 --- a/hw/intc/ioapic.c +++ b/hw/intc/ioapic.c @@ -396,6 +396,22 @@ ioapic_fix_smi_unsupported(uint64_t *entry) } } +static inline void +ioapic_fix_init_sipi_unsupported(uint64_t *entry) +{ + uint64_t delmode = *entry & IOAPIC_LVT_DELIV_MODE; + if (delmode == IOAPIC_DM_INIT << IOAPIC_LVT_DELIV_MODE_SHIFT || + delmode == IOAPIC_DM_SIPI << IOAPIC_LVT_DELIV_MODE_SHIFT) { + /* + * ignore a request for delivery mode of lowest SMI + */ + warn_report_once("attempting to set delivery mode to INIT/SIPI" + "which is not supported"); + *entry &= ~IOAPIC_LVT_DELIV_MODE; + *entry |= IOAPIC_DM_FIXED << IOAPIC_LVT_DELIV_MODE_SHIFT; + } +} + static void ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size) @@ -442,6 +458,9 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, if (s->smi_unsupported) { ioapic_fix_smi_unsupported(&s->ioredtbl[index]); } + if (s->init_sipi_unsupported) { + ioapic_fix_init_sipi_unsupported(&s->ioredtbl[index]); + } ioapic_fix_edge_remote_irr(&s->ioredtbl[index]); ioapic_service(s); } diff --git a/hw/intc/ioapic_common.c b/hw/intc/ioapic_common.c index b8ef7efbad..018bacbf96 100644 --- a/hw/intc/ioapic_common.c +++ b/hw/intc/ioapic_common.c @@ -185,6 +185,23 @@ static void ioapic_common_set_smi_unsupported(Object *obj, bool value, s->smi_unsupported = value; } +static bool ioapic_common_get_init_sipi_unsupported(Object *obj, Error **errp) +{ + IOAPICCommonState *s = IOAPIC_COMMON(obj); + return s->init_sipi_unsupported; +} + +static void ioapic_common_set_init_sipi_unsupported(Object *obj, bool value, + Error **errp) +{ + DeviceState *dev = DEVICE(obj); + IOAPICCommonState *s = IOAPIC_COMMON(obj); + /* only disabling before realize is allowed */ + assert(!dev->realized); + assert(!s->init_sipi_unsupported); + s->init_sipi_unsupported = value; +} + static void ioapic_common_init(Object *obj) { object_property_add_bool(obj, "level_trigger_unsupported", @@ -194,6 +211,10 @@ static void ioapic_common_init(Object *obj) object_property_add_bool(obj, "smi_unsupported", ioapic_common_get_smi_unsupported, ioapic_common_set_smi_unsupported); + + object_property_add_bool(obj, "init_sipi_unsupported", + ioapic_common_get_init_sipi_unsupported, + ioapic_common_set_init_sipi_unsupported); } static void ioapic_common_realize(DeviceState *dev, Error **errp) diff --git a/include/hw/i386/ioapic_internal.h b/include/hw/i386/ioapic_internal.h index 46f22a4f85..634b97426d 100644 --- a/include/hw/i386/ioapic_internal.h +++ b/include/hw/i386/ioapic_internal.h @@ -105,6 +105,7 @@ struct IOAPICCommonState { Notifier machine_done; bool level_trigger_unsupported; bool smi_unsupported; + bool init_sipi_unsupported; uint8_t version; uint64_t irq_count[IOAPIC_NUM_PINS]; int irq_level[IOAPIC_NUM_PINS]; From patchwork Thu Jul 8 00:55:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502087 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKz752HcZz9sWc for ; Thu, 8 Jul 2021 11:22:41 +1000 (AEST) Received: from localhost ([::1]:38716 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IkQ-00016K-My for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:22:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILG-0002tM-ER for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:42 -0400 Received: from mga12.intel.com ([192.55.52.136]:57606) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILD-0007L7-Ho for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:37 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101744" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101744" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:59 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770126" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:59 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 42/44] hw/i386: add a flag to disable init/sipi delivery mode of interrupt Date: Wed, 7 Jul 2021 17:55:12 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Add a new flag to X86Machine to disallow INIT/SIPI delivery mode of interrupt and pass it to ioapic creation so that ioapic disallows INIT/SIPI delivery mode. Signed-off-by: Isaku Yamahata --- hw/i386/microvm.c | 4 ++-- hw/i386/pc_piix.c | 2 +- hw/i386/pc_q35.c | 2 +- hw/i386/x86.c | 11 +++++++++-- include/hw/i386/x86.h | 7 +++++-- 5 files changed, 18 insertions(+), 8 deletions(-) diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 7504324891..c790adecfb 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -176,11 +176,11 @@ static void microvm_devices_init(MicrovmMachineState *mms) isa_bus_irqs(isa_bus, x86ms->gsi); ioapic_init_gsi(gsi_state, "machine", x86ms->eoi_intercept_unsupported, - x86ms->smi_unsupported); + x86ms->smi_unsupported, x86ms->init_sipi_unsupported); if (ioapics > 1) { x86ms->ioapic2 = ioapic_init_secondary( gsi_state, x86ms->eoi_intercept_unsupported, - x86ms->smi_unsupported); + x86ms->smi_unsupported, x86ms->init_sipi_unsupported); } kvmclock_create(true); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 0958035bf8..940cd0f47b 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -224,7 +224,7 @@ static void pc_init1(MachineState *machine, if (pcmc->pci_enabled) { ioapic_init_gsi(gsi_state, "i440fx", x86ms->eoi_intercept_unsupported, - x86ms->smi_unsupported); + x86ms->smi_unsupported, x86ms->init_sipi_unsupported); } if (tcg_enabled()) { diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 1ab8a6a78b..8f677ec136 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -257,7 +257,7 @@ static void pc_q35_init(MachineState *machine) if (pcmc->pci_enabled) { ioapic_init_gsi(gsi_state, "q35", x86ms->eoi_intercept_unsupported, - x86ms->smi_unsupported); + x86ms->smi_unsupported, x86ms->init_sipi_unsupported); } if (tcg_enabled()) { diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 3dc36e3590..24af05c313 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -610,7 +610,8 @@ void gsi_handler(void *opaque, int n, int level) void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name, bool level_trigger_unsupported, - bool smi_unsupported) + bool smi_unsupported, + bool init_sipi_unsupported) { DeviceState *dev; SysBusDevice *d; @@ -628,6 +629,8 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name, level_trigger_unsupported, NULL); object_property_set_bool(OBJECT(dev), "smi_unsupported", smi_unsupported, NULL); + object_property_set_bool(OBJECT(dev), "init_sipi_unsupported", + init_sipi_unsupported, NULL); d = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(d, &error_fatal); sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); @@ -639,7 +642,8 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name, DeviceState *ioapic_init_secondary(GSIState *gsi_state, bool level_trigger_unsupported, - bool smi_unsupported) + bool smi_unsupported, + bool init_sipi_unsupported) { DeviceState *dev; SysBusDevice *d; @@ -650,6 +654,8 @@ DeviceState *ioapic_init_secondary(GSIState *gsi_state, level_trigger_unsupported, NULL); object_property_set_bool(OBJECT(dev), "smi_unsupported", smi_unsupported, NULL); + object_property_set_bool(OBJECT(dev), "init_sipi_unsupported", + init_sipi_unsupported, NULL); d = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(d, &error_fatal); sysbus_mmio_map(d, 0, IO_APIC_SECONDARY_ADDRESS); @@ -1325,6 +1331,7 @@ static void x86_machine_initfn(Object *obj) x86ms->bus_lock_ratelimit = 0; x86ms->eoi_intercept_unsupported = false; x86ms->smi_unsupported = false; + x86ms->init_sipi_unsupported = false; object_property_add_str(obj, "kvm-type", x86_get_kvm_type, x86_set_kvm_type); diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index 3d1d74d171..bca8c2b57d 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -65,6 +65,7 @@ struct X86MachineState { uint16_t boot_cpus; bool eoi_intercept_unsupported; bool smi_unsupported; + bool init_sipi_unsupported; OnOffAuto smm; OnOffAuto acpi; @@ -143,9 +144,11 @@ qemu_irq x86_allocate_cpu_irq(void); void gsi_handler(void *opaque, int n, int level); void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name, bool eoi_intercept_unsupported, - bool smi_unsupported); + bool smi_unsupported, + bool init_sipi_unsupported); DeviceState *ioapic_init_secondary(GSIState *gsi_state, bool eoi_intercept_unsupported, - bool smi_unsupported); + bool smi_unsupported, + bool init_sipi_unsupported); #endif From patchwork Thu Jul 8 00:55:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502089 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKz8f10Xcz9sWc for ; Thu, 8 Jul 2021 11:24:02 +1000 (AEST) Received: from localhost ([::1]:45872 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1Ilj-0005p8-Ko for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:23:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38314) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILF-0002tK-Sm for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:42 -0400 Received: from mga12.intel.com ([192.55.52.136]:57610) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILE-0007LH-CZ for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:37 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101746" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101746" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:56:00 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770130" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:59 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 43/44] i386/tdx: disallow level interrupt and SMI/INIT/SIPI delivery mode Date: Wed, 7 Jul 2021 17:55:13 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata TDX doesn't allow level interrupt and SMI/INIT/SIPI interrupt delivery mode. So disallow them. Signed-off-by: Isaku Yamahata --- hw/i386/x86.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 24af05c313..c372403b87 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -1307,6 +1307,9 @@ static int x86_kvm_type(MachineState *ms, const char *vm_type) kvm_type = KVM_X86_LEGACY_VM; } else if (!g_ascii_strcasecmp(vm_type, "tdx")) { kvm_type = KVM_X86_TDX_VM; + X86_MACHINE(ms)->eoi_intercept_unsupported = true; + X86_MACHINE(ms)->smi_unsupported = true; + X86_MACHINE(ms)->init_sipi_unsupported = true; } else { error_report("Unknown kvm-type specified '%s'", vm_type); exit(1); From patchwork Thu Jul 8 00:55:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 1502077 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GKyzj7088z9sXM for ; Thu, 8 Jul 2021 11:16:17 +1000 (AEST) Received: from localhost ([::1]:45058 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1IeF-0003Vq-Ki for incoming@patchwork.ozlabs.org; Wed, 07 Jul 2021 21:16:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38330) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILM-0002uN-CR for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:44 -0400 Received: from mga12.intel.com ([192.55.52.136]:57600) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1ILK-0007Kk-KH for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:43 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101748" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101748" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:56:00 -0700 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770134" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:56:00 -0700 From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 44/44] i386/tdx: disable S3/S4 unconditionally Date: Wed, 7 Jul 2021 17:55:14 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Isaku Yamahata Disable S3/S4 unconditionally when TDX is enabled. Because cpu state is protected, it's not allowed to reset cpu state. So S3/S4 can't be supported. Signed-off-by: Isaku Yamahata --- target/i386/kvm/tdx.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 0621317b0a..0dd6d94c2a 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -31,6 +31,9 @@ #include "sysemu/tdx.h" #include "tdx.h" +#include "hw/southbridge/piix.h" +#include "hw/i386/ich9.h" + #define TDX1_TD_ATTRIBUTE_DEBUG BIT_ULL(0) #define TDX1_TD_ATTRIBUTE_PERFMON BIT_ULL(63) #define TDX1_MIN_TSC_FREQUENCY_KHZ (100 * 1000) @@ -103,10 +106,27 @@ static TdxFirmwareEntry *tdx_get_hob_entry(TdxGuest *tdx) static void tdx_finalize_vm(Notifier *notifier, void *unused) { + Object *pm; + bool ambig; MachineState *ms = MACHINE(qdev_get_machine()); TdxGuest *tdx = TDX_GUEST(ms->cgs); TdxFirmwareEntry *entry; + /* + * object look up logic is copied from acpi_get_pm_info() + * @ hw/ie86/acpi-build.c + * This property override needs to be done after machine initialization + * as there is no ordering of creation of objects/properties. + */ + pm = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig); + if (ambig || !pm) { + pm = object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambig); + } + if (!ambig && pm) { + object_property_set_uint(pm, ACPI_PM_PROP_S3_DISABLED, 1, NULL); + object_property_set_uint(pm, ACPI_PM_PROP_S4_DISABLED, 1, NULL); + } + tdvf_hob_create(tdx, tdx_get_hob_entry(tdx)); for_each_fw_entry(&tdx->fw, entry) {