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[60.242.147.73]) by smtp.gmail.com with ESMTPSA id u10sm7010014pfh.123.2021.06.25.19.38.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 19:38:34 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 26 Jun 2021 12:38:15 +1000 Message-Id: <20210626023824.1124164-2-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210626023824.1124164-1-npiggin@gmail.com> References: <20210626023824.1124164-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 01/10] Remove support for POWER8 DD1 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This significantly simplifies the SLW code. Signed-off-by: Nicholas Piggin Reviewed-by: Stewart Smith --- core/cpu.c | 14 +- hw/slw.c | 323 ---------------------------------------------- include/skiboot.h | 3 - 3 files changed, 8 insertions(+), 332 deletions(-) diff --git a/core/cpu.c b/core/cpu.c index d30bef8e0..16660a14d 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -987,7 +987,7 @@ void init_boot_cpu(void) case PVR_TYPE_P8E: case PVR_TYPE_P8: proc_gen = proc_gen_p8; - hile_supported = PVR_VERS_MAJ(mfspr(SPR_PVR)) >= 2; + hile_supported = true; hid0_hile = SPR_HID0_POWER8_HILE; hid0_attn = SPR_HID0_POWER8_ENABLE_ATTN; break; @@ -1029,6 +1029,11 @@ void init_boot_cpu(void) cpu_thread_count = 1; } + if (proc_gen == proc_gen_p8 && (PVR_VERS_MAJ(mfspr(SPR_PVR)) == 1)) { + prerror("CPU: POWER8 DD1 is not supported\n"); + abort(); + } + if (is_power9n(pvr) && (PVR_VERS_MAJ(pvr) == 1)) { prerror("CPU: POWER9N DD1 is not supported\n"); abort(); @@ -1547,7 +1552,7 @@ static int64_t opal_reinit_cpus(uint64_t flags) } /* * Now we need to mark ourselves "active" or we'll be skipped - * by the various "for_each_active_..." calls done by slw_reinit() + * by the various "for_each_active_..." */ this_cpu()->state = cpu_state_active; this_cpu()->in_reinit = true; @@ -1618,10 +1623,7 @@ static int64_t opal_reinit_cpus(uint64_t flags) rc = OPAL_SUCCESS; } - /* Handle P8 DD1 SLW reinit */ - if (flags != 0 && proc_gen == proc_gen_p8 && !hile_supported) - rc = slw_reinit(flags); - else if (flags != 0) + if (flags != 0) rc = OPAL_UNSUPPORTED; /* And undo the above */ diff --git a/hw/slw.c b/hw/slw.c index 625ee886e..2f78b0e6c 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -28,10 +28,6 @@ #include #include -static uint32_t slw_saved_reset[0x100]; - -static bool slw_current_le = false; - enum wakeup_engine_states wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; bool has_deep_states = false; @@ -51,125 +47,6 @@ DEFINE_LOG_ENTRY(OPAL_RC_SLW_REG, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_INFO, OPAL_NA); -static void slw_do_rvwinkle(void *data) -{ - struct cpu_thread *cpu = this_cpu(); - struct cpu_thread *master = data; - uint64_t lpcr = mfspr(SPR_LPCR); - struct proc_chip *chip; - - /* Setup our ICP to receive IPIs */ - icp_prep_for_pm(); - - /* Setup LPCR to wakeup on external interrupts only */ - mtspr(SPR_LPCR, ((lpcr & ~SPR_LPCR_P8_PECE) | SPR_LPCR_P8_PECE2)); - isync(); - - prlog(PR_DEBUG, "SLW: CPU PIR 0x%04x going to rvwinkle...\n", - cpu->pir); - - /* Tell that we got it */ - cpu->state = cpu_state_rvwinkle; - - enter_p8_pm_state(1); - - /* Restore SPRs */ - init_shared_sprs(); - init_replicated_sprs(); - - /* Ok, it's ours again */ - cpu->state = cpu_state_active; - - prlog(PR_DEBUG, "SLW: CPU PIR 0x%04x woken up !\n", cpu->pir); - - /* Cleanup our ICP */ - reset_cpu_icp(); - - /* Resync timebase */ - chiptod_wakeup_resync(); - - /* Restore LPCR */ - mtspr(SPR_LPCR, lpcr); - isync(); - - /* If we are passed a master pointer we are the designated - * waker, let's proceed. If not, return, we are finished. - */ - if (!master) - return; - - prlog(PR_DEBUG, "SLW: CPU PIR 0x%04x waiting for master...\n", - cpu->pir); - - /* Allriiiight... now wait for master to go down */ - while(master->state != cpu_state_rvwinkle) - sync(); - - /* XXX Wait one second ! (should check xscom state ? ) */ - time_wait_ms(1000); - - for_each_chip(chip) { - struct cpu_thread *c; - uint64_t tmp; - for_each_available_core_in_chip(c, chip->id) { - xscom_read(chip->id, - XSCOM_ADDR_P8_EX_SLAVE(pir_to_core_id(c->pir), - EX_PM_IDLE_STATE_HISTORY_PHYP), - &tmp); - prlog(PR_TRACE, "SLW: core %x:%x" - " history: 0x%016llx (mid2)\n", - chip->id, pir_to_core_id(c->pir), - tmp); - } - } - - prlog(PR_DEBUG, "SLW: Waking master (PIR 0x%04x)...\n", master->pir); - - /* Now poke all the secondary threads on the master's core */ - for_each_cpu(cpu) { - if (!cpu_is_sibling(cpu, master) || (cpu == master)) - continue; - icp_kick_cpu(cpu); - - /* Wait for it to claim to be back (XXX ADD TIMEOUT) */ - while(cpu->state != cpu_state_active) - sync(); - } - - /* Now poke the master and be gone */ - icp_kick_cpu(master); -} - -static void slw_patch_reset(void) -{ - uint32_t *src, *dst, *sav; - - src = &reset_patch_start; - dst = (uint32_t *)0x100; - sav = slw_saved_reset; - while(src < &reset_patch_end) { - *(sav++) = *(dst); - *(dst++) = *(src++); - } - sync_icache(); -} - -static void slw_unpatch_reset(void) -{ - extern uint32_t reset_patch_start; - extern uint32_t reset_patch_end; - uint32_t *src, *dst, *sav; - - src = &reset_patch_start; - dst = (uint32_t *)0x100; - sav = slw_saved_reset; - while(src < &reset_patch_end) { - *(dst++) = *(sav++); - src++; - } - sync_icache(); -} - static bool slw_general_init(struct proc_chip *chip, struct cpu_thread *c) { uint32_t core = pir_to_core_id(c->pir); @@ -253,15 +130,6 @@ static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c) return true; } -static bool slw_unset_overrides(struct proc_chip *chip, struct cpu_thread *c) -{ - uint32_t core = pir_to_core_id(c->pir); - - /* XXX FIXME: Save and restore the overrides */ - prlog(PR_DEBUG, "SLW: slw_unset_overrides %x:%x\n", chip->id, core); - return true; -} - static bool slw_set_idle_mode(struct proc_chip *chip, struct cpu_thread *c) { uint32_t core = pir_to_core_id(c->pir); @@ -1055,197 +923,6 @@ void add_cpu_idle_state_properties(void) free(pm_ctrl_reg_mask_buf); } -static void slw_cleanup_core(struct proc_chip *chip, struct cpu_thread *c) -{ - uint64_t tmp; - int rc; - - /* Display history to check transition */ - rc = xscom_read(chip->id, - XSCOM_ADDR_P8_EX_SLAVE(pir_to_core_id(c->pir), - EX_PM_IDLE_STATE_HISTORY_PHYP), - &tmp); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_GET), - "SLW: Failed to read PM_IDLE_STATE_HISTORY\n"); - /* XXX error handling ? return false; */ - } - - prlog(PR_DEBUG, "SLW: core %x:%x history: 0x%016llx (new1)\n", - chip->id, pir_to_core_id(c->pir), tmp); - - rc = xscom_read(chip->id, - XSCOM_ADDR_P8_EX_SLAVE(pir_to_core_id(c->pir), - EX_PM_IDLE_STATE_HISTORY_PHYP), - &tmp); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_GET), - "SLW: Failed to read PM_IDLE_STATE_HISTORY\n"); - /* XXX error handling ? return false; */ - } - - prlog(PR_DEBUG, "SLW: core %x:%x history: 0x%016llx (new2)\n", - chip->id, pir_to_core_id(c->pir), tmp); - - /* - * XXX FIXME: Error out if the transition didn't reach rvwinkle ? - */ - - /* - * XXX FIXME: We should restore a bunch of the EX bits we - * overwrite to sane values here - */ - slw_unset_overrides(chip, c); -} - -static void slw_cleanup_chip(struct proc_chip *chip) -{ - struct cpu_thread *c; - - for_each_available_core_in_chip(c, chip->id) - slw_cleanup_core(chip, c); -} - -static void slw_patch_scans(struct proc_chip *chip, bool le_mode) -{ - int64_t rc; - uint64_t old_val, new_val; - - rc = sbe_xip_get_scalar((void *)chip->slw_base, - "skip_ex_override_ring_scans", &old_val); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: Failed to read scan override on chip %d\n", - chip->id); - return; - } - - new_val = le_mode ? 0 : 1; - - prlog(PR_TRACE, "SLW: Chip %d, LE value was: %lld, setting to %lld\n", - chip->id, old_val, new_val); - - rc = sbe_xip_set_scalar((void *)chip->slw_base, - "skip_ex_override_ring_scans", new_val); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: Failed to set LE mode on chip %d\n", chip->id); - return; - } -} - -int64_t slw_reinit(uint64_t flags) -{ - struct proc_chip *chip; - struct cpu_thread *cpu; - bool has_waker = false; - bool target_le = slw_current_le; - - if (flags & OPAL_REINIT_CPUS_HILE_BE) - target_le = false; - if (flags & OPAL_REINIT_CPUS_HILE_LE) - target_le = true; - - prlog(PR_TRACE, "SLW Reinit from CPU PIR 0x%04x," - " HILE set to %s endian...\n", - this_cpu()->pir, - target_le ? "little" : "big"); - - /* Prepare chips/cores for rvwinkle */ - for_each_chip(chip) { - if (!chip->slw_base) { - log_simple_error(&e_info(OPAL_RC_SLW_INIT), - "SLW: Not found on chip %d\n", chip->id); - return OPAL_HARDWARE; - } - - slw_patch_scans(chip, target_le); - } - slw_current_le = target_le; - - /* XXX Save HIDs ? Or do that in head.S ... */ - - slw_patch_reset(); - - /* rvwinkle everybody and pick one to wake me once I rvwinkle myself */ - for_each_available_cpu(cpu) { - struct cpu_thread *master = NULL; - - if (cpu == this_cpu()) - continue; - - /* Pick up a waker for myself: it must not be a sibling of - * the current CPU and must be a thread 0 (so it gets to - * sync its timebase before doing time_wait_ms() - */ - if (!has_waker && !cpu_is_sibling(cpu, this_cpu()) && - cpu_is_thread0(cpu)) { - has_waker = true; - master = this_cpu(); - } - __cpu_queue_job(cpu, "slw_do_rvwinkle", - slw_do_rvwinkle, master, true); - - /* Wait for it to claim to be down */ - while(cpu->state != cpu_state_rvwinkle) - sync(); - } - - /* XXX Wait one second ! (should check xscom state ? ) */ - prlog(PR_TRACE, "SLW: Waiting one second...\n"); - time_wait_ms(1000); - prlog(PR_TRACE, "SLW: Done.\n"); - - for_each_chip(chip) { - struct cpu_thread *c; - uint64_t tmp; - for_each_available_core_in_chip(c, chip->id) { - xscom_read(chip->id, - XSCOM_ADDR_P8_EX_SLAVE(pir_to_core_id(c->pir), - EX_PM_IDLE_STATE_HISTORY_PHYP), - &tmp); - prlog(PR_DEBUG, "SLW: core %x:%x" - " history: 0x%016llx (mid)\n", - chip->id, pir_to_core_id(c->pir), tmp); - } - } - - - /* Wake everybody except on my core */ - for_each_cpu(cpu) { - if (cpu->state != cpu_state_rvwinkle || - cpu_is_sibling(cpu, this_cpu())) - continue; - icp_kick_cpu(cpu); - - /* Wait for it to claim to be back (XXX ADD TIMEOUT) */ - while(cpu->state != cpu_state_active) - sync(); - } - - /* Did we find a waker ? If we didn't, that means we had no - * other core in the system, we can't do it - */ - if (!has_waker) { - prlog(PR_TRACE, "SLW: No candidate waker, giving up !\n"); - return OPAL_HARDWARE; - } - - /* Our siblings are rvwinkling, and our waker is waiting for us - * so let's just go down now - */ - slw_do_rvwinkle(NULL); - - slw_unpatch_reset(); - - for_each_chip(chip) - slw_cleanup_chip(chip); - - prlog(PR_TRACE, "SLW Reinit complete !\n"); - - return OPAL_SUCCESS; -} - static void slw_patch_regs(struct proc_chip *chip) { struct cpu_thread *c; diff --git a/include/skiboot.h b/include/skiboot.h index d33c02506..331aa9501 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -312,9 +312,6 @@ extern void nx_p9_rng_late_init(void); -/* SLW reinit function for switching core settings */ -extern int64_t slw_reinit(uint64_t flags); - /* Patch SPR in SLW image */ extern int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val); From patchwork Sat Jun 26 02:38:16 2021 Content-Type: text/plain; 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[60.242.147.73]) by smtp.gmail.com with ESMTPSA id u10sm7010014pfh.123.2021.06.25.19.38.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 19:38:36 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 26 Jun 2021 12:38:16 +1000 Message-Id: <20210626023824.1124164-3-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210626023824.1124164-1-npiggin@gmail.com> References: <20210626023824.1124164-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 02/10] Introduce hwprobe facility to avoid hard-coding probe functions X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith hwprobe is a little system to have different hardware probing modules run in the dependency order they choose rather than hard coding that order in core/init.c. Signed-off-by: Stewart Smith --- core/Makefile.inc | 1 + core/hwprobe.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++ core/init.c | 3 ++ include/skiboot.h | 39 +++++++++++++++++++++++++- skiboot.lds.S | 6 ++++ 5 files changed, 118 insertions(+), 1 deletion(-) create mode 100644 core/hwprobe.c diff --git a/core/Makefile.inc b/core/Makefile.inc index 829800e5b..f80019b6a 100644 --- a/core/Makefile.inc +++ b/core/Makefile.inc @@ -13,6 +13,7 @@ CORE_OBJS += timer.o i2c.o rtc.o flash.o sensor.o ipmi-opal.o CORE_OBJS += flash-subpartition.o bitmap.o buddy.o pci-quirk.o powercap.o psr.o CORE_OBJS += pci-dt-slot.o direct-controls.o cpufeatures.o CORE_OBJS += flash-firmware-versions.o opal-dump.o +CORE_OBJS += hwprobe.o ifeq ($(SKIBOOT_GCOV),1) CORE_OBJS += gcov-profiling.o diff --git a/core/hwprobe.c b/core/hwprobe.c new file mode 100644 index 000000000..de331af48 --- /dev/null +++ b/core/hwprobe.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2021 Stewart Smith */ + +#define pr_fmt(fmt) "HWPROBE: " fmt +#include +#include + +static bool hwprobe_deps_satisfied(const struct hwprobe *hwp) +{ + struct hwprobe *hwprobe; + const char *dep; + unsigned int i; + + if (hwp->deps == NULL) + return true; + + dep = hwp->deps[0]; + + prlog(PR_TRACE, "Checking deps for %s\n", hwp->name); + + while (dep != NULL) { + prlog(PR_TRACE, "Checking %s dep %s\n", hwp->name, dep); + hwprobe = &__hwprobes_start; + for (i = 0; &hwprobe[i] < &__hwprobes_end; i++) { + if(strcmp(hwprobe[i].name,dep) == 0 && + !hwprobe[i].probed) + return false; + } + dep++; + } + + prlog(PR_TRACE, "deps for %s are satisfied!\n", hwp->name); + return true; + +} + +void probe_hardware(void) +{ + struct hwprobe *hwprobe; + unsigned int i; + bool work_todo = true; + bool did_something = true; + + while (work_todo) { + work_todo = false; + did_something = false; + hwprobe = &__hwprobes_start; + prlog(PR_DEBUG, "Begin loop\n"); + for (i = 0; &hwprobe[i] < &__hwprobes_end; i++) { + if (hwprobe[i].probed) + continue; + if (hwprobe_deps_satisfied(&hwprobe[i])) { + prlog(PR_DEBUG, "Probing %s...\n", hwprobe[i].name); + if (hwprobe[i].probe) + hwprobe[i].probe(); + did_something = true; + hwprobe[i].probed = true; + } else { + prlog(PR_DEBUG, "Dependencies for %s not yet satisfied, skipping\n", + hwprobe[i].name); + work_todo = true; + } + } + + if (work_todo && !did_something) { + prlog(PR_ERR, "Cannot satisfy dependencies! Bailing out\n"); + break; + } + } +} diff --git a/core/init.c b/core/init.c index d5ba67edd..ed3229172 100644 --- a/core/init.c +++ b/core/init.c @@ -1333,6 +1333,9 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) probe_npu2(); probe_npu3(); + /* Probe all HWPROBE hardware we have code linked for*/ + probe_hardware(); + /* Initialize PCI */ pci_init_slots(); diff --git a/include/skiboot.h b/include/skiboot.h index 331aa9501..d104c7a89 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -1,5 +1,7 @@ // SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later -/* Copyright 2013-2019 IBM Corp. */ +/* Copyright 2013-2019 IBM Corp. + * Copyright 2021 Stewart Smith + */ #ifndef __SKIBOOT_H #define __SKIBOOT_H @@ -342,4 +344,39 @@ extern int fake_nvram_info(uint32_t *total_size); extern int fake_nvram_start_read(void *dst, uint32_t src, uint32_t len); extern int fake_nvram_write(uint32_t offset, void *src, uint32_t size); +/* + * A bunch of hardware needs to be probed, sometimes in a particular order. + * Very simple dependency graph, with a even simpler way to resolve it. + * But it means we can now at link time choose what hardware we support. + * This struct should not be defined directly but with the macros. + */ +struct hwprobe { + const char *name; + void (*probe)(void); + + bool probed; + + /* NULL or NULL-terminated array of strings */ + const char **deps; +}; + +#define DEFINE_HWPROBE(__name, __probe) \ +static const struct hwprobe __used __section(".hwprobes") hwprobe_##__name = { \ + .name = #__name, \ + .probe = __probe, \ + .deps = NULL, \ +} + +#define DEFINE_HWPROBE_DEPS(__name, __probe, ...) \ +static const struct hwprobe __used __section(".hwprobes") hwprobe_##__name = { \ + .name = #__name, \ + .probe = __probe, \ + .deps = (const char *[]){ __VA_ARGS__, NULL}, \ +} + +extern struct hwprobe __hwprobes_start; +extern struct hwprobe __hwprobes_end; + +extern void probe_hardware(void); + #endif /* __SKIBOOT_H */ diff --git a/skiboot.lds.S b/skiboot.lds.S index 5a7f9e316..c8e6e747c 100644 --- a/skiboot.lds.S +++ b/skiboot.lds.S @@ -164,6 +164,12 @@ SECTIONS __platforms_end = .; } + .hwprobes : { + __hwprobes_start = .; + KEEP(*(.hwprobes)) + __hwprobes_end = .; + } + /* Relocations */ . = ALIGN(0x10); .dynamic : { From patchwork Sat Jun 26 02:38:17 2021 Content-Type: text/plain; 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[60.242.147.73]) by smtp.gmail.com with ESMTPSA id u10sm7010014pfh.123.2021.06.25.19.38.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 19:38:38 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 26 Jun 2021 12:38:17 +1000 Message-Id: <20210626023824.1124164-4-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210626023824.1124164-1-npiggin@gmail.com> References: <20210626023824.1124164-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 03/10] hwprobe: convert PHB, NPU subsystems to hwprobe X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith [npiggin: split out from initial hwprobe pach] Signed-off-by: Stewart Smith --- core/init.c | 11 ----------- hw/npu.c | 2 ++ hw/npu2-common.c | 2 ++ hw/npu3.c | 2 ++ hw/phb3.c | 2 +- hw/phb4.c | 2 ++ 6 files changed, 9 insertions(+), 12 deletions(-) diff --git a/core/init.c b/core/init.c index ed3229172..3d190e4ff 100644 --- a/core/init.c +++ b/core/init.c @@ -1322,17 +1322,6 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* NX init */ nx_init(); - /* Probe PHB3 on P8 */ - probe_phb3(); - - /* Probe PHB4 on P9 */ - probe_phb4(); - - /* Probe NPUs */ - probe_npu(); - probe_npu2(); - probe_npu3(); - /* Probe all HWPROBE hardware we have code linked for*/ probe_hardware(); diff --git a/hw/npu.c b/hw/npu.c index dba7ee50f..2b5364c33 100644 --- a/hw/npu.c +++ b/hw/npu.c @@ -1691,3 +1691,5 @@ void probe_npu(void) dt_for_each_compatible(dt_root, np, "ibm,power8-npu-pciex") npu_create_phb(np); } + +DEFINE_HWPROBE_DEPS(npu, probe_npu, "phb3"); diff --git a/hw/npu2-common.c b/hw/npu2-common.c index 3bc9bcee6..87ebf8232 100644 --- a/hw/npu2-common.c +++ b/hw/npu2-common.c @@ -679,3 +679,5 @@ void probe_npu2(void) setup_devices(npu); } } + +DEFINE_HWPROBE_DEPS(npu2, probe_npu2, "phb4"); diff --git a/hw/npu3.c b/hw/npu3.c index 03461373e..92af96b23 100644 --- a/hw/npu3.c +++ b/hw/npu3.c @@ -547,3 +547,5 @@ void probe_npu3(void) npu3_init(npu); } } + +DEFINE_HWPROBE_DEPS(npu3, probe_npu3, "phb4"); diff --git a/hw/phb3.c b/hw/phb3.c index 8af6b6164..320023e57 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -5049,4 +5049,4 @@ void probe_phb3(void) phb3_create(np); } - +DEFINE_HWPROBE(phb3, probe_phb3); diff --git a/hw/phb4.c b/hw/phb4.c index 31f9fa250..7c7ba994e 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -6087,3 +6087,5 @@ void probe_phb4(void) dt_for_each_compatible(dt_root, np, "ibm,power9-pciex") phb4_create(np); } + +DEFINE_HWPROBE(phb4, probe_phb4); From patchwork Sat Jun 26 02:38:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1497536 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=jO7dvs4A; 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[60.242.147.73]) by smtp.gmail.com with ESMTPSA id u10sm7010014pfh.123.2021.06.25.19.38.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 19:38:41 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 26 Jun 2021 12:38:18 +1000 Message-Id: <20210626023824.1124164-5-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210626023824.1124164-1-npiggin@gmail.com> References: <20210626023824.1124164-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 04/10] Add CONFIG_P8 with PHB3 behind it X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith We can use a base CPU of POWER9 if we don't have P8. We can also hide PHB3 code behind this, and shave 12kb off skiboot.lid.xz [npiggin: add cpp define, fail gracefully on P8] Signed-off-by: Stewart Smith --- Makefile | 2 ++ Makefile.main | 15 ++++++++++++++- core/cpu.c | 11 +++++++++-- hw/Makefile.inc | 8 ++++++-- 4 files changed, 31 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index d236df9ec..625f212ea 100644 --- a/Makefile +++ b/Makefile @@ -59,6 +59,8 @@ ELF_ABI_v2 ?= $(LITTLE_ENDIAN) DEAD_CODE_ELIMINATION ?= 0 # Try to build without FSP code CONFIG_FSP?=1 +# Try to build without POWER8 support +CONFIG_P8?=1 # # Where is the source directory, must be a full path (no ~) diff --git a/Makefile.main b/Makefile.main index d21f27be3..ef8ee6289 100644 --- a/Makefile.main +++ b/Makefile.main @@ -99,7 +99,11 @@ CPPFLAGS += -DDEBUG -DCCAN_LIST_DEBUG endif CFLAGS := -fno-strict-aliasing -pie -fpie -fno-pic -m64 -fno-asynchronous-unwind-tables +ifeq ($(CONFIG_P8),1) CFLAGS += -mcpu=power8 +else +CFLAGS += -mcpu=power9 +endif CFLAGS += -Wl,--oformat,elf64-powerpc -ggdb # r13,r14,r15 are preserved for OS to use as fixed registers. # These could be saved and restored in and out of skiboot, but it's more @@ -159,6 +163,10 @@ else CFLAGS += -fno-stack-protector endif +# Add preprocessor defines for CONFIG_ options here +ifeq ($(CONFIG_P8),1) +CFLAGS += -DCONFIG_P8=1 +endif CFLAGS += $(call try-cflag,$(CC),-Wjump-misses-init) \ $(call try-cflag,$(CC),-Wsuggest-attribute=const) \ @@ -174,7 +182,12 @@ LDFLAGS := -m64 -static -nostdlib -pie LDFLAGS += -Wl,-pie LDFLAGS += -Wl,-Ttext-segment,$(LD_TEXT) -Wl,-N -Wl,--build-id=none LDFLAGS += -Wl,--no-multi-toc -LDFLAGS += -mcpu=power8 -Wl,--oformat,elf64-powerpc +ifeq ($(CONFIG_P8),1) +LDFLAGS += -mcpu=power8 +else +LDFLAGS += -mcpu=power9 +endif +LDFLAGS += -Wl,--oformat,elf64-powerpc LDFLAGS_FINAL = -m elf64lppc --no-multi-toc -N --build-id=none --whole-archive LDFLAGS_FINAL += -static -nostdlib -pie -Ttext-segment=$(LD_TEXT) --oformat=elf64-powerpc LDFLAGS_FINAL += --orphan-handling=warn diff --git a/core/cpu.c b/core/cpu.c index 16660a14d..353a0372d 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -1029,9 +1029,16 @@ void init_boot_cpu(void) cpu_thread_count = 1; } - if (proc_gen == proc_gen_p8 && (PVR_VERS_MAJ(mfspr(SPR_PVR)) == 1)) { - prerror("CPU: POWER8 DD1 is not supported\n"); + if (proc_gen == proc_gen_p8) { +#ifdef CONFIG_P8 + if (PVR_VERS_MAJ(mfspr(SPR_PVR)) == 1) { + prerror("CPU: POWER8 DD1 is not supported\n"); + abort(); + } +#else + prerror("CPU: POWER8 detected but CONFIG_P8 not set\n"); abort(); +#endif } if (is_power9n(pvr) && (PVR_VERS_MAJ(pvr) == 1)) { diff --git a/hw/Makefile.inc b/hw/Makefile.inc index a7f450cf7..1f042c239 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -3,13 +3,17 @@ SUBDIRS += hw HW_OBJS = xscom.o chiptod.o lpc.o lpc-uart.o psi.o HW_OBJS += homer.o slw.o occ.o fsi-master.o centaur.o imc.o HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-compress.o nx-842.o nx-gzip.o -HW_OBJS += phb3.o sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o -HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o +HW_OBJS += sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o +HW_OBJS += dts.o lpc-rtc.o xive.o phb4.o HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o HW_OBJS += npu-opal.o npu3.o npu3-nvlink.o npu3-hw-procedures.o HW_OBJS += ocmb.o +HW_OBJS += npu.o npu-hw-procedures.o +ifeq ($(CONFIG_P8),1) +HW_OBJS += phb3.o +endif HW=hw/built-in.a include $(SRC)/hw/fsp/Makefile.inc From patchwork Sat Jun 26 02:38:19 2021 Content-Type: text/plain; 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[60.242.147.73]) by smtp.gmail.com with ESMTPSA id u10sm7010014pfh.123.2021.06.25.19.38.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 19:38:43 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 26 Jun 2021 12:38:19 +1000 Message-Id: <20210626023824.1124164-6-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210626023824.1124164-1-npiggin@gmail.com> References: <20210626023824.1124164-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 05/10] hw/slw: Move P8 bits behind CONFIG_P8 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This saves about 3kB from skiboot.lid.xz Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 2 + hw/slw.c | 136 +++++++++++++++++++++++-------------------- libpore/Makefile.inc | 8 ++- 3 files changed, 80 insertions(+), 66 deletions(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 03777543a..c7288e3d6 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -267,6 +267,7 @@ static void cleanup_cpu_state(void) if (cpu_is_thread0(cpu)) { /* XXX should reset the SLW SPR restore values*/ +#ifdef CONFIG_P8 if (proc_gen == proc_gen_p8) { /* If somebody was in fast_sleep, we may have a * workaround to undo @@ -282,6 +283,7 @@ static void cleanup_cpu_state(void) */ cleanup_local_tlb(); } +#endif /* And we might have lost TB sync */ chiptod_wakeup_resync(); diff --git a/hw/slw.c b/hw/slw.c index 2f78b0e6c..9428e155d 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -31,19 +31,20 @@ enum wakeup_engine_states wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; bool has_deep_states = false; -DEFINE_LOG_ENTRY(OPAL_RC_SLW_INIT, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, - OPAL_PLATFORM_FIRMWARE, OPAL_PREDICTIVE_ERR_GENERAL, - OPAL_NA); - DEFINE_LOG_ENTRY(OPAL_RC_SLW_SET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_INFO, OPAL_NA); -DEFINE_LOG_ENTRY(OPAL_RC_SLW_GET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, +DEFINE_LOG_ENTRY(OPAL_RC_SLW_REG, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_INFO, OPAL_NA); -DEFINE_LOG_ENTRY(OPAL_RC_SLW_REG, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, +#ifdef CONFIG_P8 +DEFINE_LOG_ENTRY(OPAL_RC_SLW_INIT, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, + OPAL_PLATFORM_FIRMWARE, OPAL_PREDICTIVE_ERR_GENERAL, + OPAL_NA); + +DEFINE_LOG_ENTRY(OPAL_RC_SLW_GET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_INFO, OPAL_NA); @@ -97,39 +98,6 @@ static bool slw_set_overrides(struct proc_chip *chip, struct cpu_thread *c) return true; } -static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c) -{ - uint64_t tmp; - int rc; - uint32_t core = pir_to_core_id(c->pir); - - /* Clear special wakeup bits that could hold power mgt */ - rc = xscom_write(chip->id, - XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP), - 0); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_SET), - "SLW: Failed to write EC_PPM_SPECIAL_WKUP_HYP\n"); - return false; - } - /* Read back for debug */ - rc = xscom_read(chip->id, - XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP), - &tmp); - if (tmp) - prlog(PR_WARNING, - "SLW: core %d EC_PPM_SPECIAL_WKUP_HYP read 0x%016llx\n", - core, tmp); - rc = xscom_read(chip->id, - XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_OTR), - &tmp); - if (tmp) - prlog(PR_WARNING, - "SLW: core %d EC_PPM_SPECIAL_WKUP_OTR read 0x%016llx\n", - core, tmp); - return true; -} - static bool slw_set_idle_mode(struct proc_chip *chip, struct cpu_thread *c) { uint32_t core = pir_to_core_id(c->pir); @@ -221,6 +189,40 @@ static bool idle_prepare_core(struct proc_chip *chip, struct cpu_thread *c) return true; } +#endif + +static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c) +{ + uint64_t tmp; + int rc; + uint32_t core = pir_to_core_id(c->pir); + + /* Clear special wakeup bits that could hold power mgt */ + rc = xscom_write(chip->id, + XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP), + 0); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_SET), + "SLW: Failed to write EC_PPM_SPECIAL_WKUP_HYP\n"); + return false; + } + /* Read back for debug */ + rc = xscom_read(chip->id, + XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP), + &tmp); + if (tmp) + prlog(PR_WARNING, + "SLW: core %d EC_PPM_SPECIAL_WKUP_HYP read 0x%016llx\n", + core, tmp); + rc = xscom_read(chip->id, + XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_OTR), + &tmp); + if (tmp) + prlog(PR_WARNING, + "SLW: core %d EC_PPM_SPECIAL_WKUP_OTR read 0x%016llx\n", + core, tmp); + return true; +} /* Define device-tree fields */ #define MAX_NAME_LEN 16 @@ -923,31 +925,6 @@ void add_cpu_idle_state_properties(void) free(pm_ctrl_reg_mask_buf); } -static void slw_patch_regs(struct proc_chip *chip) -{ - struct cpu_thread *c; - void *image = (void *)chip->slw_base; - int rc; - - for_each_available_cpu(c) { - if (c->chip_id != chip->id) - continue; - - /* Clear HRMOR */ - rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, - P8_SPR_HRMOR, 0, - cpu_get_core_index(c), - cpu_get_thread_index(c)); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: Failed to set HRMOR for CPU %x\n", - c->pir); - } - - /* XXX Add HIDs etc... */ - } -} - static void slw_init_chip_p9(struct proc_chip *chip) { struct cpu_thread *c; @@ -975,6 +952,32 @@ static bool slw_image_check_p9(struct proc_chip *chip) } +#ifdef CONFIG_P8 +static void slw_patch_regs(struct proc_chip *chip) +{ + struct cpu_thread *c; + void *image = (void *)chip->slw_base; + int rc; + + for_each_available_cpu(c) { + if (c->chip_id != chip->id) + continue; + + /* Clear HRMOR */ + rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, + P8_SPR_HRMOR, 0, + cpu_get_core_index(c), + cpu_get_thread_index(c)); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: Failed to set HRMOR for CPU %x\n", + c->pir); + } + + /* XXX Add HIDs etc... */ + } +} + static bool slw_image_check_p8(struct proc_chip *chip) { int64_t rc; @@ -1124,6 +1127,7 @@ static int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t enter) } opal_call(OPAL_CONFIG_CPU_IDLE_STATE, opal_config_cpu_idle_state, 2); +#endif int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) { @@ -1159,6 +1163,7 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) rc = p9_stop_save_cpureg((void *)chip->homer_base, sprn, val, cpu_pir); +#ifdef CONFIG_P8 } else if (proc_gen == proc_gen_p8) { int spr_is_supported = 0; void *image; @@ -1182,6 +1187,7 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) sprn, val, cpu_get_core_index(c), cpu_get_thread_index(c)); +#endif } else { log_simple_error(&e_info(OPAL_RC_SLW_REG), "SLW: proc_gen not supported\n"); @@ -1213,6 +1219,7 @@ void slw_init(void) return; } if (proc_gen == proc_gen_p8) { +#ifdef CONFIG_P8 for_each_chip(chip) { slw_init_chip_p8(chip); if(slw_image_check_p8(chip)) @@ -1221,6 +1228,7 @@ void slw_init(void) slw_late_init_p8(chip); } p8_sbe_init_timer(); +#endif } else if (proc_gen == proc_gen_p9) { for_each_chip(chip) { slw_init_chip_p9(chip); diff --git a/libpore/Makefile.inc b/libpore/Makefile.inc index 1060a0492..701bb1004 100644 --- a/libpore/Makefile.inc +++ b/libpore/Makefile.inc @@ -1,5 +1,9 @@ -LIBPORE_SRCS = p8_pore_table_gen_api_fixed.C p9_stop_api.C p9_stop_util.C -LIBPORE_SRCS += p8_pore_table_static_data.c sbe_xip_image.c pore_inline_assembler.c +LIBPORE_SRCS = p9_stop_api.C p9_stop_util.C +LIBPORE_SRCS += sbe_xip_image.c pore_inline_assembler.c +ifeq ($(CONFIG_P8),1) +LIBPORE_SRCS += p8_pore_table_gen_api_fixed.C p8_pore_table_static_data.c +endif + LIBPORE_OBJS_1 = $(LIBPORE_SRCS:%.c=%.o) LIBPORE_OBJS = $(LIBPORE_OBJS_1:%.C=%.o) SUBDIRS += libpore From patchwork Sat Jun 26 02:38:20 2021 Content-Type: text/plain; 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[60.242.147.73]) by smtp.gmail.com with ESMTPSA id u10sm7010014pfh.123.2021.06.25.19.38.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 19:38:46 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 26 Jun 2021 12:38:20 +1000 Message-Id: <20210626023824.1124164-7-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210626023824.1124164-1-npiggin@gmail.com> References: <20210626023824.1124164-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 06/10] hwprobe: convert vas_init(), nx_init() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith [npiggin: remove imc_init because it moved later in boot (fbcbd4e47c)] Signed-off-by: Stewart Smith --- core/init.c | 6 ------ hw/nx.c | 2 ++ hw/vas.c | 2 ++ 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/core/init.c b/core/init.c index 3d190e4ff..a3601d0c8 100644 --- a/core/init.c +++ b/core/init.c @@ -1316,12 +1316,6 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* Catalog decompression routine */ imc_decompress_catalog(); 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[60.242.147.73]) by smtp.gmail.com with ESMTPSA id u10sm7010014pfh.123.2021.06.25.19.38.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 19:38:48 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 26 Jun 2021 12:38:21 +1000 Message-Id: <20210626023824.1124164-8-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210626023824.1124164-1-npiggin@gmail.com> References: <20210626023824.1124164-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 07/10] npu: move npu_set_fence_state() to phb_ops X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith This lets us consider not building in npu.o Signed-off-by: Stewart Smith --- core/hmi.c | 2 +- hw/npu.c | 7 +++++-- include/npu.h | 1 - include/pci.h | 3 +++ 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/core/hmi.c b/core/hmi.c index 120fe4b57..ee4c168e3 100644 --- a/core/hmi.c +++ b/core/hmi.c @@ -768,7 +768,7 @@ static void find_npu_checkstop_reason(int flat_chip_id, npu_fir_action0, npu_fir_action1); /* Set the NPU to fenced since it can't recover. */ - npu_set_fence_state(p, true); + phb->ops->set_fence_state(phb, true); /* Set up the HMI event */ hmi_evt->severity = OpalHMI_SEV_WARNING; diff --git a/hw/npu.c b/hw/npu.c index 2b5364c33..6992e7e72 100644 --- a/hw/npu.c +++ b/hw/npu.c @@ -925,7 +925,9 @@ static int64_t npu_eeh_next_error(struct phb *phb, } /* For use in error injection and handling. */ -void npu_set_fence_state(struct npu *p, bool fence) { +static void npu_set_fence_state(struct phb *phb, bool fence) { + struct npu *p = phb_to_npu(phb); + p->fenced = fence; if (fence) @@ -968,7 +970,7 @@ static int64_t npu_err_inject(struct phb *phb, uint64_t pe_number, return OPAL_PARAMETER; } else if (type == 1) { /* Emulate fence mode. */ - npu_set_fence_state(p, true); + npu_set_fence_state(phb, true); } else { /* Cause a freeze with an invalid MMIO read. If the BAR is not * enabled, this will checkstop the machine. @@ -1012,6 +1014,7 @@ static const struct phb_ops npu_ops = { .get_diag_data2 = NULL, .set_capi_mode = NULL, .set_capp_recovery = NULL, + .set_fence_state = npu_set_fence_state, }; static void assign_mmio_bars(uint32_t gcid, uint32_t xscom, diff --git a/include/npu.h b/include/npu.h index 50cc9c9fc..45818a28f 100644 --- a/include/npu.h +++ b/include/npu.h @@ -153,7 +153,6 @@ int64_t npu_dev_procedure(void *dev, struct pci_cfg_reg_filter *pcrf, uint32_t offset, uint32_t len, uint32_t *data, bool write); -void npu_set_fence_state(struct npu *p, bool fence); void npu_dev_procedure_reset(struct npu_dev *dev); #define NPUDBG(p, fmt, a...) prlog(PR_DEBUG, "NPU%d: " fmt, \ diff --git a/include/pci.h b/include/pci.h index eb23a6d9b..05d02171b 100644 --- a/include/pci.h +++ b/include/pci.h @@ -340,6 +340,9 @@ struct phb_ops { /* Get/set PBCQ Tunnel BAR register */ void (*get_tunnel_bar)(struct phb *phb, uint64_t *addr); int64_t (*set_tunnel_bar)(struct phb *phb, uint64_t addr); + + /* Currently only used by NPU HMI code */ + void (*set_fence_state)(struct phb *phb, bool fence); }; enum phb_type { From patchwork Sat Jun 26 02:38:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1497540 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=G5CIPc+b; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GBdP474Ylz9sW8 for ; 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[60.242.147.73]) by smtp.gmail.com with ESMTPSA id u10sm7010014pfh.123.2021.06.25.19.38.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 19:38:50 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 26 Jun 2021 12:38:22 +1000 Message-Id: <20210626023824.1124164-9-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210626023824.1124164-1-npiggin@gmail.com> References: <20210626023824.1124164-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 08/10] npu: Move npu.o and npu-hw-procedules.o under CONIFG_P8 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith This saves an extra 6kb of skiboot.lid.xz. Signed-off-by: Stewart Smith --- hw/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/Makefile.inc b/hw/Makefile.inc index 1f042c239..ebb9ca86a 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -10,9 +10,9 @@ HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o HW_OBJS += npu-opal.o npu3.o npu3-nvlink.o npu3-hw-procedures.o HW_OBJS += ocmb.o -HW_OBJS += npu.o npu-hw-procedures.o ifeq ($(CONFIG_P8),1) HW_OBJS += phb3.o +HW_OBJS += npu.o npu-hw-procedures.o endif HW=hw/built-in.a From patchwork Sat Jun 26 02:38:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1497541 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=lF3X+5+V; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GBdP90nKFz9sWX for ; Sat, 26 Jun 2021 12:39:25 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4GBdP95tf1z3c2N for ; Sat, 26 Jun 2021 12:39:25 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=lF3X+5+V; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::102f; helo=mail-pj1-x102f.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=lF3X+5+V; dkim-atps=neutral Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4GBdNc3w50z3btf for ; Sat, 26 Jun 2021 12:38:56 +1000 (AEST) Received: by mail-pj1-x102f.google.com with SMTP id bb20so6484301pjb.3 for ; Fri, 25 Jun 2021 19:38:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GvnCKoF29kdbmkxah4LSbdMv9etwRxhflcL2rCiuvU4=; b=lF3X+5+VzeqX/nUtAjr9jjvnZPwStDsA4DgTahuPwFr0mB9lBH97AL8k3qHZDzKQZU tLYvfTKdg+JCGuSwHOsTNB7kzAnRXYvTtX5rT8rqJVM9BO04iqZK1EXUmy4AdkAXH8/8 Yzsiftg2DLGsFoMWJoLAJ9Q1mYbM1za1B5llgLmuqKn3g4CDpPlo1C+DcjaiH7XqJ+xC VPs4kjwH+8vhk2l3EV/1rl+PnF9suEbVNLBuNhPErPeMx+AnDeZqJyYidaUraVGs7wIE BpDQwJJGBDJQ11TxPQR/LcJoAe0DA2C0pv45ByHC3SgJ/G+LKMZ6dD5+CucxVEMzFXuU 4MdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GvnCKoF29kdbmkxah4LSbdMv9etwRxhflcL2rCiuvU4=; b=Qx+atQ+b72CjrkGIm1yRdxdIrkawgG42iLl+3G7hpzTkH7C/X56WdBpezhURK1yHbT Fj8cq4Hq1yvzljXzoiQqTxHNGFccnHbqy16ZeykjhnuJalJNLLabbdUfXyiynJXUiskw upjpQZZ98yvIjQq3WHePrZVZbajmuDnRxq0w9fRrZM9Sgo+8vU0VXs+krOLLD3A+Cta2 7iEwLwdUrkQLrdBwxKgyvsqhFskGqA+Krdxe6Jq7NrCMVCwleweTg1303g4YhogetiF2 eay8ijxOMqmzf2mWDQYogTedKucpqPyr0E14hH9GRV+9y2LY2xTU1uEdnByd1ttN8872 kf4A== X-Gm-Message-State: AOAM531UhR/wV8d5W+jtINo+xBXxmSW0ferLi+NMO9VKKsrVQZFyz4G6 87phzzdSdekFf8xUbJZfHc5S7d92HfQ= X-Google-Smtp-Source: ABdhPJy7uIaLbAyzXfdqIBuRrW1BfofPRkc6uT7EGi2h+oy8vU9n99mrJA4jz96XvkjZOGol7MUsHA== X-Received: by 2002:a17:90a:4a91:: with SMTP id f17mr25034453pjh.175.1624675133156; Fri, 25 Jun 2021 19:38:53 -0700 (PDT) Received: from bobo.ozlabs.ibm.com (60-242-147-73.tpgi.com.au. [60.242.147.73]) by smtp.gmail.com with ESMTPSA id u10sm7010014pfh.123.2021.06.25.19.38.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 19:38:52 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 26 Jun 2021 12:38:23 +1000 Message-Id: <20210626023824.1124164-10-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210626023824.1124164-1-npiggin@gmail.com> References: <20210626023824.1124164-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 09/10] platforms: put P8 platforms behind CONFIG_P8 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith Shaves an additional 4kb off skiboot.lid.xz. Signed-off-by: Stewart Smith --- platforms/astbmc/Makefile.inc | 12 ++++++++---- platforms/ibm-fsp/Makefile.inc | 7 ++++++- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/platforms/astbmc/Makefile.inc b/platforms/astbmc/Makefile.inc index 24e94039f..bd0e578f0 100644 --- a/platforms/astbmc/Makefile.inc +++ b/platforms/astbmc/Makefile.inc @@ -1,14 +1,18 @@ SUBDIRS += $(PLATDIR)/astbmc ASTBMC_OBJS = pnor.o common.o slots.o \ - palmetto.o habanero.o firestone.o \ - p8dtu.o p8dnu.o \ - garrison.o barreleye.o \ witherspoon.o zaius.o romulus.o p9dsu.o \ - vesnin.o nicole.o mihawk.o mowgli.o \ + nicole.o mihawk.o mowgli.o \ talos.o blackbird.o \ swift.o +ifeq ($(CONFIG_P8),1) +ASTBMC_OBJS += palmetto.o habanero.o firestone.o \ + p8dtu.o p8dnu.o \ + garrison.o barreleye.o \ + vesnin.o +endif + ASTBMC = $(PLATDIR)/astbmc/built-in.a $(ASTBMC): $(ASTBMC_OBJS:%=$(PLATDIR)/astbmc/%) diff --git a/platforms/ibm-fsp/Makefile.inc b/platforms/ibm-fsp/Makefile.inc index 8883f09c1..fd80a79a9 100644 --- a/platforms/ibm-fsp/Makefile.inc +++ b/platforms/ibm-fsp/Makefile.inc @@ -1,7 +1,12 @@ SUBDIRS += $(PLATDIR)/ibm-fsp IBM_FSP_OBJS = common.o lxvpd.o hostservices.o fsp-vpd.o \ - firenze.o firenze-pci.o zz.o + firenze-pci.o zz.o + +ifeq ($(CONFIG_P8),1) +IBM_FSP_OBJS += firenze.o +endif + IBM_FSP = $(PLATDIR)/ibm-fsp/built-in.a ifeq ($(CONFIG_FSP),1) From patchwork Sat Jun 26 02:38:24 2021 Content-Type: text/plain; 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[60.242.147.73]) by smtp.gmail.com with ESMTPSA id u10sm7010014pfh.123.2021.06.25.19.38.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 19:38:55 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 26 Jun 2021 12:38:24 +1000 Message-Id: <20210626023824.1124164-11-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210626023824.1124164-1-npiggin@gmail.com> References: <20210626023824.1124164-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 10/10] npu: Add CONFIG_NPU to optionally skip NPU code X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Stewart Smith Saves a whopping 39kb of skiboot.lid.xz. Signed-off-by: Stewart Smith --- Makefile | 2 ++ Makefile.main | 4 ++++ core/hmi.c | 10 +++++++++- core/init.c | 2 +- core/platform.c | 1 - hw/Makefile.inc | 12 +++++++++--- hw/npu2.c | 1 + include/npu2.h | 6 ++++++ include/pci.h | 3 +++ platforms/astbmc/Makefile.inc | 16 +++++++++++----- 10 files changed, 46 insertions(+), 11 deletions(-) diff --git a/Makefile b/Makefile index 625f212ea..ce61e3af0 100644 --- a/Makefile +++ b/Makefile @@ -61,6 +61,8 @@ DEAD_CODE_ELIMINATION ?= 0 CONFIG_FSP?=1 # Try to build without POWER8 support CONFIG_P8?=1 +# Try and build without any NPU support +CONFIG_NPU?=1 # # Where is the source directory, must be a full path (no ~) diff --git a/Makefile.main b/Makefile.main index ef8ee6289..9f523a789 100644 --- a/Makefile.main +++ b/Makefile.main @@ -168,6 +168,10 @@ ifeq ($(CONFIG_P8),1) CFLAGS += -DCONFIG_P8=1 endif +ifeq ($(CONFIG_NPU),1) +CFLAGS += -DCONFIG_NPU=1 +endif + CFLAGS += $(call try-cflag,$(CC),-Wjump-misses-init) \ $(call try-cflag,$(CC),-Wsuggest-attribute=const) \ $(call try-cflag,$(CC),-Wsuggest-attribute=noreturn) \ diff --git a/core/hmi.c b/core/hmi.c index ee4c168e3..446ceee96 100644 --- a/core/hmi.c +++ b/core/hmi.c @@ -561,6 +561,7 @@ static void find_nx_checkstop_reason(int flat_chip_id, queue_hmi_event(hmi_evt, 0, out_flags); } +#ifdef CONFIG_NPU static bool phb_is_npu2(struct dt_node *dn) { return (dt_node_is_compatible(dn, "ibm,power9-npu-pciex") || @@ -691,7 +692,7 @@ static void find_npu2_checkstop_reason(int flat_chip_id, npu2_hmi_verbose = true; if (npu2_hmi_verbose) { - npu2_dump_scoms(flat_chip_id); + phb->ops->dump_debug_data(flat_chip_id); prlog(PR_ERR, " _________________________ \n"); prlog(PR_ERR, "< It's Debug time! >\n"); prlog(PR_ERR, " ------------------------- \n"); @@ -779,6 +780,13 @@ static void find_npu_checkstop_reason(int flat_chip_id, /* The HMI is "recoverable" because it shouldn't crash the system */ queue_hmi_event(hmi_evt, 1, out_flags); } +#else +static void find_npu_checkstop_reason(int flat_chip_id __unused, + struct OpalHMIEvent *hmi_evt __unused, + uint64_t *out_flags __unused) +{ +} +#endif static void decode_malfunction(struct OpalHMIEvent *hmi_evt, uint64_t *out_flags) { diff --git a/core/init.c b/core/init.c index a3601d0c8..79baac27b 100644 --- a/core/init.c +++ b/core/init.c @@ -1316,7 +1316,7 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* Catalog decompression routine */ imc_decompress_catalog(); - /* Probe all HWPROBE hardware we have code linked for*/ + /* Probe all HWPROBE hardware we have code linked for */ probe_hardware(); /* Initialize PCI */ diff --git a/core/platform.c b/core/platform.c index 320fdea03..3f4c8bdd5 100644 --- a/core/platform.c +++ b/core/platform.c @@ -226,7 +226,6 @@ static struct platform generic_platform = { .start_preload_resource = generic_start_preload_resource, .resource_loaded = generic_resource_loaded, .ocapi = &generic_ocapi, - .npu2_device_detect = npu2_i2c_presence_detect, /* Assumes ZZ */ }; const struct bmc_platform *bmc_platform = &generic_bmc; diff --git a/hw/Makefile.inc b/hw/Makefile.inc index ebb9ca86a..8815f436b 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -5,15 +5,21 @@ HW_OBJS += homer.o slw.o occ.o fsi-master.o centaur.o imc.o HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-compress.o nx-842.o nx-gzip.o HW_OBJS += sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o HW_OBJS += dts.o lpc-rtc.o xive.o phb4.o -HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o -HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o -HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o +HW_OBJS += fake-nvram.o lpc-mbox.o +ifeq ($(CONFIG_NPU),1) +HW_OBJS += npu2.o npu2-hw-procedures.o +HW_OBJS += npu2-common.o npu2-opencapi.o HW_OBJS += npu-opal.o npu3.o npu3-nvlink.o npu3-hw-procedures.o +endif +HW_OBJS += phys-map.o sbe-p9.o capp.o +HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o HW_OBJS += ocmb.o ifeq ($(CONFIG_P8),1) HW_OBJS += phb3.o +ifeq ($(CONFIG_NPU),1) HW_OBJS += npu.o npu-hw-procedures.o endif +endif HW=hw/built-in.a include $(SRC)/hw/fsp/Makefile.inc diff --git a/hw/npu2.c b/hw/npu2.c index cf57eeb0c..e18a1b7b1 100644 --- a/hw/npu2.c +++ b/hw/npu2.c @@ -1316,6 +1316,7 @@ static const struct phb_ops npu_ops = { .set_capi_mode = NULL, .set_capp_recovery = NULL, .tce_kill = npu2_tce_kill, + .dump_debug_data = npu2_dump_scoms, }; static void assign_mmio_bars(uint64_t gcid, uint32_t scom, uint64_t reg[2], uint64_t mm_win[2]) diff --git a/include/npu2.h b/include/npu2.h index eb7c45587..6ab33c702 100644 --- a/include/npu2.h +++ b/include/npu2.h @@ -212,7 +212,13 @@ static inline struct phb *npu2_dev_to_phb(struct npu2_dev *ndev) } } +#ifdef CONFIG_NPU void npu2_i2c_presence_detect(struct npu2 *npu); +#else +static inline void npu2_i2c_presence_detect(struct npu2 *npu __unused) +{ +} +#endif int npu2_opencapi_init_npu(struct npu2 *npu); int npu2_nvlink_init_npu(struct npu2 *npu); void npu2_nvlink_create_phb(struct npu2 *npu, struct dt_node *dn); diff --git a/include/pci.h b/include/pci.h index 05d02171b..c70a507dc 100644 --- a/include/pci.h +++ b/include/pci.h @@ -343,6 +343,9 @@ struct phb_ops { /* Currently only used by NPU HMI code */ void (*set_fence_state)(struct phb *phb, bool fence); + + /* The most terrible of situtions, dump debug data to console. */ + void (*dump_debug_data)(int flat_chip_id); }; enum phb_type { diff --git a/platforms/astbmc/Makefile.inc b/platforms/astbmc/Makefile.inc index bd0e578f0..4d24db579 100644 --- a/platforms/astbmc/Makefile.inc +++ b/platforms/astbmc/Makefile.inc @@ -1,16 +1,22 @@ SUBDIRS += $(PLATDIR)/astbmc ASTBMC_OBJS = pnor.o common.o slots.o \ - witherspoon.o zaius.o romulus.o p9dsu.o \ - nicole.o mihawk.o mowgli.o \ - talos.o blackbird.o \ - swift.o + witherspoon.o romulus.o p9dsu.o \ + nicole.o mowgli.o \ + talos.o blackbird.o + +ifeq ($(CONFIG_NPU),1) +ASTBMC_OBJS += zaius.o mihawk.o swift.o +endif ifeq ($(CONFIG_P8),1) ASTBMC_OBJS += palmetto.o habanero.o firestone.o \ p8dtu.o p8dnu.o \ - garrison.o barreleye.o \ + barreleye.o \ vesnin.o +ifeq ($(CONFIG_NPU),1) +ASTBMC_OBJS += garrison.o +endif endif ASTBMC = $(PLATDIR)/astbmc/built-in.a