From patchwork Fri Jun 25 06:19:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1496922 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=Tzbw8u3E; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GB6LZ5ztQz9sRf for ; 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Fri, 25 Jun 2021 06:20:05 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:05 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:16 +0530 Message-Id: <20210625061937.47314-2-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: NR2W7GXNbyVaFznfFRjfJPSSr5VsjdzV X-Proofpoint-GUID: NR2W7GXNbyVaFznfFRjfJPSSr5VsjdzV X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_01:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 mlxlogscore=999 phishscore=0 spamscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 01/22] cpu: Add retry in cpu_pm_disable to kick cpus out of idle X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vaidyanathan Srinivasan Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Vaidyanathan Srinivasan cpu_pm_idle sets pm_enabled = false and expected all cpus to exit idle. This is needed to re-enter with new settings. Right after cpu_bringup() we call copy_sreset_vector() and then cpu_set_sreset_enable(true). At this time some cpus are still yet to enter idle and hence miss the doorbell to wakeup. This leads to cpu_pm_idle waiting forever. This pattern happens on some system in fused-core mode. The fact that pm_enabled flag is changing right in the middle of idle entry is see from the "cpu_idle_p9 called with pm disabled" traces. One method to fix this race is to retry the door-bell after a timeout. This patch implements a small time out (few seconds) and then issues the doorbell once again to kick the cpu that entered idle late after missing the pm_enabled = false flag. This checking loop run in smt_lowest() and hence the timeout number maps to couple of seconds which is sufficient to let the cpus settle in idle and make them see the doorbell and exit. Example boot log: [ 288.309322810,7] INIT: CPU PIR 0x000d called in [ 288.309320768,7] INIT: CPU PIR 0x000b called in [ 288.314603802,7] INIT: CPU PIR 0x0020 called in [ 288.321303468,5] CPU: All 88 processors called in... [ 288.315056796,6] cpu_idle_p9 called on cpu 0x024e with pm disabled [ 288.321308091,6] cpu_idle_p9 called on cpu 0x0264 with pm disabled [ 288.314424259,6] cpu_idle_p9 called on cpu 0x025b with pm disabled [ 288.324928307,6] cpu_idle_p9 called on cpu 0x0065 with pm disabled [ 305.207316004,6] cpu_pm_disable TIMEOUT on cpu 0x0261 to exit idle [ 322.093298501,6] cpu_pm_disable TIMEOUT on cpu 0x0263 to exit idle [ 338.491281028,6] cpu_pm_disable TIMEOUT on cpu 0x0265 to exit idle [ 355.377263492,6] cpu_pm_disable TIMEOUT on cpu 0x0267 to exit idle [ 372.263245960,6] cpu_pm_disable TIMEOUT on cpu 0x0269 to exit idle [ 389.149228389,6] cpu_pm_disable TIMEOUT on cpu 0x026b to exit idle [ 406.035210852,6] cpu_pm_disable TIMEOUT on cpu 0x026d to exit idle [ 422.433193381,6] cpu_pm_disable TIMEOUT on cpu 0x026f to exit idle [ 422.433277720,6] CHIPTOD: Calculated MCBS is 0x25 (Cfreq=2000000000 Tfreq=32000000) Reported-by: Vasant Hegde Signed-off-by: Vaidyanathan Srinivasan [Reworded commit message - Vasant] Signed-off-by: Vasant Hegde --- core/cpu.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/core/cpu.c b/core/cpu.c index d30bef8e0..f2b5bbc5d 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -437,7 +437,7 @@ static unsigned int cpu_idle_p9(enum cpu_wake_cause wake_on) unsigned int vec = 0; if (!pm_enabled) { - prlog_once(PR_DEBUG, "cpu_idle_p9 called pm disabled\n"); + prlog(PR_DEBUG, "cpu_idle_p9 called on cpu 0x%04x with pm disabled\n", cpu->pir); return vec; } @@ -593,6 +593,7 @@ no_pm: static void cpu_pm_disable(void) { struct cpu_thread *cpu; + unsigned int timeout; pm_enabled = false; sync(); @@ -610,10 +611,18 @@ static void cpu_pm_disable(void) p9_dbell_send(cpu->pir); } + /* This code is racy with cpus entering idle, late ones miss the dbell */ + smt_lowest(); for_each_available_cpu(cpu) { - while (cpu->in_sleep || cpu->in_idle) + timeout = 0x08000000; + while ((cpu->in_sleep || cpu->in_idle) && --timeout) barrier(); + if (!timeout) { + prlog(PR_DEBUG, "cpu_pm_disable TIMEOUT on cpu 0x%04x to exit idle\n", + cpu->pir); + p9_dbell_send(cpu->pir); + } } smt_medium(); } From patchwork Fri Jun 25 06:19:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1496923 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 25 Jun 2021 06:20:08 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:17 +0530 Message-Id: <20210625061937.47314-3-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 7IA4L49g1Jv2cudV_t3wgYsbQ4IWiPfi X-Proofpoint-GUID: nb9iSGCFtvxaWkwEuqljH2qSvAfzFpq3 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_02:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 clxscore=1015 malwarescore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 02/22] core/mce: POWER9 fix machine check decoding of async errors X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Nicholas Piggin Async machine check errors due to bad real address from store or foreign link time out comes with the load/store bit (PPC bit 42) set in SRR1 but the cause is set in SRR1 not DSISR, unlike other errors that have the load/store bit set. This behaviour was omitted from the POWER9 User Manual but it is confirmed to be the expected one. Update the machine check decoder to match. Signed-off-by: Nicholas Piggin --- core/mce.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/core/mce.c b/core/mce.c index a07eeb6a8..3f5091628 100644 --- a/core/mce.c +++ b/core/mce.c @@ -175,6 +175,19 @@ void decode_mce(uint64_t srr0, uint64_t srr1, return; } + /* + * Async machine check due to bad real address from store or foreign + * link time out comes with the load/store bit (PPC bit 42) set in + * SRR1, but the cause comes in SRR1 not DSISR. Clear bit 42 so we're + * directed to the ierror table so it will find the cause (which + * describes it correctly as a store error). + */ + if (SRR1_MC_LOADSTORE(srr1) && + ((srr1 & 0x081c0000) == 0x08140000 || + (srr1 & 0x081c0000) == 0x08180000)) { + srr1 &= ~PPC_BIT(42); + } + if (SRR1_MC_LOADSTORE(srr1)) { decode_derror(mce_p9_derror_table, dsisr, type, error_str); if (*type & MCE_INVOLVED_EA) From patchwork Fri Jun 25 06:19:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1496924 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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Fri, 25 Jun 2021 06:20:10 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:10 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:18 +0530 Message-Id: <20210625061937.47314-4-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: J9Al9wWDAvOPgq_jtvGAXpotpF8dhs3Z X-Proofpoint-GUID: J9Al9wWDAvOPgq_jtvGAXpotpF8dhs3Z X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_01:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 mlxlogscore=999 phishscore=0 spamscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 03/22] VAS: Define p9_get_rma_bar() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haren Myneni Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Haren Myneni Setting the Remote Memory Access BAR address is used in a couple of places which should be defined as a common function. On p10, paste base address format is changed (using primary topology index instead of node/chip IDs). This patch adds p9_get_rma_bar() for P9. Whereas get_rma_bar() on P10 and future processors which will be added in later patches. Signed-off-by: Haren Myneni --- hw/vas.c | 119 ++++++++++++++++++++++++++++++------------------------- 1 file changed, 65 insertions(+), 54 deletions(-) diff --git a/hw/vas.c b/hw/vas.c index c70094b7d..393ad801e 100644 --- a/hw/vas.c +++ b/hw/vas.c @@ -155,12 +155,72 @@ static void reset_fir(struct proc_chip *chip) vas_scom_write(chip, VAS_FIR_ACTION1, 0xf8fffefffffc8000ull); } -#define RMA_LSMP_64K_SYS_ID PPC_BITMASK(8, 12) -#define RMA_LSMP_64K_NODE_ID PPC_BITMASK(15, 18) -#define RMA_LSMP_64K_CHIP_ID PPC_BITMASK(19, 21) +/* VAS workbook: Section 1.3.3.1: Send Message w/ Paste Commands (cl_rma_w) */ +/* P9 paste base address format */ +#define P9_RMA_LSMP_64K_SYS_ID PPC_BITMASK(8, 12) +#define P9_RMA_LSMP_64K_NODE_ID PPC_BITMASK(15, 18) +#define P9_RMA_LSMP_64K_CHIP_ID PPC_BITMASK(19, 21) #define RMA_LSMP_WINID_START_BIT 32 #define RMA_LSMP_WINID_NUM_BITS 16 +/* + * The start/base of the paste BAR is computed using the tables 1.1 through + * 1.4 in Section 1.3.3.1 (Send Message w/Paste Commands (cl_rma_w)) of VAS + * P9 Workbook. + * + * With 64K mode and Large SMP Mode the bits are used as follows: + * + * Bits Values Comments + * -------------------------------------- + * 0:7 0b 0000_0000 Reserved + * 8:12 0b 0000_1 System id/Foreign Index 0:4 + * 13:14 0b 00 Foreign Index 5:6 + * + * 15:18 0 throuh 15 Node id (0 through 15) + * 19:21 0 through 7 Chip id (0 throuh 7) + * 22:23 0b 00 Unused, Foreign index 7:8 + * + * 24:31 0b 0000_0000 RPN 0:7, Reserved + * 32:47 0 through 64K Send Window Id + * 48:51 0b 0000 Spare + * + * 52 0b 0 Reserved + * 53 0b 1 Report Enable (Set to 1 for NX). + * 54 0b 0 Reserved + * + * 55:56 0b 00 Snoop Bus + * 57:63 0b 0000_000 Reserved + * + * Except for a few bits, the small SMP mode computation is similar. + * + * TODO: Detect and compute address for small SMP mode. + * + * Example: For Node 0, Chip 0, Window id 4, Report Enable 1: + * + * Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7 + * 00000000 00001000 00000000 00000000 00000000 00000100 00000100 00000000 + * | || | | | | + * +-+-++++ +-------+-------+ v + * | | | Report Enable + * v v v + * Node Chip Window id 4 + * + * Thus the paste address for window id 4 is 0x00080000_00040400 and + * the _base_ paste address for Node 0 Chip 0 is 0x00080000_00000000. + */ + +static void p9_get_rma_bar(int chipid, uint64_t *val) +{ + uint64_t v; + + v = 0ULL; + v = SETFIELD(P9_RMA_LSMP_64K_SYS_ID, v, 1); + v = SETFIELD(P9_RMA_LSMP_64K_NODE_ID, v, P9_GCID2NODEID(chipid)); + v = SETFIELD(P9_RMA_LSMP_64K_CHIP_ID, v, P9_GCID2CHIPID(chipid)); + + *val = v; +} + /* * Initialize RMA BAR on this chip to correspond to its node/chip id. * This will cause VAS to accept paste commands to targeted for this chip. @@ -171,10 +231,7 @@ static int init_rma(struct proc_chip *chip) int rc; uint64_t val; - val = 0ULL; - val = SETFIELD(RMA_LSMP_64K_SYS_ID, val, 1); - val = SETFIELD(RMA_LSMP_64K_NODE_ID, val, P9_GCID2NODEID(chip->id)); - val = SETFIELD(RMA_LSMP_64K_CHIP_ID, val, P9_GCID2CHIPID(chip->id)); + p9_get_rma_bar(chip->id, &val); rc = vas_scom_write(chip, VAS_RMA_BAR, val); if (rc) @@ -209,49 +266,6 @@ static int init_rma(struct proc_chip *chip) * separate page. Thus with a page size of 64K, the length of the paste * BAR for a chip is VAS_WINDOWS_PER_CHIP times 64K (or 4GB for Power9). * - * The start/base of the paste BAR is computed using the tables 1.1 through - * 1.4 in Section 1.3.3.1 (Send Message w/Paste Commands (cl_rma_w)) of VAS - * P9 Workbook. - * - * With 64K mode and Large SMP Mode the bits are used as follows: - * - * Bits Values Comments - * -------------------------------------- - * 0:7 0b 0000_0000 Reserved - * 8:12 0b 0000_1 System id/Foreign Index 0:4 - * 13:14 0b 00 Foreign Index 5:6 - * - * 15:18 0 throuh 15 Node id (0 through 15) - * 19:21 0 through 7 Chip id (0 throuh 7) - * 22:23 0b 00 Unused, Foreign index 7:8 - * - * 24:31 0b 0000_0000 RPN 0:7, Reserved - * 32:47 0 through 64K Send Window Id - * 48:51 0b 0000 Spare - * - * 52 0b 0 Reserved - * 53 0b 1 Report Enable (Set to 1 for NX). - * 54 0b 0 Reserved - * - * 55:56 0b 00 Snoop Bus - * 57:63 0b 0000_000 Reserved - * - * Except for a few bits, the small SMP mode computation is similar. - * - * TODO: Detect and compute address for small SMP mode. - * - * Example: For Node 0, Chip 0, Window id 4, Report Enable 1: - * - * Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7 - * 00000000 00001000 00000000 00000000 00000000 00000100 00000100 00000000 - * | || | | | | - * +-+-++++ +-------+-------+ v - * | | | Report Enable - * v v v - * Node Chip Window id 4 - * - * Thus the paste address for window id 4 is 0x00080000_00040400 and - * the _base_ paste address for Node 0 Chip 0 is 0x00080000_00000000. */ #define VAS_PASTE_BAR_LEN (1ULL << 32) /* 4GB - see above */ @@ -259,10 +273,7 @@ static inline void get_paste_bar(int chipid, uint64_t *start, uint64_t *len) { uint64_t val; - val = 0ULL; - val = SETFIELD(RMA_LSMP_64K_SYS_ID, val, 1); - val = SETFIELD(RMA_LSMP_64K_NODE_ID, val, P9_GCID2NODEID(chipid)); - val = SETFIELD(RMA_LSMP_64K_CHIP_ID, val, P9_GCID2CHIPID(chipid)); + p9_get_rma_bar(chipid, &val); *start = val; *len = VAS_PASTE_BAR_LEN; From patchwork Fri Jun 25 06:19:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1496925 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=Ue0RbHBX; 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Fri, 25 Jun 2021 06:20:12 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:11 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:19 +0530 Message-Id: <20210625061937.47314-5-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: S3Q7LEaD-rnerqW5B27m8XLXgZduEvHH X-Proofpoint-GUID: S3Q7LEaD-rnerqW5B27m8XLXgZduEvHH X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_02:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 malwarescore=0 spamscore=0 clxscore=1015 adultscore=0 suspectscore=0 mlxlogscore=999 phishscore=0 impostorscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 04/22] hdata/vpd: Add new FRU part number keyword X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Vasant Hegde --- hdata/vpd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hdata/vpd.c b/hdata/vpd.c index 010f59660..c778de346 100644 --- a/hdata/vpd.c +++ b/hdata/vpd.c @@ -105,6 +105,7 @@ static const struct vpd_key_map vpd_key_table[] = { {"EV", "enclosure"}, {"FM", "frame"}, + {"FN", "fru-stocking-part-number"}, {"HB", "host-rio-pci-card"}, {"HD", "high-speed-card"}, From patchwork Fri Jun 25 06:19:20 2021 Content-Type: text/plain; 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Fri, 25 Jun 2021 06:20:15 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7CFA64203F; Fri, 25 Jun 2021 06:20:14 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:14 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:20 +0530 Message-Id: <20210625061937.47314-6-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: nzk9t6-Wt2asuk4MuXcIAdMcfuackJvW X-Proofpoint-GUID: FDb82MBHToVlpT8qhohPCkWGfUCSGb-h X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_02:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 clxscore=1015 malwarescore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 05/22] external/trace: Fall back to read() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Oliver O'Halloran Not all kernels support mmap() on an OPAL exported memory range. Fall back to allocating a buffer and using the normal file IO system calls to read the contents of the trace buffer in those cases. This does mean we can't use "follow" mode since we can't monitor the raw trace data effectively, but otherwise it works fine. Signed-off-by: Oliver O'Halloran --- external/trace/dump_trace.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/external/trace/dump_trace.c b/external/trace/dump_trace.c index aba684b5b..5a832c791 100644 --- a/external/trace/dump_trace.c +++ b/external/trace/dump_trace.c @@ -261,6 +261,7 @@ int main(int argc, char *argv[]) { struct trace_reader *trs; struct trace_info *ti; + bool no_mmap = false; struct stat sb; int fd, opt, i; @@ -296,13 +297,26 @@ int main(int argc, char *argv[]) err(1, "Stating %s", argv[1]); ti = mmap(NULL, sb.st_size, PROT_READ, MAP_PRIVATE, fd, 0); - if (ti == MAP_FAILED) - err(1, "Mmaping %s", argv[i]); + if (ti == MAP_FAILED) { + no_mmap = true; + + ti = ezalloc(sb.st_size); + if (!ti) + err(1, "allocating memory for %s", argv[i]); + + if (read(fd, ti, sb.st_size) == -1) + err(1, "reading from %s", argv[i]); + } trs[i].tb = &ti->tb; list_head_init(&trs[i].traces); } + if (no_mmap) { + fprintf(stderr, "disabling follow mode: can't mmap() OPAL export files\n"); + follow = 0; + } + do { load_traces(trs, argc); display_traces(trs, argc); From patchwork Fri Jun 25 06:19:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1496927 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=XqKpj75K; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GB6M41qcgz9sX5 for ; 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Fri, 25 Jun 2021 06:20:17 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6BF6C4203F; Fri, 25 Jun 2021 06:20:16 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:16 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:21 +0530 Message-Id: <20210625061937.47314-7-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Yn77Z9v7G8NBo979X86uNG5N7xSiJRAw X-Proofpoint-GUID: vdGw5apHNnEcmjsKwpgPtRtcauG-FVV7 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_02:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=999 spamscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 bulkscore=0 adultscore=0 impostorscore=0 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 06/22] external/trace: Print timestamps in prlog()'s format X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Oliver O'Halloran Make the trace tool's output format match that of skiboot's prlog(). Printing a timebase tick count in hex isn't terribly useful and having a common format makes correlating trace entries to log entries much easier. Signed-off-by: Oliver O'Halloran --- external/trace/dump_trace.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/external/trace/dump_trace.c b/external/trace/dump_trace.c index 5a832c791..c68eea894 100644 --- a/external/trace/dump_trace.c +++ b/external/trace/dump_trace.c @@ -45,13 +45,18 @@ static void *ezalloc(size_t size) return p; } +#define TB_HZ 512000000ul + static void display_header(const struct trace_hdr *h) { static u64 prev_ts; u64 ts = be64_to_cpu(h->timestamp); - printf("%16lx (+%8lx) [%03x] : ", - ts, prev_ts ? (ts - prev_ts) : 0, be16_to_cpu(h->cpu)); + printf("[%5lu.%09lu,%d] (+%8lx) [%03x] : ", + ts / TB_HZ, /* match the usual skiboot log header */ + ts % TB_HZ, + h->type, /* hey why not */ + prev_ts ? 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Fri, 25 Jun 2021 06:20:20 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9042D4203F; Fri, 25 Jun 2021 06:20:18 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:18 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:22 +0530 Message-Id: <20210625061937.47314-8-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Zg-XDobwUB-S_jI2bSPRk1EagXzcOdoj X-Proofpoint-GUID: 8Itsw_rEWjo2lu81OO6Wvtpm6QfP0Vfw X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_02:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 07/22] trace: Add nvram hack to use the old trace export behaviour X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Oliver O'Halloran Previously we put all the trace buffer exports in the exports/ node. However, there's one trace buffer for each core so I moved them into a subdirectory since they were crowding up the place. Most kernels don't support recursively exporting subnodes though so kernel's don't have support for recursively exporting subnodes, so add a hack to restore the old behaviour for now. Signed-off-by: Oliver O'Halloran [Fixed run-trace test case - Vasant] Signed-off-by: Vasant Hegde --- core/init.c | 3 +++ core/test/run-trace.c | 5 +++++ core/trace.c | 17 ++++++++++------- include/trace.h | 1 + 4 files changed, 19 insertions(+), 7 deletions(-) diff --git a/core/init.c b/core/init.c index d5ba67edd..09749f475 100644 --- a/core/init.c +++ b/core/init.c @@ -1369,6 +1369,9 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* Disable protected execution facility in BML */ cpu_disable_pef(); + /* export the trace buffers */ + trace_add_dt_props(); + /* Now release parts of memory nodes we haven't used ourselves... */ mem_region_release_unused(); diff --git a/core/test/run-trace.c b/core/test/run-trace.c index b26827643..88b090358 100644 --- a/core/test/run-trace.c +++ b/core/test/run-trace.c @@ -102,6 +102,11 @@ struct debug_descriptor debug_descriptor = { .trace_mask = -1 }; +const char *nvram_query_safe(const char *key __unused) +{ + return NULL; +} + void lock_caller(struct lock *l, const char *caller) { (void)caller; diff --git a/core/trace.c b/core/trace.c index 5a3ad4921..561bd79e0 100644 --- a/core/trace.c +++ b/core/trace.c @@ -18,6 +18,7 @@ #include #include #include +#include #define DEBUG_TRACES @@ -155,7 +156,7 @@ void trace_add(union trace *trace, u8 type, u16 len) unlock(&ti->lock); } -static void trace_add_dt_props(void) +void trace_add_dt_props(void) { uint64_t boot_buf_phys = (uint64_t) &boot_tracebuf.trace_info; struct dt_node *exports, *traces; @@ -168,9 +169,14 @@ static void trace_add_dt_props(void) if (!exports) return; - traces = dt_new(exports, "traces"); - if (!exports) - return; + /* + * nvram hack to put all the trace buffer exports in the exports + * node. This is useful if the kernel doesn't also export subnodes. + */ + if (nvram_query_safe("flat-trace-buf")) + traces = exports; + else + traces = dt_new(exports, "traces"); prop = malloc(sizeof(u64) * 2 * be32_to_cpu(debug_descriptor.num_traces)); @@ -256,7 +262,4 @@ void init_trace_buffers(void) continue; t->trace = t->primary->trace; } - - /* Trace node in DT. */ - trace_add_dt_props(); } diff --git a/include/trace.h b/include/trace.h index 04c8440b9..1b1be249c 100644 --- a/include/trace.h +++ b/include/trace.h @@ -25,6 +25,7 @@ struct trace_info { /* Allocate trace buffers once we know memory topology */ void init_trace_buffers(void); +void trace_add_dt_props(void); /* This will fill in timestamp and cpu; you must do type and len. */ void trace_add(union trace *trace, u8 type, u16 len); From patchwork Fri Jun 25 06:19:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1496929 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 25 Jun 2021 06:20:20 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:23 +0530 Message-Id: <20210625061937.47314-9-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: iAAV0gmuT_UeY8GUXRN0oCZjS_cm7QEv X-Proofpoint-GUID: txoRPs2l59drAP0EpwDR4liRCpsX3Mco X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_02:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 08/22] i2c,trace: Add I2C operation trace events X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Oliver O'Halloran Add support for tracing I2C transactions performed by skiboot. This covers both internally initiated I2C ops and those that requested by the kernel via the OPAL API. Signed-off-by: Oliver O'Halloran --- core/i2c.c | 32 ++++++++++++++++++++++++++++++++ external/trace/dump_trace.c | 33 +++++++++++++++++++++++++++++++++ include/i2c.h | 9 +-------- include/trace_types.h | 12 ++++++++++++ 4 files changed, 78 insertions(+), 8 deletions(-) diff --git a/core/i2c.c b/core/i2c.c index fd9308126..b4313d430 100644 --- a/core/i2c.c +++ b/core/i2c.c @@ -13,6 +13,7 @@ #include #include #include +#include static LIST_HEAD(i2c_bus_list); @@ -38,6 +39,34 @@ struct i2c_bus *i2c_find_bus_by_id(uint32_t opal_id) return NULL; } +static inline void i2c_trace_req(struct i2c_request *req, int rc) +{ + struct trace_i2c t; + + memset(&t, 0, sizeof(t)); + + t.bus = req->bus->opal_id; + t.type = req->op | (req->offset_bytes << 4); + t.i2c_addr = req->dev_addr; + t.smbus_reg = req->offset & 0xffff; // FIXME: log whole offset + t.size = req->rw_len; + t.rc = rc; + + /* FIXME: trace should not be a union... */ + trace_add((void *)&t, TRACE_I2C, sizeof(t)); +} + +int64_t i2c_queue_req(struct i2c_request *req) +{ + int64_t ret = req->bus->queue_req(req); + + i2c_trace_req(req, OPAL_ASYNC_COMPLETION); + + if (!ret) + req->req_state = i2c_req_queued; + return ret; +} + static void opal_i2c_request_complete(int rc, struct i2c_request *req) { uint64_t token = (uint64_t)(unsigned long)req->user_data; @@ -45,6 +74,8 @@ static void opal_i2c_request_complete(int rc, struct i2c_request *req) opal_queue_msg(OPAL_MSG_ASYNC_COMP, NULL, NULL, cpu_to_be64(token), cpu_to_be64(rc)); + i2c_trace_req(req, rc); + free(req); } @@ -177,6 +208,7 @@ int64_t i2c_request_sync(struct i2c_request *req) req->req_state = i2c_req_new; } + i2c_trace_req(req, rc); count = 0; for (i = 0; i < req->rw_len && count < sizeof(buf); i++) { count += snprintf(buf+count, sizeof(buf)-count, "%02x", diff --git a/external/trace/dump_trace.c b/external/trace/dump_trace.c index c68eea894..f54dfa081 100644 --- a/external/trace/dump_trace.c +++ b/external/trace/dump_trace.c @@ -149,6 +149,36 @@ static void dump_uart(struct trace_uart *t) } } +static void dump_i2c(struct trace_i2c *t) +{ + uint16_t type = be16_to_cpu(t->type); + + printf("I2C: bus: %d dev: %02x len: %x ", + be16_to_cpu(t->bus), + be16_to_cpu(t->i2c_addr), + be16_to_cpu(t->size) + ); + + switch (type & 0x3) { + case 0: + printf("read"); + break; + case 1: + printf("write"); + break; + case 2: + printf("smbus read from %x", be16_to_cpu(t->smbus_reg)); + break; + case 3: + printf("smbus write to %x", be16_to_cpu(t->smbus_reg)); + break; + default: + printf("u wot?"); + } + + printf(", rc = %hd\n", (int16_t) be16_to_cpu(t->rc)); +} + static void load_traces(struct trace_reader *trs, int count) { struct trace_entry *te; @@ -189,6 +219,9 @@ static void print_trace(union trace *t) case TRACE_UART: dump_uart(&t->uart); break; + case TRACE_I2C: + dump_i2c(&t->i2c); + break; default: printf("UNKNOWN(%u) CPU %u length %u\n", t->hdr.type, be16_to_cpu(t->hdr.cpu), diff --git a/include/i2c.h b/include/i2c.h index c4ad805d4..2c67a0ea2 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -61,14 +61,7 @@ struct i2c_request { extern void i2c_add_bus(struct i2c_bus *bus); extern struct i2c_bus *i2c_find_bus_by_id(uint32_t opal_id); -static inline int64_t i2c_queue_req(struct i2c_request *req) -{ - int64_t ret = req->bus->queue_req(req); - - if (!ret) - req->req_state = i2c_req_queued; - return ret; -} +int64_t i2c_queue_req(struct i2c_request *req); static inline uint64_t i2c_run_req(struct i2c_request *req) { diff --git a/include/trace_types.h b/include/trace_types.h index 5942a1fa4..4ebf5a0a8 100644 --- a/include/trace_types.h +++ b/include/trace_types.h @@ -16,6 +16,7 @@ #define TRACE_FSP_MSG 4 /* FSP message sent/received */ #define TRACE_FSP_EVENT 5 /* FSP driver event */ #define TRACE_UART 6 /* UART driver traces */ +#define TRACE_I2C 7 /* I2C driver traces */ /* One per cpu, plus one for NMIs */ struct tracebuf { @@ -107,6 +108,16 @@ struct trace_uart { __be16 in_count; }; +struct trace_i2c { + struct trace_hdr hdr; + u16 bus; + u16 type; + u16 i2c_addr; + u16 smbus_reg; + u16 size; + s16 rc; +}; + union trace { struct trace_hdr hdr; /* Trace types go here... */ @@ -116,6 +127,7 @@ union trace { struct trace_fsp_msg fsp_msg; struct trace_fsp_event fsp_evt; struct trace_uart uart; + struct trace_i2c i2c; }; #endif /* __TRACE_TYPES_H */ From patchwork Fri Jun 25 06:19:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1496930 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=Xas2yW0N; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GB6MP6zM0z9sX5 for ; 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Fri, 25 Jun 2021 06:20:23 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 822AC42045; Fri, 25 Jun 2021 06:20:22 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:22 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:24 +0530 Message-Id: <20210625061937.47314-10-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: oiklJ0fm1XqnR9H6iVTUAbxVHuY3sxvH X-Proofpoint-GUID: MeVpJ8UBN9u-NbM0r3U39DkMH1sgSrIl X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_02:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 09/22] hw/p8-i2c: Add p8_i2c_find_bus_by_port() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Oliver O'Halloran Adds a way to find the struct i2c_bus for a given chip ID, engine ID, and port ID. HDAT indicates which I2C master is relevant using this information so it comes up a fair bit. Signed-off-by: Oliver O'Halloran --- hw/p8-i2c.c | 26 ++++++++++++++++++++++++++ include/i2c.h | 3 +++ 2 files changed, 29 insertions(+) diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c index eb9bbf55d..40d9ae48b 100644 --- a/hw/p8-i2c.c +++ b/hw/p8-i2c.c @@ -1606,3 +1606,29 @@ void p8_i2c_init(void) p8_i2c_init_one(i2cm, i); } } + +struct i2c_bus *p8_i2c_find_bus_by_port(uint32_t chip_id, int eng, int port_num) +{ + struct proc_chip *chip = get_chip(chip_id); + struct p8_i2c_master *m, *master = NULL; + struct p8_i2c_master_port *port; + + if (!chip) + return NULL; + + list_for_each(&chip->i2cms, m, link) { + if (m->engine_id == eng) { + master = m; + break; + } + } + + if (!master) + return NULL; + + list_for_each(&master->ports, port, link) + if (port->port_num == port_num) + return &port->bus; + + return NULL; +} diff --git a/include/i2c.h b/include/i2c.h index 2c67a0ea2..8ec32ad1c 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -61,6 +61,9 @@ struct i2c_request { extern void i2c_add_bus(struct i2c_bus *bus); extern struct i2c_bus *i2c_find_bus_by_id(uint32_t opal_id); +/* not generic, but useful */ +struct i2c_bus *p8_i2c_find_bus_by_port(uint32_t chip_id, int eng, int port_id); + int64_t i2c_queue_req(struct i2c_request *req); static inline uint64_t i2c_run_req(struct i2c_request *req) From patchwork Fri Jun 25 06:19:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1496931 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=fWnIw904; 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Fri, 25 Jun 2021 06:20:25 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7F15E42049; Fri, 25 Jun 2021 06:20:25 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4AAFE4204C; Fri, 25 Jun 2021 06:20:24 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:23 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:25 +0530 Message-Id: <20210625061937.47314-11-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: ed-b26ATdnotOnc-ArtvB4ly0fA6PIL3 X-Proofpoint-GUID: jFR3V7w4WJxxjKsfvW23eFwTZ2Pav7Ah X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_01:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 phishscore=0 priorityscore=1501 spamscore=0 impostorscore=0 mlxscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 10/22] hw/p8-i2c: Print interrupt status per master X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Oliver O'Halloran Whether I2C interrupts work or not depends on the type of master. Currently we print a single message to indicate whether IRQs work or not, but this will be wrong if we have I2C interrupts on the host and we happen to probe a Centaur I2C master first. Fix this by adding a message to the per-master print indicating whether the master has an interrupt or not. Signed-off-by: Oliver O'Halloran --- hw/p8-i2c.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c index 40d9ae48b..adefa2781 100644 --- a/hw/p8-i2c.c +++ b/hw/p8-i2c.c @@ -1446,7 +1446,6 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) struct p8_i2c_master *master; struct list_head *chip_list; uint64_t ex_stat, default_timeout; - static bool irq_printed; int64_t rc; master = zalloc(sizeof(*master)); @@ -1495,8 +1494,11 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) init_timer(&master->recovery, p8_i2c_recover, master); init_timer(&master->sensor_cache, p8_i2c_enable_scache, master); - prlog(PR_INFO, "I2C: Chip %08x Eng. %d Clock %d Mhz\n", - master->chip_id, master->engine_id, lb_freq / 1000000); + master->irq_ok = p8_i2c_has_irqs(master); + + prlog(PR_INFO, "I2C: Chip %08x Eng. %d Clock %d Mhz %s\n", + master->chip_id, master->engine_id, lb_freq / 1000000, + master->irq_ok ? "" : "(no interrupt)"); /* Disable OCC cache during inits */ if (master->type == I2C_CENTAUR) { @@ -1525,14 +1527,6 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) list_head_init(&master->req_list); list_head_init(&master->ports); - /* Check if interrupt is usable */ - master->irq_ok = p8_i2c_has_irqs(master); - if (!irq_printed) { - irq_printed = true; - prlog(PR_INFO, "I2C: Interrupts %sfunctional\n", - master->irq_ok ? "" : "non-"); - } - /* Re-enable the sensor cache, we aren't touching HW anymore */ if (master->type == I2C_CENTAUR) centaur_enable_sensor_cache(master->chip_id); From patchwork Fri Jun 25 06:19:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1496932 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=M5dqcTcn; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GB6Mb0Xh8z9sRf for ; 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Fri, 25 Jun 2021 06:20:27 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 252D54204C; Fri, 25 Jun 2021 06:20:26 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:25 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:26 +0530 Message-Id: <20210625061937.47314-12-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: eAVJvOEgVH6O0203PQuPR7iwTFYAT0Wh X-Proofpoint-ORIG-GUID: NYOG9B9TLXxQPvXgAyW2r696SrjqDzsE X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_02:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 priorityscore=1501 phishscore=0 mlxscore=0 clxscore=1015 mlxlogscore=999 suspectscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 11/22] hw/p8-i2c: Set poll interval from the current port X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Oliver O'Halloran The rate at which we need to poll the master depends on the speed of the bus. Faster I2C buses will require more frequent polling so it doesn't make a whole lot of sense to set this on a per-master basis. This patch sets the master's polling interval to a per-port setting calculated from the port speed. Signed-off-by: Oliver O'Halloran --- hw/p8-i2c.c | 23 +++++++---------------- 1 file changed, 7 insertions(+), 16 deletions(-) diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c index adefa2781..53f2c2ede 100644 --- a/hw/p8-i2c.c +++ b/hw/p8-i2c.c @@ -234,6 +234,7 @@ struct p8_i2c_master_port { uint32_t port_num; uint32_t bit_rate_div; /* Divisor to set bus speed*/ uint64_t byte_timeout; /* Timeout per byte */ + uint64_t poll_interval; /* Polling interval */ struct list_node link; }; @@ -1016,7 +1017,7 @@ static int p8_i2c_start_request(struct p8_i2c_master *master, struct i2c_request *req) { struct p8_i2c_master_port *port; - uint64_t cmd, poll_interval; + uint64_t cmd; int64_t rc; DBG("Starting req %d len=%d addr=%02x (offset=%x)\n", @@ -1151,10 +1152,10 @@ static int p8_i2c_start_request(struct p8_i2c_master *master, * cases */ if (!opal_booting() && master->irq_ok) - poll_interval = TIMER_POLL; + master->poll_interval = TIMER_POLL; else - poll_interval = master->poll_interval; - schedule_timer(&master->poller, poll_interval); + master->poll_interval = port->poll_interval; + schedule_timer(&master->poller, master->poll_interval); /* If we don't have a user-set timeout then use the master's default */ if (!req->timeout) @@ -1441,7 +1442,7 @@ static void p8_i2c_add_bus_prop(struct p8_i2c_master_port *port) static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) { struct p8_i2c_master_port *port; - uint32_t lb_freq, count, max_bus_speed; + uint32_t lb_freq, count; struct dt_node *i2cm_port; struct p8_i2c_master *master; struct list_head *chip_list; @@ -1546,7 +1547,6 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) /* Add master to chip's list */ list_add_tail(chip_list, &master->link); - max_bus_speed = 0; default_timeout = master->irq_ok ? I2C_TIMEOUT_IRQ_MS : @@ -1558,8 +1558,7 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) port->port_num = dt_prop_get_u32(i2cm_port, "reg"); port->master = master; speed = dt_prop_get_u32(i2cm_port, "bus-frequency"); - if (speed > max_bus_speed) - max_bus_speed = speed; + port->poll_interval = p8_i2c_get_poll_interval(speed); port->bit_rate_div = p8_i2c_get_bit_rate_divisor(lb_freq, speed); port->bus.dt_node = i2cm_port; @@ -1580,14 +1579,6 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) "ibm,port-name"), speed/1000); port++; } - - /* When at runtime and we have the i2c irq, we just use it - * (see p8_i2c_start_request), but in the situation where - * one of those isn't the case (e.g. during boot), we need - * a better poll interval to efficiently crank the i2c machine. - * poll_interval is that interval. - */ - master->poll_interval = (max_bus_speed) ? p8_i2c_get_poll_interval(max_bus_speed) : TIMER_POLL; } void p8_i2c_init(void) From patchwork Fri Jun 25 06:19:27 2021 Content-Type: text/plain; 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Fri, 25 Jun 2021 06:20:29 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0518542047; Fri, 25 Jun 2021 06:20:28 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:27 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:27 +0530 Message-Id: <20210625061937.47314-13-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: oOy4PoDC_fxP8_in8N5b-W1ihcQSk8Go X-Proofpoint-GUID: fNj4QMP8YQxe4AsvE4FCIGhzUusYkbkM X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_01:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 clxscore=1015 phishscore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 bulkscore=0 malwarescore=0 lowpriorityscore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 12/22] hw/p8-i2c: Move port init into a separate function X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Oliver O'Halloran Move it out in preparation for adding the ability to add new ports on the fly. Signed-off-by: Oliver O'Halloran --- hw/p8-i2c.c | 93 ++++++++++++++++++++++++++--------------------------- 1 file changed, 45 insertions(+), 48 deletions(-) diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c index 53f2c2ede..33541aaa6 100644 --- a/hw/p8-i2c.c +++ b/hw/p8-i2c.c @@ -1439,14 +1439,52 @@ static void p8_i2c_add_bus_prop(struct p8_i2c_master_port *port) } } -static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) +static struct p8_i2c_master_port *p8_i2c_init_one_port(struct p8_i2c_master *m, + struct dt_node *n, uint64_t lb_freq) { struct p8_i2c_master_port *port; - uint32_t lb_freq, count; - struct dt_node *i2cm_port; + uint64_t def_timeout; + uint32_t speed, div; + + port = zalloc(sizeof(*port)); + if (!port) + return NULL; + + def_timeout = m->irq_ok ? I2C_TIMEOUT_IRQ_MS : I2C_TIMEOUT_POLL_MS; + + speed = dt_prop_get_u32_def(n, "bus-frequency", 100000); + div = p8_i2c_get_bit_rate_divisor(lb_freq, speed); + + /* p8-i2c stuff */ + port->master = m; + port->bit_rate_div = div; + port->poll_interval = p8_i2c_get_poll_interval(speed); + port->port_num = dt_prop_get_u32(n, "reg"); + port->byte_timeout = dt_prop_get_u32_def(n, "timeout-ms", def_timeout); + list_add_tail(&m->ports, &port->link); + + /* core i2c stuff */ + port->bus.dt_node = n; + port->bus.queue_req = p8_i2c_queue_request; + port->bus.run_req = p8_i2c_run_request; + i2c_add_bus(&port->bus); + + /* add the bus name and compatible (if needed) */ + p8_i2c_add_bus_prop(port); + + prlog(PR_INFO, " P%d: <%s> %d kHz\n", port->port_num, + (char *) dt_prop_get(n, "ibm,port-name"), speed / 1000); + + return port; +} + +static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) +{ struct p8_i2c_master *master; struct list_head *chip_list; - uint64_t ex_stat, default_timeout; + struct dt_node *i2cm_port; + uint64_t ex_stat; + uint32_t lb_freq; int64_t rc; master = zalloc(sizeof(*master)); @@ -1532,53 +1570,12 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) if (master->type == I2C_CENTAUR) centaur_enable_sensor_cache(master->chip_id); - /* Allocate ports driven by this master */ - count = 0; - dt_for_each_child(i2cm, i2cm_port) - count++; - - port = zalloc(sizeof(*port) * count); - if (!port) { - log_simple_error(&e_info(OPAL_RC_I2C_INIT), - "I2C: Insufficient memory\n"); - free(master); - return; - } - /* Add master to chip's list */ list_add_tail(chip_list, &master->link); - default_timeout = master->irq_ok ? - I2C_TIMEOUT_IRQ_MS : - I2C_TIMEOUT_POLL_MS; - - dt_for_each_child(i2cm, i2cm_port) { - uint32_t speed; - - port->port_num = dt_prop_get_u32(i2cm_port, "reg"); - port->master = master; - speed = dt_prop_get_u32(i2cm_port, "bus-frequency"); - port->poll_interval = p8_i2c_get_poll_interval(speed); - port->bit_rate_div = - p8_i2c_get_bit_rate_divisor(lb_freq, speed); - port->bus.dt_node = i2cm_port; - port->bus.queue_req = p8_i2c_queue_request; - port->bus.run_req = p8_i2c_run_request; - - port->byte_timeout = dt_prop_get_u32_def(i2cm_port, - "timeout-ms", default_timeout); - - i2c_add_bus(&port->bus); - list_add_tail(&master->ports, &port->link); - - /* Add OPAL properties to the bus node */ - p8_i2c_add_bus_prop(port); - prlog(PR_INFO, " P%d: <%s> %d kHz\n", - port->port_num, - (char *)dt_prop_get(i2cm_port, - "ibm,port-name"), speed/1000); - port++; - } + /* initialise ports */ + dt_for_each_child(i2cm, i2cm_port) + p8_i2c_init_one_port(master, i2cm_port, lb_freq); } void p8_i2c_init(void) From patchwork Fri Jun 25 06:19:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1496934 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; 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Fri, 25 Jun 2021 06:20:29 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:29 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:28 +0530 Message-Id: <20210625061937.47314-14-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 1G9ysahkwn-mT8iDqx8U_LGFLNzT8gN8 X-Proofpoint-GUID: uoDj76O5K1AqtAg0mpeXhLtO1RqMgOKZ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_01:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 mlxlogscore=999 phishscore=0 spamscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 13/22] hdat/i2c: Rework i2c device creation X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Oliver O'Halloran We've got functions to instantiate I2C buses at various places inside of the skiboot code base (in hdat, firenze-pci, and in witherspoon). The HDAT ones are the most generic so re-work those a bit and export the functions used to add DT nodes for I2C masters and the ports below them. Signed-off-by: Oliver O'Halloran --- hdata/i2c.c | 171 ++++++++++++++++++++++++++++++++------------------ include/i2c.h | 5 ++ 2 files changed, 114 insertions(+), 62 deletions(-) diff --git a/hdata/i2c.c b/hdata/i2c.c index b4309dba5..8aa93d8f5 100644 --- a/hdata/i2c.c +++ b/hdata/i2c.c @@ -7,86 +7,128 @@ #include #include #include +#include #include "spira.h" #include "hdata.h" -struct i2c_dev { - uint8_t i2cm_engine; - uint8_t i2cm_port; - __be16 i2c_bus_freq; +/* + * These should probably be in hw/p8-i2c.c. However, that would require the HDAT + * test to #include hw/p8-i2c.c which is probably going to be more trouble than + * it's worth. So these helpers are here instead. + */ +struct dt_node *p8_i2c_add_master_node(struct dt_node *xscom, int eng_id) +{ + uint64_t clk, size, xscom_base; + struct dt_node *i2cm; - /* i2c slave info */ - uint8_t type; - uint8_t dev_addr; - uint8_t dev_port; - uint8_t __reserved; + dt_for_each_compatible(xscom, i2cm, "ibm,power8-i2cm") + if (dt_prop_get_u32(i2cm, "chip-engine#") == eng_id) + return i2cm; - __be32 purpose; - __be32 i2c_link; - __be16 slca_index; -}; + /* XXX: Might need to be updated for new chips */ + if (proc_gen >= proc_gen_p9) + size = 0x1000; + else + size = 0x20; -#define P9_I2CM_XSCOM_SIZE 0x1000 -#define P9_I2CM_XSCOM_BASE 0xa0000 + xscom_base = 0xa0000 + size * eng_id; -static struct dt_node *get_i2cm_node(struct dt_node *xscom, int engine) -{ - uint64_t xscom_base = P9_I2CM_XSCOM_BASE + P9_I2CM_XSCOM_SIZE * (uint64_t)engine; - struct dt_node *i2cm; - uint64_t freq, clock; - - i2cm = dt_find_by_name_addr(xscom, "i2cm", xscom_base); - if (!i2cm) { - i2cm = dt_new_addr(xscom, "i2cm", xscom_base); - dt_add_property_cells(i2cm, "reg", xscom_base, - P9_I2CM_XSCOM_SIZE); - - dt_add_property_strings(i2cm, "compatible", - "ibm,power8-i2cm", "ibm,power9-i2cm"); - - dt_add_property_cells(i2cm, "#size-cells", 0); - dt_add_property_cells(i2cm, "#address-cells", 1); - dt_add_property_cells(i2cm, "chip-engine#", engine); - - freq = dt_prop_get_u64_def(xscom, "bus-frequency", 0); - clock = (u32)(freq / 4); - if (clock) - dt_add_property_cells(i2cm, "clock-frequency", clock); - else - dt_add_property_cells(i2cm, "clock-frequency", 150000000); + i2cm = dt_new_addr(xscom, "i2cm", xscom_base); + if (!i2cm) + return NULL; + + if (proc_gen >= proc_gen_p9) { + dt_add_property_strings(i2cm, "compatible", "ibm,power8-i2cm", + "ibm,power9-i2cm"); + } else { + dt_add_property_strings(i2cm, "compatible", "ibm,power8-i2cm"); } + dt_add_property_cells(i2cm, "reg", xscom_base, size); + dt_add_property_cells(i2cm, "#size-cells", 0); + dt_add_property_cells(i2cm, "#address-cells", 1); + dt_add_property_cells(i2cm, "chip-engine#", eng_id); + + /* + * The i2cm runs at 1/4th the PIB frequency. If we don't know the PIB + * frequency then pick 150MHz which should be in the right ballpark. + */ + clk = dt_prop_get_u64_def(xscom, "bus-frequency", 0); + if (clk) + dt_add_property_cells(i2cm, "clock-frequency", clk / 4); + else + dt_add_property_cells(i2cm, "clock-frequency", 150000000); + return i2cm; } -static struct dt_node *get_bus_node(struct dt_node *i2cm, int port, int freq) +struct dt_node *__p8_i2c_add_port_node(struct dt_node *master, int port_id, + uint32_t bus_speed) { - struct dt_node *bus; + struct dt_node *port; + uint32_t speed; + + dt_for_each_child(master, port) + if (dt_prop_get_u32(port, "reg") == port_id) + goto check_speed; - bus = dt_find_by_name_addr(i2cm, "i2c-bus", port); - if (!bus) { - bus = dt_new_addr(i2cm, "i2c-bus", port); - dt_add_property_cells(bus, "reg", port); - dt_add_property_cells(bus, "#size-cells", 0); - dt_add_property_cells(bus, "#address-cells", 1); + port = dt_new_addr(master, "i2c-bus", port_id); + if (!port) + return NULL; - /* The P9 I2C master is fully compatible with the P8 one */ - dt_add_property_strings(bus, "compatible", "ibm,opal-i2c", + dt_add_property_cells(port, "reg", port_id); + dt_add_property_cells(port, "#size-cells", 0); + dt_add_property_cells(port, "#address-cells", 1); + + /* The P9 I2C master is fully compatible with the P8 one */ + if (proc_gen >= proc_gen_p9) { + dt_add_property_strings(port, "compatible", "ibm,opal-i2c", "ibm,power8-i2c-port", "ibm,power9-i2c-port"); + } else { + dt_add_property_strings(port, "compatible", "ibm,opal-i2c", + "ibm,power8-i2c-port"); + } - /* - * use the clock frequency as the bus frequency until we - * have actual devices on the bus. Adding a device will - * reduce the frequency to something that all devices - * can tolerate. - */ - dt_add_property_cells(bus, "bus-frequency", freq * 1000); +check_speed: + speed = dt_prop_get_u32_def(port, "bus-frequency", 0xffffffff); + if (bus_speed < speed) { + dt_check_del_prop(port, "bus-frequency"); + dt_add_property_cells(port, "bus-frequency", bus_speed); } - return bus; + return port; +} + + +struct dt_node *p8_i2c_add_port_node(struct dt_node *xscom, int eng_id, + int port_id, uint32_t bus_freq) +{ + struct dt_node *i2cm; + + i2cm = p8_i2c_add_master_node(xscom, eng_id); + if (!i2cm) + return NULL; + + return __p8_i2c_add_port_node(i2cm, port_id, bus_freq); } +struct i2c_dev { + uint8_t i2cm_engine; + uint8_t i2cm_port; + __be16 i2c_bus_freq; + + /* i2c slave info */ + uint8_t type; + uint8_t dev_addr; + uint8_t dev_port; + uint8_t __reserved; + + __be32 purpose; + __be32 i2c_link; + __be16 slca_index; +}; + struct hdat_i2c_type { uint32_t id; const char *name; @@ -192,7 +234,7 @@ struct host_i2c_hdr { int parse_i2c_devs(const struct HDIF_common_hdr *hdr, int idata_index, struct dt_node *xscom) { - struct dt_node *i2cm, *bus, *node; + struct dt_node *bus, *node; const struct hdat_i2c_type *type; const struct hdat_i2c_info *info; const struct i2c_dev *dev; @@ -262,9 +304,14 @@ int parse_i2c_devs(const struct HDIF_common_hdr *hdr, int idata_index, if (dev->i2cm_engine >= 4 && proc_gen == proc_gen_p9) continue; - i2cm = get_i2cm_node(xscom, dev->i2cm_engine); - bus = get_bus_node(i2cm, dev->i2cm_port, - be16_to_cpu(dev->i2c_bus_freq)); + bus = p8_i2c_add_port_node(xscom, dev->i2cm_engine, dev->i2cm_port, + be16_to_cpu(dev->i2c_bus_freq) * 1000); + + if (!bus) { + prerror("Unable to add node for e%dp%d under %s\n", + dev->i2cm_engine, dev->i2cm_port, xscom->name); + continue; + } /* * Looks like hostboot gives the address as an 8 bit, left diff --git a/include/i2c.h b/include/i2c.h index 8ec32ad1c..9ad307b3f 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -63,6 +63,11 @@ extern struct i2c_bus *i2c_find_bus_by_id(uint32_t opal_id); /* not generic, but useful */ struct i2c_bus *p8_i2c_find_bus_by_port(uint32_t chip_id, int eng, int port_id); +struct dt_node *p8_i2c_add_master_node(struct dt_node *xscom, int eng_id); +struct dt_node *__p8_i2c_add_port_node(struct dt_node *master, int port_id, + uint32_t bus_speed); +struct dt_node *p8_i2c_add_port_node(struct dt_node *xscom, int eng_id, + int port_id, uint32_t bus_freq); int64_t i2c_queue_req(struct i2c_request *req); From patchwork Fri Jun 25 06:19:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1496935 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=Pmf8szf+; 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Fri, 25 Jun 2021 06:20:33 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 285004203F; Fri, 25 Jun 2021 06:20:33 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0317642047; Fri, 25 Jun 2021 06:20:32 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:31 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:29 +0530 Message-Id: <20210625061937.47314-15-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: vZjPyQsP_3-0DLGlSL1qsQR3hsuLnQNb X-Proofpoint-GUID: O8Y1reugsDt2rXeQFBNzIKKoVoSmXT8v X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_02:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 bulkscore=0 spamscore=0 adultscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 mlxlogscore=999 lowpriorityscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 14/22] hw/p8-i2c: Add buses at runtime X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Oliver O'Halloran When booting skiboot we initialise any I2C masters after probing the platform, but before initialising the platform (or NVRAM). Due to this we need to ensure that all the I2C masters we might want to use are in the DT before the platform is initialised. This causes problems since we might want to add another master (e.g. on witherspoon we might need to add a port for the I2C OpenCAPI I2C bus). It's possible to hack around this by adding a new node in the probe function, but the probe function runs very early before many essential services are initialised (e.g. LPC). We might want to add another I2C bus after learning that we have a riser card installed and it's not possible to do that until later in boot. To accommodate those use cases we can add support for adding a new bus at runtime. Signed-off-by: Oliver O'Halloran --- hw/p8-i2c.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++----- include/i2c.h | 3 ++ 2 files changed, 78 insertions(+), 8 deletions(-) diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c index 33541aaa6..31b2e79cd 100644 --- a/hw/p8-i2c.c +++ b/hw/p8-i2c.c @@ -196,6 +196,7 @@ enum p8_i2c_master_type { }; struct p8_i2c_master { + struct dt_node *dt_node; struct lock lock; /* Lock to guard the members */ enum p8_i2c_master_type type; /* P8 vs. Centaur */ uint64_t start_time; /* Request start time */ @@ -1440,10 +1441,10 @@ static void p8_i2c_add_bus_prop(struct p8_i2c_master_port *port) } static struct p8_i2c_master_port *p8_i2c_init_one_port(struct p8_i2c_master *m, - struct dt_node *n, uint64_t lb_freq) + struct dt_node *n) { struct p8_i2c_master_port *port; - uint64_t def_timeout; + uint64_t def_timeout, lb_freq; uint32_t speed, div; port = zalloc(sizeof(*port)); @@ -1452,6 +1453,7 @@ static struct p8_i2c_master_port *p8_i2c_init_one_port(struct p8_i2c_master *m, def_timeout = m->irq_ok ? I2C_TIMEOUT_IRQ_MS : I2C_TIMEOUT_POLL_MS; + lb_freq = dt_prop_get_u32_def(m->dt_node, "clock-frequency", 150000000); speed = dt_prop_get_u32_def(n, "bus-frequency", 100000); div = p8_i2c_get_bit_rate_divisor(lb_freq, speed); @@ -1478,7 +1480,8 @@ static struct p8_i2c_master_port *p8_i2c_init_one_port(struct p8_i2c_master *m, return port; } -static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) +static struct p8_i2c_master *p8_i2c_init_one(struct dt_node *i2cm, + enum p8_i2c_master_type type) { struct p8_i2c_master *master; struct list_head *chip_list; @@ -1492,7 +1495,7 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) log_simple_error(&e_info(OPAL_RC_I2C_INIT), "I2C: Failed to allocate master " "structure\n"); - return; + return NULL; } master->type = type; @@ -1504,6 +1507,7 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) master->chip_id = dt_get_chip_id(i2cm); master->engine_id = dt_prop_get_u32(i2cm, "chip-engine#"); master->xscom_base = dt_get_address(i2cm, 0, NULL); + master->dt_node = i2cm; if (master->type == I2C_CENTAUR) { struct centaur_chip *centaur = get_centaur(master->chip_id); if (centaur == NULL) { @@ -1511,7 +1515,7 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) "I2C: Failed to get centaur 0x%x ", master->chip_id); free(master); - return; + return NULL; } chip_list = ¢aur->i2cms; @@ -1521,7 +1525,7 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) if (master->engine_id > 0) { prlog(PR_ERR, "I2C: Skipping Centaur Master #1\n"); free(master); - return; + return NULL; } } else { struct proc_chip *chip = get_chip(master->chip_id); @@ -1559,7 +1563,7 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) centaur_enable_sensor_cache(master->chip_id); free(master); - return; + return NULL; } master->fifo_size = GETFIELD(I2C_EXTD_STAT_FIFO_SIZE, ex_stat); @@ -1575,7 +1579,9 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) /* initialise ports */ dt_for_each_child(i2cm, i2cm_port) - p8_i2c_init_one_port(master, i2cm_port, lb_freq); + p8_i2c_init_one_port(master, i2cm_port); + + return master; } void p8_i2c_init(void) @@ -1614,3 +1620,64 @@ struct i2c_bus *p8_i2c_find_bus_by_port(uint32_t chip_id, int eng, int port_num) return NULL; } + +/* Adds a new i2c port to the DT and initialises it */ +struct i2c_bus *p8_i2c_add_bus(uint32_t chip_id, int eng_id, int port_id, + uint32_t bus_speed) +{ + struct proc_chip *c = get_chip(chip_id); + struct p8_i2c_master *m, *master = NULL; + struct p8_i2c_master_port *port; + struct dt_node *pn; + + if (!c) { + prerror("I2C: Unable to add i2c bus: c%de%dp%d: chip doesn't exist\n", + chip_id, eng_id, port_id); + return NULL; + } + + list_for_each(&c->i2cms, m, link) { + if (m->engine_id == eng_id) { + master = m; + break; + } + } + + if (!master) { + struct dt_node *mn; + + mn = p8_i2c_add_master_node(c->devnode, eng_id); + if (!mn) { + prerror("I2C: Unable to add DT node for I2CM c%xe%d\n", + chip_id, eng_id); + return NULL; + } + + master = p8_i2c_init_one(mn, I2C_POWER8); + if (!master) { + prerror("I2C: Unable to initialise I2CM c%xe%d\n", + chip_id, eng_id); + return NULL; + } + } + + list_for_each(&master->ports, port, link) + if (port->port_num == port_id) + return &port->bus; + + pn = __p8_i2c_add_port_node(master->dt_node, port_id, bus_speed); + if (!pn) { + prerror("I2C: Unable to add dt node for bus c%xe%dp%d\n", + chip_id, eng_id, port_id); + return NULL; + } + + port = p8_i2c_init_one_port(master, pn); + if (!port) { + prerror("I2C: Unable to init bus c%xe%dp%d\n", + chip_id, eng_id, port_id); + return NULL; + } + + return &port->bus; +} diff --git a/include/i2c.h b/include/i2c.h index 9ad307b3f..a644bd427 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -69,6 +69,9 @@ struct dt_node *__p8_i2c_add_port_node(struct dt_node *master, int port_id, struct dt_node *p8_i2c_add_port_node(struct dt_node *xscom, int eng_id, int port_id, uint32_t bus_freq); +struct i2c_bus *p8_i2c_add_bus(uint32_t chip_id, int eng_id, int port_id, + uint32_t bus_speed); + int64_t i2c_queue_req(struct i2c_request *req); static inline uint64_t i2c_run_req(struct i2c_request *req) From patchwork Fri Jun 25 06:19:30 2021 Content-Type: text/plain; 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Fri, 25 Jun 2021 06:20:35 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CDC9042042; Fri, 25 Jun 2021 06:20:33 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:33 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:30 +0530 Message-Id: <20210625061937.47314-16-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Fhhxah3yyaj-P73cyrQfGSahoSrIHDiy X-Proofpoint-GUID: Ixug0VFuoM19o0HjqhJ3XuggmUmBMQHF X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_01:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 phishscore=0 priorityscore=1501 spamscore=0 impostorscore=0 mlxscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 15/22] hw/p8-i2c: Make OCCFLG register base address configurable at runtime X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Oliver O'Halloran Prepare for POWER10 support which changes the OCCFLG register base address. Signed-off-by: Oliver O'Halloran [Replaced perror with prlog - Vasant] Signed-off-by: Vasant Hegde --- hw/p8-i2c.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c index 31b2e79cd..6e24c3e82 100644 --- a/hw/p8-i2c.c +++ b/hw/p8-i2c.c @@ -935,22 +935,23 @@ static bool occ_uses_master(struct p8_i2c_master *master) return false; } -#define OCCFLG_BASE 0x00000000006C08A -#define OCCFLG_CLEAR 0x00000000006C08B -#define OCCFLG_SET 0x00000000006C08C +static uint32_t occflg; +#define OCCFLG_BASE 0 +#define OCCFLG_CLEAR 1 +#define OCCFLG_SET 2 static int occ_i2c_lock(struct p8_i2c_master *master) { u64 occflags, busflag; int rc; - if (!occ_uses_master(master)) + if (!occ_uses_master(master) || !occflg) return 0; if (master->occ_lock_acquired) return 0; - rc = xscom_read(master->chip_id, OCCFLG_BASE, &occflags); + rc = xscom_read(master->chip_id, occflg, &occflags); if (rc) { prerror("I2C: Failed to read OCC FLAG register\n"); return rc; @@ -966,7 +967,7 @@ static int occ_i2c_lock(struct p8_i2c_master *master) (u32) GETFIELD(PPC_BITMASK(18, 19), occflags), (u32) GETFIELD(PPC_BITMASK(20, 21), occflags)); - rc = xscom_write(master->chip_id, OCCFLG_SET, busflag); + rc = xscom_write(master->chip_id, occflg + OCCFLG_SET, busflag); if (rc) { prerror("I2C: Failed to write OCC FLAG register\n"); return rc; @@ -989,10 +990,10 @@ static int occ_i2c_unlock(struct p8_i2c_master *master) u64 busflag, occflags; int rc; - if (!occ_uses_master(master)) + if (!occ_uses_master(master) || !occflg) return 0; - rc = xscom_read(master->chip_id, OCCFLG_BASE, &occflags); + rc = xscom_read(master->chip_id, occflg, &occflags); if (rc) { prerror("I2C: Failed to read OCC Flag register\n"); return rc; @@ -1005,7 +1006,7 @@ static int occ_i2c_unlock(struct p8_i2c_master *master) master->chip_id, master->engine_id, occflags); } - rc = xscom_write(master->chip_id, OCCFLG_CLEAR, busflag); + rc = xscom_write(master->chip_id, occflg + OCCFLG_CLEAR, busflag); if (rc) prerror("I2C: Failed to write OCC Flag register\n"); @@ -1589,6 +1590,11 @@ void p8_i2c_init(void) struct dt_node *i2cm; int i; + /* setup the handshake reg */ + occflg = 0x6C08A; + + prlog(PR_INFO, "I2C: OCC flag reg: %x\n", occflg); + for (i = 0; i < MAX_I2C_TYPE; i++) { dt_for_each_compatible(dt_root, i2cm, compat[i]) p8_i2c_init_one(i2cm, i); From patchwork Fri Jun 25 06:19:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1496937 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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Fri, 25 Jun 2021 06:20:35 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:35 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:31 +0530 Message-Id: <20210625061937.47314-17-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: ZjmEMTfqEpdhooVkB0xXt5X3rRqHXidQ X-Proofpoint-GUID: ZjmEMTfqEpdhooVkB0xXt5X3rRqHXidQ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_01:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 clxscore=1015 phishscore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 bulkscore=0 malwarescore=0 lowpriorityscore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 16/22] external/xscom-utils: Add P9P chip info X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Vasant Hegde --- external/xscom-utils/adu_scoms.py | 2 ++ external/xscom-utils/getscom.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/external/xscom-utils/adu_scoms.py b/external/xscom-utils/adu_scoms.py index 6273eadb1..d651b7e9f 100755 --- a/external/xscom-utils/adu_scoms.py +++ b/external/xscom-utils/adu_scoms.py @@ -174,6 +174,8 @@ class GetSCom(object): name = "P9 (Nimbus) processor" elif id == 0xd4: name = "P9 (Cumulus) processor" + elif id == 0xd9: + name = "P9P (Axone) processor" elif id == 0xe9: name = "Centaur memory buffer" else: diff --git a/external/xscom-utils/getscom.c b/external/xscom-utils/getscom.c index bb28139d8..c18a04972 100644 --- a/external/xscom-utils/getscom.c +++ b/external/xscom-utils/getscom.c @@ -53,6 +53,9 @@ static void print_chip_info(uint32_t chip_id) case 0xd4: name = "P9 (Cumulus) processor"; break; + case 0xd9: + name = "P9P (Axone) processor"; + break; case 0xe9: name = "Centaur memory buffer"; break; From patchwork Fri Jun 25 06:19:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1496941 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=c+yPcOca; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GB6NQ1hZPz9sRf for ; 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Fri, 25 Jun 2021 06:20:40 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6536C42045; Fri, 25 Jun 2021 06:20:40 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 80D8542042; Fri, 25 Jun 2021 06:20:38 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:38 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:32 +0530 Message-Id: <20210625061937.47314-18-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: rMO8_KUAU9j4FljDLN_QSHzPztFqlErl X-Proofpoint-ORIG-GUID: Fkd4RwH3xmwiaOMKKlMeBi8me4p66sO5 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_01:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 17/22] fast-reboot: Fix the bonus cleanup_cpu_state() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Oliver O'Halloran Signed-off-by: Oliver O'Halloran Signed-off-by: Cédric Le Goater Signed-off-by: Vaidyanathan Srinivasan --- core/fast-reboot.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 03777543a..ac9b3b284 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -264,8 +264,11 @@ static void cleanup_cpu_state(void) xive_cpu_reset(); /* Per core cleanup */ - if (cpu_is_thread0(cpu)) { - /* XXX should reset the SLW SPR restore values*/ + if (cpu_is_thread0(cpu) || cpu_is_core_chiplet_primary(cpu)) { + /* Shared SPRs whacked back to normal */ + + /* XXX Update the SLW copies ! Also dbl check HIDs etc... */ + init_shared_sprs(); if (proc_gen == proc_gen_p8) { /* If somebody was in fast_sleep, we may have a @@ -286,6 +289,11 @@ static void cleanup_cpu_state(void) /* And we might have lost TB sync */ chiptod_wakeup_resync(); } + + /* Per-thread additional cleanup */ + init_replicated_sprs(); + + // XXX Cleanup SLW, check HIDs ... } /* Entry from asm after a fast reset */ From patchwork Fri Jun 25 06:19:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1496938 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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Fri, 25 Jun 2021 06:20:42 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 82DAA42052; Fri, 25 Jun 2021 06:20:42 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 02E9142041; Fri, 25 Jun 2021 06:20:41 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:40 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:33 +0530 Message-Id: <20210625061937.47314-19-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: EJkXnh6-huJyxTGCuhPTrOnmrpvMsjmK X-Proofpoint-GUID: zf1GKdZit8f06nYx9PsUX3xLusoFHbB_ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_01:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 malwarescore=0 spamscore=0 bulkscore=0 mlxlogscore=999 lowpriorityscore=0 impostorscore=0 clxscore=1011 phishscore=0 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 18/22] asm/head.S: Fix early SPR inits for big core X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Nicholas Piggin Without this the shared SPRs on the secondary cores are not set. Signed-off-by: Nicholas Piggin Signed-off-by: Michael Neuling --- asm/head.S | 34 +++++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/asm/head.S b/asm/head.S index 7058f734d..d773bde04 100644 --- a/asm/head.S +++ b/asm/head.S @@ -380,23 +380,39 @@ boot_entry: #endif mtmsrd %r3,0 - /* If fused, t1 is primary chiplet and must init shared sprs */ + mfspr %r31,SPR_PIR + andi. %r3,%r25,1 - beq not_fused + bne fused - mfspr %r31,SPR_PIR - andi. %r3,%r31,1 - bnel init_shared_sprs + /* Apply core-mask PIR */ + and %r0,%r31,%r26 -not_fused: - /* Check our PIR, avoid threads */ - mfspr %r31,SPR_PIR - and. %r0,%r31,%r26 + /* t0 is primary for small-core */ + cmpdi %r0,0 bne secondary_wait /* Initialize per-core SPRs */ bl init_shared_sprs + b go_primary + +fused: + /* Apply core-mask PIR */ + ori %r0,%r26,1 /* include both sub-cores in the core mask */ + and %r0,%r31,%r0 + + /* If fused, t0, t1 are primaries for sub-cores */ + cmpdi %r0,0 + bne 1f + bl init_shared_sprs + b go_primary /* but only t0 can be a boot CPU */ +1: + cmpdi %r0,1 + bne secondary_wait + bl init_shared_sprs + b secondary_wait +go_primary: /* Pick a boot CPU, cpu index in r31 */ LOAD_IMM32(%r3, boot_sem - __head) add %r3,%r3,%r30 From patchwork Fri Jun 25 06:19:34 2021 Content-Type: text/plain; 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Fri, 25 Jun 2021 06:20:45 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1DDD24203F; Fri, 25 Jun 2021 06:20:43 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:42 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:34 +0530 Message-Id: <20210625061937.47314-20-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: rYIpFUqtvlK6Yl86QsfFdtJSk8Xa60ey X-Proofpoint-GUID: -wfCCVnf7-Vu_q75zQEdErVYBLoBgFYi X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_02:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 19/22] core/cpu: Initialize all cpu thread areas to avoid invalid memory access. X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Mahesh Salgaonkar Starting from p10 hostboot will no longer clear all the system memory except its own space. OPAL uses the memory at SKIBOOT_BASE + SKIBOOT_SIZE for cpu stack with pir as index. With hostboot no longer clearing memory this region may hold junk contents. Currently opal initialize cpu stack memory only for cpu pir that is found on the device-tree. For the rest, the cpu thread contents are uninitialized. This sometime causes for_each_cpu* macros to return cpu thread for pir/cpu which isn't present on the system. The for_each_cpu* macros iterate over cpu stacks using pir as index and returns cpu thread pointer if state != cpu_state_no_cpu. For cpus that are not found on device-tree the state may hold junk value leading OPAL to access invalid cpu thread area. This further leads to accessing pointers with junk values causing machine check (MCE) during OPAL init code. Fix this by Initializing all the cpu thread areas upto cpu_max_pir. [ 182.049714372,3] *********************************************** [ 182.049878580,3] Fatal MCE at 0000000030039738 .init_trace_buffers+0x21c MSR 9000000000201002 [ 182.049943811,3] Cause: load real address error [ 182.049968681,3] Effective address: 0x480113a4791c4a50 [ 182.050000736,3] CFAR : 00000000300395b8 MSR : 9000000000201002 [ 182.050035376,3] SRR0 : 0000000030039738 SRR1 : 9000000000201002 [ 182.050072878,3] HSRR0: 0000000030020024 HSRR1: 9000000000001000 [ 182.050117303,3] DSISR: 00000040 DAR : 480113a4791c4a50 [ 182.050149054,3] LR : 0000000030039744 CTR : 0000000000000000 [ 182.050182991,3] CR : 42000224 XER : 00000000 [ 182.050217262,3] GPR00: 000000003003962c GPR16: 0000000032d50000 [ 182.050255746,3] GPR01: 0000000032d53a50 GPR17: 0000000030003198 [ 182.050288081,3] GPR02: 000000003014cb00 GPR18: 0000000000000000 [ 182.050331474,3] GPR03: 0000000031c50000 GPR19: 0000000000000000 [ 182.050371934,3] GPR04: 0000000000000000 GPR20: 0000000000000000 [ 182.050416212,3] GPR05: ffffffffffffffff GPR21: 0000000000000001 [ 182.050454130,3] GPR06: 0000000000000005 GPR22: 00000000300f74eb [ 182.050488053,3] GPR07: 0000000000000028 GPR23: 00000000000fffd8 [ 182.050522774,3] GPR08: 000000000000067f GPR24: 00000000000fff40 [ 182.050566878,3] GPR09: 480113a4791c4a18 GPR25: 0000000000000070 [ 182.050601524,3] GPR10: 00000000078b0353 GPR26: 00000000300f7527 [ 182.050640345,3] GPR11: 0000000000000000 GPR27: 00000000300f7516 [ 182.050680816,3] GPR12: 0000000042000222 GPR28: 000000003acd0000 [ 182.050724099,3] GPR13: 000000000025a908 GPR29: 000000003acd0000 [ 182.050759728,3] GPR14: 0000000000000000 GPR30: 0000000000000000 [ 182.050790430,3] GPR15: 0000000000000000 GPR31: 00000000301f0038 CPU 0228 Backtrace: S: 0000000032d53d60 R: 000000003003962c .init_trace_buffers+0x110 S: 0000000032d53e30 R: 0000000030022f84 .main_cpu_entry+0x550 S: 0000000032d53f00 R: 00000000300031f8 not_fused+0x11c Signed-off-by: Mahesh Salgaonkar Signed-off-by: Nicholas Piggin [Folded Nick's patch to that added mark_all_secondary_cpus_absent() - Vasant] Signed-off-by: Vasant Hegde --- core/cpu.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/core/cpu.c b/core/cpu.c index f2b5bbc5d..dbc1ff445 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -1150,10 +1150,30 @@ void init_cpu_max_pir(void) prlog(PR_DEBUG, "CPU: New max PIR set to 0x%x\n", cpu_max_pir); } +/* + * Set cpu->state to cpu_state_no_cpu for all secondaries, before the dt is + * parsed and they will be flipped to present as populated CPUs are found. + * + * Some configurations (e.g., with memory encryption) will not zero system + * memory at boot, so can't rely on cpu->state to be zero (== cpu_state_no_cpu). + */ +static void mark_all_secondary_cpus_absent(void) +{ + unsigned int pir; + struct cpu_thread *cpu; + + for (pir = 0; pir <= cpu_max_pir; pir++) { + cpu = &cpu_stacks[pir].cpu; + if (cpu == boot_cpu) + continue; + cpu->state = cpu_state_no_cpu; + } +} + void init_all_cpus(void) { struct dt_node *cpus, *cpu; - unsigned int thread; + unsigned int pir, thread; int dec_bits = find_dec_bits(); cpus = dt_find_by_path(dt_root, "/cpus"); @@ -1161,9 +1181,11 @@ void init_all_cpus(void) init_tm_suspend_mode_property(); + mark_all_secondary_cpus_absent(); + /* Iterate all CPUs in the device-tree */ dt_for_each_child(cpus, cpu) { - unsigned int pir, server_no, chip_id, threads; + unsigned int server_no, chip_id, threads; enum cpu_thread_state state; const struct dt_property *p; struct cpu_thread *t, *pt0, *pt1; From patchwork Fri Jun 25 06:19:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1496940 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=fTeeXFtO; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GB6NK2SjYz9sRf for ; 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Fri, 25 Jun 2021 06:20:45 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:45 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:35 +0530 Message-Id: <20210625061937.47314-21-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: s2-cJY3fKCxzrLpuLSZhp2_gS969BKmD X-Proofpoint-ORIG-GUID: s2-cJY3fKCxzrLpuLSZhp2_gS969BKmD X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_01:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 mlxlogscore=999 adultscore=0 impostorscore=0 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 20/22] hw/imc: Cleanup code to define scom addr for IMC at run time X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Anju T Sudhakar Currently scom addresses for IMC are defined at compile time. The scom addresses may vary for different processor generations. So clean up the code to pick the right scom addresses, based on the processor version at run time. Signed-off-by: Anju T Sudhakar --- hw/imc.c | 34 ++++++++++++++++++++++++++++++++-- include/imc.h | 4 ++-- 2 files changed, 34 insertions(+), 4 deletions(-) diff --git a/hw/imc.c b/hw/imc.c index c186da04c..cae112041 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -28,6 +28,15 @@ * b’000’- 4K entries * 64 per * entry = 256K buffersize */ +static uint64_t TRACE_IMC_ADDR; +static uint64_t CORE_IMC_EVENT_MASK_ADDR; +/* + * Initialise these with the pdbar and htm scom port address array + * at run time, based on the processor version. + */ +static unsigned int *pdbar_scom_index; +static unsigned int *htm_scom_index; + /* * Nest IMC PMU names along with their bit values as represented in the * imc_chip_avl_vector(in struct imc_chip_cb, look at include/imc.h). @@ -142,13 +151,13 @@ static bool is_nest_mem_initialized(struct imc_chip_cb *ptr) * SCOM port addresses in the arrays below, each for Hardware Trace Macro (HTM) * mode and PDBAR. */ -static unsigned int pdbar_scom_index[] = { +static unsigned int pdbar_scom_index_p9[] = { 0x1001220B, 0x1001230B, 0x1001260B, 0x1001270B }; -static unsigned int htm_scom_index[] = { +static unsigned int htm_scom_index_p9[] = { 0x10012200, 0x10012300, 0x10012600, @@ -530,6 +539,22 @@ void imc_decompress_catalog(void) xz_start_decompress(imc_xz); } +static int setup_imc_scoms(void) +{ + switch (proc_gen) { + case proc_gen_p9: + CORE_IMC_EVENT_MASK_ADDR = CORE_IMC_EVENT_MASK_ADDR_P9; + TRACE_IMC_ADDR = TRACE_IMC_ADDR_P9; + pdbar_scom_index = pdbar_scom_index_p9; + htm_scom_index = htm_scom_index_p9; + return 0; + default: + prerror("%s: Unknown cpu type\n", __func__); + break; + } + return -1; +} + /* * Load the IMC pnor partition and find the appropriate sub-partition * based on the platform's PVR. @@ -624,6 +649,11 @@ imc_mambo: disable_imc_type_from_dt(dev, IMC_COUNTER_CHIP); } + if (setup_imc_scoms()) { + prerror("IMC: Failed to setup the scoms\n"); + goto err; + } + /* * If the dt_attach_root() fails, "imc-counters" node will not be * seen in the device-tree and hence OS should not make any diff --git a/include/imc.h b/include/imc.h index 7aae7921b..a446dc581 100644 --- a/include/imc.h +++ b/include/imc.h @@ -109,7 +109,7 @@ struct imc_chip_cb /* * Core IMC SCOMs */ -#define CORE_IMC_EVENT_MASK_ADDR 0x20010AA8ull +#define CORE_IMC_EVENT_MASK_ADDR_P9 0x20010AA8ull #define CORE_IMC_EVENT_MASK 0x0402010000000000ull #define CORE_IMC_PDBAR_MASK 0x0003ffffffffe000ull #define CORE_IMC_HTM_MODE_ENABLE 0xE800000000000000ull @@ -132,7 +132,7 @@ struct imc_chip_cb * | | | * *CPMC1SEL *CPMC2SEL *BUFFERSIZE */ -#define TRACE_IMC_ADDR 0x20010AA9ull +#define TRACE_IMC_ADDR_P9 0x20010AA9ull #define TRACE_IMC_SAMPLESEL(x) ((uint64_t)x << 62) #define TRACE_IMC_CPMC_LOAD(x) ((0xffffffff - (uint64_t)x) << 30) #define TRACE_IMC_CPMC1SEL(x) ((uint64_t)x << 23) From patchwork Fri Jun 25 06:19:36 2021 Content-Type: text/plain; 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Fri, 25 Jun 2021 06:20:47 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:47 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:36 +0530 Message-Id: <20210625061937.47314-22-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: mqBsA-D22H9PgUEvt7rISMO8dtBy_2wq X-Proofpoint-GUID: mqBsA-D22H9PgUEvt7rISMO8dtBy_2wq X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_01:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 mlxlogscore=999 phishscore=0 spamscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 21/22] hw/imc: Use the xscom macros for IMC based on platform X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Anju T Sudhakar The xscom macros defined in the skiboot are platform specific. IMC opal APIs use these xscom definitions, to read and write to scom ports. Cleanup the code to pick the appropriate xscom macro definition based on the running platform. Signed-off-by: Anju T Sudhakar --- hw/imc.c | 95 ++++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 61 insertions(+), 34 deletions(-) diff --git a/hw/imc.c b/hw/imc.c index cae112041..e7893b50e 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -700,6 +700,33 @@ static int stop_api_init(struct proc_chip *chip, int phys_core_id, return ret; } +/* Function to return the scom address for the specified core */ +static uint32_t get_imc_scom_addr_for_core(int core, uint64_t addr) +{ + uint32_t scom_addr; + + switch (proc_gen) { + case proc_gen_p9: + scom_addr = XSCOM_ADDR_P9_EC(core, addr); + return scom_addr; + default: + return 0; + } +} + +/* Function to return the scom address for the specified core in the quad */ +static uint32_t get_imc_scom_addr_for_quad(int core, uint64_t addr) +{ + uint32_t scom_addr; + + switch (proc_gen) { + case proc_gen_p9: + scom_addr = XSCOM_ADDR_P9_EQ(core, addr); + return scom_addr; + default: + return 0; + } +} /* * opal_imc_counters_init : This call initialize the IMC engine. * @@ -712,7 +739,7 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu struct cpu_thread *c = find_cpu_by_pir(cpu_pir); int port_id, phys_core_id; int ret; - uint32_t scoms; + uint32_t pdbar_addr, event_mask_addr, htm_addr, trace_addr; uint64_t trace_scom_val = TRACE_IMC_SCOM(IMC_TRACE_SAMPLESEL_VAL, IMC_TRACE_CPMCLOAD_VAL, 0, IMC_TRACE_CPMC2SEL_VAL, @@ -735,6 +762,12 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) return OPAL_SUCCESS; + /* Get the scom address for this core, based on the platform */ + pdbar_addr = get_imc_scom_addr_for_quad(phys_core_id, + pdbar_scom_index[port_id]); + event_mask_addr = get_imc_scom_addr_for_core(phys_core_id, + CORE_IMC_EVENT_MASK_ADDR); + /* * Core IMC hardware mandate initing of three scoms * to enbale or disable of the Core IMC engine. @@ -750,9 +783,7 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu */ - if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EQ(phys_core_id, - pdbar_scom_index[port_id]), + if (xscom_write(c->chip_id, pdbar_addr, (u64)(CORE_IMC_PDBAR_MASK & addr))) { prerror("error in xscom_write for pdbar\n"); return OPAL_HARDWARE; @@ -762,18 +793,15 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) { struct proc_chip *chip = get_chip(c->chip_id); - scoms = XSCOM_ADDR_P9_EQ(phys_core_id, - pdbar_scom_index[port_id]); - ret = stop_api_init(chip, phys_core_id, scoms, + ret = stop_api_init(chip, phys_core_id, pdbar_addr, (u64)(CORE_IMC_PDBAR_MASK & addr), P9_STOP_SCOM_REPLACE, P9_STOP_SECTION_EQ_SCOM, "pdbar"); if (ret) return ret; - scoms = XSCOM_ADDR_P9_EC(phys_core_id, - CORE_IMC_EVENT_MASK_ADDR); - ret = stop_api_init(chip, phys_core_id, scoms, + ret = stop_api_init(chip, phys_core_id, + event_mask_addr, (u64)CORE_IMC_EVENT_MASK, P9_STOP_SCOM_REPLACE, P9_STOP_SECTION_CORE_SCOM, @@ -786,17 +814,16 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu } } - if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EC(phys_core_id, - CORE_IMC_EVENT_MASK_ADDR), - (u64)CORE_IMC_EVENT_MASK)) { + if (xscom_write(c->chip_id, event_mask_addr, + (u64)CORE_IMC_EVENT_MASK)) { prerror("error in xscom_write for event mask\n"); return OPAL_HARDWARE; } - if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EQ(phys_core_id, - htm_scom_index[port_id]), + /* Get the scom address for htm_mode scom based on the platform */ + htm_addr = get_imc_scom_addr_for_quad(phys_core_id, + htm_scom_index[port_id]); + if (xscom_write(c->chip_id, htm_addr, (u64)CORE_IMC_HTM_MODE_DISABLE)) { prerror("error in xscom_write for htm mode\n"); return OPAL_HARDWARE; @@ -812,13 +839,17 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) return OPAL_SUCCESS; + trace_addr = get_imc_scom_addr_for_core(phys_core_id, + TRACE_IMC_ADDR); + htm_addr = get_imc_scom_addr_for_quad(phys_core_id, + htm_scom_index[port_id]); + if (has_deep_states) { if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) { struct proc_chip *chip = get_chip(c->chip_id); - scoms = XSCOM_ADDR_P9_EC(phys_core_id, - TRACE_IMC_ADDR); - ret = stop_api_init(chip, phys_core_id, scoms, + ret = stop_api_init(chip, phys_core_id, + trace_addr, trace_scom_val, P9_STOP_SCOM_REPLACE, P9_STOP_SECTION_CORE_SCOM, @@ -830,15 +861,11 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu return OPAL_HARDWARE; } } - if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EQ(phys_core_id, htm_scom_index[port_id]), - (u64)CORE_IMC_HTM_MODE_DISABLE)) { + if (xscom_write(c->chip_id, htm_addr, (u64)CORE_IMC_HTM_MODE_DISABLE)) { prerror("IMC-trace: error in xscom_write for htm mode\n"); return OPAL_HARDWARE; } - if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EC(phys_core_id, - TRACE_IMC_ADDR), trace_scom_val)) { + if (xscom_write(c->chip_id, trace_addr, trace_scom_val)) { prerror("IMC-trace: error in xscom_write for trace mode\n"); return OPAL_HARDWARE; } @@ -857,6 +884,7 @@ static int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir) struct cpu_thread *c = find_cpu_by_pir(cpu_pir); struct imc_chip_cb *cb; int port_id, phys_core_id; + uint32_t htm_addr; if (!c) return OPAL_PARAMETER; @@ -890,16 +918,15 @@ static int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir) if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) return OPAL_SUCCESS; + htm_addr = get_imc_scom_addr_for_quad(phys_core_id, + htm_scom_index[port_id]); /* * Enables the core imc engine by appropriately setting * bits 4-9 of the HTM_MODE scom port. No initialization * is done in this call. This just enables the the counters * to count with the previous initialization. */ - if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EQ(phys_core_id, - htm_scom_index[port_id]), - (u64)CORE_IMC_HTM_MODE_ENABLE)) { + if (xscom_write(c->chip_id, htm_addr, (u64)CORE_IMC_HTM_MODE_ENABLE)) { prerror("IMC OPAL_start: error in xscom_write for htm_mode\n"); return OPAL_HARDWARE; } @@ -918,6 +945,7 @@ static int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir) struct imc_chip_cb *cb; struct cpu_thread *c = find_cpu_by_pir(cpu_pir); int port_id, phys_core_id; + uint32_t htm_addr; if (!c) return OPAL_PARAMETER; @@ -952,14 +980,13 @@ static int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir) if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) return OPAL_SUCCESS; + htm_addr = get_imc_scom_addr_for_quad(phys_core_id, + htm_scom_index[port_id]); /* * Disables the core imc engine by clearing * bits 4-9 of the HTM_MODE scom port. */ - if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EQ(phys_core_id, - htm_scom_index[port_id]), - (u64) CORE_IMC_HTM_MODE_DISABLE)) { + if (xscom_write(c->chip_id, htm_addr, (u64) CORE_IMC_HTM_MODE_DISABLE)) { prerror("error in xscom_write for htm_mode\n"); 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Fri, 25 Jun 2021 06:20:49 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.46.25]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 25 Jun 2021 06:20:49 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 25 Jun 2021 11:49:37 +0530 Message-Id: <20210625061937.47314-23-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> References: <20210625061937.47314-1-hegdevasant@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: cr1nPQVcFUNKoVGqb3Hkc0xYl2D9AUlw X-Proofpoint-GUID: cr1nPQVcFUNKoVGqb3Hkc0xYl2D9AUlw X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_02:2021-06-24, 2021-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 bulkscore=0 spamscore=0 adultscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 mlxlogscore=999 lowpriorityscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106250034 Subject: [Skiboot] [PATCH 22/22] hw/imc: Do scoms on the secondary core in fused core mode for core-imc counters X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Anju T Sudhakar Core IMC hardware mandates initiating of three scoms to enable or disable of the Core IMC engine. This has to be done for each core, and is done in the opal_imc_counters_init(). In fused core mode, the scom has to be done explicitly for the secondary core to enable or disable core IMC engine in that core. Do the scom for the secondary core, by calculating the core id from the incoming cpu id. This patch is based on the series, Initial fused-core support for POWER9 [v5]: https://lists.ozlabs.org/pipermail/skiboot/2020-April/016778.html Signed-off-by: Anju T Sudhakar --- hw/imc.c | 153 ++++++++++++++++++++++++++++++++----------------------- 1 file changed, 90 insertions(+), 63 deletions(-) diff --git a/hw/imc.c b/hw/imc.c index e7893b50e..dab668fe6 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -727,6 +727,82 @@ static uint32_t get_imc_scom_addr_for_quad(int core, uint64_t addr) return 0; } } + +static int64_t core_imc_counters_init(uint64_t addr, int port_id, + int phys_core_id, struct cpu_thread *c) +{ + uint32_t pdbar_addr, event_mask_addr, htm_addr; + int ret; + + /* Get the scom address for this core, based on the platform */ + pdbar_addr = get_imc_scom_addr_for_quad(phys_core_id, + pdbar_scom_index[port_id]); + event_mask_addr = get_imc_scom_addr_for_core(phys_core_id, + CORE_IMC_EVENT_MASK_ADDR); + + /* + * Core IMC hardware mandate initing of three scoms + * to enbale or disable of the Core IMC engine. + * + * PDBAR: Scom contains the real address to store per-core + * counter data in memory along with other bits. + * + * EventMask: Scom contain bits to denote event to multiplex + * at different MSR[HV PR] values, along with bits for + * sampling duration. + * + * HTM Scom: scom to enable counter data movement to memory. + */ + + + if (xscom_write(c->chip_id, pdbar_addr, + (u64)(CORE_IMC_PDBAR_MASK & addr))) { + prerror("error in xscom_write for pdbar\n"); + return OPAL_HARDWARE; + } + + if (has_deep_states) { + if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) { + struct proc_chip *chip = get_chip(c->chip_id); + + ret = stop_api_init(chip, phys_core_id, pdbar_addr, + (u64)(CORE_IMC_PDBAR_MASK & addr), + P9_STOP_SCOM_REPLACE, + P9_STOP_SECTION_EQ_SCOM, + "pdbar"); + if (ret) + return ret; + ret = stop_api_init(chip, phys_core_id, + event_mask_addr, + (u64)CORE_IMC_EVENT_MASK, + P9_STOP_SCOM_REPLACE, + P9_STOP_SECTION_CORE_SCOM, + "event_mask"); + if (ret) + return ret; + } else { + prerror("IMC: Wakeup engine not present!"); + return OPAL_HARDWARE; + } + } + + if (xscom_write(c->chip_id, event_mask_addr, + (u64)CORE_IMC_EVENT_MASK)) { + prerror("error in xscom_write for event mask\n"); + return OPAL_HARDWARE; + } + + /* Get the scom address for htm_mode scom based on the platform */ + htm_addr = get_imc_scom_addr_for_quad(phys_core_id, + htm_scom_index[port_id]); + if (xscom_write(c->chip_id, htm_addr, + (u64)CORE_IMC_HTM_MODE_DISABLE)) { + prerror("error in xscom_write for htm mode\n"); + return OPAL_HARDWARE; + } + return OPAL_SUCCESS; +} + /* * opal_imc_counters_init : This call initialize the IMC engine. * @@ -739,7 +815,7 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu struct cpu_thread *c = find_cpu_by_pir(cpu_pir); int port_id, phys_core_id; int ret; - uint32_t pdbar_addr, event_mask_addr, htm_addr, trace_addr; + uint32_t htm_addr, trace_addr; uint64_t trace_scom_val = TRACE_IMC_SCOM(IMC_TRACE_SAMPLESEL_VAL, IMC_TRACE_CPMCLOAD_VAL, 0, IMC_TRACE_CPMC2SEL_VAL, @@ -762,73 +838,24 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) return OPAL_SUCCESS; - /* Get the scom address for this core, based on the platform */ - pdbar_addr = get_imc_scom_addr_for_quad(phys_core_id, - pdbar_scom_index[port_id]); - event_mask_addr = get_imc_scom_addr_for_core(phys_core_id, - CORE_IMC_EVENT_MASK_ADDR); - + ret = core_imc_counters_init(addr, port_id, phys_core_id, c); + if (ret < 0) + return ret; /* - * Core IMC hardware mandate initing of three scoms - * to enbale or disable of the Core IMC engine. - * - * PDBAR: Scom contains the real address to store per-core - * counter data in memory along with other bits. - * - * EventMask: Scom contain bits to denote event to multiplex - * at different MSR[HV PR] values, along with bits for - * sampling duration. - * - * HTM Scom: scom to enable counter data movement to memory. + * If fused core is supported, do the scoms for the + * secondary core also. */ + if (this_cpu()->is_fused_core) { + struct cpu_thread *c1 = find_cpu_by_pir(cpu_pir ^ 1); + phys_core_id = pir_to_core_id(c1->pir); + port_id = phys_core_id % 4; - if (xscom_write(c->chip_id, pdbar_addr, - (u64)(CORE_IMC_PDBAR_MASK & addr))) { - prerror("error in xscom_write for pdbar\n"); - return OPAL_HARDWARE; - } - - if (has_deep_states) { - if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) { - struct proc_chip *chip = get_chip(c->chip_id); - - ret = stop_api_init(chip, phys_core_id, pdbar_addr, - (u64)(CORE_IMC_PDBAR_MASK & addr), - P9_STOP_SCOM_REPLACE, - P9_STOP_SECTION_EQ_SCOM, - "pdbar"); - if (ret) - return ret; - ret = stop_api_init(chip, phys_core_id, - event_mask_addr, - (u64)CORE_IMC_EVENT_MASK, - P9_STOP_SCOM_REPLACE, - P9_STOP_SECTION_CORE_SCOM, - "event_mask"); - if (ret) - return ret; - } else { - prerror("IMC: Wakeup engine not present!"); - return OPAL_HARDWARE; - } - } - - if (xscom_write(c->chip_id, event_mask_addr, - (u64)CORE_IMC_EVENT_MASK)) { - prerror("error in xscom_write for event mask\n"); - return OPAL_HARDWARE; - } - - /* Get the scom address for htm_mode scom based on the platform */ - htm_addr = get_imc_scom_addr_for_quad(phys_core_id, - htm_scom_index[port_id]); - if (xscom_write(c->chip_id, htm_addr, - (u64)CORE_IMC_HTM_MODE_DISABLE)) { - prerror("error in xscom_write for htm mode\n"); - return OPAL_HARDWARE; + ret = core_imc_counters_init(addr, port_id, phys_core_id, c1); + if (ret < 0) + return ret; } - return OPAL_SUCCESS; + return ret; case OPAL_IMC_COUNTERS_TRACE: if (!c) return OPAL_PARAMETER;