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Thu, 27 May 2021 11:52:58 +0000 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 27 May 2021 11:52:57 +0000 Received: from buildserver-hdc-comms.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.15) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 May 2021 04:52:55 -0700 From: Om Prakash Singh To: , , , , CC: , , , , , Om Prakash Singh Subject: [RESEND PATCH V1 1/5] PCI: tegra: Fix handling BME_CHGED event Date: Thu, 27 May 2021 17:22:42 +0530 Message-ID: <20210527115246.20509-2-omp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210527115246.20509-1-omp@nvidia.com> References: <20210527115246.20509-1-omp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fe494918-8997-429f-e936-08d92105f949 X-MS-TrafficTypeDiagnostic: BN8PR12MB3201: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2887; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2021 11:52:58.9530 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fe494918-8997-429f-e936-08d92105f949 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.36];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3201 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org In tegra_pcie_ep_hard_irq(), APPL_INTR_STATUS_L0 is stored in val and again APPL_INTR_STATUS_L1_0_0 is also stored in val. So when execution reaches "if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT)", val is not correct. Signed-off-by: Om Prakash Singh --- drivers/pci/controller/dwc/pcie-tegra194.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index bafd2c6ab3c2..c51d666c9d87 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -615,10 +615,10 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) struct tegra_pcie_dw *pcie = arg; struct dw_pcie_ep *ep = &pcie->pci.ep; int spurious = 1; - u32 val, tmp; + u32 val_l0, val, tmp; - val = appl_readl(pcie, APPL_INTR_STATUS_L0); - if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) { + val_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0); + if (val_l0 & APPL_INTR_STATUS_L0_LINK_STATE_INT) { val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0); appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0); @@ -636,7 +636,7 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) spurious = 0; } - if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) { + if (val_l0 & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) { val = appl_readl(pcie, APPL_INTR_STATUS_L1_15); appl_writel(pcie, val, APPL_INTR_STATUS_L1_15); @@ -648,8 +648,8 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) if (spurious) { dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", - val); - appl_writel(pcie, val, APPL_INTR_STATUS_L0); + val_l0); + appl_writel(pcie, val_l0, APPL_INTR_STATUS_L0); } return IRQ_HANDLED; From patchwork Thu May 27 11:52:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Om Prakash Singh X-Patchwork-Id: 1484561 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=DPUtwxTM; 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Thu, 27 May 2021 04:52:58 -0700 From: Om Prakash Singh To: , , , , CC: , , , , , Om Prakash Singh Subject: [RESEND PATCH V1 2/5] PCI: tegra: Fix MSI-X programming Date: Thu, 27 May 2021 17:22:43 +0530 Message-ID: <20210527115246.20509-3-omp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210527115246.20509-1-omp@nvidia.com> References: <20210527115246.20509-1-omp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a9fd129b-e75e-4a28-1651-08d92105fc58 X-MS-TrafficTypeDiagnostic: DM6PR12MB3737: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:327; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xegRNsU5lPTsdmjOJLZHSFcPY/CIK1jQnhmGdcD41eizudW3GLeJeJZ2WMN43HjgARGrlUvO9dUGfpdJWy7o5C5rYirJ1wAH6h0DxQFZ630aiV+znYvwxHF9OY0zK8YQR8o0GBwDkb2oCQaFiVm2ghQHK0plDtZwB6T35kYe28/foURs/n7KOyCvf6DHAFy0NK54OIGuwSib8rLnF8NixXCsAfh90THaVFJt/wVGwqWmwtLhSB1c+DEtZ2PTtk2CWzL5wBYVln6uMfoy86mkJIITV6eF/otKABcei0jMutEjn4r4GINMryecr5FOSojiGNx2nV3w6bVNxFPv43IkQWIkRY2yYryWzuM5YlCBNpQKCV0cfRijhbfFACNn1/IN051hZaGnst5uu95eSxDUOPePgJV5TkHHbkgtULNHtltkpOMYGv4LSQ1cKuKG1LBcsqHjRT0At30e+TCgqSTIbZsBt3ovWEgzTXSV5kuFMpTQeSkuJTR9AuRkoQpvLCvUgOuhLGChpqgVoCxWQruVKlbw/m6k54h9XthU2f91eu0SuBAdnBAkeKT2q3VRpq03kZs2ViBTgsPSLPPJ9aXO5jqY4l+bx6fUTMgZqt5X/6QUT9kzRf/nZswPd52SHwf/1mwX7Lx4NS3PJwEtlpQrDP+17hkSYCO+x7T2P20Erus= X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(136003)(346002)(39860400002)(376002)(396003)(46966006)(36840700001)(186003)(26005)(54906003)(336012)(2616005)(47076005)(1076003)(316002)(36906005)(478600001)(110136005)(426003)(5660300002)(8936002)(107886003)(7696005)(82310400003)(82740400003)(86362001)(83380400001)(8676002)(356005)(4326008)(36860700001)(36756003)(70586007)(2906002)(6636002)(7636003)(70206006)(6666004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2021 11:53:04.0710 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a9fd129b-e75e-4a28-1651-08d92105fc58 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3737 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Lower order MSI-X address is programmed in MSIX_ADDR_MATCH_HIGH_OFF DBI register instead of higher order address. This patch fixes this programming mistake. Signed-off-by: Om Prakash Singh --- drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index c51d666c9d87..58fc2615014d 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1863,7 +1863,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK); val |= MSIX_ADDR_MATCH_LOW_OFF_EN; dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_LOW_OFF, val); - val = (lower_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK); + val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK); dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val); ret = dw_pcie_ep_init_complete(ep); From patchwork Thu May 27 11:52:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Om Prakash Singh X-Patchwork-Id: 1484563 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.36 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.36; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.36) by DM6NAM11FT066.mail.protection.outlook.com (10.13.173.179) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4129.25 via Frontend Transport; Thu, 27 May 2021 11:53:06 +0000 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 27 May 2021 11:53:05 +0000 Received: from buildserver-hdc-comms.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.15) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 May 2021 04:53:02 -0700 From: Om Prakash Singh To: , , , , CC: , , , , , Om Prakash Singh Subject: [RESEND PATCH V1 3/5] PCI: tegra: Disable interrupts before entering L2 Date: Thu, 27 May 2021 17:22:44 +0530 Message-ID: <20210527115246.20509-4-omp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210527115246.20509-1-omp@nvidia.com> References: <20210527115246.20509-1-omp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 83425fd2-10ff-46e1-6503-08d92105fdeb X-MS-TrafficTypeDiagnostic: DM5PR1201MB0156: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2021 11:53:06.7142 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83425fd2-10ff-46e1-6503-08d92105fdeb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.36];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0156 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra194 implements suspend_noirq() hook and during the system suspend, the link is taken to L2 state after PME_Turn_off handshake and if it doesn't go into L2, PERST# is asserted. It is observed that with some of the endpoints (Ex:- Marvell SATA controller), the link doesn't go into L2 state and asserting PERST# results in Surprise Link Down error and the corresponding AER interrupt is also raised. Since the system is in noirq phase, this interrupt is not served. Both PME and AER interrupts are served by the same wire interrupt in Tegra194, and since the PCIe sub-system enables wake capability for PME interrupt, having a pending AER interrupt is treated as PME wake interrupt by the system and prevents the system going into the suspend state. To address this issue, the interrupts are disabled before taking the link into L2 state as the interrupts are not expected anyway from the controller afterward. Signed-off-by: Om Prakash Singh --- drivers/pci/controller/dwc/pcie-tegra194.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 58fc2615014d..ae62fdc840e6 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1593,6 +1593,16 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) return; } + /* + * PCIe controller exits from L2 only if reset is applied, so + * controller doesn't handle interrupts. But in cases where + * L2 entry fails, PERST# is asserted which can trigger surprise + * link down AER. However this function call happens in + * suspend_noirq(), so AER interrupt will not be processed. + * Disable all interrupts to avoid such a scenario. + */ + appl_writel(pcie, 0x0, APPL_INTR_EN_L0_0); + if (tegra_pcie_try_link_l2(pcie)) { dev_info(pcie->dev, "Link didn't transition to L2 state\n"); /* From patchwork Thu May 27 11:52:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Om Prakash Singh X-Patchwork-Id: 1484565 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=hveRruq+; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FrR683T6Vz9sW7 for ; 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Thu, 27 May 2021 11:53:10 +0000 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 27 May 2021 04:53:09 -0700 Received: from buildserver-hdc-comms.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.15) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 May 2021 04:53:06 -0700 From: Om Prakash Singh To: , , , , CC: , , , , , Om Prakash Singh Subject: [RESEND PATCH V1 4/5] PCI: tegra: Don't allow suspend when Tegra PCIe is in EP mode Date: Thu, 27 May 2021 17:22:45 +0530 Message-ID: <20210527115246.20509-5-omp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210527115246.20509-1-omp@nvidia.com> References: <20210527115246.20509-1-omp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b8c38a60-a37d-4b12-2f36-08d92105ffed X-MS-TrafficTypeDiagnostic: BN6PR1201MB2531: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4502; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2021 11:53:10.0833 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8c38a60-a37d-4b12-2f36-08d92105ffed X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.32];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB2531 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org When Tegra PCIe is in endpoint mode it should be available for root port. PCIe link up by root port fails if it is in suspend state. So, don't allow Tegra to suspend when endpoint mode is enabled. Signed-off-by: Om Prakash Singh --- drivers/pci/controller/dwc/pcie-tegra194.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index ae62fdc840e6..93c89f2084a7 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2276,6 +2276,11 @@ static int tegra_pcie_dw_suspend_late(struct device *dev) struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); u32 val; + if (pcie->mode == DW_PCIE_EP_TYPE) { + dev_err(dev, "Tegra PCIe is in EP mode, suspend not allowed"); + return -EPERM; + } + if (!pcie->link_state) return 0; From patchwork Thu May 27 11:52:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Om Prakash Singh X-Patchwork-Id: 1484567 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT052.mail.protection.outlook.com (10.13.172.111) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4129.25 via Frontend Transport; Thu, 27 May 2021 11:53:14 +0000 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 27 May 2021 11:53:13 +0000 Received: from buildserver-hdc-comms.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.15) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 May 2021 04:53:10 -0700 From: Om Prakash Singh To: , , , , CC: , , , , , Om Prakash Singh Subject: [RESEND PATCH V1 5/5] PCI: tegra: Cleanup unused code Date: Thu, 27 May 2021 17:22:46 +0530 Message-ID: <20210527115246.20509-6-omp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210527115246.20509-1-omp@nvidia.com> References: <20210527115246.20509-1-omp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3c96e8d9-303a-4568-c0ea-08d92106025b X-MS-TrafficTypeDiagnostic: MN2PR12MB3888: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:148; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2021 11:53:14.1664 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c96e8d9-303a-4568-c0ea-08d92106025b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3888 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Remove unused code from function tegra_pcie_config_ep. Signed-off-by: Om Prakash Singh --- drivers/pci/controller/dwc/pcie-tegra194.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 93c89f2084a7..096aa5306fda 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2045,13 +2045,6 @@ static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie, return ret; } - name = devm_kasprintf(dev, GFP_KERNEL, "tegra_pcie_%u_ep_work", - pcie->cid); - if (!name) { - dev_err(dev, "Failed to create PCIe EP work thread string\n"); - return -ENOMEM; - } - pm_runtime_enable(dev); ret = dw_pcie_ep_init(ep);