From patchwork Wed May 26 08:43:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 1483924 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=rrgdliZo; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FqkxV2JYKz9sTD for ; Wed, 26 May 2021 18:43:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233093AbhEZIo4 (ORCPT ); Wed, 26 May 2021 04:44:56 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44602 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232918AbhEZIoz (ORCPT ); Wed, 26 May 2021 04:44:55 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14Q8hH7p050656; Wed, 26 May 2021 03:43:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622018597; bh=OoFhCptIPab1wWjNKqETXIysZNtoiUpz9z0Sf7DMLwI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rrgdliZoFsx+EeMb6Fb+r6cbcCFnUr2baarxK2xgQTHq30tzYDoRcg+islwITIMsi aDiWwxVfeLqiaoiAVUcvt1blkKha25E8wfi2paIQQZcbQphlZif1LPL3vtpjBhwt/V gZdcyaIv8YHtaf9Jz2WFAULJS+YTlOzeiUQcG+Z8= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14Q8hHXL067034 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 03:43:17 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 03:43:17 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 03:43:17 -0500 Received: from lokesh-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14Q8h75V049811; Wed, 26 May 2021 03:43:13 -0500 From: Lokesh Vutla To: , , , Rob Herring CC: , Sekhar Nori , Vignesh R , Nishanth Menon , , Device Tree Mailing List , Linux ARM Mailing List , Linux OMAP Mailing List , Lokesh Vutla Subject: [PATCH 1/4] arm: dts: ti: drop usage of redundant compatible Date: Wed, 26 May 2021 14:13:03 +0530 Message-ID: <20210526084306.6534-2-lokeshvutla@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210526084306.6534-1-lokeshvutla@ti.com> References: <20210526084306.6534-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Commit 229110c1aa691 ("ARM: dts: am437x/am33xx/da850: Add new ECAP and EPWM bindings") added ti,am3352-ehrpwm compatible which is similar to ti,am33xx-ehrpwm but without out t,hwmod properties. But with commit 58bfbea5b1c68 ("ARM: dts: am437x/am33xx: Remove hwmod entries for ECAP and EPWM nodes") dropped support for all ti,hwmod for ehrpwm, but missed deprecating ti,am33xx-ehrpwm compatible. So drop ti,am33xx-ehrpwm from DT as it is no longer needed. ti-ehrpwn driver still support ti,am33xx-ehrpwm in order to maintain backward compatibility. Signed-off-by: Lokesh Vutla --- .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 13 ++++++------- arch/arm/boot/dts/am33xx-l4.dtsi | 9 +++------ arch/arm/boot/dts/am437x-l4.dtsi | 18 ++++++------------ arch/arm/boot/dts/da850.dtsi | 6 ++---- 4 files changed, 17 insertions(+), 29 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index c7e28f6d28be..e124e41418d8 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -2,10 +2,10 @@ TI SOC EHRPWM based PWM controller Required properties: - compatible: Must be "ti,-ehrpwm". - for am33xx - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; - for am4372 - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm"; + for am33xx - compatible = "ti,am3352-ehrpwm"; + for am4372 - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm"; for am654 - compatible = "ti,am654-ehrpwm", "ti-am3352-ehrpwm"; - for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm"; + for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm"; for dra746 - compatible = "ti,dra746-ehrpwm", "ti-am3352-ehrpwm"; - #pwm-cells: should be 3. See pwm.yaml in this directory for a description of the cells format. The only third cell flag supported by this binding is @@ -19,7 +19,7 @@ Optional properties: Example: ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */ - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x100>; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; @@ -27,16 +27,15 @@ ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */ }; ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */ - compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; + compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; - ti,hwmods = "ehrpwm0"; }; ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */ - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x1f00000 0x2000>; }; diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 039a9ab4c7ea..fbf3458ab246 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -2017,8 +2017,7 @@ eqep0: counter@180 { }; ehrpwm0: pwm@200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; @@ -2078,8 +2077,7 @@ eqep1: counter@180 { }; ehrpwm1: pwm@200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; @@ -2139,8 +2137,7 @@ eqep2: counter@180 { }; ehrpwm2: pwm@200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index e217ffc09770..e796b9bcc54e 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -1760,8 +1760,7 @@ ecap0: ecap@100 { ehrpwm0: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; @@ -1812,8 +1811,7 @@ ecap1: ecap@100 { ehrpwm1: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; @@ -1864,8 +1862,7 @@ ecap2: ecap@100 { ehrpwm2: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; @@ -1905,8 +1902,7 @@ epwmss3: epwmss@0 { ehrpwm3: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; @@ -1946,8 +1942,7 @@ epwmss4: epwmss@0 { ehrpwm4: pwm@48308200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; @@ -1987,8 +1982,7 @@ epwmss5: epwmss@0 { ehrpwm5: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 7cf31b6e48b7..afdf3d3747ce 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -574,8 +574,7 @@ mmc1: mmc@21b000 { status = "disabled"; }; ehrpwm0: pwm@300000 { - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x300000 0x2000>; clocks = <&psc1 17>, <&ehrpwm_tbclk>; @@ -584,8 +583,7 @@ ehrpwm0: pwm@300000 { status = "disabled"; }; ehrpwm1: pwm@302000 { - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x302000 0x2000>; clocks = <&psc1 17>, <&ehrpwm_tbclk>; From patchwork Wed May 26 08:43:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 1483928 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=wTvgNktd; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Fqkxf2QXJz9s24 for ; Wed, 26 May 2021 18:43:34 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233167AbhEZIpD (ORCPT ); Wed, 26 May 2021 04:45:03 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44616 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233118AbhEZIo7 (ORCPT ); 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Wed, 26 May 2021 03:43:21 -0500 Received: from lokesh-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14Q8h75W049811; Wed, 26 May 2021 03:43:17 -0500 From: Lokesh Vutla To: , , , Rob Herring CC: , Sekhar Nori , Vignesh R , Nishanth Menon , , Device Tree Mailing List , Linux ARM Mailing List , Linux OMAP Mailing List , Lokesh Vutla Subject: [PATCH 2/4] dt-bindings: pwm: tiehrpwm: Make clock and clock-names as required properties Date: Wed, 26 May 2021 14:13:04 +0530 Message-ID: <20210526084306.6534-3-lokeshvutla@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210526084306.6534-1-lokeshvutla@ti.com> References: <20210526084306.6534-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Driver fails to probe when 'clock' and 'clock-names' properties are not populated in DT. But the binding documentation says these properties are optional. Fix this by making 'clock' and 'clock-names' properties as required. Signed-off-by: Lokesh Vutla --- Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index e124e41418d8..8eae48c9c5cd 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -11,8 +11,6 @@ Required properties: the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. - reg: physical base address and size of the registers map. - -Optional properties: - clocks: Handle to the PWM's time-base and functional clock. - clock-names: Must be set to "tbclk" and "fck". @@ -38,6 +36,8 @@ ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */ compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x1f00000 0x2000>; + clocks = <&psc1 17>, <&ehrpwm_tbclk>; + clock-names = "fck", "tbclk"; }; ehrpwm0: pwm@4843e200 { /* EHRPWM on dra746 */ From patchwork Wed May 26 08:43:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 1483930 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=wB8DZNot; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Fqkxl4kyTz9s24 for ; Wed, 26 May 2021 18:43:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232412AbhEZIpJ (ORCPT ); Wed, 26 May 2021 04:45:09 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44662 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233168AbhEZIpD (ORCPT ); Wed, 26 May 2021 04:45:03 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14Q8hQXi050692; Wed, 26 May 2021 03:43:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622018606; bh=u0xVOj8QY88CY3HHK41dwx4rZLKyf5aV5Tezwk+tDAU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wB8DZNotUSU+c+E2VgA8kdyIg4PAqcxcSS/1Z1bSof0yM0OO4lLBufDyRhk33U2kf N5dgSrRUJELas2TdIDnlPinzdBFhIh1FZNT7ZXQQFkDd57vAGgYrFNarGbxUn5kf2t BvAOvtT7NiVlce/DzGL/wUMyZglAu85WpL/hcwMM= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14Q8hQAw054998 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 03:43:26 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 03:43:25 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 03:43:25 -0500 Received: from lokesh-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14Q8h75X049811; Wed, 26 May 2021 03:43:21 -0500 From: Lokesh Vutla To: , , , Rob Herring CC: , Sekhar Nori , Vignesh R , Nishanth Menon , , Device Tree Mailing List , Linux ARM Mailing List , Linux OMAP Mailing List , Lokesh Vutla Subject: [PATCH 3/4] dt-bindings: pwm: pwm-tiehrpwm: Convert to json schema Date: Wed, 26 May 2021 14:13:05 +0530 Message-ID: <20210526084306.6534-4-lokeshvutla@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210526084306.6534-1-lokeshvutla@ti.com> References: <20210526084306.6534-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Convert the tiehrpwm binding to DT schema format using json-schema. Signed-off-by: Lokesh Vutla --- .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 49 -------------- .../devicetree/bindings/pwm/pwm-tiehrpwm.yaml | 64 +++++++++++++++++++ 2 files changed, 64 insertions(+), 49 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt deleted file mode 100644 index 8eae48c9c5cd..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ /dev/null @@ -1,49 +0,0 @@ -TI SOC EHRPWM based PWM controller - -Required properties: -- compatible: Must be "ti,-ehrpwm". - for am33xx - compatible = "ti,am3352-ehrpwm"; - for am4372 - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm"; - for am654 - compatible = "ti,am654-ehrpwm", "ti-am3352-ehrpwm"; - for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm"; - for dra746 - compatible = "ti,dra746-ehrpwm", "ti-am3352-ehrpwm"; -- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of - the cells format. The only third cell flag supported by this binding is - PWM_POLARITY_INVERTED. -- reg: physical base address and size of the registers map. -- clocks: Handle to the PWM's time-base and functional clock. -- clock-names: Must be set to "tbclk" and "fck". - -Example: - -ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */ - compatible = "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48300200 0x100>; - clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; -}; - -ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */ - compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48300200 0x80>; - clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; -}; - -ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */ - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x1f00000 0x2000>; - clocks = <&psc1 17>, <&ehrpwm_tbclk>; - clock-names = "fck", "tbclk"; -}; - -ehrpwm0: pwm@4843e200 { /* EHRPWM on dra746 */ - compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x4843e200 0x80>; - clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; - clock-names = "tbclk", "fck"; -}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.yaml b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.yaml new file mode 100644 index 000000000000..84a8d6d38cee --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-tiehrpwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI SOC EHRPWM based PWM controller + +maintainers: + - Vignesh R + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + oneOf: + - const: ti,am3352-ehrpwm + - items: + - enum: + - ti,da850-ehrpwm + - ti,am4372-ehrpwm + - ti,dra746-ehrpwm + - ti,am654-ehrpwm + - const: ti,am3352-ehrpwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + description: | + See pwm.yaml in this directory for a description of the cells format. + The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. + + clock-names: + items: + - const: tbclk + - const: fck + + clocks: + maxItems: 2 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */ + compatible = "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48300200 0x100>; + clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + }; From patchwork Wed May 26 08:43:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 1483934 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=T0+lXOl0; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Fqkxq03Whz9sVt for ; Wed, 26 May 2021 18:43:43 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233137AbhEZIpL (ORCPT ); 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Wed, 26 May 2021 03:43:30 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 03:43:30 -0500 Received: from lokesh-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14Q8h75Y049811; Wed, 26 May 2021 03:43:26 -0500 From: Lokesh Vutla To: , , , Rob Herring CC: , Sekhar Nori , Vignesh R , Nishanth Menon , , Device Tree Mailing List , Linux ARM Mailing List , Linux OMAP Mailing List , Lokesh Vutla Subject: [PATCH 4/4] dt-bindings: pwm: pwm-tiehrpwm: Add compatible string for AM64 SoC Date: Wed, 26 May 2021 14:13:06 +0530 Message-ID: <20210526084306.6534-5-lokeshvutla@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210526084306.6534-1-lokeshvutla@ti.com> References: <20210526084306.6534-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Add compatible string for AM64 SoC in device tree binding. Signed-off-by: Lokesh Vutla --- Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.yaml b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.yaml index 84a8d6d38cee..347ba356a3f5 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.yaml @@ -22,6 +22,7 @@ properties: - ti,am4372-ehrpwm - ti,dra746-ehrpwm - ti,am654-ehrpwm + - ti,am64-ehrpwm - const: ti,am3352-ehrpwm reg: