From patchwork Sun May 23 23:56:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1482574 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=QyWkmTzx; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FpHLb3D17z9sRf for ; Mon, 24 May 2021 09:56:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232082AbhEWX6E (ORCPT ); Sun, 23 May 2021 19:58:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232037AbhEWX6C (ORCPT ); Sun, 23 May 2021 19:58:02 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4BA5C061756; Sun, 23 May 2021 16:56:33 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id v5so31181359ljg.12; Sun, 23 May 2021 16:56:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MpvhPzX1ymg5vSIOj/R3c0XtSN9hCFreWZQ1rMcnPsI=; b=QyWkmTzxYCt90Z8KdFxCKVvjljk2oYwWSLjmMgJ9SimCxxdmWmY6YP5Fo2t9PEs3xl y0OXXKFsYObWXYkSpeSOIxdmlisEdcvx8eVnBxHaesYi2sAnYZyG1uYp5q5Urs82v8kk F5xHe8qLUdhW6QHNi696dZu24ll+lxwR2w3nNj8gEbLLpQoLGWDKRm2qjU2DH5vM18K9 OeH3vnszSjk6qB+nY6Y7fzStME2ts2BaxxRPpfrMUByd0/EedQLSV0jMLVX/fs52bf3r Tah+5TUDZ0paoZTqI42BDOBr/dKfOMj1M3SX8vsKQaPRuWnnhbCjwoQE5mHeqtTqeeWh lxlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MpvhPzX1ymg5vSIOj/R3c0XtSN9hCFreWZQ1rMcnPsI=; b=au1d9bjJmLBn5ymPBM3QPJGFKioad0TRxREmhH9WWrW2AmIQREtvHSloh6qPobXqlF wP558mjDUpWCUWSadoiAUbPeOzUZi57vnwkYNZ6kWs8CLACTS+LJ+/Mswx20QOd5qNWN CdJT8UJYFEG8q0aStiku56AUoUrdvH5agf5y7EhVzoAXmEefVzzp7dQd5uXKzGj7h3iO 0GIu/APotxp+0To0u4gqXjlFmTSJ8Gj9Tk9xLDkOM4idnxMH749OB35jCSLQA43B0KT6 QrBHk777yxltGvi2OyupLk0sU1MLmm0S9XUBO+YdE2keBZXwrMdtRG685HUk7rRfnbRD llZw== X-Gm-Message-State: AOAM533Pz2Lx9/hKY2+DeZ6ri0UrDOBDn0AGNfm8tF7GGK2W0ei2MymZ UjDQkk8SMuq5GDeMorFSjbY= X-Google-Smtp-Source: ABdhPJzD0kOaSu31tu2RIX4r32z9rtPujOvi7Q/nkRexmgRdTsqYkZmJNq36lQE3+XcOdsZ5+9FIMA== X-Received: by 2002:a05:651c:14c:: with SMTP id c12mr9009930ljd.72.1621814192271; Sun, 23 May 2021 16:56:32 -0700 (PDT) Received: from localhost.localdomain (109-252-193-110.dynamic.spd-mgts.ru. [109.252.193.110]) by smtp.gmail.com with ESMTPSA id h4sm1092987lfv.247.2021.05.23.16.56.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 May 2021 16:56:32 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Zhang Rui , Daniel Lezcano , Amit Kucheria , Andreas Westman Dorcsak , Maxim Schwalm , Svyatoslav Ryhel , Ihor Didenko , Ion Agorria , Matt Merhar , Peter Geis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 1/7] dt-bindings: thermal: Add binding for Tegra30 thermal sensor Date: Mon, 24 May 2021 02:56:14 +0300 Message-Id: <20210523235620.31538-2-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210523235620.31538-1-digetx@gmail.com> References: <20210523235620.31538-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org All NVIDIA Tegra30 SoCs have on-chip sensors which monitor temperature and voltage of the SoC. Sensors also controls CPU x2 freq throttle and emits emergency shutdown signal. TSENSOR has has two separate channels for each sensor placed in a different parts of the SoC. Add binding for the sensor hardware. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../thermal/nvidia,tegra30-tsensor.yaml | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra30-tsensor.yaml diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra30-tsensor.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra30-tsensor.yaml new file mode 100644 index 000000000000..6182090d313c --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra30-tsensor.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/nvidia,tegra30-tsensor.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra30 Thermal Sensor + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +description: | + TSENSOR provides thermal and voltage sensors which monitor temperature + and voltage of the chip. Sensors are placed across the die to gauge the + temperature of the whole chip. The TSENSOR module: + + Generates an interrupt to SW to lower temperature via DVFS on reaching + a certain thermal/voltage threshold. + + Generates a signal to the CAR to reduce CPU frequency by half on reaching + a certain thermal/voltage threshold. + + Generates a signal to the PMC when the temperature reaches dangerously high + levels to reset the chip and sets a flag in the PMC. + + TSENSOR has two channels which monitor two different spots of the SoC. + +properties: + compatible: + const: nvidia,tegra30-tsensor + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + + "#cooling-cells": + const: 2 + + assigned-clock-parents: true + assigned-clock-rates: true + assigned-clocks: true + +required: + - compatible + - reg + - clocks + - resets + - interrupts + - "#thermal-sensor-cells" + - "#cooling-cells" + +additionalProperties: false + +examples: + - | + thermal-sensor@70014000 { + compatible = "nvidia,tegra30-tsensor"; + reg = <0x70014000 0x500>; + interrupts = <0 102 4>; + clocks = <&clk 100>; + resets = <&rst 100>; + + #thermal-sensor-cells = <1>; + #cooling-cells = <2>; + }; From patchwork Sun May 23 23:56:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1482571 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=qq7JN01n; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FpHLZ1hb1z9sVb for ; Mon, 24 May 2021 09:56:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232051AbhEWX6C (ORCPT ); Sun, 23 May 2021 19:58:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231982AbhEWX6C (ORCPT ); Sun, 23 May 2021 19:58:02 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE392C06138A; Sun, 23 May 2021 16:56:34 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id v5so31181407ljg.12; Sun, 23 May 2021 16:56:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XcXraiNoRPU0G8oGIVhPyNHE4YAr90zRs8GgZNjViE0=; b=qq7JN01neQFC1nt1RjhBXkkYdgb4M6Fkr5RK4eftNKgiX2uBFK4m0JQgi6+Dt68+ks f2/PZ1Wklem3LRx9B0h7lD6ODGuXTuPrMK48GtmQwxXcbIdG8Mq3wKIrMVtY5r5gTH7+ oARR27AZL/lyvH8lgg6mRrbQ3gtkWgJ7HQLs5a0S9DOsfp6T4wSdrp44a220ftmVJ11Y nbGwN6kljms3UGPxXOXkdW7kxw8hlZFIzUywkEGGQVvcKkVs/uQEmY3UWo76Sdg2kgWj Kqvcy0LwG4jw9T4cDSGt0TjhUaDE0A2WcSvZ+Ikz7CrnkpsuflydX25BL16qmkW6rYQA TXJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XcXraiNoRPU0G8oGIVhPyNHE4YAr90zRs8GgZNjViE0=; b=FzYbqY0LnGguVSWcNshSodKecdbwZHvJqC9ykrOE5k7MTCiKA8/7Bnrjkc9qu67nHo nFdw3uygpZZTlQxUU2ql7WtZZaSIl/sLxI0VWPAegfsxv9CKYHJod9gNmcnEn4evICBt zEDTewBMWfemGCu1Eb+z9OnCOEilPmcU1fOmUWdz1SVXWD4TS7FHAi8exqedks7YGWdy nKy3aj4TdUR+/eYwUVPOBX7TwsF4hzYsEzIkfiVqIN75WN9v+ytI3FOxQ2NJpfXG5TZ5 tEzxP87icxO38Vvfb/sblHO3WDahc0MzNlVBiVdXOaMpwMEAQo7lzJvMvAl9rpCB8EU4 qwUA== X-Gm-Message-State: AOAM531+nxPtxxITtStM5yruMGG4TTCQOsQKyLxKYI4GUVXiDIksjz6i mr7lDF39wyfb+KbGgcDmCMY= X-Google-Smtp-Source: ABdhPJyGEtTfR/XlS0JbwxpHNSb/95KFeP7p5VWXUtSjIHC+KvqddbHIkOaAxluzNUbkM2dsWIP4zg== X-Received: by 2002:a2e:a78c:: with SMTP id c12mr14735696ljf.421.1621814193058; Sun, 23 May 2021 16:56:33 -0700 (PDT) Received: from localhost.localdomain (109-252-193-110.dynamic.spd-mgts.ru. [109.252.193.110]) by smtp.gmail.com with ESMTPSA id h4sm1092987lfv.247.2021.05.23.16.56.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 May 2021 16:56:32 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Zhang Rui , Daniel Lezcano , Amit Kucheria , Andreas Westman Dorcsak , Maxim Schwalm , Svyatoslav Ryhel , Ihor Didenko , Ion Agorria , Matt Merhar , Peter Geis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 2/7] thermal: thermal_of: Stop zone device before unregistering it Date: Mon, 24 May 2021 02:56:15 +0300 Message-Id: <20210523235620.31538-3-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210523235620.31538-1-digetx@gmail.com> References: <20210523235620.31538-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Zone device is enabled after thermal_zone_of_sensor_register() completion, but it's not disabled before senors if unregistered, leaving temperature polling active. This results in accessing a disabled zone device and produces a warning about this problem. Stop zone device before unregistering it in order to fix this "use-after-free" problem. Signed-off-by: Dmitry Osipenko --- drivers/thermal/thermal_of.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/thermal/thermal_of.c b/drivers/thermal/thermal_of.c index 5b76f9a1280d..6379f26a335f 100644 --- a/drivers/thermal/thermal_of.c +++ b/drivers/thermal/thermal_of.c @@ -559,6 +559,9 @@ void thermal_zone_of_sensor_unregister(struct device *dev, if (!tz) return; + /* stop temperature polling */ + thermal_zone_device_disable(tzd); + mutex_lock(&tzd->lock); tzd->ops->get_temp = NULL; tzd->ops->get_trend = NULL; From patchwork Sun May 23 23:56:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1482577 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=CdwiSwwG; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FpHLd04zCz9sRf for ; Mon, 24 May 2021 09:56:41 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232110AbhEWX6F (ORCPT ); Sun, 23 May 2021 19:58:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232086AbhEWX6E (ORCPT ); Sun, 23 May 2021 19:58:04 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7AB92C06138B; Sun, 23 May 2021 16:56:35 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id t17so14502723ljd.9; Sun, 23 May 2021 16:56:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AqIoL8w6UW8nZZQW4Ci4myc0ad3mcz0KynC5WY0Sz8A=; b=CdwiSwwGxruJPsrcExQZXd+thphvqthJtvltwu8MjAEeiP34K5ntFdrxNpRTVBEWgc KEC8dcdF4l3TuMG7TOMtWJV6ttPR4hD+0xBO3ER9G9dbQsqaULwlw8krwb3KRfZH3fWn 1GkEdtTlzQAPXnntzONcv3COzlApbQ6/g9pFJ6EmhrdLPJyP9JCpD3tIAxfOzvNV+iIa cnPUNIhDtPgjjHni6Z9D9AZT189MU3UblxBFEYnf5ptbzuzaf3EjEym1t5x4mSu/B2AU nD25VhBKX2LFHtafrIKpud2oFAMtcpXMrnMFfyKgMlNBih0gMwTaNY6XIidv1WR9JuGp 79iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AqIoL8w6UW8nZZQW4Ci4myc0ad3mcz0KynC5WY0Sz8A=; b=Z00MoDZFD20D2LXRhhMHeNI/yTxUcsBcLF4W/IvbC+unBANhZ/q+NCmwgBIBZ2naf1 eJt3p8ZUm8Luq1yTxlp0ulJIh/AuryqwR/YCo4ne3zuxOrBUg3Ddfy1ULI+KoRTmBoJD bGmCf2eWUFZe4zmDNGOwiX2x+TpSW53zjqucenA9DAVDQh/HMKlag67PQLrEHFKjubnx EjbxJDLTmiBLZJVRxMq8qji6aSiSWpa2CYZYDdUNiSc7V0eFUu7HH5uqR0wvnO5xX83m pJX4HQXEHiBCWcLYPusOA7Y+wDNgGAxUNtPTCRqE1nlE3DJVgRKOSY6rD85H+nVSHm5p xmmQ== X-Gm-Message-State: AOAM532v6x28OHgoC12eiwC7W2DTxtLBX963tbLECCnDJPjkXSI8LEIx l4s7H5CVIAJ80eybDDVBZaqb2onpfhI= X-Google-Smtp-Source: ABdhPJzvXCYRUvjdpvm97UZ/DwBEkwCqXYw7tSvJBy8GMv2Qxgp2uFDwc3ZHwmcDjtAK6cKsb9hZ6g== X-Received: by 2002:a2e:b44f:: with SMTP id o15mr15180872ljm.497.1621814193846; Sun, 23 May 2021 16:56:33 -0700 (PDT) Received: from localhost.localdomain (109-252-193-110.dynamic.spd-mgts.ru. [109.252.193.110]) by smtp.gmail.com with ESMTPSA id h4sm1092987lfv.247.2021.05.23.16.56.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 May 2021 16:56:33 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Zhang Rui , Daniel Lezcano , Amit Kucheria , Andreas Westman Dorcsak , Maxim Schwalm , Svyatoslav Ryhel , Ihor Didenko , Ion Agorria , Matt Merhar , Peter Geis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 3/7] thermal/core: Export thermal_cooling_device_stats_update() Date: Mon, 24 May 2021 02:56:16 +0300 Message-Id: <20210523235620.31538-4-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210523235620.31538-1-digetx@gmail.com> References: <20210523235620.31538-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org NVIDIA Tegra30 thermal sensor driver has a hardware-controlled CPU cooling feature that halves CPU frequency once a specified trip point is breached. In order to account the hardware state transitions, which are reported by interrupt, the sensor driver needs to report the cooling state transition and this is done by thermal_cooling_device_stats_update(). The sensor driver could be compiled as a loadable driver module, but this API function isn't exported, hence export it. Signed-off-by: Dmitry Osipenko --- drivers/thermal/thermal_sysfs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/thermal/thermal_sysfs.c b/drivers/thermal/thermal_sysfs.c index 1c4aac8464a7..ab373280f853 100644 --- a/drivers/thermal/thermal_sysfs.c +++ b/drivers/thermal/thermal_sysfs.c @@ -690,6 +690,7 @@ void thermal_cooling_device_stats_update(struct thermal_cooling_device *cdev, unlock: spin_unlock(&stats->lock); } +EXPORT_SYMBOL_GPL(thermal_cooling_device_stats_update); static ssize_t total_trans_show(struct device *dev, struct device_attribute *attr, char *buf) From patchwork Sun May 23 23:56:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1482576 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=oGLvWRFp; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FpHLc1byvz9sW1 for ; Mon, 24 May 2021 09:56:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231982AbhEWX6E (ORCPT ); Sun, 23 May 2021 19:58:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232070AbhEWX6D (ORCPT ); Sun, 23 May 2021 19:58:03 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D004C061574; Sun, 23 May 2021 16:56:36 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id c15so31193904ljr.7; Sun, 23 May 2021 16:56:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IH8BMDskWfmbR7tPWOs8vAh4oaheRb/8a6mIZbgp2B4=; b=oGLvWRFpn5ZqI6+nuSAekW+G1v3PtiEFKgMabOZg5y1s19RE5KD+l2lYah6C7LypEq U0JVvCFt6V8Z8vIzxKh8QaGr3XsDmF12yMbLZs1RHQf71ehg77MJYjS5zLVxJkbkaQ0C sPPmhByDQl58lex50x3RPwFvN9uPaZ/0swIvMDAXa5xgCjrpvdofN+lIG6cixuQDQGsK M33fkgUP8ts0h3T4HsV/H7Mz5iazUtNmKEXu2NkMk+lDi1xc7vlegUVFiTkjdaxbKaYK OVVfEOFCFbL9b3hJwPvC0YdQm1zpnTxLzI2HCVD6iRJRbPxWqdKDJCj5mAIA0dza3rdl 8vUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IH8BMDskWfmbR7tPWOs8vAh4oaheRb/8a6mIZbgp2B4=; b=t+OAkfnSFGmdA9nygI+yIusD5E+frAnZrMU99pbYHzttnOYETTdqZZRrVgiqxbtWrr GFhOI4rYB+HmwpHbCC8aZ4YihHOeIQoARbMW0pDWWCNPd7bhQe8tc6lkM43dQPMXcZUn nQZuY5Or6zAuVMb7E81L0wP6MPj04liLFXnXm7CaTeHURR6XUg8iM0Dr/wgALS6TGDn6 +V/V03YJcG8N9NT7deyzQ3I3d7CSMcykJcPfj/yrYaQ3MSaltmwRKxPDM+XZUZ4mtqWT gchH/cot98FmWA6IZAka6GKgv7v5CxLmgk+pW27iKKUueYsk8LLnxKpjTXbPrjCLTxB1 HrxQ== X-Gm-Message-State: AOAM5314rW4skC2My3H1xVFtzuOttcMfIeWOdE7Etx5ID9sIK27UNzaz 4rJ5RnS4d+1DMkJtZkqMBm8= X-Google-Smtp-Source: ABdhPJyGVycaw4GYj6Y9fWjfyvUClDF56ivkKUTusQljRmaKpByu1mnTMhbRXOti1FVtKLUEj9JHNg== X-Received: by 2002:a2e:7a06:: with SMTP id v6mr14609566ljc.219.1621814194693; Sun, 23 May 2021 16:56:34 -0700 (PDT) Received: from localhost.localdomain (109-252-193-110.dynamic.spd-mgts.ru. [109.252.193.110]) by smtp.gmail.com with ESMTPSA id h4sm1092987lfv.247.2021.05.23.16.56.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 May 2021 16:56:34 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Zhang Rui , Daniel Lezcano , Amit Kucheria , Andreas Westman Dorcsak , Maxim Schwalm , Svyatoslav Ryhel , Ihor Didenko , Ion Agorria , Matt Merhar , Peter Geis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 4/7] thermal/drivers/tegra: Add driver for Tegra30 thermal sensor Date: Mon, 24 May 2021 02:56:17 +0300 Message-Id: <20210523235620.31538-5-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210523235620.31538-1-digetx@gmail.com> References: <20210523235620.31538-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org All NVIDIA Tegra30 SoCs have a two-channel on-chip sensor unit which monitors temperature and voltage of the SoC. Sensors control CPU frequency throttling, which is activated by hardware once preprogrammed temperature level is breached, they also send signal to Power Management controller to perform emergency shutdown on a critical overheat of the SoC die. Add driver for the Tegra30 TSENSOR module, exposing it as a thermal sensor and a cooling device. Tested-by: Andreas Westman Dorcsak # Asus TF700T Tested-by: Maxim Schwalm # Asus TF700T Tested-by: Svyatoslav Ryhel # Asus TF201T Tested-by: Ihor Didenko # Asus TF300T Tested-by: Ion Agorria # Asus TF201T Tested-by: Matt Merhar # Ouya Tested-by: Peter Geis # Ouya Signed-off-by: Dmitry Osipenko --- drivers/thermal/tegra/Kconfig | 7 + drivers/thermal/tegra/Makefile | 1 + drivers/thermal/tegra/tegra30-tsensor.c | 736 ++++++++++++++++++++++++ 3 files changed, 744 insertions(+) create mode 100644 drivers/thermal/tegra/tegra30-tsensor.c diff --git a/drivers/thermal/tegra/Kconfig b/drivers/thermal/tegra/Kconfig index 46c2215867cd..019e3a2eb69e 100644 --- a/drivers/thermal/tegra/Kconfig +++ b/drivers/thermal/tegra/Kconfig @@ -18,4 +18,11 @@ config TEGRA_BPMP_THERMAL Enable this option for support for sensing system temperature of NVIDIA Tegra systems-on-chip with the BPMP coprocessor (Tegra186). +config TEGRA30_TSENSOR + tristate "Tegra30 Thermal Sensor" + depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST + help + Enable this option to support thermal management of NVIDIA Tegra30 + system-on-chip. + endmenu diff --git a/drivers/thermal/tegra/Makefile b/drivers/thermal/tegra/Makefile index 0f2b66edf0d2..eb27d194c583 100644 --- a/drivers/thermal/tegra/Makefile +++ b/drivers/thermal/tegra/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_TEGRA_SOCTHERM) += tegra-soctherm.o obj-$(CONFIG_TEGRA_BPMP_THERMAL) += tegra-bpmp-thermal.o +obj-$(CONFIG_TEGRA30_TSENSOR) += tegra30-tsensor.o tegra-soctherm-y := soctherm.o soctherm-fuse.o tegra-soctherm-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124-soctherm.o diff --git a/drivers/thermal/tegra/tegra30-tsensor.c b/drivers/thermal/tegra/tegra30-tsensor.c new file mode 100644 index 000000000000..f7562eac01d6 --- /dev/null +++ b/drivers/thermal/tegra/tegra30-tsensor.c @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Tegra30 SoC Thermal Sensor driver + * + * Based on downstream HWMON driver from NVIDIA. + * Copyright (C) 2011 NVIDIA Corporation + * + * Author: Dmitry Osipenko + * Copyright (C) 2021 GRATE-DRIVER project + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "../thermal_core.h" +#include "../thermal_hwmon.h" + +#define TSENSOR_SENSOR0_CONFIG0 0x0 +#define TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP BIT(0) +#define TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN BIT(1) +#define TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN BIT(2) +#define TSENSOR_SENSOR0_CONFIG0_DVFS_EN BIT(3) +#define TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN BIT(4) +#define TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN BIT(5) +#define TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN BIT(6) +#define TSENSOR_SENSOR0_CONFIG0_M GENMASK(23, 8) +#define TSENSOR_SENSOR0_CONFIG0_N GENMASK(31, 24) + +#define TSENSOR_SENSOR0_CONFIG1 0x8 +#define TSENSOR_SENSOR0_CONFIG1_TH1 GENMASK(15, 0) +#define TSENSOR_SENSOR0_CONFIG1_TH2 GENMASK(31, 16) + +#define TSENSOR_SENSOR0_CONFIG2 0xc +#define TSENSOR_SENSOR0_CONFIG2_TH3 GENMASK(15, 0) + +#define TSENSOR_SENSOR0_STATUS0 0x18 +#define TSENSOR_SENSOR0_STATUS0_STATE GENMASK(2, 0) +#define TSENSOR_SENSOR0_STATUS0_INTR BIT(8) +#define TSENSOR_SENSOR0_STATUS0_CURRENT_VALID BIT(9) + +#define TSENSOR_SENSOR0_TS_STATUS1 0x1c +#define TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT GENMASK(31, 16) + +#define TEGRA30_FUSE_TEST_PROG_VER 0x28 + +#define TEGRA30_FUSE_TSENSOR_CALIB 0x98 +#define TEGRA30_FUSE_TSENSOR_CALIB_LOW GENMASK(15, 0) +#define TEGRA30_FUSE_TSENSOR_CALIB_HIGH GENMASK(31, 16) + +#define TEGRA30_FUSE_SPARE_BIT 0x144 + +struct tegra_tsensor; + +struct tegra_tsensor_calibration_data { + int a, b, m, n, p, r; +}; + +struct tegra_tsensor_channel { + void __iomem *regs; + unsigned int id; + struct tegra_tsensor *ts; + struct thermal_zone_device *tzd; +}; + +struct tegra_tsensor { + void __iomem *regs; + bool swap_channels; + struct clk *clk; + struct device *dev; + struct reset_control *rst; + struct tegra_tsensor_channel ch[2]; + struct thermal_cooling_device *cdev; + struct tegra_tsensor_calibration_data calib; +}; + +static int tegra_tsensor_hw_enable(const struct tegra_tsensor *ts) +{ + u32 val; + int err; + + err = reset_control_assert(ts->rst); + if (err) { + dev_err(ts->dev, "failed to assert hardware reset: %d\n", err); + return err; + } + + err = clk_prepare_enable(ts->clk); + if (err) { + dev_err(ts->dev, "failed to enable clock: %d\n", err); + return err; + } + + fsleep(1000); + + err = reset_control_deassert(ts->rst); + if (err) { + dev_err(ts->dev, "failed to deassert hardware reset: %d\n", err); + goto disable_clk; + } + + /* + * Sensors are enabled after reset by default, but not gauging + * until clock counter is programmed. + * + * M: number of reference clock pulses after which every + * temperature / voltage measurement is made + * + * N: number of reference clock counts for which the counter runs + */ + val = FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_M, 12500); + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_N, 255); + + /* apply the same configuration to both channels */ + writel_relaxed(val, ts->regs + 0x40 + TSENSOR_SENSOR0_CONFIG0); + writel_relaxed(val, ts->regs + 0x80 + TSENSOR_SENSOR0_CONFIG0); + + return 0; + +disable_clk: + clk_disable_unprepare(ts->clk); + + return err; +} + +static int tegra_tsensor_hw_disable(const struct tegra_tsensor *ts) +{ + int err; + + err = reset_control_assert(ts->rst); + if (err) { + dev_err(ts->dev, "failed to assert hardware reset: %d\n", err); + return err; + } + + clk_disable_unprepare(ts->clk); + + return 0; +} + +static void devm_tegra_tsensor_hw_disable(void *data) +{ + const struct tegra_tsensor *ts = data; + + tegra_tsensor_hw_disable(ts); +} + +static int tegra_tsensor_get_temp(void *data, int *temp) +{ + const struct tegra_tsensor_channel *tsc = data; + const struct tegra_tsensor *ts = tsc->ts; + int err, c1, c2, c3, c4, counter; + u32 val; + + /* + * Counter will be invalid if hardware is misprogrammed or not enough + * time passed since the time when sensor was enabled. + */ + err = readl_relaxed_poll_timeout(tsc->regs + TSENSOR_SENSOR0_STATUS0, val, + val & TSENSOR_SENSOR0_STATUS0_CURRENT_VALID, + 21 * USEC_PER_MSEC, + 21 * USEC_PER_MSEC * 50); + if (err) { + dev_err_once(ts->dev, "ch%u: counter invalid\n", tsc->id); + return err; + } + + val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_TS_STATUS1); + counter = FIELD_GET(TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT, val); + + /* + * This shouldn't happen with a valid counter status, nevertheless + * lets verify the value since it's in a separate (from status) + * register. + */ + if (counter == 0xffff) { + dev_err_once(ts->dev, "ch%u: counter overflow\n", tsc->id); + return -EINVAL; + } + + /* + * temperature = a * counter + b + * temperature = m * (temperature ^ 2) + n * temperature + p + */ + c1 = DIV_ROUND_CLOSEST(ts->calib.a * counter + ts->calib.b, 1000000); + c1 = c1 ?: 1; + c2 = DIV_ROUND_CLOSEST(ts->calib.p, c1); + c3 = c1 * ts->calib.m; + c4 = ts->calib.n; + + *temp = DIV_ROUND_CLOSEST(c1 * (c2 + c3 + c4), 1000); + + return 0; +} + +static int tegra_tsensor_temp_to_counter(const struct tegra_tsensor *ts, int temp) +{ + int c1, c2; + + c1 = DIV_ROUND_CLOSEST(ts->calib.p - temp * 1000, ts->calib.m); + c2 = -ts->calib.r - int_sqrt(ts->calib.r * ts->calib.r - c1); + + return DIV_ROUND_CLOSEST(c2 * 1000000 - ts->calib.b, ts->calib.a); +} + +static int tegra_tsensor_set_trips(void *data, int low, int high) +{ + const struct tegra_tsensor_channel *tsc = data; + const struct tegra_tsensor *ts = tsc->ts; + u32 val; + + /* + * TSENSOR doesn't trigger interrupt on the "low" temperature breach, + * hence bail out if high temperature is unspecified. + */ + if (high == INT_MAX) + return 0; + + val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1); + val &= ~TSENSOR_SENSOR0_CONFIG1_TH1; + + high = tegra_tsensor_temp_to_counter(ts, high); + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH1, high); + writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1); + + return 0; +} + +static const struct thermal_zone_of_device_ops ops = { + .get_temp = tegra_tsensor_get_temp, + .set_trips = tegra_tsensor_set_trips, +}; + +static int tegra_tsensor_get_max_state(struct thermal_cooling_device *cdev, + unsigned long *state) +{ + *state = 1; + + return 0; +} + +static bool tegra_tsensor_channel_div2_active(const struct tegra_tsensor *ts, + unsigned int id) +{ + u32 val; + + val = readl_relaxed(ts->ch[id].regs + TSENSOR_SENSOR0_CONFIG0); + if (!FIELD_GET(TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN, val)) + return false; + + val = readl_relaxed(ts->ch[id].regs + TSENSOR_SENSOR0_STATUS0); + + /* CPU frequency is halved when LEVEL2 is breached */ + return FIELD_GET(TSENSOR_SENSOR0_STATUS0_STATE, val) > 2; +} + +static int tegra_tsensor_get_cur_state(struct thermal_cooling_device *cdev, + unsigned long *state) +{ + const struct tegra_tsensor *ts = cdev->devdata; + unsigned int i, div2_state = 0; + + for (i = 0; i < ARRAY_SIZE(ts->ch); i++) + div2_state |= tegra_tsensor_channel_div2_active(ts, i); + + *state = div2_state; + + return 0; +} + +static int tegra_tsensor_set_cur_state(struct thermal_cooling_device *cdev, + unsigned long state) +{ + /* state is controlled by hardware and can't be changed by software */ + return -EOPNOTSUPP; +} + +static const struct thermal_cooling_device_ops tegra_tsensor_cpu_cooling_ops = { + .get_max_state = tegra_tsensor_get_max_state, + .get_cur_state = tegra_tsensor_get_cur_state, + .set_cur_state = tegra_tsensor_set_cur_state, +}; + +static bool +tegra_tsensor_handle_channel_interrupt(const struct tegra_tsensor *ts, + unsigned int id) +{ + const struct tegra_tsensor_channel *tsc = &ts->ch[id]; + u32 val; + + val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_STATUS0); + writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_STATUS0); + + if (FIELD_GET(TSENSOR_SENSOR0_STATUS0_STATE, val) == 5) + dev_err_ratelimited(ts->dev, "ch%u: counter overflowed\n", id); + + if (!FIELD_GET(TSENSOR_SENSOR0_STATUS0_INTR, val)) + return false; + + thermal_zone_device_update(tsc->tzd, THERMAL_EVENT_UNSPECIFIED); + + return true; +} + +static irqreturn_t tegra_tsensor_isr(int irq, void *data) +{ + const struct tegra_tsensor *ts = data; + bool div2_state = false; + bool handled = false; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { + div2_state |= tegra_tsensor_channel_div2_active(ts, i); + handled |= tegra_tsensor_handle_channel_interrupt(ts, i); + } + + thermal_cooling_device_stats_update(ts->cdev, div2_state); + + return handled ? IRQ_HANDLED : IRQ_NONE; +} + +static int tegra_tsensor_disable_hw_channel(const struct tegra_tsensor *ts, + unsigned int id) +{ + const struct tegra_tsensor_channel *tsc = &ts->ch[id]; + struct thermal_zone_device *tzd = tsc->tzd; + u32 val; + int err; + + if (!tzd) + goto stop_channel; + + err = thermal_zone_device_disable(tzd); + if (err) { + dev_err(ts->dev, "ch%u: failed to disable zone: %d\n", id, err); + return err; + } + +stop_channel: + /* stop channel gracefully */ + val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0); + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP, 1); + writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0); + + return 0; +} + +static void tegra_tsensor_get_hw_channel_trips(struct thermal_zone_device *tzd, + int *hot_trip, int *crit_trip) +{ + unsigned int i; + + /* + * 90C is the maximal critical temperature of all Tegra30 SoC variants, + * use it for the default trip if unspecified in a device-tree. + */ + *hot_trip = 85000; + *crit_trip = 90000; + + for (i = 0; i < tzd->trips; i++) { + enum thermal_trip_type type; + int trip_temp; + + tzd->ops->get_trip_temp(tzd, i, &trip_temp); + tzd->ops->get_trip_type(tzd, i, &type); + + if (type == THERMAL_TRIP_HOT) + *hot_trip = trip_temp; + + if (type == THERMAL_TRIP_CRITICAL) + *crit_trip = trip_temp; + } + + /* clamp hardware trips to the calibration limits */ + *hot_trip = clamp(*hot_trip, 25000, 90000); + + /* + * Kernel will perform a normal system shut down if it will + * see that critical temperature is breached, hence set the + * hardware limit by 5C higher in order to allow system to + * shut down gracefully before sending signal to the Power + * Management controller. + */ + *crit_trip = clamp(*crit_trip + 5000, 25000, 90000); +} + +static int tegra_tsensor_enable_hw_channel(const struct tegra_tsensor *ts, + unsigned int id) +{ + const struct tegra_tsensor_channel *tsc = &ts->ch[id]; + struct thermal_zone_device *tzd = tsc->tzd; + int err, hot_trip = 0, crit_trip = 0; + u32 val; + + if (!tzd) { + val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0); + val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP; + writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0); + + return 0; + } + + tegra_tsensor_get_hw_channel_trips(tzd, &hot_trip, &crit_trip); + + /* prevent potential racing with tegra_tsensor_set_trips() */ + mutex_lock(&tzd->lock); + + dev_info_once(ts->dev, "ch%u: CPU freq div2 throttle trip set to %dC\n", + id, DIV_ROUND_CLOSEST(hot_trip, 1000)); + + dev_info_once(ts->dev, "ch%u: PMC emergency shutdown trip set to %dC\n", + id, DIV_ROUND_CLOSEST(crit_trip, 1000)); + + hot_trip = tegra_tsensor_temp_to_counter(ts, hot_trip); + crit_trip = tegra_tsensor_temp_to_counter(ts, crit_trip); + + /* program LEVEL2 counter threshold */ + val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1); + val &= ~TSENSOR_SENSOR0_CONFIG1_TH2; + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH2, hot_trip); + writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1); + + /* program LEVEL3 counter threshold */ + val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG2); + val &= ~TSENSOR_SENSOR0_CONFIG2_TH3; + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG2_TH3, crit_trip); + writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG2); + + /* + * Enable sensor, DIV2 throttle, emergency shutdown, interrupts + * for level 1/2/3 breaches and counter overflow condition. + * + * Thermal levels supported by hardware: + * + * Level 0 = cold + * Level 1 = passive cooling (cpufreq DVFS) + * Level 2 = passive cooling assisted by hardware (DIV2) + * Level 3 = emergency shutdown assisted by hardware (PMC) + */ + val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0); + val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP; + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_DVFS_EN, 1); + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN, 1); + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN, 1); + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN, 1); + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN, 1); + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN, 1); + writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0); + + mutex_unlock(&tzd->lock); + + err = thermal_zone_device_enable(tzd); + if (err) { + dev_err(ts->dev, "ch%u: failed to enable zone: %d\n", id, err); + return err; + } + + return 0; +} + +static bool tegra_tsensor_fuse_read_spare(unsigned int spare) +{ + u32 val = 0; + + tegra_fuse_readl(TEGRA30_FUSE_SPARE_BIT + spare * 4, &val); + + return !!val; +} + +static int tegra_tsensor_nvmem_setup(struct tegra_tsensor *ts) +{ + u32 i, ate_ver = 0, cal = 0, t1_25C = 0, t2_90C = 0; + int err, c1_25C, c2_90C; + + err = tegra_fuse_readl(TEGRA30_FUSE_TEST_PROG_VER, &ate_ver); + if (err) { + dev_err_probe(ts->dev, err, "failed to get ATE version\n"); + return err; + } + + if (ate_ver < 8) { + dev_info(ts->dev, "unsupported ATE version: %u\n", ate_ver); + return -ENODEV; + } + + /* + * We have two TSENSOR channels in a two different spots on SoC. + * Second channel provides more accurate data on older SoC versions, + * use it as a primary channel. + */ + if (ate_ver <= 21) { + dev_info_once(ts->dev, + "older ATE version detected, channels remapped\n"); + ts->swap_channels = true; + } + + err = tegra_fuse_readl(TEGRA30_FUSE_TSENSOR_CALIB, &cal); + if (err) { + dev_err(ts->dev, "failed to get calibration data: %d\n", err); + return err; + } + + /* get calibrated counter values for 25C/90C thresholds */ + c1_25C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_LOW, cal); + c2_90C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_HIGH, cal); + + /* and calibrated temperatures corresponding to the counter values */ + for (i = 0; i < 7; i++) { + t1_25C |= tegra_tsensor_fuse_read_spare(14 + i) << i; + t1_25C |= tegra_tsensor_fuse_read_spare(21 + i) << i; + + t2_90C |= tegra_tsensor_fuse_read_spare(0 + i) << i; + t2_90C |= tegra_tsensor_fuse_read_spare(7 + i) << i; + } + + if (c2_90C - c1_25C <= t2_90C - t1_25C) { + dev_err(ts->dev, "invalid calibration data: %d %d %u %u\n", + c2_90C, c1_25C, t2_90C, t1_25C); + return -EINVAL; + } + + /* all calibration coefficients are premultiplied by 1000000 */ + + ts->calib.a = DIV_ROUND_CLOSEST((t2_90C - t1_25C) * 1000000, + (c2_90C - c1_25C)); + + ts->calib.b = t1_25C * 1000000 - ts->calib.a * c1_25C; + + if (tegra_sku_info.revision == TEGRA_REVISION_A01) { + ts->calib.m = -2775; + ts->calib.n = 1338811; + ts->calib.p = -7300000; + } else { + ts->calib.m = -3512; + ts->calib.n = 1528943; + ts->calib.p = -11100000; + } + + /* except the coefficient of a reduced quadratic equation */ + ts->calib.r = DIV_ROUND_CLOSEST(ts->calib.n, ts->calib.m * 2); + + dev_info_once(ts->dev, + "calibration: %d %d %u %u ATE ver: %u SoC rev: %u\n", + c2_90C, c1_25C, t2_90C, t1_25C, ate_ver, + tegra_sku_info.revision); + + return 0; +} + +static int tegra_tsensor_register_channel(struct tegra_tsensor *ts, + unsigned int id) +{ + struct tegra_tsensor_channel *tsc = &ts->ch[id]; + unsigned int hw_id = ts->swap_channels ? !id : id; + + tsc->ts = ts; + tsc->id = id; + tsc->regs = ts->regs + 0x40 * (hw_id + 1); + + tsc->tzd = devm_thermal_zone_of_sensor_register(ts->dev, id, tsc, &ops); + if (IS_ERR(tsc->tzd)) { + if (PTR_ERR(tsc->tzd) != -ENODEV) + return dev_err_probe(ts->dev, PTR_ERR(tsc->tzd), + "failed to register thermal zone\n"); + + /* + * It's okay if sensor isn't assigned to any thermal zone + * in a device-tree. + */ + tsc->tzd = NULL; + return 0; + } + + if (devm_thermal_add_hwmon_sysfs(tsc->tzd)) + dev_warn(ts->dev, "failed to add hwmon sysfs attributes\n"); + + return 0; +} + +static int tegra_tsensor_probe(struct platform_device *pdev) +{ + struct tegra_tsensor *ts; + unsigned int i; + int err, irq; + + ts = devm_kzalloc(&pdev->dev, sizeof(*ts), GFP_KERNEL); + if (!ts) + return -ENOMEM; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ts->dev = &pdev->dev; + platform_set_drvdata(pdev, ts); + + ts->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ts->regs)) + return PTR_ERR(ts->regs); + + ts->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(ts->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(ts->clk), + "failed to get clock\n"); + + ts->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(ts->rst)) + return dev_err_probe(&pdev->dev, PTR_ERR(ts->rst), + "failed to get reset control\n"); + + err = tegra_tsensor_nvmem_setup(ts); + if (err) + return err; + + err = tegra_tsensor_hw_enable(ts); + if (err) + return err; + + err = devm_add_action_or_reset(&pdev->dev, + devm_tegra_tsensor_hw_disable, + ts); + if (err) + return err; + + for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { + err = tegra_tsensor_register_channel(ts, i); + if (err) + return err; + } + + ts->cdev = devm_thermal_of_cooling_device_register(&pdev->dev, + pdev->dev.of_node, "tegra-cpu-div2-throttle", + ts, &tegra_tsensor_cpu_cooling_ops); + if (IS_ERR(ts->cdev)) + return dev_err_probe(&pdev->dev, PTR_ERR(ts->cdev), + "failed to register cooling device\n"); + + err = devm_request_threaded_irq(&pdev->dev, irq, NULL, + tegra_tsensor_isr, IRQF_ONESHOT, + "tegra_tsensor", ts); + if (err) + return dev_err_probe(&pdev->dev, err, + "failed to request interrupt\n"); + + for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { + err = tegra_tsensor_enable_hw_channel(ts, i); + if (err) + return err; + } + + return 0; +} + +static int __maybe_unused tegra_tsensor_suspend(struct device *dev) +{ + struct tegra_tsensor *ts = dev_get_drvdata(dev); + unsigned int i; + int err; + + for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { + err = tegra_tsensor_disable_hw_channel(ts, i); + if (err) + goto enable_channel; + } + + err = tegra_tsensor_hw_disable(ts); + if (err) + goto enable_channel; + + return 0; + +enable_channel: + while (i--) + tegra_tsensor_enable_hw_channel(ts, i); + + return err; +} + +static int __maybe_unused tegra_tsensor_resume(struct device *dev) +{ + struct tegra_tsensor *ts = dev_get_drvdata(dev); + unsigned int i; + int err; + + err = tegra_tsensor_hw_enable(ts); + if (err) + return err; + + for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { + err = tegra_tsensor_enable_hw_channel(ts, i); + if (err) + return err; + } + + return 0; +} + +static const struct dev_pm_ops tegra_tsensor_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_tsensor_suspend, + tegra_tsensor_resume) +}; + +static const struct of_device_id tegra_tsensor_of_match[] = { + { .compatible = "nvidia,tegra30-tsensor", }, + {}, +}; +MODULE_DEVICE_TABLE(of, tegra_tsensor_of_match); + +static struct platform_driver tegra_tsensor_driver = { + .probe = tegra_tsensor_probe, + .driver = { + .name = "tegra30-tsensor", + .of_match_table = tegra_tsensor_of_match, + .pm = &tegra_tsensor_pm_ops, + }, +}; +module_platform_driver(tegra_tsensor_driver); + +MODULE_DESCRIPTION("NVIDIA Tegra30 Thermal Sensor driver"); +MODULE_AUTHOR("Dmitry Osipenko "); +MODULE_LICENSE("GPL"); From patchwork Sun May 23 23:56:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1482578 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=h6Y1AlQB; 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[109.252.193.110]) by smtp.gmail.com with ESMTPSA id h4sm1092987lfv.247.2021.05.23.16.56.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 May 2021 16:56:35 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Zhang Rui , Daniel Lezcano , Amit Kucheria , Andreas Westman Dorcsak , Maxim Schwalm , Svyatoslav Ryhel , Ihor Didenko , Ion Agorria , Matt Merhar , Peter Geis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 5/7] ARM: tegra_defconfig: Enable CONFIG_TEGRA30_TSENSOR Date: Mon, 24 May 2021 02:56:18 +0300 Message-Id: <20210523235620.31538-6-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210523235620.31538-1-digetx@gmail.com> References: <20210523235620.31538-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enable NVIDIA Tegra30 SoC thermal sensor driver in tegra_defconfig. Signed-off-by: Dmitry Osipenko --- arch/arm/configs/tegra_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 3d8d8af9524d..63e7f3261e6d 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -169,6 +169,7 @@ CONFIG_THERMAL_STATISTICS=y CONFIG_CPU_THERMAL=y CONFIG_DEVFREQ_THERMAL=y CONFIG_TEGRA_SOCTHERM=m +CONFIG_TEGRA30_TSENSOR=m CONFIG_WATCHDOG=y CONFIG_MAX77620_WATCHDOG=y CONFIG_TEGRA_WATCHDOG=y From patchwork Sun May 23 23:56:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1482579 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=GXlfBtDs; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FpHLg0WV8z9sVb for ; Mon, 24 May 2021 09:56:43 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232146AbhEWX6H (ORCPT ); Sun, 23 May 2021 19:58:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232118AbhEWX6G (ORCPT ); Sun, 23 May 2021 19:58:06 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9D22C061574; Sun, 23 May 2021 16:56:37 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id q3so7935053lfu.2; Sun, 23 May 2021 16:56:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uG0wF9x5J31B5QovgpxzHE3VxGkFw0gZRlBKzlTkO48=; b=GXlfBtDsEcz8SOTu0s85MYLXwpR3w4tYPEhGTnICUEGdahTvGlMK/PtnMSsb2eurc7 zCwGraA3D6irN8HTs7OVdrueAJ2HNKmWfv3PzWZXJnbUrayCn1umhI2wNiqyAfFphrZ6 pzz6E74ZtVZ0uAX/VJDTmHzup0SxbwyoOZBPvQ4TILThtLQh27vCfiTwsN+0jrLQtuJ9 Z7hBWWjtAx/QxkvS4+4UYmesyNvD3o0qqXqa6PMveOUsWVqvryh0abHwW6xWtYMVO/Zt bdjYZb5N397xKdYL9xcQ5oK+R9wSUXzjC2FfTdtc6blD7PgS9HajavDbM1Zd1qum77aA 3viA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uG0wF9x5J31B5QovgpxzHE3VxGkFw0gZRlBKzlTkO48=; b=Ay5bu+DWXWomOGyrCBU1OwCxnc9JLZ0vZGZusCon/VTKDfaq46VBm6o0dIaAwdNLa9 YH7YQpxHJtLAx6HoK0SypOycaon9hot5LmB5uV2tF9jBVeDwqVfuYv+uw64CxKG94z4z OMwAZO1NjkvJ0kPAHLAeHo6swfdKnk2HswOTVXitAUExLsBV8oI4GLHBcwbq2En50KWf TQg7iFN5VPtJT8SRO0pkZceu7oA4CT2xj3Gc3RxANqo0iRkpWztufO4aveFvtXA045Q6 lBHciV/8+KbzRr6JekmtUWceQENEJu5QHzVUfQGIqOk+KaFy2pifQu3PNHXxtm/bk9FY LVOQ== X-Gm-Message-State: AOAM530JILaJEeR/3ezlyuLapHSx+30qVcyFFYMVL7iL0GewZQjwKO74 y+j/bt6r8FaTB7oGR/spol4= X-Google-Smtp-Source: ABdhPJw8cOaLpHsBtUfzGgrnqy96pVFl4VAe2Ohcac5CSdlltqtHzTYmr9H+N5urC74YZaZx42jBCQ== X-Received: by 2002:ac2:5c1a:: with SMTP id r26mr2323180lfp.344.1621814196277; Sun, 23 May 2021 16:56:36 -0700 (PDT) Received: from localhost.localdomain (109-252-193-110.dynamic.spd-mgts.ru. [109.252.193.110]) by smtp.gmail.com with ESMTPSA id h4sm1092987lfv.247.2021.05.23.16.56.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 May 2021 16:56:36 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Zhang Rui , Daniel Lezcano , Amit Kucheria , Andreas Westman Dorcsak , Maxim Schwalm , Svyatoslav Ryhel , Ihor Didenko , Ion Agorria , Matt Merhar , Peter Geis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 6/7] ARM: multi_v7_defconfig: Enable CONFIG_TEGRA30_TSENSOR Date: Mon, 24 May 2021 02:56:19 +0300 Message-Id: <20210523235620.31538-7-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210523235620.31538-1-digetx@gmail.com> References: <20210523235620.31538-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enable NVIDIA Tegra30 SoC thermal sensor driver in multi_v7_defconfig. Signed-off-by: Dmitry Osipenko --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 52a0400fdd92..fc346f87d7f9 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -523,6 +523,7 @@ CONFIG_BRCMSTB_THERMAL=m CONFIG_GENERIC_ADC_THERMAL=m CONFIG_ST_THERMAL_MEMMAP=y CONFIG_TEGRA_SOCTHERM=m +CONFIG_TEGRA30_TSENSOR=m CONFIG_UNIPHIER_THERMAL=y CONFIG_DA9063_WATCHDOG=m CONFIG_XILINX_WATCHDOG=y From patchwork Sun May 23 23:56:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1482580 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=VHGfKQeD; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FpHLh05QMz9sVb for ; Mon, 24 May 2021 09:56:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232169AbhEWX6J (ORCPT ); Sun, 23 May 2021 19:58:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232137AbhEWX6H (ORCPT ); Sun, 23 May 2021 19:58:07 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A13B6C06138A; Sun, 23 May 2021 16:56:38 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id b26so22035219lfq.4; Sun, 23 May 2021 16:56:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SZjslNJj0RrvMEBltMfpTerrLG/TtMo8+YaLhqfm6kQ=; b=VHGfKQeD5DEVYG9/7bqRxsUqwRkh1peG1GhTmILCWbDJezl5ACdD1+ZypwzgY9Y/ov 4w5EkjNuRX2/0xvcDA2WHkKd3gYxB4x0dVJvyDRBE58GpDg9kNGVQXHRZCSDMEZfoIUD 2007ERvoRrCmRslHscWMo8H1s6zWgU07H0MoYTCQzd72SOhqaPm9/aYPNhvi1cRCX8oF dXAVwkHZJjrJBvRuLKjcSAAOehArhU0N3+RplQ+ImSi9BcCPkGe0nlKkb3LcX5TdTqPe JpCnhRs4oyhf14u6PQC0HTnXzXhPLQG1/xPYJxFaDB16njlmiaZKTZqR352mpsOHYNqC SS+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SZjslNJj0RrvMEBltMfpTerrLG/TtMo8+YaLhqfm6kQ=; b=IRoFwGHyvDvvfkkTcpPeyuaxzXNfRzppSvNpVdtB2uXCPHdnz8WRZsRAL7Ou3qx1A8 OCEPlBO3BMbaazQpYwieZQEREWKp6x0PlV5rsCIcK3YfOz8FZNm4o6f891kHMhnMzvly vD1IJtCInym1TgDMKmUTAzv5hKGaBddPwVYqwCnFOyuuLPwUPCUIIHqbtEM2vPfETmRK IjBVysLYMOHBDuKqgr8X6TcdLRu2NuN5WwugTKfEiNDe6+SYLTx9H6hxvZEp9tEiBqcE 4M7Gy1eic1ZFnBC41+nrw9OnJ7nAnuV6C0pmK7eQqECU0s8FpccEPCbvXbgAaPfYJ3N6 mldg== X-Gm-Message-State: AOAM531gGNhRpmCe5UfWK/z2n7ULaomDwa0GUCrB6bTzowSD1apon+vg Cu9vTXWp0iWHQfn79l2qytM= X-Google-Smtp-Source: ABdhPJz34PfRmncVj1km4qFInTQvlWxQpf3C3erhxrfDRu0zzc54ylbOCFTpiH8MDp/QJwu+pbhecQ== X-Received: by 2002:a19:495b:: with SMTP id l27mr9261746lfj.230.1621814197047; Sun, 23 May 2021 16:56:37 -0700 (PDT) Received: from localhost.localdomain (109-252-193-110.dynamic.spd-mgts.ru. [109.252.193.110]) by smtp.gmail.com with ESMTPSA id h4sm1092987lfv.247.2021.05.23.16.56.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 May 2021 16:56:36 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Zhang Rui , Daniel Lezcano , Amit Kucheria , Andreas Westman Dorcsak , Maxim Schwalm , Svyatoslav Ryhel , Ihor Didenko , Ion Agorria , Matt Merhar , Peter Geis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 7/7] ARM: tegra: Add SoC thermal sensor to Tegra30 device-trees Date: Mon, 24 May 2021 02:56:20 +0300 Message-Id: <20210523235620.31538-8-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210523235620.31538-1-digetx@gmail.com> References: <20210523235620.31538-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add the on-chip SoC thermal sensor to Tegra30 device-trees. Now CPU temperature reporting and thermal throttling is available on all Tegra30 devices universally. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-ouya.dts | 16 +++++ arch/arm/boot/dts/tegra30.dtsi | 93 ++++++++++++++++++++++++++++-- 2 files changed, 105 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index e767ac227a81..d792ce5c64c0 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -468,6 +468,22 @@ map1 { }; }; }; + + tsensor-channel0 { + trips { + dvfs-alert { + temperature = <70000>; + }; + + cpu-div2-throttle { + temperature = <75000>; + }; + + soc-critical { + temperature = <90000>; + }; + }; + }; }; vdd_12v_in: vdd_12v_in { diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index c577c191be4b..6becbadef210 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include #include "tegra30-peripherals-opp.dtsi" @@ -800,6 +801,21 @@ fuse@7000f800 { reset-names = "fuse"; }; + tsensor: tsensor@70014000 { + compatible = "nvidia,tegra30-tsensor"; + reg = <0x70014000 0x500>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; + resets = <&tegra_car TEGRA30_CLK_TSENSOR>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>; + assigned-clock-rates = <500000>; + + #thermal-sensor-cells = <1>; + #cooling-cells = <2>; + }; + hda@70030000 { compatible = "nvidia,tegra30-hda"; reg = <0x70030000 0x10000>; @@ -1062,32 +1078,36 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; + #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; + #cooling-cells = <2>; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; + #cooling-cells = <2>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; + #cooling-cells = <2>; }; }; @@ -1102,4 +1122,69 @@ pmu { <&{/cpus/cpu@2}>, <&{/cpus/cpu@3}>; }; + + thermal-zones { + tsensor-channel0 { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsensor 0>; + + trips { + level1_trip: dvfs-alert { + /* throttle at 67C until temperature drops to 66.8C */ + temperature = <67000>; + hysteresis = <200>; + type = "passive"; + }; + + level2_trip: cpu-div2-throttle { + /* hardware CPU x2 freq throttle at 70C */ + temperature = <70000>; + hysteresis = <200>; + type = "hot"; + }; + + soc-critical { + /* hardware shut down at 80C */ + temperature = <80000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&level1_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&level2_trip>; + cooling-device = <&tsensor THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + tsensor-channel1 { + status = "disabled"; + + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <0>; /* milliseconds */ + + thermal-sensors = <&tsensor 1>; + + trips { + dvfs-alert { + temperature = <80000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + }; };