From patchwork Wed May 5 08:21:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 1474173 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=Mh5N5lb2; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FZqS91m9fz9sRR for ; Wed, 5 May 2021 18:21:45 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DC72982CBA; Wed, 5 May 2021 10:21:32 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1620202893; bh=437J2IRYkcC0RbHMZANpTyajyruV3WCYj+zrG/VaaUM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=Mh5N5lb2QCkDhGH0CZQiWVY5CZtWiWbAu/SNNB2XgqBPX3HJHfiiaHRMoJqtVqRf2 ySaalenS7VSDQ3WBDpSrXdKDb6rEHAT9COzaHwu7yQk7e1aAKUVm3Gw5oX8/zEvUEc +HM1XIcR65xYMvmbdYR4LnHeTbcdoia788TjgL+Vq79uf3fbPgsHYM6VsOtUMSUzX7 uq/mjBaMypkFsCx19S8vWJz79YrqC0O+6WRThDsN6GzRubBtQdwsq0rr2eDv/sEpB0 6NxA+VOp4XHX9VBc9K88lmMHk/i5vccATLqes/KO3hXb3RV45qVHkZwLK6U/7zcs5L RGv79tH3FXCcw== Received: by phobos.denx.de (Postfix, from userid 109) id C240482CBD; Wed, 5 May 2021 10:21:28 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mout-u-204.mailbox.org (mout-u-204.mailbox.org [91.198.250.253]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 46913806CE for ; Wed, 5 May 2021 10:21:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp1.mailbox.org (smtp1.mailbox.org [IPv6:2001:67c:2050:105:465:1:1:0]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-204.mailbox.org (Postfix) with ESMTPS id 4FZqRm1Q2szQjww; Wed, 5 May 2021 10:21:24 +0200 (CEST) Received: from smtp1.mailbox.org ([80.241.60.240]) by spamfilter05.heinlein-hosting.de (spamfilter05.heinlein-hosting.de [80.241.56.123]) (amavisd-new, port 10030) with ESMTP id D5gfOkws0uIx; Wed, 5 May 2021 10:21:20 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Cc: Kostya Porotchkin , Nadav Haklai Subject: [PATCH v2 1/2] arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN913x DB Date: Wed, 5 May 2021 10:21:18 +0200 Message-Id: <20210505082119.693205-2-sr@denx.de> In-Reply-To: <20210505082119.693205-1-sr@denx.de> References: <20210505082119.693205-1-sr@denx.de> MIME-Version: 1.0 X-MBO-SPAM-Probability: ****** X-Rspamd-Score: 8.96 / 15.00 / 15.00 X-Rspamd-Queue-Id: 42CC51868 X-Rspamd-UID: 4e3b50 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: Konstantin Porotchkin This patch adds the dtsi/dts files needed to support the Marvell Octeon TX2 CN913x DB. This is only the base port with not all interfaces supported fully. Signed-off-by: Konstantin Porotchkin Signed-off-by: Stefan Roese --- Changes in v2: - Changed commit text from CN9132 to CN913x as it supports all variants - Merge identical DT nodes from the A & B variants into the common dtsi files - Change Copyright notice to 2018-2021 as requested by Marvell arch/arm/dts/Makefile | 6 + arch/arm/dts/cn9130-db-A.dts | 55 +++++ arch/arm/dts/cn9130-db-B.dts | 51 +++++ arch/arm/dts/cn9130-db-dev-info.dtsi | 44 ++++ arch/arm/dts/cn9130-db.dtsi | 316 +++++++++++++++++++++++++++ arch/arm/dts/cn9131-db-A.dts | 54 +++++ arch/arm/dts/cn9131-db-B.dts | 69 ++++++ arch/arm/dts/cn9131-db.dtsi | 166 ++++++++++++++ arch/arm/dts/cn9132-db-A.dts | 13 ++ arch/arm/dts/cn9132-db-B.dts | 13 ++ arch/arm/dts/cn9132-db.dtsi | 217 ++++++++++++++++++ 11 files changed, 1004 insertions(+) create mode 100644 arch/arm/dts/cn9130-db-A.dts create mode 100644 arch/arm/dts/cn9130-db-B.dts create mode 100644 arch/arm/dts/cn9130-db-dev-info.dtsi create mode 100644 arch/arm/dts/cn9130-db.dtsi create mode 100644 arch/arm/dts/cn9131-db-A.dts create mode 100644 arch/arm/dts/cn9131-db-B.dts create mode 100644 arch/arm/dts/cn9131-db.dtsi create mode 100644 arch/arm/dts/cn9132-db-A.dts create mode 100644 arch/arm/dts/cn9132-db-B.dts create mode 100644 arch/arm/dts/cn9132-db.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a5cae010c263..92e68ca4361b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -237,6 +237,12 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-xp-maxbcm.dtb \ armada-xp-synology-ds414.dtb \ armada-xp-theadorable.dtb \ + cn9130-db-A.dtb \ + cn9130-db-B.dtb \ + cn9131-db-A.dtb \ + cn9131-db-B.dtb \ + cn9132-db-A.dtb \ + cn9132-db-B.dtb \ cn9130-crb-A.dtb \ cn9130-crb-B.dtb diff --git a/arch/arm/dts/cn9130-db-A.dts b/arch/arm/dts/cn9130-db-A.dts new file mode 100644 index 000000000000..90d6e4a26faa --- /dev/null +++ b/arch/arm/dts/cn9130-db-A.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#include "cn9130-db.dtsi" + +/ { + model = "Marvell CN9130 development board (CP NOR) setup(A)"; + + aliases { + spi0 = &cp0_spi1; + }; +}; + +/* + * CP related configuration + */ +&cp0_pinctl { + /* MPP Bus: + * [0-11] RGMII1 + * [12] GPIO GE-IN + * [13-16] SPI1 + * [17-27] NAND + * [28] MSS_GPIO[5] XXX:(mode nr from a3900) + * [29-30] SATA + * [31] MSS_GPIO[4] XXX:(mode nr from a3900) + * [32,34] SMI + * [33] SDIO + * [35-36] I2C1 + * [37-38] I2C0 + * [39-43] SDIOctrl + * [44-55] RGMII2 + * [56-62] SDIO + */ + + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 3 3 3 3 3 3 3 3 3 3 + 3 3 0 3 3 3 3 1 1 1 + 1 1 1 1 1 1 1 1 3 9 + 9 3 7 6 7 2 2 2 2 1 + 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1 1 0xe 0xe 0xe 0xe + 0xe 0xe 0xe>; +}; + +/* U54 */ +&cp0_nand { + status = "disabled"; +}; + +/* U55 */ +&cp0_spi1 { + status = "okay"; +}; diff --git a/arch/arm/dts/cn9130-db-B.dts b/arch/arm/dts/cn9130-db-B.dts new file mode 100644 index 000000000000..fb52aa856bef --- /dev/null +++ b/arch/arm/dts/cn9130-db-B.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#include "cn9130-db.dtsi" + +/ { + model = "Marvell CN9130 development board (CP NAND) setup(B)"; +}; + +/* + * CP related configuration + */ +&cp0_pinctl { + /* MPP Bus: + * [0-11] RGMII1 + * [12] GPIO GE-IN + * [13-14] SPI1 + * [15-27] NAND + * [28] MSS_GPIO[5] XXX:(mode nr from a3900) + * [29-30] SATA + * [31] MSS_GPIO[4] XXX:(mode nr from a3900) + * [32,34] SMI + * [33] SDIO + * [35-36] I2C1 + * [37-38] I2C0 + * [39-43] SDIOctrl + * [44-55] RGMII2 + * [56-62] SDIO + */ + + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 3 3 3 3 3 3 3 3 3 3 + 3 3 0 2 3 1 1 1 1 1 + 1 1 1 1 1 1 1 1 3 9 + 9 3 7 6 7 2 2 2 2 1 + 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1 1 0xe 0xe 0xe 0xe + 0xe 0xe 0xe>; +}; + +/* U54 */ +&cp0_nand { + status = "okay"; +}; + +/* U55 */ +&cp0_spi1 { + status = "disabled"; +}; diff --git a/arch/arm/dts/cn9130-db-dev-info.dtsi b/arch/arm/dts/cn9130-db-dev-info.dtsi new file mode 100644 index 000000000000..68e9c0bd1461 --- /dev/null +++ b/arch/arm/dts/cn9130-db-dev-info.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ +/ { + /* This should go only into devel boards */ + compatible = "marvell,cp110"; + sar { + #address-cells = <1>; + #size-cells = <0>; + + sar_fields { + compatible = "marvell,sample-at-reset"; + reg = <0x4c 0x4e>; + chip_count = <2>; + bit_width = <5>; + freq { + key = "freq"; + description = "CPU/DDR and PIDI frequencies"; + start-bit = <0>; + bit-length = <4>; + option-cnt = <3>; + options = "0x0", "CPU/DDR = 0x0: 2000/1200 Mhz, PIDI = 0: 1Ghz", + "0x2", "CPU/DDR = 0x6: 2200/1200 Mhz, PIDI = 0: 1Ghz", + "0x4", "CPU/DDR = 0xD: 1600/1200 Mhz, PIDI = 0: 1Ghz"; + default = <0x2>; + status = "okay"; + }; + boot_mode { + key = "boot_mode"; + description = "Boot mode options"; + start-bit = <4>; + bit-length = <6>; + option-cnt = <4>; + options = "0xE", "CP0_NAND PIDI BW-8bit, PS-4KB, ECC-4bit\t(supported configuration: B)", + "0xF", "CP0_NAND PIDI BW-8bit, PS-4KB, ECC-8bit\t(supported configuration: B)", + "0x2A", "AP_EMMC", + "0x32", "CP1_SPI_1 24bits"; + default = <0x32>; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/dts/cn9130-db.dtsi b/arch/arm/dts/cn9130-db.dtsi new file mode 100644 index 000000000000..1b28732ee752 --- /dev/null +++ b/arch/arm/dts/cn9130-db.dtsi @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#include "cn9130.dtsi" /* include SoC device tree */ +#include "cn9130-db-dev-info.dtsi" + +/ { + model = "DB-CN-9130"; + compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd", + "marvell,cn9030", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + i2c0 = &cp0_i2c0; + gpio0 = &ap_gpio0; + gpio1 = &cp0_gpio0; + gpio2 = &cp0_gpio1; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + cp0 { + config-space { + i2c@701000 { + /* U36 */ + expander0: pca953x@21 { + compatible = "nxp,pca9555"; + #gpio-cells = <2>; + reg = <0x21>; + status = "okay"; + }; + }; + sdhci@780000 { + vqmmc-supply = <&cp0_reg_sd_vccq>; + vmmc-supply = <&cp0_reg_sd_vcc>; + }; + + ap_reg_mmc_vccq: ap_mmc_vccq@0 { + compatible = "regulator-gpio"; + regulator-name = "ap_mmc_vccq"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&expander0 8 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1 + 3300000 0x0>; + }; + cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 { + compatible = "regulator-fixed"; + regulator-name = "cp0-xhci0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + regulator-force-boot-off; + gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; + }; + + cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 { + compatible = "regulator-fixed"; + regulator-name = "cp0-xhci1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + regulator-force-boot-off; + gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; + }; + cp0_reg_sd_vccq: cp0_sd_vccq@0 { + compatible = "regulator-gpio"; + regulator-name = "cp0_sd_vccq"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&expander0 15 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1 + 3300000 0x0>; + }; + cp0_reg_sd_vcc: cp0_sd_vcc@0 { + compatible = "regulator-fixed"; + regulator-name = "cp0_sd_vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + cp0_reg_usb3_current_lim0:cp0_usb3_current_limiter@0 { + compatible = "regulator-fixed"; + regulator-min-microamp = <900000>; + regulator-max-microamp = <900000>; + regulator-force-boot-off; + gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; + }; + + cp0_reg_usb3_current_lim1: cp0_usb3_current_limiter@1 { + compatible = "regulator-fixed"; + regulator-min-microamp = <900000>; + regulator-max-microamp = <900000>; + regulator-force-boot-off; + gpio = <&expander0 5 GPIO_ACTIVE_HIGH>; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +/* + * AP related configuration + */ +&ap_pinctl { + /* MPP Bus: + * SDIO [0-10, 12] + * UART0 [11,19] + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 1 1 1 1 1 1 1 1 1 1 + 1 3 1 0 0 0 0 0 0 3 >; +}; + +/* on-board eMMC - U9 */ +&ap_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&ap_emmc_pins>; + vqmmc-supply = <&ap_reg_mmc_vccq>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + status = "okay"; +}; + +/* + * CP related configuration + */ +&cp0_pinctl { + cp0_nand_pins: cp0-nand-pins { + marvell,pins = <15 16 17 18 19 20 21 22 23 24 25 26 27 >; + marvell,function = <1>; + }; + cp0_nand_rb: cp0-nand-rb { + marvell,pins = < 13 >; + marvell,function = <2>; + }; +}; + +/* + * CP0 + */ +&cp0_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&cp0_i2c1 { + status = "okay"; +}; + +/* CON 28 */ +&cp0_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_sdhci_pins>; + bus-width = <4>; + status = "okay"; +}; + +/* U54 */ +&cp0_nand { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_nand_pins &cp0_nand_rb>; + status = "disabled"; +}; + +/* U55 */ +&cp0_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_spi0_pins>; + reg = <0x700680 0x50>, /* control */ + <0x2000000 0x1000000>, /* CS0 */ + <0 0xffffffff>, /* CS1 */ + <0 0xffffffff>, /* CS2 */ + <0 0xffffffff>; /* CS3 */ + status = "disabled"; + + spi-flash@0 { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "jedec,spi-nor", "spi-flash"; + reg = <0x0>; + /* On-board MUX does not allow higher frequencies */ + spi-max-frequency = <40000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x200000>; + }; + + partition@400000 { + label = "Filesystem"; + reg = <0x200000 0xe00000>; + }; + }; + }; +}; + +&cp0_comphy { + phy0 { + phy-type = ; + }; + + phy1 { + phy-type = ; + }; + + phy2 { + phy-type = ; + }; + + phy3 { + phy-type = ; + }; + + phy4 { + phy-type = ; + phy-speed = ; + }; + + phy5 { + phy-type = ; + }; +}; + +/* SLM-1521-V2, CON6 */ +&cp0_pcie0 { + num-lanes = <4>; + status = "disabled"; +}; + +&cp0_mdio { + status = "okay"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cp0_ethernet { + status = "okay"; +}; + +/* SLM-1521-V2, CON9 */ +&cp0_eth0 { + status = "okay"; + phy-mode = "sfi"; +}; + +/* CON56 */ +&cp0_eth1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +/* CON57 */ +&cp0_eth2 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; +}; + +/* SLM-1521-V2, CON2 */ +&cp0_sata0 { + status = "okay"; +}; + +&cp0_utmi0 { + status = "okay"; +}; + +&cp0_utmi1 { + status = "okay"; +}; + +&cp0_usb3_0 { + status = "okay"; + vbus-supply = <&cp0_reg_usb3_vbus0>; + current-limiter = <&cp0_reg_usb3_current_lim0>; + vbus-disable-delay = <500>; +}; + +&cp0_usb3_1 { + status = "okay"; + vbus-supply = <&cp0_reg_usb3_vbus1>; + current-limiter = <&cp0_reg_usb3_current_lim1>; + vbus-disable-delay = <500>; +}; + +&cp0_pcie0 { + status = "okay"; +}; diff --git a/arch/arm/dts/cn9131-db-A.dts b/arch/arm/dts/cn9131-db-A.dts new file mode 100644 index 000000000000..81aff17e31d5 --- /dev/null +++ b/arch/arm/dts/cn9131-db-A.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#include "cn9130-db-A.dts" +#include "cn9131-db.dtsi" + +/ { + model = "Marvell CN9131 development board (CP NOR) setup(A)"; + compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; + +&cp1_comphy { + /* Serdes Configuration: + * Lane 0: PCIe0 (x2) + * Lane 1: PCIe0 (x2) + * Lane 2: unconnected + * Lane 3: USB1 + * Lane 4: SFP (port 0) + * Lane 5: SATA1 + */ + phy0 { + phy-type = ; + }; + phy1 { + phy-type = ; + }; + phy2 { + phy-type = ; + }; + phy3 { + phy-type = ; + }; + phy4 { + phy-type = ; + phy-speed = ; + }; + phy5 { + phy-type = ; + }; +}; + +&cp1_ethernet { + status = "okay"; +}; + +/* CON50 */ +&cp1_eth0 { + status = "okay"; + phy-mode = "sfi"; /* lane-4 */ + marvell,sfp-tx-disable-gpio = <&cp1_gpio0 9 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/dts/cn9131-db-B.dts b/arch/arm/dts/cn9131-db-B.dts new file mode 100644 index 000000000000..0269183620ea --- /dev/null +++ b/arch/arm/dts/cn9131-db-B.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#include "cn9130-db-B.dts" +#include "cn9131-db.dtsi" + +/ { + model = "Marvell CN9131 development board (CP NAND) setup(B)"; + compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; + +&cp1_comphy { + /* Serdes Configuration: + * Lane 0: PCIe0 (x2) + * Lane 1: PCIe0 (x2) + * Lane 2: SFI (port 0) + * Lane 3: USB1 + * Lane 4: SGMII (port 1) + * Lane 5: SATA1 + */ + phy0 { + phy-type = ; + }; + phy1 { + phy-type = ; + }; + phy2 { + phy-type = ; + phy-speed = ; + }; + phy3 { + phy-type = ; + }; + phy4 { + phy-type = ; + phy-speed = ; + }; + phy5 { + phy-type = ; + }; +}; + +&cp1_ethernet { + status = "okay"; +}; + +/* 3310 RJ45 CON55 */ +&cp1_eth0 { + status = "okay"; + phy-mode = "sfi"; /* lane-2 */ + phy = <&sfi_phy8>; /* required by 3310 fw download */ +}; + +/* CON50 */ +&cp1_eth1 { + status = "okay"; + phy-mode = "sgmii"; /* lane-4 */ + marvell,sfp-tx-disable-gpio = <&cp1_gpio0 9 GPIO_ACTIVE_HIGH>; +}; + +&cp1_xmdio { + status = "okay"; + sfi_phy8: ethernet-phy@8 { + reg = <8>; + }; +}; diff --git a/arch/arm/dts/cn9131-db.dtsi b/arch/arm/dts/cn9131-db.dtsi new file mode 100644 index 000000000000..5057605584d1 --- /dev/null +++ b/arch/arm/dts/cn9131-db.dtsi @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#undef CP110_NAME +#undef CP110_NUM +#undef CP110_PCIE_MEM_SIZE +#undef CP110_PCIEx_CPU_MEM_BASE +#undef CP110_PCIEx_BUS_MEM_BASE + +/* CP110-1 Settings */ +#define CP110_NAME cp1 +#define CP110_NUM 1 +#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) +#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000) +#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) + +#include "armada-cp110.dtsi" + +/ { + model = "Marvell CN9131 development board"; + compatible = "marvell,cn9131-db"; + + aliases { + gpio3 = &cp1_gpio0; + gpio4 = &cp1_gpio1; + }; + + cp1 { + config-space { + cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_xhci0_vbus_pins>; + regulator-name = "cp1-xhci0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + regulator-force-boot-off; + gpio = <&cp1_gpio0 3 GPIO_ACTIVE_HIGH>; + }; + cp1_reg_usb3_current_lim0: cp1_usb3_current_limiter@0 { + compatible = "regulator-fixed"; + regulator-min-microamp = <900000>; + regulator-max-microamp = <900000>; + regulator-force-boot-off; + gpio = <&cp1_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + cp1_pcie_reset_pins: cp1-pcie-reset-pins { + marvell,pins = <0>; + marvell,function = <0>; + }; + }; + }; +}; + +&cp1_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp1_i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +/* CON40 */ +&cp1_pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp1_pcie_reset_pins>; + marvell,reset-gpio = <&cp1_gpio0 0 GPIO_ACTIVE_LOW>; + status = "okay"; + num-lanes = <2>; + /* non-prefetchable memory */ + ranges = <0x82000000 0 0xe2000000 0 0xe2000000 0 0xf00000>; +}; + +&cp1_pinctl { + compatible = "marvell,mvebu-pinctrl", + "marvell,cp115-standalone-pinctrl"; + bank-name ="cp1-110"; + + /* MPP Bus: + * [0-12] GPIO + * [13-16] SPI1 + * [17-27] GPIO (Default) + * [28] SATA1_PRESENT_ACTIVEn + * [29-34] GPIO (Default) + * [35-36] xSMI + * [37-38] I2C0 + * [39-62] GPIO + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x3 0x3 0x3 0x3 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9 0x0 + 0x0 0x0 0x0 0x0 0x0 0x7 0x7 0x2 0x2 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 >; + + cp1_i2c0_pins: cp1-i2c-pins-0 { + marvell,pins = < 37 38 >; + marvell,function = <2>; + }; + cp1_spi0_pins: cp1-spi-pins-0 { + marvell,pins = < 13 14 15 16 >; + marvell,function = <3>; + }; + cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins { + marvell,pins = <3>; + marvell,function = <0>; + }; +}; + +/* CON32 */ +&cp1_sata0 { + status = "okay"; +}; + +/* U24 */ +&cp1_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp1_spi0_pins>; + reg = <0x700680 0x50>, /* control */ + <0x2000000 0x1000000>, /* CS0 */ + <0 0xffffffff>, /* CS1 */ + <0 0xffffffff>, /* CS2 */ + <0 0xffffffff>; /* CS3 */ + status = "okay"; + + spi-flash@0 { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "jedec,spi-nor", "spi-flash"; + reg = <0x0>; + /* On-board MUX does not allow higher frequencies */ + spi-max-frequency = <40000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x200000>; + }; + + partition@400000 { + label = "Filesystem"; + reg = <0x200000 0xe00000>; + }; + }; + }; +}; + +/* CON58 */ +&cp1_usb3_1 { + vbus-supply = <&cp1_reg_usb3_vbus0>; + current-limiter = <&cp1_reg_usb3_current_lim0>; + vbus-disable-delay = <500>; + status = "okay"; +}; + +&cp1_utmi1 { + status = "okay"; +}; diff --git a/arch/arm/dts/cn9132-db-A.dts b/arch/arm/dts/cn9132-db-A.dts new file mode 100644 index 000000000000..ba9b8a25d1d8 --- /dev/null +++ b/arch/arm/dts/cn9132-db-A.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#include "cn9131-db-A.dts" +#include "cn9132-db.dtsi" + +/ { + model = "Marvell CN9132 development board (CP NOR) setup(A)"; + compatible = "marvell,cn9132-db", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; diff --git a/arch/arm/dts/cn9132-db-B.dts b/arch/arm/dts/cn9132-db-B.dts new file mode 100644 index 000000000000..e126e23ea65f --- /dev/null +++ b/arch/arm/dts/cn9132-db-B.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#include "cn9131-db-B.dts" +#include "cn9132-db.dtsi" + +/ { + model = "Marvell CN9132 development board (CP NAND) setup(B)"; + compatible = "marvell,cn9132-db-B", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; diff --git a/arch/arm/dts/cn9132-db.dtsi b/arch/arm/dts/cn9132-db.dtsi new file mode 100644 index 000000000000..d51a4d0b30e6 --- /dev/null +++ b/arch/arm/dts/cn9132-db.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#undef CP110_NAME +#undef CP110_NUM +#undef CP110_PCIE_MEM_SIZE +#undef CP110_PCIEx_CPU_MEM_BASE +#undef CP110_PCIEx_BUS_MEM_BASE + +/* CP110-2 Settings */ +#define CP110_NAME cp2 +#define CP110_NUM 2 +#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) +#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000) +#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) + +#include "armada-cp110.dtsi" + +/ { + model = "Marvell CN9132 development board"; + compatible = "marvell,cn9132-db"; + + aliases { + gpio5 = &cp2_gpio0; + gpio6 = &cp2_gpio1; + }; + + cp2 { + config-space { + sdhci@780000 { + vqmmc-supply = <&cp2_reg_sd_vccq>; + }; + + cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 { + compatible = "regulator-fixed"; + regulator-name = "cp2-xhci0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + regulator-force-boot-off; + gpio = <&cp2_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + + cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 { + compatible = "regulator-fixed"; + regulator-name = "cp2-xhci1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + regulator-force-boot-off; + gpio = <&cp2_gpio0 3 GPIO_ACTIVE_HIGH>; + }; + cp2_reg_sd_vccq: cp2_sd_vccq@0 { + compatible = "regulator-gpio"; + regulator-name = "cp2_sd_vcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + /* cp2_mpp49 */ + gpios = <&cp2_gpio1 17 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1 + 3300000 0x0>; + }; + cp2_reg_usb3_current_lim0: cp2_usb3_current_limiter@0 { + compatible = "regulator-fixed"; + regulator-min-microamp = <900000>; + regulator-max-microamp = <900000>; + regulator-force-boot-off; + gpio = <&cp2_gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + cp2_reg_usb3_current_lim1: cp2_usb3_current_limiter@1 { + compatible = "regulator-fixed"; + regulator-min-microamp = <900000>; + regulator-max-microamp = <900000>; + regulator-force-boot-off; + gpio = <&cp2_gpio0 1 GPIO_ACTIVE_HIGH>; + }; + }; + }; +}; + +&cp2_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp2_i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&cp2_pinctl { + compatible = "marvell,mvebu-pinctrl", + "marvell,cp115-standalone-pinctrl"; + bank-name ="cp2-110"; + + /* MPP Bus: + * [0-26] GPIO + * [27] SATA0_PRESENT_ACTIVEn + * [28] SATA1_PRESENT_ACTIVEn + * [29-31, 33] GPIO (Default) + * [32,34] SMI + * [37-38] I2C0 + * [39-53] GPIO + * [54] SD_CRD_RSTn (out) + * [55] SD_CRD_DT (in) + * [56-62] SDIO + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9 0x9 0x0 + 0x0 0x0 0x8 0x0 0x8 0x0 0x0 0x2 0x2 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0xa 0xb 0xe 0xe 0xe 0xe + 0xe 0xe 0xe >; + + cp2_i2c0_pins: cp2-i2c-pins-0 { + marvell,pins = < 37 38 >; + marvell,function = <2>; + }; + + cp2_sdhci_pins: cp2-sdhi-pins-0 { + marvell,pins = < 56 57 58 59 60 61 >; + marvell,function = <14>; + }; +}; + +&cp2_usb3_0 { + status = "okay"; + vbus-supply = <&cp2_reg_usb3_vbus0>; + current-limiter = <&cp2_reg_usb3_current_lim0>; + vbus-disable-delay = <500>; +}; + +/* SLM-1521-V2, CON11 */ +&cp2_usb3_1 { + status = "okay"; + vbus-supply = <&cp2_reg_usb3_vbus1>; + current-limiter = <&cp2_reg_usb3_current_lim1>; + vbus-disable-delay = <500>; + status = "okay"; +}; + +&cp2_utmi0 { + status = "okay"; +}; + +&cp2_utmi1 { + status = "okay"; +}; + +&cp2_comphy { + phy0 { + phy-type = ; + }; + + phy1 { + phy-type = ; + }; + + phy2 { + phy-type = ; + }; + + phy3 { + phy-type = ; + }; + + phy4 { + phy-type = ; + phy-speed = ; + }; + + phy5 { + phy-type = ; + }; +}; + +&cp2_ethernet { + status = "okay"; +}; + +/* SLM-1521-V2, CON9 */ +&cp2_eth0 { + status = "okay"; + phy-mode = "sfi"; +}; + +/* SLM-1521-V2, CON6 */ +&cp2_pcie0 { + /* non-prefetchable memory */ + ranges =<0x82000000 0 0xe5000000 0 0xe5000000 0 0x1000000>; + num-lanes = <2>; + status = "okay"; +}; + +/* SLM-1521-V2, CON8 */ +&cp2_pcie2 { + num-lanes = <1>; + status = "okay"; +}; + +&cp2_pinctl { +}; + +/* SLM-1521-V2, CON4 */ +&cp2_sata0 { + status = "okay"; +}; + +/* CON 2 on SLM-1683 - microSD */ +&cp2_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp2_sdhci_pins>; + bus-width = <4>; + status = "okay"; +}; From patchwork Wed May 5 08:21:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 1474176 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=HJpAma8m; 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Wed, 5 May 2021 10:21:24 +0200 (CEST) Received: from smtp1.mailbox.org ([80.241.60.240]) by gerste.heinlein-support.de (gerste.heinlein-support.de [91.198.250.173]) (amavisd-new, port 10030) with ESMTP id JFTa532-kYpl; Wed, 5 May 2021 10:21:20 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Cc: Kostya Porotchkin , Nadav Haklai Subject: [PATCH v2 2/2] arm: octeontx2: Add Octeon TX2 CN913x DB support Date: Wed, 5 May 2021 10:21:19 +0200 Message-Id: <20210505082119.693205-3-sr@denx.de> In-Reply-To: <20210505082119.693205-1-sr@denx.de> References: <20210505082119.693205-1-sr@denx.de> MIME-Version: 1.0 X-MBO-SPAM-Probability: ***** X-Rspamd-Score: 6.59 / 15.00 / 15.00 X-Rspamd-Queue-Id: AEC7E189E X-Rspamd-UID: f03d26 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: Konstantin Porotchkin This patch adds the base support for the Marvell Octeon TX2 CN913x DB. Only one defconfig is added with this patch. Other board variants are available (NAND, MMC booting) and images for these boards can be generated by following the documentation added in the included README. Signed-off-by: Konstantin Porotchkin Signed-off-by: Stefan Roese --- Changes in v2: - Changed commit text from CN9132 to CN913x as it supports all variants - Renamed default defconfig to mvebu_db_cn9130_defconfig - Removed NAND booting defconfig and added small README board/Marvell/octeontx2_cn913x/MAINTAINERS | 2 + board/Marvell/octeontx2_cn913x/README | 24 ++++++ configs/mvebu_db_cn9130_defconfig | 89 ++++++++++++++++++++++ 3 files changed, 115 insertions(+) create mode 100644 board/Marvell/octeontx2_cn913x/README create mode 100644 configs/mvebu_db_cn9130_defconfig diff --git a/board/Marvell/octeontx2_cn913x/MAINTAINERS b/board/Marvell/octeontx2_cn913x/MAINTAINERS index d469e16ea753..5ce23c80f6b2 100644 --- a/board/Marvell/octeontx2_cn913x/MAINTAINERS +++ b/board/Marvell/octeontx2_cn913x/MAINTAINERS @@ -3,3 +3,5 @@ M: Kostya Porotchkin S: Maintained F: board/Marvell/octeontx2_cn913x/ F: configs/mvebu_crb_cn9130_defconfig +F: configs/mvebu_db_cn9132_defconfig +F: configs/mvebu_db_cn9132_nand_defconfig diff --git a/board/Marvell/octeontx2_cn913x/README b/board/Marvell/octeontx2_cn913x/README new file mode 100644 index 000000000000..3d0c8b31e4c2 --- /dev/null +++ b/board/Marvell/octeontx2_cn913x/README @@ -0,0 +1,24 @@ +Not all board variants are represented with a specific defconfig in +mainline U-Boot. Here a small documentation on how to generate U-Boot +images for all other board variants, available via different dts +files and defconfigs. + +Use a different dts than in the defconfig: + +make DEVICE_TREE=cn9131-db-B + +Use a different boot device (e.g. MMC or NAND instead of SPI NOR): + +For MMC, please make the following changes to the defconfig via +e.g. "make menuconfig": +Remove CONFIG_MVEBU_SPI_BOOT +Select CONFIG_MVEBU_MMC_BOOT +Remove CONFIG_ENV_IS_IN_SPI_FLASH +Select CONFIG_ENV_IS_IN_MMC + +For NAND, please make the following changes to the defconfig via +e.g. "make menuconfig": +Remove CONFIG_MVEBU_SPI_BOOT +Select CONFIG_MVEBU_NAND_BOOT +Remove CONFIG_ENV_IS_IN_SPI_FLASH +Select CONFIG_ENV_IS_IN_NAND diff --git a/configs/mvebu_db_cn9130_defconfig b/configs/mvebu_db_cn9130_defconfig new file mode 100644 index 000000000000..57fe525b4b65 --- /dev/null +++ b/configs/mvebu_db_cn9130_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_OCTEONTX2_CN913x=y +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x3f0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEBUG_UART_BASE=0xf0512000 +CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEFAULT_DEVICE_TREE="cn9130-db-A" +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="Marvell>> " +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_MVEBU_BUBT=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_MAC_PARTITION=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_AHCI_MVEBU=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_MISC=y +CONFIG_MVEBU_SAR=y +CONFIG_MMC_BROKEN_CD=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_NAND_PXA3XX=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_GIGE=y +CONFIG_MVPP2=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCIE_DW_MVEBU=y +CONFIG_MVEBU_COMPHY_SUPPORT=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_8K=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_KIRKWOOD_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y