From patchwork Thu Jan 18 13:10:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 862889 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zMkpp3J4jz9s74 for ; Fri, 19 Jan 2018 00:10:42 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BCF68C21E9B; Thu, 18 Jan 2018 13:10:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8F253C21E8B; Thu, 18 Jan 2018 13:10:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D09F0C21E41; Thu, 18 Jan 2018 13:10:10 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id 82C5EC21C3F for ; Thu, 18 Jan 2018 13:10:10 +0000 (UTC) Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w0ID9LDb031039; Thu, 18 Jan 2018 14:10:08 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2fgygdmd6s-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 18 Jan 2018 14:10:08 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 76DE431; Thu, 18 Jan 2018 13:10:08 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 613CC252C; Thu, 18 Jan 2018 13:10:08 +0000 (GMT) Received: from localhost (10.75.127.47) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 18 Jan 2018 14:10:08 +0100 From: To: , , , Date: Thu, 18 Jan 2018 14:10:03 +0100 Message-ID: <1516281005-32045-2-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516281005-32045-1-git-send-email-patrice.chotard@st.com> References: <1516281005-32045-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-18_06:, , signatures=0 Subject: [U-Boot] [PATCH v2 1/3] ARM: dts: stm32: Add STMMAC clocks for stm32f746 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard Add ETHMAC, ETHMACRX and ETHMACTX clocks for STMMAC. Signed-off-by: Patrice Chotard Reviewed-by: Vikas Manocha --- v2: _ add Reviewed-by arch/arm/dts/stm32f746.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 929bf82..46d148e 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -65,6 +65,9 @@ compatible = "st,stm32-dwmac"; reg = <0x40028000 0x8000>; reg-names = "stmmaceth"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>, + <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>, + <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>; interrupts = <61>, <62>; interrupt-names = "macirq", "eth_wake_irq"; snps,pbl = <8>; From patchwork Thu Jan 18 13:10:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 862891 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zMkqs6QfSz9s7v for ; Fri, 19 Jan 2018 00:11:37 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 710ECC21EA7; Thu, 18 Jan 2018 13:10:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 82D13C21EA8; Thu, 18 Jan 2018 13:10:13 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1C28EC21C3F; Thu, 18 Jan 2018 13:10:11 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id C1A04C21E2F for ; Thu, 18 Jan 2018 13:10:10 +0000 (UTC) Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w0ID9bK2031442; Thu, 18 Jan 2018 14:10:09 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2fgygdmd6y-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 18 Jan 2018 14:10:09 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5313231; Thu, 18 Jan 2018 13:10:09 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 38647252C; Thu, 18 Jan 2018 13:10:09 +0000 (GMT) Received: from localhost (10.75.127.47) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 18 Jan 2018 14:10:08 +0100 From: To: , , , Date: Thu, 18 Jan 2018 14:10:04 +0100 Message-ID: <1516281005-32045-3-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516281005-32045-1-git-send-email-patrice.chotard@st.com> References: <1516281005-32045-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG7NODE1.st.com (10.75.127.19) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-18_06:, , signatures=0 Subject: [U-Boot] [PATCH v2 2/3] clk: clk_stm32f: Remove STMMAC clock setup X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard Thanks to 'commit ba1f96672522 ("net: designware: add clock support")' we don't need anymore to setup the STMMAC clock in board. Signed-off-by: Patrice Chotard Reviewed-by: Vikas Manocha --- v2: _ add Reviewed-by arch/arm/include/asm/arch-stm32f7/stm32_periph.h | 1 - board/st/stm32f746-disco/stm32f746-disco.c | 1 - drivers/clk/clk_stm32f.c | 6 ------ 3 files changed, 8 deletions(-) diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h index ae0faef..13f9c9b 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h @@ -23,7 +23,6 @@ enum periph_id { enum periph_clock { SYSCFG_CLOCK_CFG, TIMER2_CLOCK_CFG, - STMMAC_CLOCK_CFG, }; #endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 2e8aa86..58a5ef0 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -75,7 +75,6 @@ static int stmmac_setup(void) clock_setup(SYSCFG_CLOCK_CFG); /* Set >RMII mode */ STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; - clock_setup(STMMAC_CLOCK_CFG); return 0; } diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index 63116e0..d0c7a90 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -90,7 +90,6 @@ enum periph_clock { SYSCFG_CLOCK_CFG, TIMER2_CLOCK_CFG, - STMMAC_CLOCK_CFG, }; struct stm32_clk_info stm32f4_clk_info = { @@ -359,11 +358,6 @@ void clock_setup(int peripheral) case TIMER2_CLOCK_CFG: setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); break; - case STMMAC_CLOCK_CFG: - setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN); - setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN); - setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN); - break; default: break; } From patchwork Thu Jan 18 13:10:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 862890 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zMkqm3Zf4z9s83 for ; Fri, 19 Jan 2018 00:11:32 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 045B3C21E41; Thu, 18 Jan 2018 13:11:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 536E6C21EC3; Thu, 18 Jan 2018 13:10:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 669C6C21E88; Thu, 18 Jan 2018 13:10:16 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id 6EDBCC21C3F for ; Thu, 18 Jan 2018 13:10:12 +0000 (UTC) Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w0ID9bK3031442; Thu, 18 Jan 2018 14:10:11 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2fgygdmd76-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 18 Jan 2018 14:10:11 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A727331; Thu, 18 Jan 2018 13:10:10 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 905192528; Thu, 18 Jan 2018 13:10:10 +0000 (GMT) Received: from localhost (10.75.127.45) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 18 Jan 2018 14:10:09 +0100 From: To: , , , Date: Thu, 18 Jan 2018 14:10:05 +0100 Message-ID: <1516281005-32045-4-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516281005-32045-1-git-send-email-patrice.chotard@st.com> References: <1516281005-32045-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG7NODE3.st.com (10.75.127.21) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-18_06:, , signatures=0 Subject: [U-Boot] [PATCH v2 3/3] clk: clk_stm32f: Move SYSCFG clock setup into configure_clocks() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard Move SYSCFG clock setup into configure_clocks() instead of calling clock_setup() from board file. As this clock is only needed in case of ethernet enabled and as both stm32f4 and stm32f7 are using the Designware ethernet IP, we use CONFIG_ETH_DESIGNWARE to only enable this clock if needed. Move the RMII setup from board_early_init_f() to board_init() to insure that RMII bit is set only when clock driver is initialized. Signed-off-by: Patrice Chotard --- v2: _ update commit message to explain the usage of CONFIG_ETH_DESIGNWARE flag. _ add missing CONFIG_ETH_DESIGNWARE compilation flag to enable SYSCFG clock only if ETH_DESIGNWARE is enabled on running board. arch/arm/include/asm/arch-stm32f7/stm32_periph.h | 1 - board/st/stm32f746-disco/stm32f746-disco.c | 19 ++++++------------- drivers/clk/clk_stm32f.c | 12 ++++++------ 3 files changed, 12 insertions(+), 20 deletions(-) diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h index 13f9c9b..7b8f66a 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h @@ -21,7 +21,6 @@ enum periph_id { }; enum periph_clock { - SYSCFG_CLOCK_CFG, TIMER2_CLOCK_CFG, }; diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 58a5ef0..8da7028 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -69,23 +69,10 @@ int dram_init_banksize(void) return 0; } -#ifdef CONFIG_ETH_DESIGNWARE -static int stmmac_setup(void) -{ - clock_setup(SYSCFG_CLOCK_CFG); - /* Set >RMII mode */ - STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; - - return 0; -} - int board_early_init_f(void) { - stmmac_setup(); - return 0; } -#endif #ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_OS_BOOT @@ -162,5 +149,11 @@ int board_late_init(void) int board_init(void) { gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + +#ifdef CONFIG_ETH_DESIGNWARE + /* Set >RMII mode */ + STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; +#endif + return 0; } diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index d0c7a90..2d557fd 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -67,8 +67,6 @@ #define RCC_DCKCFGRX_SDMMC1SEL BIT(28) #define RCC_DCKCFGR2_SDMMC2SEL BIT(29) -#define RCC_APB2ENR_SAI1EN BIT(22) - /* * RCC AHB1ENR specific definitions */ @@ -86,9 +84,9 @@ * RCC APB2ENR specific definitions */ #define RCC_APB2ENR_SYSCFGEN BIT(14) +#define RCC_APB2ENR_SAI1EN BIT(22) enum periph_clock { - SYSCFG_CLOCK_CFG, TIMER2_CLOCK_CFG, }; @@ -227,6 +225,11 @@ static int configure_clocks(struct udevice *dev) /* gate the SAI clock, needed for MMC 1&2 clocks */ setbits_le32(®s->apb2enr, RCC_APB2ENR_SAI1EN); +#ifdef CONFIG_ETH_DESIGNWARE + /* gate the SYSCFG clock, needed to set RMII ethernet interface */ + setbits_le32(®s->apb2enr, RCC_APB2ENR_SYSCFGEN); +#endif + return 0; } @@ -352,9 +355,6 @@ static int stm32_clk_enable(struct clk *clk) void clock_setup(int peripheral) { switch (peripheral) { - case SYSCFG_CLOCK_CFG: - setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN); - break; case TIMER2_CLOCK_CFG: setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); break;