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Tue, 27 Apr 2021 14:55:51 +0000 Received: from SDONTHINENI-DESKTOP.nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 27 Apr 2021 14:55:50 +0000 From: Shanker Donthineni To: Alex Williamson CC: Bjorn Helgaas , , , Sinan Kaya , Vikram Sethi , Shanker Donthineni Subject: [PATCH v3 1/2] PCI: Add support for a function level reset based on _RST method Date: Tue, 27 Apr 2021 09:55:34 -0500 Message-ID: <20210427145535.4034-1-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b25a730c-3252-4d85-0802-08d9098c8d12 X-MS-TrafficTypeDiagnostic: BL0PR12MB4913: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1824; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RepwdBzjkrl0wu3fuMt/t9BHGrH4uSy7qgO7SBGsebbx2pdd/tT/Dq1htyzzqKh/AqItGKiG85P0kCqotKFx2hj0JgVX0Duvudt3uTmU9nO5f9EfVAHFP9N9GRWHu7ubeUGUDGNjOXadzOCcr51Uc9lNMf1nyK3C52oilAhnOCgXPwMKbFv4A9ILdZXLO6WQTQa7fDGkYnTD1WAUTw+O/1m9TPRj7cSLewbgcbluYPHT9qb1sNlnE82vMrp28cNiGSc3BqLDuPZZx71nypOc3O149seRi+59H+tqP0RrBHZsD5MhHhg782WL4FEr5iXLW6CzJp30XidBn1SPqJ65pEcjKMe+ve18IRL+2T37KODqLYWKA92YyJa/P4ZZVwi73JuebYCTo4kmLEgs2LRHpvoeBWj7ucFzcCodvaNK8yhEPVwbGab7SextMcL9dwJKAP8rzGsMPbdxpHVWu3D7GLEkzN8nTYzEPugFCwSq3b2yQShFhZ4WJI5idBLFSscormgvMF4HVlRfig2jbj68k0f70ApNSNHEspLirDbiuk+uH5+yLqeSnfJaTkSDlBOwU1YmPeDHNo5tQAulxWYU3ozjp//X6ZcXGufm3VoPjGBMdmqWW+T1Ut0kx1KbuQqQaZW0xW5X5m/4hVxs+qwEhwZ4DmA+4MfuDkOvN9/3CDo= X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(376002)(396003)(346002)(136003)(39860400002)(46966006)(36840700001)(2906002)(36756003)(83380400001)(478600001)(426003)(336012)(6916009)(70586007)(6666004)(8676002)(54906003)(4326008)(26005)(16526019)(2616005)(8936002)(36906005)(107886003)(316002)(186003)(36860700001)(1076003)(7636003)(70206006)(82740400003)(82310400003)(47076005)(7696005)(356005)(86362001)(5660300002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2021 14:55:51.5327 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b25a730c-3252-4d85-0802-08d9098c8d12 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT046.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4913 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The _RST is a standard method specified in the ACPI specification. It provides a function level reset when it is described in the acpi_device context associated with PCI-device. Implement a new reset function pci_dev_acpi_reset() for probing RST method and execute if it is defined in the firmware. The ACPI based reset is called after the device-specific reset and before standard PCI hardware resets. Signed-off-by: Shanker Donthineni --- - Fix typo in the commit text drivers/pci/pci.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 16a17215f633..6dadb19848c2 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5054,6 +5054,35 @@ static void pci_dev_restore(struct pci_dev *dev) err_handler->reset_done(dev); } +/** + * pci_dev_acpi_reset - do a function level reset using _RST method + * @dev: device to reset + * @probe: check if _RST method is included in the acpi_device context. + */ +static int pci_dev_acpi_reset(struct pci_dev *dev, int probe) +{ +#ifdef CONFIG_ACPI + acpi_handle handle = ACPI_HANDLE(&dev->dev); + + /* Return -ENOTTY if _RST method is not included in the dev context */ + if (!handle || !acpi_has_method(handle, "_RST")) + return -ENOTTY; + + /* Return 0 for probe phase indicating that we can reset this device */ + if (probe) + return 0; + + /* Invoke _RST() method to perform a function level reset */ + if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { + pci_warn(dev, "Failed to reset the device\n"); + return -EINVAL; + } + return 0; +#else + return -ENOTTY; +#endif +} + /** * __pci_reset_function_locked - reset a PCI device function while holding * the @dev mutex lock. @@ -5089,6 +5118,9 @@ int __pci_reset_function_locked(struct pci_dev *dev) * reset mechanisms might be broken on the device. */ rc = pci_dev_specific_reset(dev, 0); + if (rc != -ENOTTY) + return rc; + rc = pci_dev_acpi_reset(dev, 0); if (rc != -ENOTTY) return rc; if (pcie_has_flr(dev)) { @@ -5127,6 +5159,9 @@ int pci_probe_reset_function(struct pci_dev *dev) might_sleep(); rc = pci_dev_specific_reset(dev, 1); + if (rc != -ENOTTY) + return rc; + rc = pci_dev_acpi_reset(dev, 1); if (rc != -ENOTTY) return rc; if (pcie_has_flr(dev)) From patchwork Tue Apr 27 14:55:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 1470713 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT013.mail.protection.outlook.com (10.13.174.227) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4065.21 via Frontend Transport; Tue, 27 Apr 2021 14:55:52 +0000 Received: from SDONTHINENI-DESKTOP.nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 27 Apr 2021 14:55:51 +0000 From: Shanker Donthineni To: Alex Williamson CC: Bjorn Helgaas , , , Sinan Kaya , Vikram Sethi , Shanker Donthineni Subject: [PATCH v3 2/2] PCI: Enable NO_BUS_RESET quirk for Nvidia GPUs Date: Tue, 27 Apr 2021 09:55:35 -0500 Message-ID: <20210427145535.4034-2-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210427145535.4034-1-sdonthineni@nvidia.com> References: <20210427145535.4034-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: dc11e3c4-2730-43ad-4f8b-08d9098c8dd8 X-MS-TrafficTypeDiagnostic: BN7PR12MB2643: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2021 14:55:52.8381 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dc11e3c4-2730-43ad-4f8b-08d9098c8dd8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR12MB2643 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On select platforms, some Nvidia GPU devices do not work with SBR. Triggering SBR would leave the device inoperable for the current system boot. It requires a system hard-reboot to get the GPU device back to normal operating condition post-SBR. For the affected devices, enable NO_BUS_RESET quirk to fix the issue. This issue will be fixed in the next generation of hardware. Signed-off-by: Shanker Donthineni --- Changes since v1: - Split patch into 2, code for handling _RST and SBR specific quirk - The RST based reset is called as a first-class mechanism in the reset code path drivers/pci/quirks.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 653660e3ba9e..1da80e772ee1 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3913,6 +3913,18 @@ static int delay_250ms_after_flr(struct pci_dev *dev, int probe) return 0; } +/* + * Some Nvidia GPU devices do not work with bus reset, SBR needs to be + * prevented for those affected devices. + */ +static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) +{ + if ((dev->device & 0xffc0) == 0x2340) + dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, + quirk_nvidia_no_bus_reset); + static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, reset_intel_82599_sfp_virtfn },