From patchwork Sat Apr 17 19:41:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1467530 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=A+wQSu24; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FN3QC4hRlz9vDc for ; Sun, 18 Apr 2021 05:42:41 +1000 (AEST) Received: from localhost ([::1]:33616 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXqpy-0007tN-JI for incoming@patchwork.ozlabs.org; Sat, 17 Apr 2021 15:42:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39336) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXqpY-0007sk-5m for qemu-devel@nongnu.org; Sat, 17 Apr 2021 15:42:12 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:39646) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXqpW-0008Am-72 for qemu-devel@nongnu.org; Sat, 17 Apr 2021 15:42:11 -0400 Received: by mail-wm1-x32b.google.com with SMTP id i21-20020a05600c3555b029012eae2af5d4so6363754wmq.4 for ; Sat, 17 Apr 2021 12:42:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CuYAxYEssZGCHU2JHke0qyk/TAhFSaPXu7Y4rIDN+sw=; b=A+wQSu24ydbrfJnh5jM0fF2ovnGlvviStL3W0HPKJWQ3stKb6cX7t6wWTuNUjKdxjw vEAmbnSyqI5qdlhuwZAF0Vd8WGGi1uxEn6JPGkVlipHLeNT4eDxWE5nhIYtYj5Rcnh2t 62OrSFu5RJu+6Y0yLuGdeq5vt/QCzu1JmwNJHBWx48xL9WG6ntvKHCPfFMasObRtpubl yxVHw1csKAg3f+Nt/D+uPO7haLe/CnOQoDnmmjpkfMkOyUYjVeBcOzlQZ2V3yhatApzG gUL87d4TPTtV1ijoY6uF3o5/jm+MHS+1mEGKUzqAhxIPXoEtCtS3lh5j+eWg8Dzx/f6D wMlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CuYAxYEssZGCHU2JHke0qyk/TAhFSaPXu7Y4rIDN+sw=; b=bYyJRvHtyAtPIHIh9zkcOReFBGOGeubfKASPwMXULRuT5I7otTbV4cIsZHJ+sZ+R6o ZbpmlRlF983kah4/VdElm5COtuoke4+UqrKo9FvtT4AeAv7O4D3rdhg6A1RjlFw4gWI9 UvAYTS2NALqOHBK7NM/C73w+UnKmkYxqn8nIB5BIOR0aNJvj3dBN5SRKo6keXnjKC1Wr Aka/EMXM/aHv2/bmjTPDLWNSyoj2vm3osingypNcoL65jNMkrrCsD6WWgUi1oXYvBsCE hnWxuC5IusDYSzJVEPHs0a2LuhhzGjc0G2l0/UI+pXE0ZpI2qDP6bgZM4/Wl56QfYOP1 R7oQ== X-Gm-Message-State: AOAM530DCocApSLNC+af5GHjgQAEzcNu10+hKhMW3sbkfYiob5N97Kyi 2Qvvzh0Q7s8qBphmR8Rn+rPMoIz8IimmkbHd X-Google-Smtp-Source: ABdhPJz5EsYW7SEeTARx/HUM3iRWJmbqHSEIIEantLzguGvhvZODTqw0PcwWj5BOMfHjWULxszBlvQ== X-Received: by 2002:a7b:c444:: with SMTP id l4mr13941414wmi.36.1618688528631; Sat, 17 Apr 2021 12:42:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c12sm17304374wro.6.2021.04.17.12.42.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Apr 2021 12:42:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/7] osdep: include glib-compat.h before other QEMU headers Date: Sat, 17 Apr 2021 20:41:59 +0100 Message-Id: <20210417194205.17057-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210417194205.17057-1-peter.maydell@linaro.org> References: <20210417194205.17057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Paolo Bonzini glib-compat.h is sort of like a system header, and it needs to include system headers (glib.h) that may dislike being included under 'extern "C"'. Move it right after all system headers and before all other QEMU headers. Signed-off-by: Paolo Bonzini Reviewed-by: Daniel P. Berrangé Reviewed-by: Peter Maydell Acked-by: Paolo Bonzini Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210416135543.20382-2-peter.maydell@linaro.org [PMM: Added comment about why glib-compat.h is special] Signed-off-by: Peter Maydell --- include/qemu/osdep.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index ba15be9c569..ab84ecc7c1c 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -111,6 +111,13 @@ extern int daemon(int, int); #define WEXITSTATUS(x) (x) #endif +/* + * This is somewhat like a system header; it must be outside any extern "C" + * block because it includes system headers itself, including glib.h, + * which will not compile if inside an extern "C" block. + */ +#include "glib-compat.h" + #ifdef _WIN32 #include "sysemu/os-win32.h" #endif @@ -123,7 +130,6 @@ extern int daemon(int, int); #include #endif -#include "glib-compat.h" #include "qemu/typedefs.h" /* From patchwork Sat Apr 17 19:42:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1467534 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=ag6lQkLD; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FN3T01nY0z9vDc for ; Sun, 18 Apr 2021 05:45:08 +1000 (AEST) Received: from localhost ([::1]:41912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXqsM-00032T-6e for incoming@patchwork.ozlabs.org; Sat, 17 Apr 2021 15:45:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39352) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXqpY-0007sr-I8 for qemu-devel@nongnu.org; Sat, 17 Apr 2021 15:42:12 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:46010) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXqpW-0008Aw-L0 for qemu-devel@nongnu.org; Sat, 17 Apr 2021 15:42:12 -0400 Received: by mail-wm1-x32c.google.com with SMTP id n4-20020a05600c4f84b029013151278decso4735067wmq.4 for ; Sat, 17 Apr 2021 12:42:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IKvxSrsMQFA/bLEF4nXFniV33pIz3YuViqa+nryAra0=; b=ag6lQkLDrerb/Hc3CIUZwWZpIb8alVnstbCWlbxoM5vtcCA2lw5dD3QinOVEFB/sXz 3yLkJwmDN+t5giq6i1JnYt73uu3LYI+FHZLKxyGhkhJTZjnZk2bOB+UzdKn6dRV4XW/K HvTTQ/b+bdNeGs1qa9808t03Sv1bWss5HCYkn8YfTPZiduyId2Y5l92ElUm19dgIw+h7 Nj/o3AAdrk04fUQQjLBgdxll6kTazugBBmX/6jb4GWZT+opzSwbAL5u5EyuRtB01aJyS ifKinGu0KbUPOd3to7xIoaHDxjCK3ZCuaHXXtS2EjWEEpI25yn027VZp2WWlML+d0WOL H2UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IKvxSrsMQFA/bLEF4nXFniV33pIz3YuViqa+nryAra0=; b=Fh+Xv7eCaiuW5xLeQEezN05+3xPL6juEonyXo5D3bU9f5Qfz61pXoAkdPEHk6wQeNk Z+zaVjNE2c4ZW2VZUhHyG5ItF3ICr7Ts4roaBdMO0A/8zMnTvwLSIU6nHg0xBdMGKMR5 Xo9GWoUmAu/SZ+CWPBT6aefBBermCAA5dm2ACFfXfW32qGJeH53tE2yp1OcIRdpk92cQ vxD1jwz8BcY8DkwXi+RqbwjpUfSwAPtsaMqKwp3+jkz/l+v+AHBY2OWwLqcxkvJw7gsW sD0RvCp4V1ix+6dg8Wh/0Cy1dPzOM2OTCK/Ga7AMUIHX06Q4GYc2GTEx1QKb4LuwmV6Y 0iVw== X-Gm-Message-State: AOAM531qRnC2FD4B0LcMzs16qsUUJyWRQXrZmSdRLQd3tEGwAXcWCYQs IIEc95JEdLD47zeL93v7mjT7hEnbXTJoKlOS X-Google-Smtp-Source: ABdhPJx+l4om8v1aprnNmcPThZmxibLcNjpa6y/IcdaX1/bMOKNUkIcKvQaGcyygS4VmEt1HioQNiQ== X-Received: by 2002:a05:600c:4ecc:: with SMTP id g12mr13474777wmq.117.1618688529359; Sat, 17 Apr 2021 12:42:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c12sm17304374wro.6.2021.04.17.12.42.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Apr 2021 12:42:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/7] osdep: protect qemu/osdep.h with extern "C" Date: Sat, 17 Apr 2021 20:42:00 +0100 Message-Id: <20210417194205.17057-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210417194205.17057-1-peter.maydell@linaro.org> References: <20210417194205.17057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Paolo Bonzini System headers may include templates if compiled with a C++ compiler, which cause the compiler to complain if qemu/osdep.h is included within a C++ source file's 'extern "C"' block. Add an 'extern "C"' block directly to qemu/osdep.h, so that system headers can be kept out of it. There is a stray declaration early in qemu/osdep.h, which needs to be special cased. Add a definition in qemu/compiler.h to make it look nice. config-host.h, CONFIG_TARGET, exec/poison.h and qemu/compiler.h are included outside the 'extern "C"' block; that is not an issue because they consist entirely of preprocessor directives. This allows us to move the include of osdep.h in our two C++ source files outside the extern "C" block they were previously using for it, which in turn means that they compile successfully against newer versions of glib which insist that glib.h is *not* inside an extern "C" block. Signed-off-by: Paolo Bonzini Reviewed-by: Daniel P. Berrangé Acked-by: Paolo Bonzini Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210416135543.20382-3-peter.maydell@linaro.org [PMM: Moved disas/arm-a64.cc osdep.h include out of its extern "C" block; explained in commit message why we're doing this] Signed-off-by: Peter Maydell --- include/qemu/compiler.h | 6 ++++++ include/qemu/osdep.h | 10 +++++++++- disas/arm-a64.cc | 2 +- disas/nanomips.cpp | 2 +- 4 files changed, 17 insertions(+), 3 deletions(-) diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index cf28bb2bcd7..091c45248b0 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -11,6 +11,12 @@ #define QEMU_STATIC_ANALYSIS 1 #endif +#ifdef __cplusplus +#define QEMU_EXTERN_C extern "C" +#else +#define QEMU_EXTERN_C extern +#endif + #define QEMU_NORETURN __attribute__ ((__noreturn__)) #define QEMU_WARN_UNUSED_RESULT __attribute__((warn_unused_result)) diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index ab84ecc7c1c..6d8562eaf40 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -57,7 +57,7 @@ #define daemon qemu_fake_daemon_function #include #undef daemon -extern int daemon(int, int); +QEMU_EXTERN_C int daemon(int, int); #endif #ifdef _WIN32 @@ -118,6 +118,10 @@ extern int daemon(int, int); */ #include "glib-compat.h" +#ifdef __cplusplus +extern "C" { +#endif + #ifdef _WIN32 #include "sysemu/os-win32.h" #endif @@ -728,4 +732,8 @@ static inline int platform_does_not_support_system(const char *command) } #endif /* !HAVE_SYSTEM_FUNCTION */ +#ifdef __cplusplus +} +#endif + #endif diff --git a/disas/arm-a64.cc b/disas/arm-a64.cc index 9fa779e175e..27613d4b256 100644 --- a/disas/arm-a64.cc +++ b/disas/arm-a64.cc @@ -17,8 +17,8 @@ * along with this program. If not, see . */ -extern "C" { #include "qemu/osdep.h" +extern "C" { #include "disas/dis-asm.h" } diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp index 2b096552719..8ddef897f0d 100644 --- a/disas/nanomips.cpp +++ b/disas/nanomips.cpp @@ -27,8 +27,8 @@ * Reference Manual", Revision 01.01, April 27, 2018 */ -extern "C" { #include "qemu/osdep.h" +extern "C" { #include "disas/dis-asm.h" } From patchwork Sat Apr 17 19:42:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1467532 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=mDbxqx9J; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FN3QK0Xt1z9vDc for ; Sun, 18 Apr 2021 05:42:49 +1000 (AEST) Received: from localhost ([::1]:33754 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXqq7-0007xm-4C for incoming@patchwork.ozlabs.org; Sat, 17 Apr 2021 15:42:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39410) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXqpb-0007vV-L1 for qemu-devel@nongnu.org; Sat, 17 Apr 2021 15:42:15 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:46709) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXqpX-0008C1-Iy for qemu-devel@nongnu.org; Sat, 17 Apr 2021 15:42:15 -0400 Received: by mail-wr1-x42b.google.com with SMTP id c15so20997969wro.13 for ; Sat, 17 Apr 2021 12:42:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X+yX84qon75IWnfGBV9DoIC7IAiy08A30WrHnxDcNWA=; b=mDbxqx9JoIiNtPO0HHXqoQjuCUGAk4XWnDx81AURiK98JIvzmcGbjzojgLh/wndUGk T++17PQRxN90walHNLvZKA6EjtKTa/KtlXXRpnjPWdZtyZ89pQAWeZg7Z6j4RPFNaAlb //gp4dVr1/zj2SKj4mf+RbvB/Tvh+3x/mi5/VBPFOHAr4KZxBK1xryDBJWjrI8YljZ31 azBboIErl3ZBoAvLlsmZwNAyH5McXZFSgkz1MYOBth2A9UuJymEaGkyN5YNGHrpviyi/ KGGYMWw85rHzMswwoqJgRG/mcpR+pGx7BDQuaO9iuKfPHy5oYCTxCtZVr6gDvXhI5nrx YPhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X+yX84qon75IWnfGBV9DoIC7IAiy08A30WrHnxDcNWA=; b=sVEJeY/L8Y//VOeQZn7o7pYoaJkpgYzibtA0DeigcFhUX46guYXZYfypdbtVKn33fB TpQaf+dm/I9cR0rtYK7xsEU7Bcni0e/F/4GPswtGj6RXcj8v5ycOsNHRTceWcQQaLquF CWtuRVWGSrFr1WC53r4jKadrWjscByRdHICwEtUcrEq/9LEaqEO2a0XCwLeEWQQUqrNU NgXAS0ThdyYXnEzLuMzoO4TKCJO82jMdFYUven65frdTnU/FmE8y2sgF5R3Htqfi3yhc cfQkkMx2PE3ZBMjDU7q+XzxPcUMTKseq9uISaDrQFyKv0HSWVqAt50cN0eO/ubiL9MQc 7OyQ== X-Gm-Message-State: AOAM530XMEOk+Qdorpih+wQxOqrjyfCG0SYOaDFoKODwf7grk62tOIFC Y1MmaR/joCyzI/eImTHqXvt8khtn/ivnjoYG X-Google-Smtp-Source: ABdhPJwjrbc+5Dy0dnoaaNo0SfncUHuQC02KKga6dqmIbldFdoAFzRfFKLiYZdS/HZ+GF8Qkiu6n8w== X-Received: by 2002:a5d:4c88:: with SMTP id z8mr5692000wrs.154.1618688530097; Sat, 17 Apr 2021 12:42:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c12sm17304374wro.6.2021.04.17.12.42.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Apr 2021 12:42:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/7] include/qemu/osdep.h: Move system includes to top Date: Sat, 17 Apr 2021 20:42:01 +0100 Message-Id: <20210417194205.17057-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210417194205.17057-1-peter.maydell@linaro.org> References: <20210417194205.17057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Mostly osdep.h puts the system includes at the top of the file; but there are a couple of exceptions where we include a system header halfway through the file. Move these up to the top with the rest so that all the system headers we include are included before we include os-win32.h or os-posix.h. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel P. Berrangé Acked-by: Paolo Bonzini Reviewed-by: Richard Henderson Message-id: 20210416135543.20382-4-peter.maydell@linaro.org Message-id: 20210414184343.26235-1-peter.maydell@linaro.org --- include/qemu/osdep.h | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 6d8562eaf40..cb2a07e472e 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -104,6 +104,15 @@ QEMU_EXTERN_C int daemon(int, int); #include #include +#ifdef CONFIG_IOVEC +#include +#endif + +#if defined(__linux__) && defined(__sparc__) +/* The SPARC definition of QEMU_VMALLOC_ALIGN needs SHMLBA */ +#include +#endif + #ifndef _WIN32 #include #else @@ -111,6 +120,10 @@ QEMU_EXTERN_C int daemon(int, int); #define WEXITSTATUS(x) (x) #endif +#ifdef __APPLE__ +#include +#endif + /* * This is somewhat like a system header; it must be outside any extern "C" * block because it includes system headers itself, including glib.h, @@ -130,10 +143,6 @@ extern "C" { #include "sysemu/os-posix.h" #endif -#ifdef __APPLE__ -#include -#endif - #include "qemu/typedefs.h" /* @@ -469,7 +478,6 @@ void qemu_anon_ram_free(void *ptr, size_t size); /* Use 1 MiB (segment size) alignment so gmap can be used by KVM. */ # define QEMU_VMALLOC_ALIGN (256 * 4096) #elif defined(__linux__) && defined(__sparc__) -#include # define QEMU_VMALLOC_ALIGN MAX(qemu_real_host_page_size, SHMLBA) #else # define QEMU_VMALLOC_ALIGN qemu_real_host_page_size @@ -549,8 +557,6 @@ struct iovec { ssize_t readv(int fd, const struct iovec *iov, int iov_cnt); ssize_t writev(int fd, const struct iovec *iov, int iov_cnt); -#else -#include #endif #ifdef _WIN32 From patchwork Sat Apr 17 19:42:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1467531 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id c12sm17304374wro.6.2021.04.17.12.42.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Apr 2021 12:42:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/7] hw/arm/armsse: Give SSE-300 its own Property array Date: Sat, 17 Apr 2021 20:42:02 +0100 Message-Id: <20210417194205.17057-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210417194205.17057-1-peter.maydell@linaro.org> References: <20210417194205.17057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" SSE-300 currently shares the SSE-200 Property array. This is bad principally because the default values of the CPU0_FPU and CPU0_DSP properties disable the FPU and DSP on the CPU. That is correct for the SSE-200 but not the SSE-300. Give the SSE-300 its own Property array with the correct SSE-300 specific settings: * SSE-300 has only one CPU, so no CPU1* properties * SSE-300 CPU has FPU and DSP Buglink: https://bugs.launchpad.net/qemu/+bug/1923861 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210415182353.8173-1-peter.maydell@linaro.org --- hw/arm/armsse.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index e5aeb9e485f..170dea8632d 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -84,7 +84,7 @@ static Property iotkit_properties[] = { DEFINE_PROP_END_OF_LIST() }; -static Property armsse_properties[] = { +static Property sse200_properties[] = { DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), @@ -97,6 +97,17 @@ static Property armsse_properties[] = { DEFINE_PROP_END_OF_LIST() }; +static Property sse300_properties[] = { + DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), + DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), + DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), + DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), + DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), + DEFINE_PROP_END_OF_LIST() +}; + static const ARMSSEDeviceInfo iotkit_devices[] = { { .name = "timer0", @@ -519,7 +530,7 @@ static const ARMSSEInfo armsse_variants[] = { .has_cpuid = true, .has_cpu_pwrctrl = false, .has_sse_counter = false, - .props = armsse_properties, + .props = sse200_properties, .devinfo = sse200_devices, .irq_is_common = sse200_irq_is_common, }, @@ -537,7 +548,7 @@ static const ARMSSEInfo armsse_variants[] = { .has_cpuid = true, .has_cpu_pwrctrl = true, .has_sse_counter = true, - .props = armsse_properties, + .props = sse300_properties, .devinfo = sse300_devices, .irq_is_common = sse300_irq_is_common, }, From patchwork Sat Apr 17 19:42:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1467535 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id c12sm17304374wro.6.2021.04.17.12.42.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Apr 2021 12:42:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 5/7] hw/arm/armsse: Make SSE-300 use Cortex-M55 Date: Sat, 17 Apr 2021 20:42:03 +0100 Message-Id: <20210417194205.17057-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210417194205.17057-1-peter.maydell@linaro.org> References: <20210417194205.17057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The SSE-300 has a Cortex-M55 (which was the whole reason for us modelling it), but we forgot to actually update the code to let it have a different CPU type from the IoTKit and SSE-200. Add CPU type as a field for ARMSSEInfo instead of hardcoding it to always use a Cortex-M33. Buglink: https://bugs.launchpad.net/qemu/+bug/1923861 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210416104010.13228-1-peter.maydell@linaro.org --- hw/arm/armsse.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 170dea8632d..2e5d0679e7b 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -56,6 +56,7 @@ typedef struct ARMSSEDeviceInfo { struct ARMSSEInfo { const char *name; + const char *cpu_type; uint32_t sse_version; int sram_banks; int num_cpus; @@ -501,6 +502,7 @@ static const ARMSSEInfo armsse_variants[] = { { .name = TYPE_IOTKIT, .sse_version = ARMSSE_IOTKIT, + .cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"), .sram_banks = 1, .num_cpus = 1, .sys_version = 0x41743, @@ -519,6 +521,7 @@ static const ARMSSEInfo armsse_variants[] = { { .name = TYPE_SSE200, .sse_version = ARMSSE_SSE200, + .cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"), .sram_banks = 4, .num_cpus = 2, .sys_version = 0x22041743, @@ -537,6 +540,7 @@ static const ARMSSEInfo armsse_variants[] = { { .name = TYPE_SSE300, .sse_version = ARMSSE_SSE300, + .cpu_type = ARM_CPU_TYPE_NAME("cortex-m55"), .sram_banks = 2, .num_cpus = 1, .sys_version = 0x7e00043b, @@ -719,8 +723,7 @@ static void armsse_init(Object *obj) name = g_strdup_printf("armv7m%d", i); object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i], TYPE_ARMV7M); - qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", - ARM_CPU_TYPE_NAME("cortex-m33")); + qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", info->cpu_type); g_free(name); name = g_strdup_printf("arm-sse-cpu-container%d", i); memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); From patchwork Sat Apr 17 19:42:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1467533 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id c12sm17304374wro.6.2021.04.17.12.42.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Apr 2021 12:42:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 6/7] target/arm: drop CF_LAST_IO/dc->condjump check Date: Sat, 17 Apr 2021 20:42:04 +0100 Message-Id: <20210417194205.17057-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210417194205.17057-1-peter.maydell@linaro.org> References: <20210417194205.17057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée This is a left over erroneous check from the days front-ends handled io start/end themselves. Regardless just because IO could be performed on the last instruction doesn't obligate the front end to do so. This fixes an abort faced by the aspeed execute-in-place support which will necessarily trigger this state (even before the one-shot CF_LAST_IO fix). The test still seems to hang once it attempts to boot the Linux kernel but I suspect this is an unrelated issue with icount and the timer handling code. The original intention of the cpu_abort (added in commit 2e70f6efa8b9 when the icount stuff was first added) seems to have been to act as an assert() to catch an unhandled corner case where the generated code would be something like: conditional branch to condlabel if its cc failed implementation of the insn (a conditional branch or trap) code emitted by gen_io_end() condlabel: gen_goto_tb or equivalent thing to go to next insn At runtime the cc-failed case would skip over the code emitted by gen_io_end(), leaving the can_do_io flag incorrectly set. In commit ba3e7926691ed33 we switched to an implementation which always clears can_do_io at the start of the following TB instead of trying to clear it at the end of a TB that did IO. So the corner case that this cpu_abort() was trying to flag is no longer possible, because the gen_io_end() call has been deleted. We can therefore safely remove the no-longer-valid assertion. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20210416170207.12504-1-alex.bennee@linaro.org Cc: Cédric Le Goater Signed-off-by: Peter Maydell --- target/arm/translate.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 62b1c2081b6..7103da2d7ab 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9199,11 +9199,6 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); - if (tb_cflags(dc->base.tb) & CF_LAST_IO && dc->condjmp) { - /* FIXME: This can theoretically happen with self-modifying code. */ - cpu_abort(cpu, "IO on conditional branch instruction"); - } - /* At this stage dc->condjmp will only be set when the skipped instruction was a conditional branch or trap, and the PC has already been written. */ From patchwork Sat Apr 17 19:42:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1467537 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=xDM3I2Pj; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FN3WP2Dhbz9vF3 for ; Sun, 18 Apr 2021 05:47:13 +1000 (AEST) Received: from localhost ([::1]:48234 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXquN-0005iX-BN for incoming@patchwork.ozlabs.org; Sat, 17 Apr 2021 15:47:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39412) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXqpd-0007yO-6v for qemu-devel@nongnu.org; Sat, 17 Apr 2021 15:42:17 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:34777) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXqpa-0008DQ-5X for qemu-devel@nongnu.org; Sat, 17 Apr 2021 15:42:16 -0400 Received: by mail-wr1-x433.google.com with SMTP id r7so17942269wrm.1 for ; Sat, 17 Apr 2021 12:42:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uRd4G6zXJmrKRNM9MFZAOKSesHEb4XI8oeHJ2++RWXE=; b=xDM3I2PjjUlwm8ktPC4sOfMYbZleTjX5OVLylB55cWvt/x5b3Zi6QTH9OKm5NK0XcW 71/lnD/bK3bZdeFUNPXChPqTVd/UW8jkl+9InX5BLrLy7/VDK634tBUc39gYp5X0GtId d0PrBI/9MiGkWXP2peoQNEW2Q6xy85+vYhhkDwIH1pfu1aMonzotb3FBduY0iIyUG1qK lX3oLETVMpvaK/5hRfdzGWo+6z+Woh5wJQr4EZXk/ugl7jlNgPHvdrhKtL8fhBd+pkUy fN9TR0aczU74UevQDMHaZ+q2iion8fnEZi0M1WL953aVFydoZ5KtmydzFS6wTRwPuL3l xzqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uRd4G6zXJmrKRNM9MFZAOKSesHEb4XI8oeHJ2++RWXE=; b=mlmB6oGAan3QtDhEyTbRIuuz31yje1fPi3lGQmwI7KELjz4Q7h7cdmosZN2+2+UaBe Yv4rteQlS1zoPVmJDn2kC5j/bgtdIS9wPsE0GkG2lhBeVsyxPAuvAKsqW4s45ObymEBn xkB3QDe90/iaIarbEcR0A9GdsWkf2yGCAJ14Np75RWDMiuLDmTf586AS1pUnhptMQraA wiKofm8LylfuxdPJnbp4zeho++8rEJQw6bb0IhKX+GwaOGQRn1J2wuOAdbZ6u2ycaoAT UL6nyxXESCpftvVtKW8NHN/OmsvMxY09VNi1/4EX15MP7rCcejlpg5rLjiHkoAdPe0sv 0d+g== X-Gm-Message-State: AOAM532ZiLNOmE2kJAFOFDAnoD3rpgX+/NWdmolJyWmLVm3SaSzhP2kW x/Qy0K7rWjEpl6jX28CSSRrq37X45MlAJ/EY X-Google-Smtp-Source: ABdhPJwqsJUKYSxAvMltak/Rh9db+hi/IxKNdLDKtOx84CrFZKKndJaqeAAzCNPeHbBuYnzQIUzbfg== X-Received: by 2002:a5d:55d2:: with SMTP id i18mr5416745wrw.280.1618688532870; Sat, 17 Apr 2021 12:42:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c12sm17304374wro.6.2021.04.17.12.42.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Apr 2021 12:42:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 7/7] accel/tcg: avoid re-translating one-shot instructions Date: Sat, 17 Apr 2021 20:42:05 +0100 Message-Id: <20210417194205.17057-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210417194205.17057-1-peter.maydell@linaro.org> References: <20210417194205.17057-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée By definition a single instruction is capable of being an IO instruction. This avoids a problem of triggering a cpu_io_recompile on a non-recorded translation which then fails because it expects tcg_tb_lookup() to succeed unconditionally. The normal use case requires a TB to be able to resolve machine state. The other users of tcg_tb_lookup() are able to tolerate a missing TB if the machine state has been resolved by other means - which in the single-shot case is always true because machine state is synced at the start of a block. Reported-by: Peter Maydell Signed-off-by: Alex Bennée Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210415162454.22056-1-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- accel/tcg/translate-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index ba6ab09790e..b12d0898d0a 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1863,7 +1863,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, if (phys_pc == -1) { /* Generate a one-shot TB with 1 insn in it */ - cflags = (cflags & ~CF_COUNT_MASK) | 1; + cflags = (cflags & ~CF_COUNT_MASK) | CF_LAST_IO | 1; } max_insns = cflags & CF_COUNT_MASK;