From patchwork Wed Apr 14 13:58:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1466275 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=h6GO/yGL; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FL3xB3CDHz9sWK for ; Wed, 14 Apr 2021 23:59:09 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B394C3947C02; Wed, 14 Apr 2021 13:59:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B394C3947C02 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1618408746; bh=Rt5Jz2v07Hzw3t/e7BJr30LC/Ok700gauIklQjQwRso=; h=References:In-Reply-To:Date:Subject:To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=h6GO/yGLt8ecXjTJGcHp4wPx+CKS/tj8xnV6OFurI+PSiExqvxmBJEDQxW630d2eB jgs4Man8VDweApgnaiKfws2Y/AnVTBq7QGUp2/JvLgGi1b0HKY2Ml6Y75OOkofnrnT WGoMbjcp7ZOL/l4FsSVZscVTFrKaCEv30k6XUd8k= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ot1-x32a.google.com (mail-ot1-x32a.google.com [IPv6:2607:f8b0:4864:20::32a]) by sourceware.org (Postfix) with ESMTPS id 4EAFC3857036 for ; Wed, 14 Apr 2021 13:59:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 4EAFC3857036 Received: by mail-ot1-x32a.google.com with SMTP id k14-20020a9d7dce0000b02901b866632f29so19408209otn.1 for ; Wed, 14 Apr 2021 06:59:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Rt5Jz2v07Hzw3t/e7BJr30LC/Ok700gauIklQjQwRso=; b=eSL2TrDD8aZZS8o3ePcpzgjPxkWMUBsdoqq49cr7jqoaIP26k9CrKrYM1pKpp1TfP4 PxYIcNRjAS6uf6wezPd2Lt5ZiMDzY/5mnHwuG5DxbqjIC2YGJ6kJYQ3CD4JBrrqbv2+8 HKK8NfxYiqBh9WyMuY0hn6RTiy3uchelpkNTSLf870z5kvrmD4Tz2jTSg/sLLIDABEsD 7bg+Qc/0jiDCiV20/LvlYmq5OK1Z3tXF/LjE94hp0ikHT/Ij/9Lb8FRGqcl5ZClsIy4S 2W8lOT6tLOdGaqLd/9T8ccfT8nbZUIPVpxHoPvwe62A9NG78OQtIj3YShaj8joFnvmrm lkHA== X-Gm-Message-State: AOAM530ZNIz1ytLXT8QIrifh1y+KTcakR7BsiqIPASsBvbmh7OJwHkwU Ho9FG7S3jv7Cadw+Pr/DJuT0/nLhV9UhibvfrZ4= X-Google-Smtp-Source: ABdhPJx44q1s+aAvUPmurc6Z3+NjbCZT9dnVhBM17vvihbbWFNnE9puVcaveEIqzSFaPA+uRiznoi30mz26QG/z5Wls= X-Received: by 2002:a05:6830:1515:: with SMTP id k21mr32606657otp.269.1618408740611; Wed, 14 Apr 2021 06:59:00 -0700 (PDT) MIME-Version: 1.0 References: <20210410145247.209214-1-hjl.tools@gmail.com> In-Reply-To: Date: Wed, 14 Apr 2021 06:58:23 -0700 Message-ID: Subject: [GCC 12] [PATCH v3] Add general_regs_only function attribute To: Martin Sebor X-Spam-Status: No, score=-3035.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: GCC Patches Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" On Tue, Apr 13, 2021 at 8:51 AM Martin Sebor wrote: > > On 4/12/21 7:03 PM, H.J. Lu wrote: > > On Mon, Apr 12, 2021 at 4:55 PM Martin Sebor wrote: > >> > >> On 4/12/21 3:53 PM, H.J. Lu via Gcc-patches wrote: > >>> On Mon, Apr 12, 2021 at 2:21 AM Richard Biener > >>> wrote: > >>>> > >>>> On Sat, Apr 10, 2021 at 5:11 PM H.J. Lu via Gcc-patches > >>>> wrote: > >>>>> > >>>>> Add inline_ignore_target function attribute to inform the compiler that > >>>>> target specific option mismatch on functions with the always_inline > >>>>> attribute may be ignored. On x86 targets, this attribute can be used on > >>>>> integer functions to ignore target non-integer option mismatch. > >>>> > >>>> I'm not sure I like such attribute but please adjust default_target_can_inline_p > >>>> accordingly (only few targets override this hook). > >>>> > >>>> Richard. > >>>> > >>> > >>> Like this? > >>> > >>> Thanks. > >> > >> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi > >> index 1ddafb3ff2c..44588566f2d 100644 > >> --- a/gcc/doc/extend.texi > >> +++ b/gcc/doc/extend.texi > >> @@ -3187,6 +3187,14 @@ int S::interface (int) __attribute__ ((ifunc > >> ("_ZN1S8resolverEv"))); > >> Indirect functions cannot be weak. Binutils version 2.20.1 or higher > >> and GNU C Library version 2.11.1 are required to use this feature. > >> > >> +@item inline_ignore_target > >> +@cindex @code{inline_ignore_target} function attribute > >> +The @code{inline_ignore_target} attribute on functions is used to > >> +inform the compiler that target specific option mismatch on functions > >> +with the @code{always_inline} attribute may be ignored. On x86 targets, > >> +this attribute can be used on integer functions to ignore target > >> +non-integer option mismatch. > >> + > >> @item interrupt > >> @itemx interrupt_handler > >> Many GCC back ends support attributes to indicate that a function is > >> > >> I'm having a hard time understanding the description above (or > >> the attribute's name for that matter). > > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99744 > > > > has a testcase. > > Thanks. My overall point is that GCC users should be able to answer > these questions from reading the documentation of the attribute in > the manual. > > > > >> The inline_ignore_target function attribute informs the compiler > >> that "target specific option mismatch on functions with the > >> @code{always_inline} attribute" may be ignored. > >> > >> What does "target specific option mismatch" mean? Is it a mismatch > > > > This refers to the message from GCC: > > > > /usr/gcc-11.0.0-x32/lib/gcc/x86_64-pc-linux-gnu/11.0.0/include/ia32intrin.h:112:1: > > error: inlining failed in call to ‘always_inline’ ‘__rdtsc’: target > > specific option mismatch > > 112 | __rdtsc (void) > > | ^~~~~~~ > > But what exactly does the target-specific option refer to, and what > does it fail to match? Presumably, it refers to the option in > the attribute on the function declaration in the PR: > > __attribute__ ((target("general-regs-only"))) > > and the inability to use the rdtsc instruction with a GPR. > > But unless the error either mentions the -mgeneral-regs-only option > by name or is followed by a note that points to the option in > the function declaration, the words "target specific option" alone > aren't enough to understand what the error means, and the text in > the manual doesn't help. > > I would suggest to improve the message and the manual. > > > > >> between target-specific optimization options added to a function by > >> attribute optimize vs other target-specific optimization options of > >> the function callers (e.g., added to them by another instance of > >> attribue optimize, or by #pragma GCC optimize), into which a function > >> with the attribute may be inlined, and where the conflict between > >> the two sets of options needs to be reconciled? And if so, should > > > > It is added to support integer functions with always_inline attribute. > > Currently x86 integer functions with always_inline attribute fail to > > compile when caller has general-regs-only target attribute and > > SSE is enabled by default. > > Thanks. I would suggest to also explain this in the manual. > > > > >> it be provided as a generic attribute for all targets? > > I'm still wondering if this should be a generic attribute. Besides > x86, I see -mgeneral-regs-only also provided by ARM and Aarch64, so > I would expect the attribute to be useful to those targets as well, > and to all other targets that add the option or one like it in > the future. I believe it's better for portability to add a generic > attribute even if it's not universally supported, than a target- > specific one. > > > > > Different targets can have different sets of conflict target specific > > options. > > > >> Also, what's "integer functions" supposed to mean? Functions that > >> return integers? > > > > An integer function can be compiled with -mgeneral-regs-only. > > I don't think that answers my question. It sounds like a property > of something you call an /integer function/. My question is: what > is [the definition of] an integer function? In other words, how can > one tell whether or not an arbitrary function is an integer function? > > The manual should either define the term /integer function/ or it > should describe what it means so that readers won't have to ask this > question. If the definition is "an integer function is one that can > be compiled without error with -mgeneral-regs-only" then then that's > what the manual should say (although I'd hope for more detail and > clarity than that.) > > > > >> This new attribute seems sufficiently specialized that I think > >> the description ought to be expanded to make it clearer what it's > >> for, why it's needed, and when and how to use it. Adding an example > >> or two might help, as would using more precise terminology. > >> > >> Separately, seeing no tests for it in the patch, I wonder how > > > > There are 2 existing tests: gcc.target/i386/pr99744-1.c and > > gcc.target/i386/pr99744-2.c. If we want to go with this approach, > > I will add inline_ignore_target to all x86 integer intrinsics with > > tests. > > I don't have much of an opinion on the approach itself (adding > an attribute to avoid the error). I'm trying to help improve > the usability of the feature to prevent gaps (underspecified > aspects) in new attributes that are then hard to sort out after > the attribute has been introduced. This affects GCC users as > well as developers and users of GCC-compatible compilers, and > eventually also GCC devs as bug reports against GCC are open by > users of other compilers that, in the absence of an unambiguous > interpretetation of both the documentation and the behavior > provide subtly different semantics than GCC. > > > > >> the new attribute interacts (or should interact) with other > >> attributes or other kinds of functions than the ones it's tested > >> with. For example, what happens when the attribute is added to > >> a function that's not declared inline, or that's declared with > >> the noinline attribute. > >> > > > > This attribute should be used together with always_inline attribute. > > I would suggest to both document this constraint and issue an error > when it's not used this way, along with a test case to verify it. > > Martin Here is a different approach with general_regs_only function attribute to let GCC know that functions use only general purpose registers. Backends can use this information to make inlining decisions. From 4e2d3e8c28c22f9aca3ad9e55fb746c7e7fb5162 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Sat, 10 Apr 2021 07:45:35 -0700 Subject: [PATCH v3] Add general_regs_only function attribute Add general_regs_only function attribute to inform the compiler that functions use only general purpose registers. When inlining such functions, non-GPR compiler options can be ignored. gcc/c-family/ PR target/99744 * c-family/c-attribs.c (c_common_attribute_table): Add general_regs_only. gcc/ PR target/99744 * common/config/i386/i386-common.c (OPTION_MASK_*) to ... * common/config/i386/i386-common.h: Here. New file. * config/i386/i386.c (ix86_can_inline_p): Ignore target non-integer option mismatch if callee has general_regs_only attribute. * config/i386/i386.h: Include common/config/i386/i386-common.h. * config/i386/ia32intrin.h (__rdtsc): Use always_inline function with general_regs_only attribute. (__rdtscp): Likewise. * config/i386/serializeintrin.h (_serialize): Likewise. * doc/extend.texi: Document general_regs_only function attribute. gcc/testsuite/ PR target/99744 * gcc.target/i386/pr99744-3.c: New test. --- gcc/c-family/c-attribs.c | 2 + gcc/common/config/i386/i386-common.c | 297 -------------------- gcc/common/config/i386/i386-common.h | 315 ++++++++++++++++++++++ gcc/config/i386/i386.c | 29 +- gcc/config/i386/i386.h | 1 + gcc/config/i386/ia32intrin.h | 16 +- gcc/config/i386/serializeintrin.h | 8 +- gcc/doc/extend.texi | 5 + gcc/testsuite/gcc.target/i386/pr99744-3.c | 13 + 9 files changed, 381 insertions(+), 305 deletions(-) create mode 100644 gcc/common/config/i386/i386-common.h create mode 100644 gcc/testsuite/gcc.target/i386/pr99744-3.c diff --git a/gcc/c-family/c-attribs.c b/gcc/c-family/c-attribs.c index c1f652d1dc9..1ca2d97a253 100644 --- a/gcc/c-family/c-attribs.c +++ b/gcc/c-family/c-attribs.c @@ -323,6 +323,8 @@ const struct attribute_spec c_common_attribute_table[] = attr_inline_exclusions }, { "artificial", 0, 0, true, false, false, false, handle_artificial_attribute, NULL }, + { "general_regs_only", 0, 0, true, false, false, false, + handle_artificial_attribute, NULL }, { "flatten", 0, 0, true, false, false, false, handle_flatten_attribute, NULL }, { "used", 0, 0, true, false, false, false, diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index 1e6c1590ac4..37ff47bd676 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -29,303 +29,6 @@ along with GCC; see the file COPYING3. If not see #include "opts.h" #include "flags.h" -/* Define a set of ISAs which are available when a given ISA is - enabled. MMX and SSE ISAs are handled separately. */ - -#define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX -#define OPTION_MASK_ISA_3DNOW_SET \ - (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET) -#define OPTION_MASK_ISA_3DNOW_A_SET \ - (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET) - -#define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE -#define OPTION_MASK_ISA_SSE2_SET \ - (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET) -#define OPTION_MASK_ISA_SSE3_SET \ - (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET) -#define OPTION_MASK_ISA_SSSE3_SET \ - (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET) -#define OPTION_MASK_ISA_SSE4_1_SET \ - (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET) -#define OPTION_MASK_ISA_SSE4_2_SET \ - (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET) -#define OPTION_MASK_ISA_AVX_SET \ - (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \ - | OPTION_MASK_ISA_XSAVE_SET) -#define OPTION_MASK_ISA_FMA_SET \ - (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET) -#define OPTION_MASK_ISA_AVX2_SET \ - (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET) -#define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR -#define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE -#define OPTION_MASK_ISA_XSAVEOPT_SET \ - (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET) -#define OPTION_MASK_ISA_AVX512F_SET \ - (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET) -#define OPTION_MASK_ISA_AVX512CD_SET \ - (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512PF_SET \ - (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512ER_SET \ - (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512DQ_SET \ - (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512BW_SET \ - (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512VL_SET \ - (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512IFMA_SET \ - (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512VBMI_SET \ - (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET) -#define OPTION_MASK_ISA2_AVX5124FMAPS_SET OPTION_MASK_ISA2_AVX5124FMAPS -#define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW -#define OPTION_MASK_ISA_AVX512VBMI2_SET \ - (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512VNNI_SET \ - (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI -#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \ - (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512BITALG_SET \ - (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16 -#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM -#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW -#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED -#define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX -#define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1 -#define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT -#define OPTION_MASK_ISA_XSAVES_SET \ - (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET) -#define OPTION_MASK_ISA_XSAVEC_SET \ - (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET) -#define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB -#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT -#define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE -#define OPTION_MASK_ISA2_AMX_INT8_SET OPTION_MASK_ISA2_AMX_INT8 -#define OPTION_MASK_ISA2_AMX_BF16_SET OPTION_MASK_ISA2_AMX_BF16 - -/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same - as -msse4.2. */ -#define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET - -#define OPTION_MASK_ISA_SSE4A_SET \ - (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET) -#define OPTION_MASK_ISA_FMA4_SET \ - (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \ - | OPTION_MASK_ISA_AVX_SET) -#define OPTION_MASK_ISA_XOP_SET \ - (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET) -#define OPTION_MASK_ISA_LWP_SET \ - OPTION_MASK_ISA_LWP - -/* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */ -#define OPTION_MASK_ISA_AES_SET \ - (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET) -#define OPTION_MASK_ISA_SHA_SET \ - (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET) -#define OPTION_MASK_ISA_PCLMUL_SET \ - (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET) - -#define OPTION_MASK_ISA_ABM_SET \ - (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT) - -#define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG -#define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD -#define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX -#define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI -#define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2 -#define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT -#define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM -#define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT -#define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16 -#define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF -#define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE -#define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32 - -#define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE -#define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND -#define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE -#define OPTION_MASK_ISA_F16C_SET \ - (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET) -#define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX -#define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO -#define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU -#define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID -#define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI -#define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK -#define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES -#define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ -#define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI -#define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B -#define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG -#define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE -#define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD -#define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE -#define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK -#define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR -#define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET -#define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL -#define OPTION_MASK_ISA2_WIDEKL_SET \ - (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET) - -/* Define a set of ISAs which aren't available when a given ISA is - disabled. MMX and SSE ISAs are handled separately. */ - -#define OPTION_MASK_ISA_MMX_UNSET \ - (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET) -#define OPTION_MASK_ISA_3DNOW_UNSET \ - (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET) -#define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A - -#define OPTION_MASK_ISA_SSE_UNSET \ - (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET) -#define OPTION_MASK_ISA_SSE2_UNSET \ - (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET) -#define OPTION_MASK_ISA_SSE3_UNSET \ - (OPTION_MASK_ISA_SSE3 \ - | OPTION_MASK_ISA_SSSE3_UNSET \ - | OPTION_MASK_ISA_SSE4A_UNSET ) -#define OPTION_MASK_ISA_SSSE3_UNSET \ - (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET) -#define OPTION_MASK_ISA_SSE4_1_UNSET \ - (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET) -#define OPTION_MASK_ISA_SSE4_2_UNSET \ - (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET ) -#define OPTION_MASK_ISA_AVX_UNSET \ - (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \ - | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \ - | OPTION_MASK_ISA_AVX2_UNSET ) -#define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA -#define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR -#define OPTION_MASK_ISA_XSAVE_UNSET \ - (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \ - | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \ - | OPTION_MASK_ISA_AVX_UNSET) -#define OPTION_MASK_ISA2_XSAVE_UNSET OPTION_MASK_ISA2_AMX_TILE_UNSET -#define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT -#define OPTION_MASK_ISA_AVX2_UNSET \ - (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET) -#define OPTION_MASK_ISA2_AVX2_UNSET \ - (OPTION_MASK_ISA2_AVXVNNI_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET) -#define OPTION_MASK_ISA_AVX512F_UNSET \ - (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \ - | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \ - | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \ - | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \ - | OPTION_MASK_ISA_AVX512VBMI2_UNSET \ - | OPTION_MASK_ISA_AVX512VNNI_UNSET \ - | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \ - | OPTION_MASK_ISA_AVX512BITALG_UNSET) -#define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD -#define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF -#define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER -#define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ -#define OPTION_MASK_ISA_AVX512BW_UNSET \ - (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET) -#define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL -#define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA -#define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI -#define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS -#define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW -#define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2 -#define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI -#define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI -#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ -#define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG -#define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16 -#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM -#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW -#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED -#define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX -#define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1 -#define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT -#define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC -#define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES -#define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB -#define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX -#define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO -#define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU -#define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID -#define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI -#define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK -#define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES -#define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ -#define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI -#define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B -#define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG -#define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE -#define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD -#define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE -#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT -#define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK -#define OPTION_MASK_ISA2_AMX_TILE_UNSET OPTION_MASK_ISA2_AMX_TILE -#define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8 -#define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16 -#define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR -#define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET -#define OPTION_MASK_ISA2_KL_UNSET \ - (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET) -#define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL - -/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same - as -mno-sse4.1. */ -#define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET - -#define OPTION_MASK_ISA_SSE4A_UNSET \ - (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET) - -#define OPTION_MASK_ISA_FMA4_UNSET \ - (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET) -#define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP -#define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP - -#define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES -#define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA -#define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL -#define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM -#define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG -#define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD -#define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX -#define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI -#define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2 -#define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT -#define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM -#define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT -#define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16 -#define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF -#define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE -#define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32 - -#define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE -#define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND -#define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE -#define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C - -#define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \ - (OPTION_MASK_ISA_MMX_UNSET \ - | OPTION_MASK_ISA_SSE_UNSET) - -#define OPTION_MASK_ISA2_AVX512F_UNSET \ - (OPTION_MASK_ISA2_AVX512BF16_UNSET \ - | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \ - | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \ - | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET) -#define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ - (OPTION_MASK_ISA2_AVX512F_UNSET) -#define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET -#define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET -#define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET -#define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET -#define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET -#define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET -#define OPTION_MASK_ISA2_SSE2_UNSET \ - (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET) -#define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET - -#define OPTION_MASK_ISA2_AVX512BW_UNSET OPTION_MASK_ISA2_AVX512BF16_UNSET - /* Set 1 << value as value of -malign-FLAG option. */ static void diff --git a/gcc/common/config/i386/i386-common.h b/gcc/common/config/i386/i386-common.h new file mode 100644 index 00000000000..4a7fd290bcf --- /dev/null +++ b/gcc/common/config/i386/i386-common.h @@ -0,0 +1,315 @@ +/* IA-32 common macros. + Copyright (C) 2021 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +/* Define a set of ISAs which are available when a given ISA is + enabled. MMX and SSE ISAs are handled separately. */ + +#define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX +#define OPTION_MASK_ISA_3DNOW_SET \ + (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET) +#define OPTION_MASK_ISA_3DNOW_A_SET \ + (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET) + +#define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE +#define OPTION_MASK_ISA_SSE2_SET \ + (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET) +#define OPTION_MASK_ISA_SSE3_SET \ + (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET) +#define OPTION_MASK_ISA_SSSE3_SET \ + (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET) +#define OPTION_MASK_ISA_SSE4_1_SET \ + (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET) +#define OPTION_MASK_ISA_SSE4_2_SET \ + (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET) +#define OPTION_MASK_ISA_AVX_SET \ + (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \ + | OPTION_MASK_ISA_XSAVE_SET) +#define OPTION_MASK_ISA_FMA_SET \ + (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET) +#define OPTION_MASK_ISA_AVX2_SET \ + (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET) +#define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR +#define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE +#define OPTION_MASK_ISA_XSAVEOPT_SET \ + (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET) +#define OPTION_MASK_ISA_AVX512F_SET \ + (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET) +#define OPTION_MASK_ISA_AVX512CD_SET \ + (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512PF_SET \ + (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512ER_SET \ + (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512DQ_SET \ + (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512BW_SET \ + (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512VL_SET \ + (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512IFMA_SET \ + (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512VBMI_SET \ + (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET) +#define OPTION_MASK_ISA2_AVX5124FMAPS_SET OPTION_MASK_ISA2_AVX5124FMAPS +#define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW +#define OPTION_MASK_ISA_AVX512VBMI2_SET \ + (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512VNNI_SET \ + (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI +#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \ + (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512BITALG_SET \ + (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16 +#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM +#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW +#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED +#define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX +#define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1 +#define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT +#define OPTION_MASK_ISA_XSAVES_SET \ + (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET) +#define OPTION_MASK_ISA_XSAVEC_SET \ + (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET) +#define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB +#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT +#define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE +#define OPTION_MASK_ISA2_AMX_INT8_SET OPTION_MASK_ISA2_AMX_INT8 +#define OPTION_MASK_ISA2_AMX_BF16_SET OPTION_MASK_ISA2_AMX_BF16 + +/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same + as -msse4.2. */ +#define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET + +#define OPTION_MASK_ISA_SSE4A_SET \ + (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET) +#define OPTION_MASK_ISA_FMA4_SET \ + (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \ + | OPTION_MASK_ISA_AVX_SET) +#define OPTION_MASK_ISA_XOP_SET \ + (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET) +#define OPTION_MASK_ISA_LWP_SET \ + OPTION_MASK_ISA_LWP + +/* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */ +#define OPTION_MASK_ISA_AES_SET \ + (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET) +#define OPTION_MASK_ISA_SHA_SET \ + (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET) +#define OPTION_MASK_ISA_PCLMUL_SET \ + (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET) + +#define OPTION_MASK_ISA_ABM_SET \ + (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT) + +#define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG +#define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD +#define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX +#define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI +#define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2 +#define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT +#define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM +#define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT +#define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16 +#define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF +#define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE +#define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32 + +#define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE +#define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND +#define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE +#define OPTION_MASK_ISA_F16C_SET \ + (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET) +#define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX +#define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO +#define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU +#define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID +#define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI +#define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK +#define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES +#define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ +#define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI +#define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B +#define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG +#define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE +#define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD +#define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE +#define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK +#define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR +#define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET +#define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL +#define OPTION_MASK_ISA2_WIDEKL_SET \ + (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET) + +/* Define a set of ISAs which aren't available when a given ISA is + disabled. MMX and SSE ISAs are handled separately. */ + +#define OPTION_MASK_ISA_MMX_UNSET \ + (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET) +#define OPTION_MASK_ISA_3DNOW_UNSET \ + (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET) +#define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A + +#define OPTION_MASK_ISA_SSE_UNSET \ + (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET) +#define OPTION_MASK_ISA_SSE2_UNSET \ + (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET) +#define OPTION_MASK_ISA_SSE3_UNSET \ + (OPTION_MASK_ISA_SSE3 \ + | OPTION_MASK_ISA_SSSE3_UNSET \ + | OPTION_MASK_ISA_SSE4A_UNSET ) +#define OPTION_MASK_ISA_SSSE3_UNSET \ + (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET) +#define OPTION_MASK_ISA_SSE4_1_UNSET \ + (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET) +#define OPTION_MASK_ISA_SSE4_2_UNSET \ + (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET ) +#define OPTION_MASK_ISA_AVX_UNSET \ + (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \ + | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \ + | OPTION_MASK_ISA_AVX2_UNSET ) +#define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA +#define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR +#define OPTION_MASK_ISA_XSAVE_UNSET \ + (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \ + | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \ + | OPTION_MASK_ISA_AVX_UNSET) +#define OPTION_MASK_ISA2_XSAVE_UNSET OPTION_MASK_ISA2_AMX_TILE_UNSET +#define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT +#define OPTION_MASK_ISA_AVX2_UNSET \ + (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET) +#define OPTION_MASK_ISA2_AVX2_UNSET \ + (OPTION_MASK_ISA2_AVXVNNI_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET) +#define OPTION_MASK_ISA_AVX512F_UNSET \ + (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \ + | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \ + | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \ + | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \ + | OPTION_MASK_ISA_AVX512VBMI2_UNSET \ + | OPTION_MASK_ISA_AVX512VNNI_UNSET \ + | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \ + | OPTION_MASK_ISA_AVX512BITALG_UNSET) +#define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD +#define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF +#define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER +#define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ +#define OPTION_MASK_ISA_AVX512BW_UNSET \ + (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET) +#define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL +#define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA +#define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI +#define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS +#define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW +#define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2 +#define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI +#define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI +#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ +#define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG +#define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16 +#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM +#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW +#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED +#define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX +#define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1 +#define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT +#define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC +#define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES +#define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB +#define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX +#define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO +#define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU +#define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID +#define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI +#define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK +#define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES +#define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ +#define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI +#define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B +#define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG +#define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE +#define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD +#define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE +#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT +#define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK +#define OPTION_MASK_ISA2_AMX_TILE_UNSET OPTION_MASK_ISA2_AMX_TILE +#define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8 +#define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16 +#define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR +#define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET +#define OPTION_MASK_ISA2_KL_UNSET \ + (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET) +#define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL + +/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same + as -mno-sse4.1. */ +#define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET + +#define OPTION_MASK_ISA_SSE4A_UNSET \ + (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET) + +#define OPTION_MASK_ISA_FMA4_UNSET \ + (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET) +#define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP +#define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP + +#define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES +#define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA +#define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL +#define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM +#define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG +#define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD +#define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX +#define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI +#define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2 +#define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT +#define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM +#define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT +#define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16 +#define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF +#define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE +#define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32 + +#define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE +#define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND +#define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE +#define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C + +#define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \ + (OPTION_MASK_ISA_MMX_UNSET \ + | OPTION_MASK_ISA_SSE_UNSET) + +#define OPTION_MASK_ISA2_AVX512F_UNSET \ + (OPTION_MASK_ISA2_AVX512BF16_UNSET \ + | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \ + | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \ + | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET) +#define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ + (OPTION_MASK_ISA2_AVX512F_UNSET) +#define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET +#define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET +#define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET +#define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET +#define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET +#define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET +#define OPTION_MASK_ISA2_SSE2_UNSET \ + (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET) +#define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET + +#define OPTION_MASK_ISA2_AVX512BW_UNSET OPTION_MASK_ISA2_AVX512BF16_UNSET diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 7c41302c75b..201a001e95a 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -553,7 +553,7 @@ ix86_can_inline_p (tree caller, tree callee) /* Changes of those flags can be tolerated for always inlines. Lets hope user knows what he is doing. */ - const unsigned HOST_WIDE_INT always_inline_safe_mask + unsigned HOST_WIDE_INT always_inline_safe_mask = (MASK_USE_8BIT_IDIV | MASK_ACCUMULATE_OUTGOING_ARGS | MASK_NO_ALIGN_STRINGOPS | MASK_AVX256_SPLIT_UNALIGNED_LOAD | MASK_AVX256_SPLIT_UNALIGNED_STORE | MASK_CLD @@ -579,13 +579,32 @@ ix86_can_inline_p (tree caller, tree callee) DECL_ATTRIBUTES (callee))); cgraph_node *callee_node = cgraph_node::get (callee); + + HOST_WIDE_INT callee_integer_isa_flags + = callee_opts->x_ix86_isa_flags; + HOST_WIDE_INT callee_integer_isa_flags2 + = callee_opts->x_ix86_isa_flags2; + + if (lookup_attribute ("general_regs_only", + DECL_ATTRIBUTES (callee))) + { + /* For general purpose register only function, callee's + integer ISA options should be a subset of the caller's + integer ISA options. */ + always_inline_safe_mask |= MASK_80387; + callee_integer_isa_flags + &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET; + callee_integer_isa_flags2 + &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET; + } + /* Callee's isa options should be a subset of the caller's, i.e. a SSE4 function can inline a SSE2 function but a SSE2 function can't inline a SSE4 function. */ - if (((caller_opts->x_ix86_isa_flags & callee_opts->x_ix86_isa_flags) - != callee_opts->x_ix86_isa_flags) - || ((caller_opts->x_ix86_isa_flags2 & callee_opts->x_ix86_isa_flags2) - != callee_opts->x_ix86_isa_flags2)) + if (((caller_opts->x_ix86_isa_flags & callee_integer_isa_flags) + != callee_integer_isa_flags) + || ((caller_opts->x_ix86_isa_flags2 & callee_integer_isa_flags2) + != callee_integer_isa_flags2)) ret = false; /* See if we have the same non-isa options. */ diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 97700d797a7..cd5aed30325 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2575,6 +2575,7 @@ constexpr wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW #include "insn-attr-common.h" +#include "common/config/i386/i386-common.h" #include "common/config/i386/i386-cpuinfo.h" class pta diff --git a/gcc/config/i386/ia32intrin.h b/gcc/config/i386/ia32intrin.h index 591394076cc..4ecc7619188 100644 --- a/gcc/config/i386/ia32intrin.h +++ b/gcc/config/i386/ia32intrin.h @@ -107,12 +107,24 @@ __rdpmc (int __S) #endif /* __iamcu__ */ /* rdtsc */ -#define __rdtsc() __builtin_ia32_rdtsc () +extern __inline unsigned long long +__attribute__((__gnu_inline__, __always_inline__, __artificial__, + __general_regs_only__)) +__rdtsc (void) +{ + return __builtin_ia32_rdtsc (); +} #ifndef __iamcu__ /* rdtscp */ -#define __rdtscp(a) __builtin_ia32_rdtscp (a) +extern __inline unsigned long long +__attribute__((__gnu_inline__, __always_inline__, __artificial__, + __general_regs_only__)) +__rdtscp (unsigned int *__A) +{ + return __builtin_ia32_rdtscp (__A); +} #endif /* __iamcu__ */ diff --git a/gcc/config/i386/serializeintrin.h b/gcc/config/i386/serializeintrin.h index e280250b198..dd27e6c7a81 100644 --- a/gcc/config/i386/serializeintrin.h +++ b/gcc/config/i386/serializeintrin.h @@ -34,7 +34,13 @@ #define __DISABLE_SERIALIZE__ #endif /* __SERIALIZE__ */ -#define _serialize() __builtin_ia32_serialize () +extern __inline void +__attribute__((__gnu_inline__, __always_inline__, __artificial__, + __general_regs_only__)) +_serialize (void) +{ + __builtin_ia32_serialize (); +} #ifdef __DISABLE_SERIALIZE__ #undef __DISABLE_SERIALIZE__ diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 1ddafb3ff2c..5ca054d9037 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -3046,6 +3046,11 @@ The target may also allow additional types in @code{format-arg} attributes. @xref{Target Format Checks,,Format Checks Specific to Particular Target Machines}. +@item general_regs_only +@cindex @code{general_regs_only} function attribute +The @code{general_regs_only} attribute on functions is used to +inform the compiler that functions use only general purpose registers. + @item gnu_inline @cindex @code{gnu_inline} function attribute This attribute should be used with a function that is also declared diff --git a/gcc/testsuite/gcc.target/i386/pr99744-3.c b/gcc/testsuite/gcc.target/i386/pr99744-3.c new file mode 100644 index 00000000000..6c505816ceb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr99744-3.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-serialize" } */ + +#include + +__attribute__ ((target("general-regs-only"))) +void +foo1 (void) +{ + _serialize (); +} + +/* { dg-error "target specific option mismatch" "" { target *-*-* } 0 } */ -- 2.30.2