From patchwork Tue Apr 13 08:07:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "wangyanan (Y)" X-Patchwork-Id: 1465597 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FKJFr5VZpz9sVw for ; Tue, 13 Apr 2021 18:10:56 +1000 (AEST) Received: from localhost ([::1]:40896 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lWE8M-0007k9-PQ for incoming@patchwork.ozlabs.org; Tue, 13 Apr 2021 04:10:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWE5m-00048x-BZ; Tue, 13 Apr 2021 04:08:14 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:5029) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWE5h-0006Pu-8t; Tue, 13 Apr 2021 04:08:14 -0400 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4FKJ8H320rzlXcY; Tue, 13 Apr 2021 16:06:07 +0800 (CST) Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 Apr 2021 16:07:49 +0800 From: Yanan Wang To: , Subject: [RFC PATCH v2 1/6] device_tree: Add qemu_fdt_add_path Date: Tue, 13 Apr 2021 16:07:40 +0800 Message-ID: <20210413080745.33004-2-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20210413080745.33004-1-wangyanan55@huawei.com> References: <20210413080745.33004-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=wangyanan55@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrew Jones , "Michael S . Tsirkin" , wanghaibin.wang@huawei.com, Yanan Wang , Shannon Zhao , Alistair Francis , prime.zeng@hisilicon.com, yangyicong@huawei.com, yuzenghui@huawei.com, Igor Mammedov , zhukeqian1@huawei.com, Jiajie Li , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except it also adds any missing subnodes in the path. We also tweak an error message of qemu_fdt_add_subnode(). We'll make use of this new function in a coming patch. Signed-off-by: Andrew Jones Signed-off-by: Yanan Wang --- include/sysemu/device_tree.h | 1 + softmmu/device_tree.c | 45 ++++++++++++++++++++++++++++++++++-- 2 files changed, 44 insertions(+), 2 deletions(-) diff --git a/include/sysemu/device_tree.h b/include/sysemu/device_tree.h index 8a2fe55622..ef060a9759 100644 --- a/include/sysemu/device_tree.h +++ b/include/sysemu/device_tree.h @@ -121,6 +121,7 @@ uint32_t qemu_fdt_get_phandle(void *fdt, const char *path); uint32_t qemu_fdt_alloc_phandle(void *fdt); int qemu_fdt_nop_node(void *fdt, const char *node_path); int qemu_fdt_add_subnode(void *fdt, const char *name); +int qemu_fdt_add_path(void *fdt, const char *path); #define qemu_fdt_setprop_cells(fdt, node_path, property, ...) \ do { \ diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c index 2691c58cf6..8592c7aa1b 100644 --- a/softmmu/device_tree.c +++ b/softmmu/device_tree.c @@ -541,8 +541,8 @@ int qemu_fdt_add_subnode(void *fdt, const char *name) retval = fdt_add_subnode(fdt, parent, basename); if (retval < 0) { - error_report("FDT: Failed to create subnode %s: %s", name, - fdt_strerror(retval)); + error_report("%s: Failed to create subnode %s: %s", + __func__, name, fdt_strerror(retval)); exit(1); } @@ -550,6 +550,47 @@ int qemu_fdt_add_subnode(void *fdt, const char *name) return retval; } +/* + * Like qemu_fdt_add_subnode(), but will add all missing + * subnodes in the path. + */ +int qemu_fdt_add_path(void *fdt, const char *path) +{ + char *dupname, *basename, *p; + int parent, retval = -1; + + if (path[0] != '/') { + return retval; + } + + parent = fdt_path_offset(fdt, "/"); + p = dupname = g_strdup(path); + + while (p) { + *p = '/'; + basename = p + 1; + p = strchr(p + 1, '/'); + if (p) { + *p = '\0'; + } + retval = fdt_path_offset(fdt, dupname); + if (retval < 0 && retval != -FDT_ERR_NOTFOUND) { + error_report("%s: Invalid path %s: %s", + __func__, path, fdt_strerror(retval)); + exit(1); + } else if (retval == -FDT_ERR_NOTFOUND) { + retval = fdt_add_subnode(fdt, parent, basename); + if (retval < 0) { + break; + } + } + parent = retval; + } + + g_free(dupname); + return retval; +} + void qemu_fdt_dumpdtb(void *fdt, int size) { const char *dumpdtb = current_machine->dumpdtb; From patchwork Tue Apr 13 08:07:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "wangyanan (Y)" X-Patchwork-Id: 1465591 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FKJCT41Htz9sVw for ; Tue, 13 Apr 2021 18:08:53 +1000 (AEST) Received: from localhost ([::1]:33004 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lWE6N-0004c2-Jk for incoming@patchwork.ozlabs.org; Tue, 13 Apr 2021 04:08:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43870) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWE5m-00049k-M5; Tue, 13 Apr 2021 04:08:14 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:5030) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWE5h-0006Pv-Fc; Tue, 13 Apr 2021 04:08:14 -0400 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4FKJ8H2l5fzlXcW; Tue, 13 Apr 2021 16:06:07 +0800 (CST) Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 Apr 2021 16:07:51 +0800 From: Yanan Wang To: , Subject: [RFC PATCH v2 2/6] hw/arm/virt: DT: Add cpu-map Date: Tue, 13 Apr 2021 16:07:41 +0800 Message-ID: <20210413080745.33004-3-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20210413080745.33004-1-wangyanan55@huawei.com> References: <20210413080745.33004-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=wangyanan55@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrew Jones , "Michael S . Tsirkin" , wanghaibin.wang@huawei.com, Yanan Wang , Shannon Zhao , Alistair Francis , prime.zeng@hisilicon.com, yangyicong@huawei.com, yuzenghui@huawei.com, Igor Mammedov , zhukeqian1@huawei.com, Jiajie Li , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones Support device tree CPU topology descriptions. Signed-off-by: Andrew Jones Signed-off-by: Yanan Wang --- hw/arm/virt.c | 41 ++++++++++++++++++++++++++++++++++++++++- include/hw/arm/virt.h | 1 + 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9f01d9041b..f4ae60ded9 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -352,10 +352,11 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms) int cpu; int addr_cells = 1; const MachineState *ms = MACHINE(vms); + const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); int smp_cpus = ms->smp.cpus; /* - * From Documentation/devicetree/bindings/arm/cpus.txt + * See Linux Documentation/devicetree/bindings/arm/cpus.yaml * On ARM v8 64-bit systems value should be set to 2, * that corresponds to the MPIDR_EL1 register size. * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs @@ -408,8 +409,45 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms) ms->possible_cpus->cpus[cs->cpu_index].props.node_id); } + if (ms->smp.cpus > 1 && !vmc->no_cpu_topology) { + qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", + qemu_fdt_alloc_phandle(ms->fdt)); + } + g_free(nodename); } + + if (ms->smp.cpus > 1 && !vmc->no_cpu_topology) { + /* + * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt + * In a SMP system, the hierarchy of CPUs is defined through four + * entities that are used to describe the layout of physical CPUs + * in the system: socket/cluster/core/thread. + */ + qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); + + for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { + char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); + char *map_path; + + if (ms->smp.threads > 1) { + map_path = g_strdup_printf( + "/cpus/cpu-map/%s%d/%s%d/%s%d", + "socket", cpu / (ms->smp.cores * ms->smp.threads), + "core", (cpu / ms->smp.threads) % ms->smp.cores, + "thread", cpu % ms->smp.threads); + } else { + map_path = g_strdup_printf( + "/cpus/cpu-map/%s%d/%s%d", + "socket", cpu / ms->smp.cores, + "core", cpu % ms->smp.cores); + } + qemu_fdt_add_path(ms->fdt, map_path); + qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); + g_free(map_path); + g_free(cpu_path); + } + } } static void fdt_add_its_gic_node(VirtMachineState *vms) @@ -2769,6 +2807,7 @@ static void virt_machine_5_2_options(MachineClass *mc) virt_machine_6_0_options(mc); compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); vmc->no_secure_gpio = true; + vmc->no_cpu_topology = true; } DEFINE_VIRT_MACHINE(5, 2) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 921416f918..4a4b98e4a7 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -129,6 +129,7 @@ struct VirtMachineClass { bool no_kvm_steal_time; bool acpi_expose_flash; bool no_secure_gpio; + bool no_cpu_topology; }; struct VirtMachineState { From patchwork Tue Apr 13 08:07:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "wangyanan (Y)" X-Patchwork-Id: 1465588 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FKJCC1tPsz9sVw for ; Tue, 13 Apr 2021 18:08:39 +1000 (AEST) Received: from localhost ([::1]:60144 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lWE69-00047a-8t for incoming@patchwork.ozlabs.org; Tue, 13 Apr 2021 04:08:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43816) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWE5k-00045x-Gj; Tue, 13 Apr 2021 04:08:12 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:5032) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWE5h-0006Qh-77; Tue, 13 Apr 2021 04:08:12 -0400 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4FKJ8H3Jb8zlXd8; Tue, 13 Apr 2021 16:06:07 +0800 (CST) Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 Apr 2021 16:07:52 +0800 From: Yanan Wang To: , Subject: [RFC PATCH v2 3/6] hw/arm/virt-acpi-build: Distinguish possible and present cpus Date: Tue, 13 Apr 2021 16:07:42 +0800 Message-ID: <20210413080745.33004-4-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20210413080745.33004-1-wangyanan55@huawei.com> References: <20210413080745.33004-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=wangyanan55@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrew Jones , "Michael S . Tsirkin" , wanghaibin.wang@huawei.com, Yanan Wang , Shannon Zhao , Alistair Francis , prime.zeng@hisilicon.com, yangyicong@huawei.com, yuzenghui@huawei.com, Igor Mammedov , Ying Fang , zhukeqian1@huawei.com, Jiajie Li , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Ying Fang When building ACPI tables regarding CPUs we should always build them for the number of possible CPUs, not the number of present CPUs. We then ensure only the present CPUs are enabled in MADT. Furthermore, it is also needed if we are going to support CPU hotplug in the future. This patch is a rework based on Andrew Jones's contribution at https://lists.gnu.org/archive/html/qemu-arm/2018-07/msg00076.html Signed-off-by: Ying Fang Signed-off-by: Yanan Wang --- hw/arm/virt-acpi-build.c | 14 ++++++++++---- hw/arm/virt.c | 3 +++ 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index f5a2b2d4cb..2ad5dad1bf 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -61,13 +61,16 @@ static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) { - MachineState *ms = MACHINE(vms); + CPUArchIdList *possible_cpus = MACHINE(vms)->possible_cpus; uint16_t i; - for (i = 0; i < ms->smp.cpus; i++) { + for (i = 0; i < possible_cpus->len; i++) { Aml *dev = aml_device("C%.03X", i); aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); aml_append(dev, aml_name_decl("_UID", aml_int(i))); + if (possible_cpus->cpus[i].cpu == NULL) { + aml_append(dev, aml_name_decl("_STA", aml_int(0))); + } aml_append(scope, dev); } } @@ -479,6 +482,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) const int *irqmap = vms->irqmap; AcpiMadtGenericDistributor *gicd; AcpiMadtGenericMsiFrame *gic_msi; + CPUArchIdList *possible_cpus = MACHINE(vms)->possible_cpus; int i; acpi_data_push(table_data, sizeof(AcpiMultipleApicTable)); @@ -489,7 +493,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base); gicd->version = vms->gic_version; - for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { + for (i = 0; i < possible_cpus->len; i++) { AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data, sizeof(*gicc)); ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); @@ -504,7 +508,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) gicc->cpu_interface_number = cpu_to_le32(i); gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity); gicc->uid = cpu_to_le32(i); - gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED); + if (possible_cpus->cpus[i].cpu != NULL) { + gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED); + } if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ)); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index f4ae60ded9..3e5d9b6f26 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2063,6 +2063,9 @@ static void machvirt_init(MachineState *machine) } qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); + + /* Initialize cpu member here since cpu hotplug is not supported yet */ + machine->possible_cpus->cpus[n].cpu = cpuobj; object_unref(cpuobj); } fdt_add_timer_nodes(vms); From patchwork Tue Apr 13 08:07:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "wangyanan (Y)" X-Patchwork-Id: 1465593 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FKJD41r2Tz9sVw for ; Tue, 13 Apr 2021 18:09:24 +1000 (AEST) Received: from localhost ([::1]:34464 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lWE6s-0005Bq-8r for incoming@patchwork.ozlabs.org; Tue, 13 Apr 2021 04:09:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43906) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWE5n-0004Cr-Uy; Tue, 13 Apr 2021 04:08:15 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:5033) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWE5h-0006RR-FY; Tue, 13 Apr 2021 04:08:15 -0400 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4FKJ8N2cm5zlXbH; Tue, 13 Apr 2021 16:06:12 +0800 (CST) Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 Apr 2021 16:07:54 +0800 From: Yanan Wang To: , Subject: [RFC PATCH v2 4/6] hw/acpi/aml-build: Add processor hierarchy node structure Date: Tue, 13 Apr 2021 16:07:43 +0800 Message-ID: <20210413080745.33004-5-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20210413080745.33004-1-wangyanan55@huawei.com> References: <20210413080745.33004-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=wangyanan55@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrew Jones , "Michael S . Tsirkin" , wanghaibin.wang@huawei.com, Yanan Wang , Shannon Zhao , Henglong Fan , Alistair Francis , prime.zeng@hisilicon.com, yangyicong@huawei.com, yuzenghui@huawei.com, Igor Mammedov , Ying Fang , zhukeqian1@huawei.com, Jiajie Li , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add a generic API to build Processor Hierarchy Node Structure(Type 0), which is strictly consistent with descriptions in ACPI 6.3: 5.2.29.1. This function will be used to build ACPI PPTT table for cpu topology. Signed-off-by: Ying Fang Signed-off-by: Henglong Fan Signed-off-by: Yanan Wang --- hw/acpi/aml-build.c | 27 +++++++++++++++++++++++++++ include/hw/acpi/aml-build.h | 4 ++++ 2 files changed, 31 insertions(+) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index d33ce8954a..75e01aea17 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1916,6 +1916,33 @@ void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms, table_data->len - slit_start, 1, oem_id, oem_table_id); } +/* + * ACPI 6.3: 5.2.29.1 Processor Hierarchy Node Structure (Type 0) + */ +void build_processor_hierarchy_node(GArray *tbl, uint32_t flags, + uint32_t parent, uint32_t id, + uint32_t *priv_rsrc, uint32_t priv_num) +{ + int i; + + build_append_byte(tbl, 0); /* Type 0 - processor */ + build_append_byte(tbl, 20 + priv_num * 4); /* Length */ + build_append_int_noprefix(tbl, 0, 2); /* Reserved */ + build_append_int_noprefix(tbl, flags, 4); /* Flags */ + build_append_int_noprefix(tbl, parent, 4); /* Parent */ + build_append_int_noprefix(tbl, id, 4); /* ACPI processor ID */ + + /* Number of private resources */ + build_append_int_noprefix(tbl, priv_num, 4); + + /* Private resources[N] */ + if (priv_num > 0 && priv_rsrc != NULL) { + for (i = 0; i < priv_num; i++) { + build_append_int_noprefix(tbl, priv_rsrc[i], 4); + } + } +} + /* build rev1/rev3/rev5.1 FADT */ void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, const char *oem_id, const char *oem_table_id) diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 471266d739..ea74b8f6ed 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -462,6 +462,10 @@ void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms, const char *oem_id, const char *oem_table_id); +void build_processor_hierarchy_node(GArray *tbl, uint32_t flags, + uint32_t parent, uint32_t id, + uint32_t *priv_rsrc, uint32_t priv_num); + void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, const char *oem_id, const char *oem_table_id); From patchwork Tue Apr 13 08:07:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "wangyanan (Y)" X-Patchwork-Id: 1465605 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FKJJg37Y5z9sVw for ; Tue, 13 Apr 2021 18:13:21 +1000 (AEST) Received: from localhost ([::1]:47914 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lWEAg-0002IJ-UK for incoming@patchwork.ozlabs.org; Tue, 13 Apr 2021 04:13:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWE5p-0004He-Kw; Tue, 13 Apr 2021 04:08:17 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:5034) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWE5m-0006Yi-Jk; Tue, 13 Apr 2021 04:08:17 -0400 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4FKJ8N30PtzlXdW; Tue, 13 Apr 2021 16:06:12 +0800 (CST) Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 Apr 2021 16:07:55 +0800 From: Yanan Wang To: , Subject: [RFC PATCH v2 5/6] hw/arm/virt-acpi-build: Add PPTT table Date: Tue, 13 Apr 2021 16:07:44 +0800 Message-ID: <20210413080745.33004-6-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20210413080745.33004-1-wangyanan55@huawei.com> References: <20210413080745.33004-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=wangyanan55@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrew Jones , "Michael S . Tsirkin" , wanghaibin.wang@huawei.com, Yanan Wang , Shannon Zhao , Alistair Francis , prime.zeng@hisilicon.com, yangyicong@huawei.com, yuzenghui@huawei.com, Igor Mammedov , Ying Fang , zhukeqian1@huawei.com, Jiajie Li , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add the Processor Properties Topology Table (PPTT) to present CPU topology information to ACPI guests. Note, while a DT boot Linux guest with a non-flat CPU topology will see socket and core IDs being sequential integers starting from zero, e.g. with -smp 4,sockets=2,cores=2,threads=1 a DT boot produces cpu: 0 package_id: 0 core_id: 0 cpu: 1 package_id: 0 core_id: 1 cpu: 2 package_id: 1 core_id: 0 cpu: 3 package_id: 1 core_id: 1 an ACPI boot produces cpu: 0 package_id: 36 core_id: 0 cpu: 1 package_id: 36 core_id: 1 cpu: 2 package_id: 96 core_id: 2 cpu: 3 package_id: 96 core_id: 3 This is due to several reasons: 1) DT cpu nodes do not have an equivalent field to what the PPTT ACPI Processor ID must be, i.e. something equal to the MADT CPU UID or equal to the UID of an ACPI processor container. In both ACPI cases those are platform dependant IDs assigned by the vendor. 2) While QEMU is the vendor for a guest, if the topology specifies SMT (> 1 thread), then, with ACPI, it is impossible to assign a core-id the same value as a package-id, thus it is not possible to have package-id=0 and core-id=0. This is because package and core containers must be in the same ACPI namespace and therefore must have unique UIDs. 3) ACPI processor containers are not required for PPTT tables to be used and, due to the limitations of which IDs are selected described above in (2), they are not helpful for QEMU, so we don't build them with this patch. In the absence of them, Linux assigns its own unique IDs. The maintainers have chosen not to use counters from zero, but rather ACPI table offsets, which explains why the numbers are so much larger than with DT. 4) When there is no SMT (threads=1) the core IDs for ACPI boot guests match the logical CPU IDs, because these IDs must be equal to the MADT CPU UID (as no processor containers are present), and QEMU uses the logical CPU ID for these MADT IDs. Tested-by: Jiajie Li Signed-off-by: Andrew Jones Signed-off-by: Ying Fang Signed-off-by: Yanan Wang --- hw/arm/virt-acpi-build.c | 63 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 2ad5dad1bf..03fd812d5a 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -436,6 +436,64 @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) vms->oem_table_id); } +/* PPTT */ +static void +build_pptt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) +{ + int pptt_start = table_data->len; + int uid = 0, cpus = 0, socket = 0; + MachineState *ms = MACHINE(vms); + unsigned int smp_cores = ms->smp.cores; + unsigned int smp_threads = ms->smp.threads; + + acpi_data_push(table_data, sizeof(AcpiTableHeader)); + + for (socket = 0; cpus < ms->possible_cpus->len; socket++) { + uint32_t socket_offset = table_data->len - pptt_start; + int core; + + build_processor_hierarchy_node( + table_data, 1, /* Physical package */ + 0, socket, /* No parent */ + NULL, 0); /* No private resources */ + + for (core = 0; core < smp_cores; core++) { + uint32_t core_offset = table_data->len - pptt_start; + int thread; + + if (smp_threads <= 1) { + build_processor_hierarchy_node( + table_data, + (1 << 1) | /* ACPI Processor ID valid */ + (1 << 3), /* ACPI 6.3 - Node is a Leaf */ + socket_offset, uid++, /* Parent is a Socket */ + NULL, 0); /* No private resources */ + } else { + build_processor_hierarchy_node( + table_data, 0, + socket_offset, core, /* Parent is a Socket */ + NULL, 0); /* No private resources */ + + for (thread = 0; thread < smp_threads; thread++) { + build_processor_hierarchy_node( + table_data, + (1 << 1) | /* ACPI Processor ID valid */ + (1 << 2) | /* ACPI 6.3 - Processor is a Thread */ + (1 << 3), /* ACPI 6.3 - Node is a Leaf */ + core_offset, uid++, /* Parent is a Core */ + NULL, 0); /* No private resources */ + } + } + } + cpus += smp_cores * smp_threads; + } + + build_header(linker, table_data, + (void *)(table_data->data + pptt_start), "PPTT", + table_data->len - pptt_start, 2, + vms->oem_id, vms->oem_table_id); +} + /* GTDT */ static void build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) @@ -707,6 +765,11 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) acpi_add_table(table_offsets, tables_blob); build_madt(tables_blob, tables->linker, vms); + if (ms->smp.cpus > 1 && !vmc->no_cpu_topology) { + acpi_add_table(table_offsets, tables_blob); + build_pptt(tables_blob, tables->linker, vms); + } + acpi_add_table(table_offsets, tables_blob); build_gtdt(tables_blob, tables->linker, vms); From patchwork Tue Apr 13 08:07:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "wangyanan (Y)" X-Patchwork-Id: 1465600 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FKJGQ2zmZz9sVw for ; Tue, 13 Apr 2021 18:11:26 +1000 (AEST) Received: from localhost ([::1]:43398 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lWE8q-0000Oj-Fw for incoming@patchwork.ozlabs.org; Tue, 13 Apr 2021 04:11:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43922) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWE5o-0004FT-UN; Tue, 13 Apr 2021 04:08:16 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:5035) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWE5m-0006Yj-Hx; Tue, 13 Apr 2021 04:08:16 -0400 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4FKJ8N2FqwzlXZs; Tue, 13 Apr 2021 16:06:12 +0800 (CST) Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 Apr 2021 16:07:56 +0800 From: Yanan Wang To: , Subject: [RFC PATCH v2 6/6] hw/arm/virt: Replace smp_parse with one that prefers cores Date: Tue, 13 Apr 2021 16:07:45 +0800 Message-ID: <20210413080745.33004-7-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20210413080745.33004-1-wangyanan55@huawei.com> References: <20210413080745.33004-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=wangyanan55@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrew Jones , "Michael S . Tsirkin" , wanghaibin.wang@huawei.com, Yanan Wang , Shannon Zhao , Alistair Francis , prime.zeng@hisilicon.com, yangyicong@huawei.com, yuzenghui@huawei.com, Igor Mammedov , zhukeqian1@huawei.com, Jiajie Li , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones The virt machine type has never used the CPU topology parameters, other than number of online CPUs and max CPUs. When choosing how to allocate those CPUs the default has been to assume cores. In preparation for using the other CPU topology parameters let's use an smp_parse that prefers cores over sockets. We can also enforce the topology matches max_cpus check because we have no legacy to preserve. Signed-off-by: Andrew Jones Signed-off-by: Yanan Wang --- hw/arm/virt.c | 76 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3e5d9b6f26..57ef961cb5 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -79,6 +79,8 @@ #include "hw/virtio/virtio-iommu.h" #include "hw/char/pl011.h" #include "qemu/guest-random.h" +#include "qapi/qmp/qerror.h" +#include "sysemu/replay.h" #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ @@ -2625,6 +2627,79 @@ static int virt_kvm_type(MachineState *ms, const char *type_str) return fixed_ipa ? 0 : requested_pa_size; } +/* + * Unlike smp_parse() in hw/core/machine.c, we prefer cores over sockets, + * e.g. '-smp 8' creates 1 socket with 8 cores. Whereas '-smp 8' with + * hw/core/machine.c's smp_parse() creates 8 sockets, each with 1 core. + * Additionally, we can enforce the topology matches max_cpus check, + * because we have no legacy to preserve. + */ +static void virt_smp_parse(MachineState *ms, QemuOpts *opts) +{ + if (opts) { + unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); + unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); + unsigned cores = qemu_opt_get_number(opts, "cores", 0); + unsigned threads = qemu_opt_get_number(opts, "threads", 0); + + /* + * Compute missing values; prefer cores over sockets and + * sockets over threads. + */ + if (cpus == 0 || cores == 0) { + sockets = sockets > 0 ? sockets : 1; + threads = threads > 0 ? threads : 1; + if (cpus == 0) { + cores = cores > 0 ? cores : 1; + cpus = cores * threads * sockets; + } else { + ms->smp.max_cpus = qemu_opt_get_number(opts, "maxcpus", cpus); + cores = ms->smp.max_cpus / (sockets * threads); + } + } else if (sockets == 0) { + threads = threads > 0 ? threads : 1; + sockets = cpus / (cores * threads); + sockets = sockets > 0 ? sockets : 1; + } else if (threads == 0) { + threads = cpus / (cores * sockets); + threads = threads > 0 ? threads : 1; + } else if (sockets * cores * threads < cpus) { + error_report("cpu topology: " + "sockets (%u) * cores (%u) * threads (%u) < " + "smp_cpus (%u)", + sockets, cores, threads, cpus); + exit(1); + } + + ms->smp.max_cpus = qemu_opt_get_number(opts, "maxcpus", cpus); + + if (ms->smp.max_cpus < cpus) { + error_report("maxcpus must be equal to or greater than smp"); + exit(1); + } + + if (sockets * cores * threads != ms->smp.max_cpus) { + error_report("cpu topology: " + "sockets (%u) * cores (%u) * threads (%u)" + "!= maxcpus (%u)", + sockets, cores, threads, + ms->smp.max_cpus); + exit(1); + } + + ms->smp.cpus = cpus; + ms->smp.cores = cores; + ms->smp.threads = threads; + ms->smp.sockets = sockets; + } + + if (ms->smp.cpus > 1) { + Error *blocker = NULL; + error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); + replay_add_blocker(blocker); + } +} + static void virt_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -2650,6 +2725,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) mc->cpu_index_to_instance_props = virt_cpu_index_to_props; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; + mc->smp_parse = virt_smp_parse; mc->kvm_type = virt_kvm_type; assert(!mc->get_hotplug_handler); mc->get_hotplug_handler = virt_machine_get_hotplug_handler;