From patchwork Wed Jan 17 13:04:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhishek Goel X-Patchwork-Id: 862256 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zM6kl0QNMz9s0g for ; Thu, 18 Jan 2018 00:05:03 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zM6kk5R4MzF0Xn for ; Thu, 18 Jan 2018 00:05:02 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=huntbag@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zM6kT4gwKzF0TK for ; Thu, 18 Jan 2018 00:04:49 +1100 (AEDT) Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w0HD0SZ7073986 for ; Wed, 17 Jan 2018 08:04:47 -0500 Received: from e06smtp12.uk.ibm.com (e06smtp12.uk.ibm.com [195.75.94.108]) by mx0a-001b2d01.pphosted.com with ESMTP id 2fj5rkusf8-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 17 Jan 2018 08:04:46 -0500 Received: from localhost by e06smtp12.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 17 Jan 2018 13:04:43 -0000 Received: from b06cxnps3074.portsmouth.uk.ibm.com (9.149.109.194) by e06smtp12.uk.ibm.com (192.168.101.142) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Wed, 17 Jan 2018 13:04:42 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w0HD4fts1048862; Wed, 17 Jan 2018 13:04:41 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5D35211C050; Wed, 17 Jan 2018 12:58:25 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8D6B511C04A; Wed, 17 Jan 2018 12:58:24 +0000 (GMT) Received: from oc0383214508.ibm.com (unknown [9.124.35.238]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 17 Jan 2018 12:58:24 +0000 (GMT) From: Abhishek Goel To: stewart@linux.vnet.ibm.com, skiboot@lists.ozlabs.org Date: Wed, 17 Jan 2018 18:34:36 +0530 X-Mailer: git-send-email 1.8.3.1 X-TM-AS-GCONF: 00 x-cbid: 18011713-0008-0000-0000-000004C2CB45 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18011713-0009-0000-0000-00001E563A3F Message-Id: <1516194276-21515-1-git-send-email-huntbag@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-17_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801170188 Subject: [Skiboot] [PATCH v5] power-mgmt : occ : Add 'freq-domain-indicator' DT property X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Add a new device-tree property freq-domain-indicator to define group of CPUs which would share same frequency. This property has been added under power-mgmt node. It is a bitmask which will have different value depending upon the generation of the processor. Bitwise AND is taken between this bitmask value and PIR of cpu. All the CPUs lying in the same frequency domain will have same result for AND. For example, for POWER8 0xFFF8 indicates core wide frequency domain. Taking AND with the PIR of CPUs will yield us a frequency domain which is core wide distribution as last 3 bits have been masked which represent the threads. For POWER9, 0xFFF0 indicates quad wide frequency domain. Taking AND with the PIR of CPUs will yield us frequency domain which is quad wise distribution as last 4 bits have been masked which represent the cores. Signed-off-by: Abhishek Goel --- v4->v5 : * Added documentation for compatibility flags. v3->v4 : * Added compatibility string "p9-occ-quirk" v2->v3 : * Added compatibility string "freq-domain-v1" v1->v2 : * Handled errors if device tree node creation failed. doc/device-tree/ibm,opal/power-mgt/occ.rst | 36 ++++++++++++++++++++++++++++++ hw/occ.c | 18 +++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/doc/device-tree/ibm,opal/power-mgt/occ.rst b/doc/device-tree/ibm,opal/power-mgt/occ.rst index d13a62b..77d4258 100644 --- a/doc/device-tree/ibm,opal/power-mgt/occ.rst +++ b/doc/device-tree/ibm,opal/power-mgt/occ.rst @@ -37,3 +37,39 @@ ibm,pstate-vcss ibm,pstate-vdds These properties list a voltage-identifier of each of the pstates listed in ibm,pstate-ids for the Vcs and Vdd values used for that pstate in that chip. Each VID is a single byte. + +ibm,opal/power-mgt/ibm,freq-domain-indicator +-------------------------------------------- + +This property is a bitmask which will have different value depending upon the +generation of the processor. Frequency domain would indicate group of CPUs +which would share same frequency. Bitwise AND is taken between this bitmask +value and PIR of cpu. All the CPUs lying in the same frequency domain will have +same result for AND. Thus frequency management can be done based on frequency +domain. A frequency domain may be a core or a quad, etc depending upon the +generation of the processor. + +For example, for POWER8 0xFFF8 indicates core wide frequency domain. Taking AND +with the PIR of CPUs will yield us a frequency domain which is core wide +distribution as last 3 bits have been masked which represent the threads. + +For POWER9, 0xFFF0 indicates quad wide frequency domain. Taking AND with +the PIR of CPUs will yield us frequency domain which is quad wise +distribution as last 4 bits have been masked which represent the cores. + +ibm,opal/power-mgt/compatible +-------------------------------------------- + +`p9-occ-quirk` + +It represents the current DVFS implementation in firmware. To set a frequency +in a quad, all cores of the quad need to set frequency in their respective +PMCR's. Ideally setting frequency on any of the core of that quad should change +frequency for the quad. + +`freq-domain-v1` + +This compatibility string helps kernel to interpret freq-domain-indicator's +format. If in future we have different format for freq-domain-indicator, future +firmwares running newer kernel will not interpret freq-domain-indicator +incorrectly. diff --git a/hw/occ.c b/hw/occ.c index f3f1231..cdd4928 100644 --- a/hw/occ.c +++ b/hw/occ.c @@ -47,6 +47,9 @@ #define MAX_OPAL_CMD_DATA_LENGTH 4090 #define MAX_OCC_RSP_DATA_LENGTH 8698 +#define P8_PIR_CORE_MASK 0xFFF8 +#define P9_PIR_QUAD_MASK 0xFFF0 + /** * OCC-OPAL Shared Memory Region * @@ -488,6 +491,7 @@ static bool add_cpu_pstate_properties(int *pstate_nom) u8 nr_pstates; bool ultra_turbo_supported; int i; + u32 freq_domain_indicator = 0; prlog(PR_DEBUG, "OCC: CPU pstate state device tree init\n"); @@ -660,6 +664,13 @@ static bool add_cpu_pstate_properties(int *pstate_nom) return false; } + if (proc_gen == proc_gen_p8) + freq_domain_indicator = P8_PIR_CORE_MASK; + else if (proc_gen == proc_gen_p9) + freq_domain_indicator = P9_PIR_QUAD_MASK; + else + prerror("OCC: freq-domain-indicator: Processor is not supported\n"); + /* Add the device-tree entries */ dt_add_property(power_mgt, "ibm,pstate-ids", dt_id, nr_pstates * sizeof(u32)); @@ -669,6 +680,13 @@ static bool add_cpu_pstate_properties(int *pstate_nom) dt_add_property_cells(power_mgt, "ibm,pstate-nominal", pnom); dt_add_property_cells(power_mgt, "ibm,pstate-max", pmax); + if (freq_domain_indicator) { + dt_add_property_cells(power_mgt, "ibm,freq-domain-indicator", + freq_domain_indicator); + dt_add_property_strings(power_mgt, "compatible", + "freq-domain-v1", "p9-occ-quirk"); + } + free(dt_freq); free(dt_id);