From patchwork Thu Apr 1 21:21:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 1461477 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=FVZIRLrn; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FBLh92ph0z9sWp for ; Fri, 2 Apr 2021 11:36:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235183AbhDAVV6 (ORCPT ); Thu, 1 Apr 2021 17:21:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235113AbhDAVV5 (ORCPT ); Thu, 1 Apr 2021 17:21:57 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F149C0613E6; Thu, 1 Apr 2021 14:21:56 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id j25so2355490pfe.2; Thu, 01 Apr 2021 14:21:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7XSm6/qzn9duNJgtAGMhBBSTeeaC2tU96ijTiVyfrw0=; b=FVZIRLrnc8G1Hy9rQgixadd2ErSk6SMttyrJQOLWi/5XMq0Cg0ILEkiaulBE+VmFta Fk/v9tsh1o+JslU3jZLly0kNadXbLPSOEuhPDchDCfF+8S5gru2p8WWxbqKKCL8Gn+UN 7FTawmIMsHV9y6QvGzuoqMw+dmO3NqCLTSZNV46hrnIU7GNJRRiaetP8xcmF7yWVCD6T BtD9+rKJJfw6+FGl6YLL7PGUiU4bxKuj6k6AwDo4c69CS6Q1oqvQCG69vvDwrXFUKHVX 9EVIsc5TM7AhBkKvC7+IudUmfss4KwzGldZ4MYRIQXDY2Hjs9e/xfVzPRoH8Sla8lgzy 6cxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7XSm6/qzn9duNJgtAGMhBBSTeeaC2tU96ijTiVyfrw0=; b=c8l4q1seS1n8aGZoSAVwl3SLTp01sdtZUv/uQQ8+zTdEdJA8E0hVJFJsvjc9acrWuN f4yqH897LVIayeaqNHR2mSdNxfK7QzO76lhQtzIQHHe9jiOQ6fLxfrUGWzpxGudZmpr9 NlC/gFu7mrUTlfqDJldT0HNzDM8xcImMf0hvbY+joTWzmscfEhbXnnVOFhklc+vdSi7T vRjS7JSLFACa9HwVFRv5K267ZVO2HJxH3I0cEBHYaZvKgrdP6FRvu1qzZgfz6n2jPHtO 5pgglHwUIsQRStGe59LA9f3qwksuFyQUbSMATkHGz9eVHj45j0kNWNvWUHVcn5RCDFnJ jnMA== X-Gm-Message-State: AOAM530EHdjnTUuJhesKRsSbFSmAPHjaTuYWXWZl44ZOEO89dLrCMUmv 1U0cJKr5M7P+TiiHk0mCIYQuZP0/xy4= X-Google-Smtp-Source: ABdhPJyfsLCcva5kpJAf0m0l/d1Xo7b+YAYAci8o03yqPZmVUlbZ1wQvQH2IXG+wFsRbemPv1EzAqw== X-Received: by 2002:a63:78cc:: with SMTP id t195mr9011398pgc.196.1617312115571; Thu, 01 Apr 2021 14:21:55 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id q5sm5926707pfk.219.2021.04.01.14.21.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 14:21:55 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Rob Herring , Mark Brown , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Jim Quinlan , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 1/6] PCI: brcmstb: Check return value of clk_prepare_enable() Date: Thu, 1 Apr 2021 17:21:41 -0400 Message-Id: <20210401212148.47033-2-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210401212148.47033-1-jim2101024@gmail.com> References: <20210401212148.47033-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Check for failure of clk_prepare_enable() on device resume. Signed-off-by: Jim Quinlan Acked-by: Florian Fainelli Fixes: 8195b7417018 ("PCI: brcmstb: Add suspend and resume pm_ops") --- drivers/pci/controller/pcie-brcmstb.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index e330e6811f0b..4ce1f3a60574 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1161,7 +1161,9 @@ static int brcm_pcie_resume(struct device *dev) int ret; base = pcie->base; - clk_prepare_enable(pcie->clk); + ret = clk_prepare_enable(pcie->clk); + if (ret) + return ret; ret = brcm_phy_start(pcie); if (ret) From patchwork Thu Apr 1 21:21:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 1461480 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=d+F70zzC; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FBLhB26QFz9shn for ; Fri, 2 Apr 2021 11:36:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235122AbhDAVWA (ORCPT ); Thu, 1 Apr 2021 17:22:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235134AbhDAVV7 (ORCPT ); Thu, 1 Apr 2021 17:21:59 -0400 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC9E3C0613E6; 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Thu, 01 Apr 2021 14:21:57 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id q5sm5926707pfk.219.2021.04.01.14.21.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 14:21:57 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Rob Herring , Mark Brown , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 2/6] dt-bindings: PCI: Add bindings for Brcmstb endpoint device voltage regulators Date: Thu, 1 Apr 2021 17:21:42 -0400 Message-Id: <20210401212148.47033-3-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210401212148.47033-1-jim2101024@gmail.com> References: <20210401212148.47033-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Similar to the regulator bindings found in "rockchip-pcie-host.txt", this allows optional regulators to be attached and controlled by the PCIe RC driver. That being said, this driver searches in the DT subnode (the EP node, eg pci@0,0) for the regulator property. The use of a regulator property in the pcie EP subnode such as "vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml file at https://github.com/devicetree-org/dt-schema/pull/54 Signed-off-by: Jim Quinlan --- Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index f90557f6deb8..f2caa5b3b281 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -64,6 +64,9 @@ properties: aspm-no-l0s: true + vpcie12v-supply: true + vpcie3v3-supply: true + brcm,scb-sizes: description: u64 giving the 64bit PCIe memory viewport size of a memory controller. There may be up to @@ -156,5 +159,6 @@ examples: <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>; brcm,enable-ssc; brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>; + vpcie12v-supply = <&vreg12>; }; }; From patchwork Thu Apr 1 21:21:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 1461482 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=rqKnVniA; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4FBLhB702dz9sWk for ; Fri, 2 Apr 2021 11:36:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235398AbhDAVWH (ORCPT ); Thu, 1 Apr 2021 17:22:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234541AbhDAVWE (ORCPT ); Thu, 1 Apr 2021 17:22:04 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E292C0613E6; Thu, 1 Apr 2021 14:22:01 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id a12so2340647pfc.7; Thu, 01 Apr 2021 14:22:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8VnZEjn3FMdva8ipBLV073OJdSwGTGi+Qmw1GQKtSJk=; b=rqKnVniAJqaznlfyFZnoH63rR6cVFwpgQ1QdlN2GJJEUGkszt41VRZqO4rpJeSuS5W ulfVwYfHvp8XURH5eqZdXRk3HjvyAmp8qq3bJ134fXnzYTTtscawCWC+iF+uCpSQq89a 7bW6bFpsWlfi63s1qgjE0H7ml3Y/BX9AFUA/0lQa0EGHhXKLZp8OCrL8X/Fvj+OpRhay d8f4T1l7t7sDxVP0p4nHlV1Vhc3gElYaA9PN8KVvin04fuQM3P6l9OTxU70AZWusuLfE 7/3vfT1uuQBVsMGt7v8BuPnU1bO9Rg9jgyDouparceLhXtuvpk6SUpfvnPtYgLP2LB0t MpVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8VnZEjn3FMdva8ipBLV073OJdSwGTGi+Qmw1GQKtSJk=; b=kgHySyivoxEL47D8qPKEW7DaOW8jsg7NkStkOnGBNOMjbuTnxc9U45zv43K5NNflNr s5NlBJ3u5XQFe+LrcGqbM1bhgVADQn1jcGEPxSuQsnH5nL3x42qpvm+qph7j1Cq3GHwF Az18zYG//0bBPeebq4kkD0934xC7EboVC9RP65i5Du47r51ESOSbc+bAtilMZnAdYIgx NKzd915+jn324bZNkbYF2On8MthFjoVCEN5CJwG74Wot802zBn4CPuWs+Ph2oNe7KqDt Hy2DSA+zQbBoj2sq1Yz0Km4RyGzvM86bM3TVrswzAEjOtH73fIdtEEG2sh/z4I2ZP7Li J3hA== X-Gm-Message-State: AOAM533lZWiUJNj3baYDTlDLiTzDI7CRO/Z+YHN1BBVXRVgnPtnu53qM ka8CRRlntxwitq3YkVNnrHGwJ3eVp3E= X-Google-Smtp-Source: ABdhPJwgmmrtZmxhTHaTcSUUdrBWSClYS0FE/GSnCuAlxz39mj1gVVrWBKV+9SHfDMvk4TEKO0KzZQ== X-Received: by 2002:a05:6a00:b86:b029:207:8ac9:85de with SMTP id g6-20020a056a000b86b02902078ac985demr9011916pfj.66.1617312120361; Thu, 01 Apr 2021 14:22:00 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id q5sm5926707pfk.219.2021.04.01.14.21.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 14:22:00 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Rob Herring , Mark Brown , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 3/6] PCI: brcmstb: Add control of slot0 device voltage regulators Date: Thu, 1 Apr 2021 17:21:43 -0400 Message-Id: <20210401212148.47033-4-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210401212148.47033-1-jim2101024@gmail.com> References: <20210401212148.47033-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This Broadcom STB has one port and connects directly to one device, be it a switch or an endpoint. We want to be able to turn on/off any regulators for that device. Control of regulators is needed because of the chicken-and-egg situation: although the regulator is "owned" by the device and would be best handled by its driver, the device cannot be discovered and probed unless its regulator is already turned on. Signed-off-by: Jim Quinlan --- drivers/pci/controller/pcie-brcmstb.c | 83 +++++++++++++++++++++++++-- 1 file changed, 78 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 4ce1f3a60574..1b0de0c7da60 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -169,6 +170,7 @@ #define SSC_STATUS_SSC_MASK 0x400 #define SSC_STATUS_PLL_LOCK_MASK 0x800 #define PCIE_BRCM_MAX_MEMC 3 +#define PCIE_BRCM_MAX_EP_REGULATORS 4 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) @@ -192,6 +194,11 @@ static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val); static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val); static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val); +static const char * const supplies[] = { + "vpcie12v-supply", + "vpcie3v3-supply", +}; + enum { RGR1_SW_INIT_1, EXT_CFG_INDEX, @@ -295,8 +302,27 @@ struct brcm_pcie { u32 hw_rev; void (*perst_set)(struct brcm_pcie *pcie, u32 val); void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); + struct regulator_bulk_data supplies[PCIE_BRCM_MAX_EP_REGULATORS]; + unsigned int num_supplies; }; +static int brcm_set_regulators(struct brcm_pcie *pcie, bool on) +{ + struct device *dev = pcie->dev; + int ret; + + if (!pcie->num_supplies) + return 0; + if (on) + ret = regulator_bulk_enable(pcie->num_supplies, pcie->supplies); + else + ret = regulator_bulk_disable(pcie->num_supplies, pcie->supplies); + if (ret) + dev_err(dev, "failed to %s EP regulators\n", + on ? "enable" : "disable"); + return ret; +} + /* * This is to convert the size of the inbound "BAR" region to the * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE @@ -1112,9 +1138,10 @@ static inline int brcm_phy_start(struct brcm_pcie *pcie) return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; } -static inline int brcm_phy_stop(struct brcm_pcie *pcie) +static inline void brcm_phy_stop(struct brcm_pcie *pcie) { - return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; + if (pcie->rescal) + brcm_phy_cntl(pcie, 0); } static void brcm_pcie_turn_off(struct brcm_pcie *pcie) @@ -1141,16 +1168,45 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie) pcie->bridge_sw_init_set(pcie, 1); } +static int brcm_pcie_get_regulators(struct brcm_pcie *pcie) +{ + struct device_node *np = pcie->np; + struct property *pp; + const unsigned int ns = ARRAY_SIZE(supplies); + unsigned int i; + int ret = 0; + + /* Look for specific pcie regulators in the RC DT node. */ + for_each_property_of_node(np, pp) { + for (i = 0; i < ns; i++) + if (strcmp(supplies[i], pp->name) == 0) + break; + if (i >= ns) + continue; + + if (pcie->num_supplies < PCIE_BRCM_MAX_EP_REGULATORS) + pcie->supplies[pcie->num_supplies++].supply + = supplies[i]; + else + dev_warn(pcie->dev, "No room for supply %s\n", + supplies[i]); + } + + if (pcie->num_supplies) + ret = devm_regulator_bulk_get(pcie->dev, pcie->num_supplies, + pcie->supplies); + return ret; +} + static int brcm_pcie_suspend(struct device *dev) { struct brcm_pcie *pcie = dev_get_drvdata(dev); - int ret; brcm_pcie_turn_off(pcie); - ret = brcm_phy_stop(pcie); + brcm_phy_stop(pcie); clk_disable_unprepare(pcie->clk); - return ret; + return brcm_set_regulators(pcie, false); } static int brcm_pcie_resume(struct device *dev) @@ -1165,6 +1221,10 @@ static int brcm_pcie_resume(struct device *dev) if (ret) return ret; + ret = brcm_set_regulators(pcie, true); + if (ret) + return ret; + ret = brcm_phy_start(pcie); if (ret) goto err; @@ -1201,6 +1261,7 @@ static void __brcm_pcie_remove(struct brcm_pcie *pcie) brcm_phy_stop(pcie); reset_control_assert(pcie->rescal); clk_disable_unprepare(pcie->clk); + brcm_set_regulators(pcie, false); } static int brcm_pcie_remove(struct platform_device *pdev) @@ -1291,6 +1352,18 @@ static int brcm_pcie_probe(struct platform_device *pdev) return ret; } + ret = brcm_pcie_get_regulators(pcie); + if (ret) { + pcie->num_supplies = 0; + if (ret != -EPROBE_DEFER) + dev_err(pcie->dev, "failed to get regulators (err=%d)\n", ret); + goto fail; + } + + ret = brcm_set_regulators(pcie, true); + if (ret) + goto fail; + ret = brcm_pcie_setup(pcie); if (ret) goto fail; From patchwork Thu Apr 1 21:21:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 1461481 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; 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Thu, 01 Apr 2021 14:22:02 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id q5sm5926707pfk.219.2021.04.01.14.22.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 14:22:02 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Rob Herring , Mark Brown , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 4/6] PCI: brcmstb: Do not turn off regulators if EP can wake up Date: Thu, 1 Apr 2021 17:21:44 -0400 Message-Id: <20210401212148.47033-5-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210401212148.47033-1-jim2101024@gmail.com> References: <20210401212148.47033-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org If any downstream device may wake up during S2/S3 suspend, we do not want to turn off its power when suspending. Signed-off-by: Jim Quinlan --- drivers/pci/controller/pcie-brcmstb.c | 58 +++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 1b0de0c7da60..4c79aff66de7 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -193,6 +193,7 @@ static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val); static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val); static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val); +static bool brcm_pcie_link_up(struct brcm_pcie *pcie); static const char * const supplies[] = { "vpcie12v-supply", @@ -304,22 +305,65 @@ struct brcm_pcie { void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); struct regulator_bulk_data supplies[PCIE_BRCM_MAX_EP_REGULATORS]; unsigned int num_supplies; + bool ep_wakeup_capable; }; -static int brcm_set_regulators(struct brcm_pcie *pcie, bool on) +static int pci_dev_may_wakeup(struct pci_dev *dev, void *data) { + bool *ret = data; + + if (device_may_wakeup(&dev->dev)) { + *ret = true; + dev_dbg(&dev->dev, "disable cancelled for wake-up device\n"); + } + return (int) *ret; +} + +enum { + TURN_OFF, /* Turn regulators off, unless an EP is wakeup-capable */ + TURN_OFF_ALWAYS, /* Turn regulators off, no exceptions */ + TURN_ON, /* Turn regulators on, unless pcie->ep_wakeup_capable */ +}; + +static int brcm_set_regulators(struct brcm_pcie *pcie, int how) +{ + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); struct device *dev = pcie->dev; int ret; if (!pcie->num_supplies) return 0; - if (on) + if (how == TURN_ON) { + if (pcie->ep_wakeup_capable) { + /* + * We are resuming from a suspend. In the + * previous suspend we did not disable the power + * supplies, so there is no need to enable them + * (and falsely increase their usage count). + */ + pcie->ep_wakeup_capable = false; + return 0; + } + } else if (how == TURN_OFF) { + /* + * If at least one device on this bus is enabled as a + * wake-up source, do not turn off regulators. + */ + pcie->ep_wakeup_capable = false; + if (bridge->bus && brcm_pcie_link_up(pcie)) { + pci_walk_bus(bridge->bus, pci_dev_may_wakeup, &pcie->ep_wakeup_capable); + if (pcie->ep_wakeup_capable) + return 0; + } + } + + if (how == TURN_ON) ret = regulator_bulk_enable(pcie->num_supplies, pcie->supplies); else ret = regulator_bulk_disable(pcie->num_supplies, pcie->supplies); if (ret) dev_err(dev, "failed to %s EP regulators\n", - on ? "enable" : "disable"); + how == TURN_ON ? "enable" : "disable"); return ret; } @@ -1206,7 +1250,7 @@ static int brcm_pcie_suspend(struct device *dev) brcm_phy_stop(pcie); clk_disable_unprepare(pcie->clk); - return brcm_set_regulators(pcie, false); + return brcm_set_regulators(pcie, TURN_OFF); } static int brcm_pcie_resume(struct device *dev) @@ -1221,7 +1265,7 @@ static int brcm_pcie_resume(struct device *dev) if (ret) return ret; - ret = brcm_set_regulators(pcie, true); + ret = brcm_set_regulators(pcie, TURN_ON); if (ret) return ret; @@ -1261,7 +1305,7 @@ static void __brcm_pcie_remove(struct brcm_pcie *pcie) brcm_phy_stop(pcie); reset_control_assert(pcie->rescal); clk_disable_unprepare(pcie->clk); - brcm_set_regulators(pcie, false); + brcm_set_regulators(pcie, TURN_OFF_ALWAYS); } static int brcm_pcie_remove(struct platform_device *pdev) @@ -1360,7 +1404,7 @@ static int brcm_pcie_probe(struct platform_device *pdev) goto fail; } - ret = brcm_set_regulators(pcie, true); + ret = brcm_set_regulators(pcie, TURN_ON); if (ret) goto fail; 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Signed-off-by: Jim Quinlan Acked-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 4c79aff66de7..44128df33785 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -265,6 +265,13 @@ static const struct pcie_cfg_data bcm2711_cfg = { .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, }; +static const struct pcie_cfg_data bcm7216_cfg = { + .offsets = pcie_offset_bcm7278, + .type = BCM7278, + .perst_set = brcm_pcie_perst_set_7278, + .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278, +}; + struct brcm_msi { struct device *dev; void __iomem *base; @@ -1325,7 +1332,7 @@ static const struct of_device_id brcm_pcie_match[] = { { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg }, { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg }, { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg }, - { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg }, + { .compatible = "brcm,bcm7216-pcie", .data = &bcm7216_cfg }, { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg }, {}, }; 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bh=9phU48RwJquj1HVaVVeNhbqrrN2jUhNbS5Biccg8yro=; b=tApooJQNKmkyta5FI3NKEoWI5a4oaWlBJImHtfIPbPgraC5zRaVGbzLwXaa/aJOV6S /Ucqj+g5P9Pw7NYjT+CQ+brclrlR1sFKT1C79Q1i/VRrjqviVnnDbJRnF51f+acW0xui g5og99f91qs8Z9QUM5tPS3lVtiMLHOFhBsUtjKEtw8Si5oXWYAbCtQQtMQYWGEimZrpD pX84BWN45TQHlf1jhLq/rl1u2nqT5dJoIP6SGMulZmjU5+WnQxTLyPboVTuMibBUIQDj 9Q5t23pe8Pve6LGo4dpdtLQIdbD9K1QOBK2IuRIVTUjzNunGuiFVJ/cS/Qz8eymQzjkN Lrgw== X-Gm-Message-State: AOAM530IYzzjc5XC1cn1wpWri/9WIZOsj1X0rvDZUbljj3sXzQDWBIRv 6ppR8jqK1+jhAtQ454AuxGHEntFaYC8= X-Google-Smtp-Source: ABdhPJzUHdMagnBlhKn7JuKQcxF83/2LF3hu3PoZB4IHWdEjl6OlL4MufW0ramrPBv1MZWu4Aaswbw== X-Received: by 2002:a17:90b:a01:: with SMTP id gg1mr10770520pjb.22.1617312127478; Thu, 01 Apr 2021 14:22:07 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id q5sm5926707pfk.219.2021.04.01.14.22.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 14:22:06 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Rob Herring , Mark Brown , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 6/6] PCI: brcmstb: Add panic/die handler to RC driver Date: Thu, 1 Apr 2021 17:21:46 -0400 Message-Id: <20210401212148.47033-7-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210401212148.47033-1-jim2101024@gmail.com> References: <20210401212148.47033-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Whereas most PCIe HW returns 0xffffffff on illegal accesses and the like, by default Broadcom's STB PCIe controller effects an abort. This simple handler determines if the PCIe controller was the cause of the abort and if so, prints out diagnostic info. Example output: brcm-pcie 8b20000.pcie: Error: Mem Acc: 32bit, Read, @0x38000000 brcm-pcie 8b20000.pcie: Type: TO=0 Abt=0 UnspReq=1 AccDsble=0 BadAddr=0 Signed-off-by: Jim Quinlan Acked-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 122 ++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 44128df33785..73a12c62b94e 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -12,11 +12,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -186,6 +188,39 @@ #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0 +/* Error report regiseters */ +#define PCIE_OUTB_ERR_TREAT 0x6000 +#define PCIE_OUTB_ERR_TREAT_CONFIG_MASK 0x1 +#define PCIE_OUTB_ERR_TREAT_MEM_MASK 0x2 +#define PCIE_OUTB_ERR_VALID 0x6004 +#define PCIE_OUTB_ERR_CLEAR 0x6008 +#define PCIE_OUTB_ERR_ACC_INFO 0x600c +#define PCIE_OUTB_ERR_ACC_INFO_CFG_ERR_MASK 0x01 +#define PCIE_OUTB_ERR_ACC_INFO_MEM_ERR_MASK 0x02 +#define PCIE_OUTB_ERR_ACC_INFO_TYPE_64_MASK 0x04 +#define PCIE_OUTB_ERR_ACC_INFO_DIR_WRITE_MASK 0x10 +#define PCIE_OUTB_ERR_ACC_INFO_BYTE_LANES_MASK 0xff00 +#define PCIE_OUTB_ERR_ACC_ADDR 0x6010 +#define PCIE_OUTB_ERR_ACC_ADDR_BUS_MASK 0xff00000 +#define PCIE_OUTB_ERR_ACC_ADDR_DEV_MASK 0xf8000 +#define PCIE_OUTB_ERR_ACC_ADDR_FUNC_MASK 0x7000 +#define PCIE_OUTB_ERR_ACC_ADDR_REG_MASK 0xfff +#define PCIE_OUTB_ERR_CFG_CAUSE 0x6014 +#define PCIE_OUTB_ERR_CFG_CAUSE_TIMEOUT_MASK 0x40 +#define PCIE_OUTB_ERR_CFG_CAUSE_ABORT_MASK 0x20 +#define PCIE_OUTB_ERR_CFG_CAUSE_UNSUPP_REQ_MASK 0x10 +#define PCIE_OUTB_ERR_CFG_CAUSE_ACC_TIMEOUT_MASK 0x4 +#define PCIE_OUTB_ERR_CFG_CAUSE_ACC_DISABLED_MASK 0x2 +#define PCIE_OUTB_ERR_CFG_CAUSE_ACC_64BIT__MASK 0x1 +#define PCIE_OUTB_ERR_MEM_ADDR_LO 0x6018 +#define PCIE_OUTB_ERR_MEM_ADDR_HI 0x601c +#define PCIE_OUTB_ERR_MEM_CAUSE 0x6020 +#define PCIE_OUTB_ERR_MEM_CAUSE_TIMEOUT_MASK 0x40 +#define PCIE_OUTB_ERR_MEM_CAUSE_ABORT_MASK 0x20 +#define PCIE_OUTB_ERR_MEM_CAUSE_UNSUPP_REQ_MASK 0x10 +#define PCIE_OUTB_ERR_MEM_CAUSE_ACC_DISABLED_MASK 0x2 +#define PCIE_OUTB_ERR_MEM_CAUSE_BAD_ADDR_MASK 0x1 + /* Forward declarations */ struct brcm_pcie; static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val); @@ -223,6 +258,7 @@ struct pcie_cfg_data { const enum pcie_type type; void (*perst_set)(struct brcm_pcie *pcie, u32 val); void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); + const bool has_err_report; }; static const int pcie_offsets[] = { @@ -270,6 +306,7 @@ static const struct pcie_cfg_data bcm7216_cfg = { .type = BCM7278, .perst_set = brcm_pcie_perst_set_7278, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278, + .has_err_report = true, }; struct brcm_msi { @@ -313,8 +350,87 @@ struct brcm_pcie { struct regulator_bulk_data supplies[PCIE_BRCM_MAX_EP_REGULATORS]; unsigned int num_supplies; bool ep_wakeup_capable; + bool has_err_report; + struct notifier_block die_notifier; }; +/* Dump out PCIe errors on die or panic */ +static int dump_pcie_error(struct notifier_block *self, unsigned long v, void *p) +{ + const struct brcm_pcie *pcie = container_of(self, struct brcm_pcie, die_notifier); + void __iomem *base = pcie->base; + int i, is_cfg_err, is_mem_err, lanes; + char *width_str, *direction_str, lanes_str[9]; + u32 info; + + if (readl(base + PCIE_OUTB_ERR_VALID) == 0) + return NOTIFY_DONE; + info = readl(base + PCIE_OUTB_ERR_ACC_INFO); + + + is_cfg_err = !!(info & PCIE_OUTB_ERR_ACC_INFO_CFG_ERR_MASK); + is_mem_err = !!(info & PCIE_OUTB_ERR_ACC_INFO_MEM_ERR_MASK); + width_str = (info & PCIE_OUTB_ERR_ACC_INFO_TYPE_64_MASK) ? "64bit" : "32bit"; + direction_str = (info & PCIE_OUTB_ERR_ACC_INFO_DIR_WRITE_MASK) ? "Write" : "Read"; + lanes = FIELD_GET(PCIE_OUTB_ERR_ACC_INFO_BYTE_LANES_MASK, info); + for (i = 0, lanes_str[8] = 0; i < 8; i++) + lanes_str[i] = (lanes & (1 << i)) ? '1' : '0'; + + if (is_cfg_err) { + u32 cfg_addr = readl(base + PCIE_OUTB_ERR_ACC_ADDR); + u32 cause = readl(base + PCIE_OUTB_ERR_CFG_CAUSE); + int bus = FIELD_GET(PCIE_OUTB_ERR_ACC_ADDR_BUS_MASK, cfg_addr); + int dev = FIELD_GET(PCIE_OUTB_ERR_ACC_ADDR_DEV_MASK, cfg_addr); + int func = FIELD_GET(PCIE_OUTB_ERR_ACC_ADDR_FUNC_MASK, cfg_addr); + int reg = FIELD_GET(PCIE_OUTB_ERR_ACC_ADDR_REG_MASK, cfg_addr); + + dev_err(pcie->dev, "Error: CFG Acc, %s, %s, Bus=%d, Dev=%d, Fun=%d, Reg=0x%x, lanes=%s\n", + width_str, direction_str, bus, dev, func, reg, lanes_str); + dev_err(pcie->dev, " Type: TO=%d Abt=%d UnsupReq=%d AccTO=%d AccDsbld=%d Acc64bit=%d\n", + !!(cause & PCIE_OUTB_ERR_CFG_CAUSE_TIMEOUT_MASK), + !!(cause & PCIE_OUTB_ERR_CFG_CAUSE_ABORT_MASK), + !!(cause & PCIE_OUTB_ERR_CFG_CAUSE_UNSUPP_REQ_MASK), + !!(cause & PCIE_OUTB_ERR_CFG_CAUSE_ACC_TIMEOUT_MASK), + !!(cause & PCIE_OUTB_ERR_CFG_CAUSE_ACC_DISABLED_MASK), + !!(cause & PCIE_OUTB_ERR_CFG_CAUSE_ACC_64BIT__MASK)); + } + + if (is_mem_err) { + u32 cause = readl(base + PCIE_OUTB_ERR_MEM_CAUSE); + u32 lo = readl(base + PCIE_OUTB_ERR_MEM_ADDR_LO); + u32 hi = readl(base + PCIE_OUTB_ERR_MEM_ADDR_HI); + u64 addr = ((u64)hi << 32) | (u64)lo; + + dev_err(pcie->dev, "Error: Mem Acc, %s, %s, @0x%llx, lanes=%s\n", + width_str, direction_str, addr, lanes_str); + dev_err(pcie->dev, " Type: TO=%d Abt=%d UnsupReq=%d AccDsble=%d BadAddr=%d\n", + !!(cause & PCIE_OUTB_ERR_MEM_CAUSE_TIMEOUT_MASK), + !!(cause & PCIE_OUTB_ERR_MEM_CAUSE_ABORT_MASK), + !!(cause & PCIE_OUTB_ERR_MEM_CAUSE_UNSUPP_REQ_MASK), + !!(cause & PCIE_OUTB_ERR_MEM_CAUSE_ACC_DISABLED_MASK), + !!(cause & PCIE_OUTB_ERR_MEM_CAUSE_BAD_ADDR_MASK)); + } + + /* Clear the error */ + writel(1, base + PCIE_OUTB_ERR_CLEAR); + + return NOTIFY_DONE; +} + +static void brcm_register_die_notifiers(struct brcm_pcie *pcie) +{ + pcie->die_notifier.notifier_call = dump_pcie_error; + register_die_notifier(&pcie->die_notifier); + atomic_notifier_chain_register(&panic_notifier_list, &pcie->die_notifier); +} + +static void brcm_unregister_die_notifiers(struct brcm_pcie *pcie) +{ + unregister_die_notifier(&pcie->die_notifier); + atomic_notifier_chain_unregister(&panic_notifier_list, &pcie->die_notifier); + pcie->die_notifier.notifier_call = NULL; +} + static int pci_dev_may_wakeup(struct pci_dev *dev, void *data) { bool *ret = data; @@ -1321,6 +1437,8 @@ static int brcm_pcie_remove(struct platform_device *pdev) struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); pci_stop_root_bus(bridge->bus); + if (pcie->has_err_report) + brcm_unregister_die_notifiers(pcie); pci_remove_root_bus(bridge->bus); __brcm_pcie_remove(pcie); @@ -1360,6 +1478,7 @@ static int brcm_pcie_probe(struct platform_device *pdev) pcie->np = np; pcie->reg_offsets = data->offsets; pcie->type = data->type; + pcie->has_err_report = data->has_err_report; pcie->perst_set = data->perst_set; pcie->bridge_sw_init_set = data->bridge_sw_init_set; @@ -1439,6 +1558,9 @@ static int brcm_pcie_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pcie); + if (pcie->has_err_report) + brcm_register_die_notifiers(pcie); + return pci_host_probe(bridge); fail: __brcm_pcie_remove(pcie);