From patchwork Tue Mar 23 14:32:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 1457238 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=uenDb9Q4; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F4YkR3HMxz9sSC for ; Wed, 24 Mar 2021 01:33:03 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E4E153850425; Tue, 23 Mar 2021 14:32:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E4E153850425 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1616509977; bh=OD8TUETbUMDA//1/47XiEZFPgIOIl5Zeu/o4XEjxGz0=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=uenDb9Q43l2P/mB3JPZI8tx392sFRIoGPcokjR3VJ4t1dsRAdxR0N/UjFwzi4WQyF UZ9b73fTwmh+ZAPf3ealYv96LJeFYJ3xY5BSMBEUuE7q6quxJFB2OhsRuO8M2ySv3g 3WpeKPjerxzYBxoamSM2n9i1Vxq+rqukKRgaqOwM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by sourceware.org (Postfix) with ESMTPS id B3059385EC54 for ; Tue, 23 Mar 2021 14:32:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org B3059385EC54 Received: by mail-wr1-x433.google.com with SMTP id c8so8093149wrq.11 for ; Tue, 23 Mar 2021 07:32:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=OD8TUETbUMDA//1/47XiEZFPgIOIl5Zeu/o4XEjxGz0=; b=eRzgfxXrs2WxuCjvVoOQs01+BS40PhTR7PgPxm2bnD8mNCiF7bKpLUTCJWWZ3abk1J nOV40BoOSSEwLg4nE2u9N2Z7N1lIw+aws0B60zd/HEwPJrqL1AbvujsdTOMMvRaZst29 mlYdYNCeSkJ1VEp+AfShtaSbtxgd87ViHvZzqR+yn/hh6L9hTmQ8+aG9kRORqoA2p5K3 WAd/I9vnAVbQZIi8vcpcgViWmrxGr0snrt10bn4/ASPwPBeDisqNhs5KcknnJSQX+LYe iYB71WGd/jb2i1hMFkA+job8oyRMYMaqmn2MwFtqyZjDl72qidW1oS+D+2OglLtf5scM CTNw== X-Gm-Message-State: AOAM533T4JVwNVYOyP/OgW6N4wyyoELhIG8J37w/+1pxLa0Ah8AUBg2N 5VXHbH3+g4rvuK5VdfhtjYnRLScAfIxgdR11 X-Google-Smtp-Source: ABdhPJxB/0aXiq06BiYGqc3ICPTfW4m+gCCjPdy/r6P2gnkNvLnI6OnPmMT0NdJaSqGUVRsGZZ8PFA== X-Received: by 2002:a05:6000:c7:: with SMTP id q7mr4366084wrx.356.1616509972263; Tue, 23 Mar 2021 07:32:52 -0700 (PDT) Received: from localhost.localdomain (static.42.136.251.148.clients.your-server.de. [148.251.136.42]) by smtp.gmail.com with ESMTPSA id h62sm3312102wmf.37.2021.03.23.07.32.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Mar 2021 07:32:51 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH 1/8] testsuite/arm: Add arm_v8_2a_fp16_neon and arm_v8_2a_bf16_neon options Date: Tue, 23 Mar 2021 14:32:43 +0000 Message-Id: <1616509970-26398-2-git-send-email-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616509970-26398-1-git-send-email-christophe.lyon@linaro.org> References: <1616509970-26398-1-git-send-email-christophe.lyon@linaro.org> X-Spam-Status: No, score=-14.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" A few tests lack the dg-add-options directives associated with the dg-require-effective-target they are using. Adding them enables to pass the right float-abi option, and thus make the tests pass instead of emit an error. For instance, we now pass -mfloat-abi=softfp on arm-linux-gnueabi targets and the tests pass. 2021-03-19 Christophe Lyon gcc/testsuite/ * gcc.target/arm/bfloat16_scalar_typecheck.c: Add arm_v8_2a_fp16_neon and arm_v8_2a_bf16_neon. * gcc.target/arm/bfloat16_vector_typecheck_1.c: Likewise. * gcc.target/arm/bfloat16_vector_typecheck_2.c: Likewise. --- gcc/testsuite/gcc.target/arm/bfloat16_scalar_typecheck.c | 2 ++ gcc/testsuite/gcc.target/arm/bfloat16_vector_typecheck_1.c | 2 ++ gcc/testsuite/gcc.target/arm/bfloat16_vector_typecheck_2.c | 6 ++++-- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/bfloat16_scalar_typecheck.c b/gcc/testsuite/gcc.target/arm/bfloat16_scalar_typecheck.c index 672641e..8c80c55 100644 --- a/gcc/testsuite/gcc.target/arm/bfloat16_scalar_typecheck.c +++ b/gcc/testsuite/gcc.target/arm/bfloat16_scalar_typecheck.c @@ -2,6 +2,8 @@ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_ok } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ +/* { dg-add-options arm_v8_2a_fp16_neon } */ +/* { dg-add-options arm_v8_2a_bf16_neon } */ /* { dg-additional-options "-march=armv8.6-a+bf16+fp16 -Wno-pedantic -O3 --save-temps" } */ #include diff --git a/gcc/testsuite/gcc.target/arm/bfloat16_vector_typecheck_1.c b/gcc/testsuite/gcc.target/arm/bfloat16_vector_typecheck_1.c index ba39cb6..f3c350b 100644 --- a/gcc/testsuite/gcc.target/arm/bfloat16_vector_typecheck_1.c +++ b/gcc/testsuite/gcc.target/arm/bfloat16_vector_typecheck_1.c @@ -2,6 +2,8 @@ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_ok } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ +/* { dg-add-options arm_v8_2a_fp16_neon } */ +/* { dg-add-options arm_v8_2a_bf16_neon } */ /* { dg-additional-options "-march=armv8.6-a+bf16+fp16 -Wno-pedantic -O3 --save-temps" } */ #include diff --git a/gcc/testsuite/gcc.target/arm/bfloat16_vector_typecheck_2.c b/gcc/testsuite/gcc.target/arm/bfloat16_vector_typecheck_2.c index 16669dc..de0ade5 100644 --- a/gcc/testsuite/gcc.target/arm/bfloat16_vector_typecheck_2.c +++ b/gcc/testsuite/gcc.target/arm/bfloat16_vector_typecheck_2.c @@ -2,6 +2,8 @@ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ /* { dg-require-effective-target arm_v8_2a_fp16_neon_ok } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ +/* { dg-add-options arm_v8_2a_fp16_neon } */ +/* { dg-add-options arm_v8_2a_bf16_neon } */ /* { dg-additional-options "-march=armv8.6-a+bf16+fp16 -Wno-pedantic -O3 --save-temps" } */ #include @@ -25,8 +27,8 @@ float is_a_float16; double is_a_double; bfloat16x8_t foo3 (void) { return (bfloat16x8_t) 0x12345678123456781234567812345678; } - /* { dg-error {integer constant is too large for its type} "" {target *-*-*} 27 } */ - /* { dg-error {cannot convert a value of type 'long long int' to vector type '__simd128_bfloat16_t' which has different size} "" {target *-*-*} 27 } */ + /* { dg-error {integer constant is too large for its type} "" {target *-*-*} .-1 } */ + /* { dg-error {cannot convert a value of type 'long long int' to vector type '__simd128_bfloat16_t' which has different size} "" {target *-*-*} .-2 } */ bfloat16x8_t footest (bfloat16x8_t vector0) { From patchwork Tue Mar 23 14:32:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 1457240 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; 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[148.251.136.42]) by smtp.gmail.com with ESMTPSA id h62sm3312102wmf.37.2021.03.23.07.32.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Mar 2021 07:32:52 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH 2/8] testsuite/arm: Add arm_v8_2a_i8mm options in gcc.target/arm/simd/vmmla_1.c Date: Tue, 23 Mar 2021 14:32:44 +0000 Message-Id: <1616509970-26398-3-git-send-email-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616509970-26398-1-git-send-email-christophe.lyon@linaro.org> References: <1616509970-26398-1-git-send-email-christophe.lyon@linaro.org> X-Spam-Status: No, score=-14.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" We need to add the options corresponding to the arm_v8_2a_i8mm_ok effective target in order to use the right float-abi option: -mfloat-abi=softfp makes the test pass for arm-linux-gnueabi, while no -mfloat-abi option is needed for arm-linux-gnueabihf. 2021-03-19 Christophe Lyon gcc/testsuite/ * gcc.target/arm/simd/vmmla_1.c: Add arm_v8_2a_i8mm options. --- gcc/testsuite/gcc.target/arm/simd/vmmla_1.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/arm/simd/vmmla_1.c b/gcc/testsuite/gcc.target/arm/simd/vmmla_1.c index d33ebf3..a88c4ea 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vmmla_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vmmla_1.c @@ -1,6 +1,7 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_v8_2a_i8mm_ok } */ -/* { dg-options "-save-temps -O2 -march=armv8.2-a+i8mm -mfpu=auto -mfloat-abi=hard" } */ +/* { dg-options "-save-temps -O2 -mfpu=auto" } */ +/* { dg-add-options arm_v8_2a_i8mm } */ #include "arm_neon.h" From patchwork Tue Mar 23 14:32:45 2021 Content-Type: text/plain; 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[148.251.136.42]) by smtp.gmail.com with ESMTPSA id h62sm3312102wmf.37.2021.03.23.07.32.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Mar 2021 07:32:53 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH 3/8] testsuite/arm: Remove useless -mfloat-abi option Date: Tue, 23 Mar 2021 14:32:45 +0000 Message-Id: <1616509970-26398-4-git-send-email-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616509970-26398-1-git-send-email-christophe.lyon@linaro.org> References: <1616509970-26398-1-git-send-email-christophe.lyon@linaro.org> X-Spam-Status: No, score=-14.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" These tests pass with their current dg-add-options, no need to force -mfloat=abi. I've noticed no impact on armv8_1m-shift-imm-1.c and armv8_1m-shift-reg-1.c, bf16_reinterpret.c now passes on arm-linux-gnueabi and bf16_dup.c now passes on arm-linux-gnueabihf. This allows pr51534.c to pass when forcing -mfloat-abi=soft in runtestflags, otherwise we get an error '-mfloat-abi=soft and -mfloat-abi=hard may not be used together' because we try to compile with both flags. 2021-03-19 Christophe Lyon gcc/testsuite/ * gcc.target/arm/armv8_1m-shift-imm-1.c: Remove -mfloat=abi option. * gcc.target/arm/armv8_1m-shift-reg-1.c: Likewise. * gcc.target/arm/bf16_dup.c: Likewise. * gcc.target/arm/bf16_reinterpret.c: Likewise. * gcc.target/arm/pr51534.c: Remove -mfloat=abi option. --- gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c | 2 +- gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c | 2 +- gcc/testsuite/gcc.target/arm/bf16_dup.c | 2 +- gcc/testsuite/gcc.target/arm/bf16_reinterpret.c | 2 +- gcc/testsuite/gcc.target/arm/pr51534.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c index 883fbb09..84f13e2 100644 --- a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mfloat-abi=softfp -mlittle-endian" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-options "-O2 -mlittle-endian" } */ /* { dg-add-options arm_v8_1m_mve } */ long long longval1; diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c index e125ff8..8668b6b 100644 --- a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mfloat-abi=softfp -mlittle-endian" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-options "-O2 -mlittle-endian" } */ /* { dg-add-options arm_v8_1m_mve } */ long long longval2; diff --git a/gcc/testsuite/gcc.target/arm/bf16_dup.c b/gcc/testsuite/gcc.target/arm/bf16_dup.c index 94be99a..b62bce1 100644 --- a/gcc/testsuite/gcc.target/arm/bf16_dup.c +++ b/gcc/testsuite/gcc.target/arm/bf16_dup.c @@ -1,7 +1,7 @@ /* { dg-do assemble { target { arm*-*-* } } } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ /* { dg-add-options arm_v8_2a_bf16_neon } */ -/* { dg-additional-options "-save-temps -march=armv8.2-a+bf16+fp16 -mfloat-abi=softfp" } */ +/* { dg-additional-options "-save-temps -march=armv8.2-a+bf16+fp16" } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/arm/bf16_reinterpret.c b/gcc/testsuite/gcc.target/arm/bf16_reinterpret.c index e7d30a9..9e36fc5 100644 --- a/gcc/testsuite/gcc.target/arm/bf16_reinterpret.c +++ b/gcc/testsuite/gcc.target/arm/bf16_reinterpret.c @@ -1,7 +1,7 @@ /* { dg-do assemble { target { arm*-*-* } } } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ /* { dg-add-options arm_v8_2a_bf16_neon } */ -/* { dg-additional-options "-save-temps -march=armv8.2-a+fp16+bf16 -mfloat-abi=hard -mfpu=crypto-neon-fp-armv8" } */ +/* { dg-additional-options "-save-temps -march=armv8.2-a+fp16+bf16 -mfpu=crypto-neon-fp-armv8" } */ #include diff --git a/gcc/testsuite/gcc.target/arm/pr51534.c b/gcc/testsuite/gcc.target/arm/pr51534.c index f675a44..3711b45 100644 --- a/gcc/testsuite/gcc.target/arm/pr51534.c +++ b/gcc/testsuite/gcc.target/arm/pr51534.c @@ -3,7 +3,7 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -mfloat-abi=hard -O3" } */ +/* { dg-options "-save-temps -O3" } */ /* { dg-add-options arm_neon } */ #include From patchwork Tue Mar 23 14:32:46 2021 Content-Type: text/plain; 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[148.251.136.42]) by smtp.gmail.com with ESMTPSA id h62sm3312102wmf.37.2021.03.23.07.32.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Mar 2021 07:32:54 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH 4/8] testsuite/arm: Add arm_softfp_ok or arm_hard_ok as needed. Date: Tue, 23 Mar 2021 14:32:46 +0000 Message-Id: <1616509970-26398-5-git-send-email-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616509970-26398-1-git-send-email-christophe.lyon@linaro.org> References: <1616509970-26398-1-git-send-email-christophe.lyon@linaro.org> X-Spam-Status: No, score=-14.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Several tests override the -mfloat-abi option detected by their effective targets. Make sure it is supported, so that these tests are unsupported rather than failures (the inclusion of arm_neon.h otherwise fails for lack of gnu/stubs-*.h) This avoids failures with bfloat16_simd_2_1.c bfloat16_simd_3_1.c bf16_vldn_1.c bf16_vstn_1.c on arm-linux-gnueabi and pr51968.c bfloat16_simd_1_2.c bfloat16_simd_2_2.c bfloat16_simd_3_2.c on arm-linux-gnueabihf. On arm-eabi with default cpu/fpu/mode and a+rm multilibs, bfloat16_simd_2_1.c, bfloat16_simd_3_1.c, bf16_vstn_1.c and bf16_vldn_1.c become unsupported instead of pass because arm_hard_ok fails with "selected processor lacks an FPU". Since we also override the fpu in dg-additional-options, we'd need another effective target (say arm_hard_neon_ok) that would check -mfloat-abi=hard -mfpu=neon at the same time. But we have already so many arm effective targets, it doesn't seem like a good way forward. 2021-03-19 Christophe Lyon gcc/testsuite/ * gcc.target/arm/bfloat16_simd_1_2.c: Add arm_softfp_ok. * gcc.target/arm/bfloat16_simd_2_2.c: Likewise. * gcc.target/arm/bfloat16_simd_3_2.c: Likewise. * gcc.target/arm/pr51968.c: Likewise. * gcc.target/arm/bfloat16_simd_2_1.c: arm_hard_ok. * gcc.target/arm/bfloat16_simd_3_1.c: Likewise. * gcc.target/arm/simd/bf16_vldn_1.c: Likewise. * gcc.target/arm/simd/bf16_vstn_1.c: Likewise. --- gcc/testsuite/gcc.target/arm/bfloat16_simd_1_2.c | 1 + gcc/testsuite/gcc.target/arm/bfloat16_simd_2_1.c | 1 + gcc/testsuite/gcc.target/arm/bfloat16_simd_2_2.c | 1 + gcc/testsuite/gcc.target/arm/bfloat16_simd_3_1.c | 1 + gcc/testsuite/gcc.target/arm/bfloat16_simd_3_2.c | 1 + gcc/testsuite/gcc.target/arm/pr51968.c | 3 ++- gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c | 1 + gcc/testsuite/gcc.target/arm/simd/bf16_vstn_1.c | 1 + 8 files changed, 9 insertions(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/arm/bfloat16_simd_1_2.c b/gcc/testsuite/gcc.target/arm/bfloat16_simd_1_2.c index 4ffcc54..95eecec 100644 --- a/gcc/testsuite/gcc.target/arm/bfloat16_simd_1_2.c +++ b/gcc/testsuite/gcc.target/arm/bfloat16_simd_1_2.c @@ -1,4 +1,5 @@ /* { dg-do assemble { target { arm*-*-* } } } */ +/* { dg-require-effective-target arm_softfp_ok } */ /* { dg-require-effective-target arm_v8_neon_ok } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ /* { dg-additional-options "-march=armv8.2-a+bf16 -mfloat-abi=softfp -mfpu=auto" } */ diff --git a/gcc/testsuite/gcc.target/arm/bfloat16_simd_2_1.c b/gcc/testsuite/gcc.target/arm/bfloat16_simd_2_1.c index 05ee4d8..02b4c41 100644 --- a/gcc/testsuite/gcc.target/arm/bfloat16_simd_2_1.c +++ b/gcc/testsuite/gcc.target/arm/bfloat16_simd_2_1.c @@ -1,4 +1,5 @@ /* { dg-do assemble { target { arm*-*-* } } } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_neon_ok } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ /* { dg-additional-options "-march=armv8.2-a -mfloat-abi=hard -mfpu=neon-fp-armv8" } */ diff --git a/gcc/testsuite/gcc.target/arm/bfloat16_simd_2_2.c b/gcc/testsuite/gcc.target/arm/bfloat16_simd_2_2.c index 15fba31..175bfa5 100644 --- a/gcc/testsuite/gcc.target/arm/bfloat16_simd_2_2.c +++ b/gcc/testsuite/gcc.target/arm/bfloat16_simd_2_2.c @@ -1,4 +1,5 @@ /* { dg-do assemble { target { arm*-*-* } } } */ +/* { dg-require-effective-target arm_softfp_ok } */ /* { dg-require-effective-target arm_v8_neon_ok } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ /* { dg-additional-options "-march=armv8.2-a -mfloat-abi=softfp -mfpu=neon-fp-armv8" } */ diff --git a/gcc/testsuite/gcc.target/arm/bfloat16_simd_3_1.c b/gcc/testsuite/gcc.target/arm/bfloat16_simd_3_1.c index b9b7606..d2326c2 100644 --- a/gcc/testsuite/gcc.target/arm/bfloat16_simd_3_1.c +++ b/gcc/testsuite/gcc.target/arm/bfloat16_simd_3_1.c @@ -1,4 +1,5 @@ /* { dg-do assemble { target { arm*-*-* } } } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_neon_ok } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ /* { dg-additional-options "-march=armv8.2-a -mfloat-abi=hard -mfpu=neon-fp-armv8" } */ diff --git a/gcc/testsuite/gcc.target/arm/bfloat16_simd_3_2.c b/gcc/testsuite/gcc.target/arm/bfloat16_simd_3_2.c index ab1fe10..346253b 100644 --- a/gcc/testsuite/gcc.target/arm/bfloat16_simd_3_2.c +++ b/gcc/testsuite/gcc.target/arm/bfloat16_simd_3_2.c @@ -1,4 +1,5 @@ /* { dg-do assemble { target { arm*-*-* } } } */ +/* { dg-require-effective-target arm_softfp_ok } */ /* { dg-require-effective-target arm_v8_neon_ok } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ /* { dg-additional-options "-march=armv8.2-a -mfloat-abi=softfp -mfpu=neon-fp-armv8" } */ diff --git a/gcc/testsuite/gcc.target/arm/pr51968.c b/gcc/testsuite/gcc.target/arm/pr51968.c index 7814702..c06da48 100644 --- a/gcc/testsuite/gcc.target/arm/pr51968.c +++ b/gcc/testsuite/gcc.target/arm/pr51968.c @@ -1,7 +1,8 @@ /* PR target/51968 */ /* { dg-do compile } */ -/* { dg-options "-O2 -march=armv7-a -mfloat-abi=softfp -mfpu=neon" } */ +/* { dg-require-effective-target arm_softfp_ok } */ /* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -march=armv7-a -mfloat-abi=softfp -mfpu=neon" } */ #include struct T { int8x8x2_t val; }; diff --git a/gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c b/gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c index 663e769..4d91614 100644 --- a/gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c @@ -1,4 +1,5 @@ /* { dg-do assemble } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ /* { dg-add-options arm_v8_2a_bf16_neon } */ /* { dg-additional-options "-save-temps -O2 -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/bf16_vstn_1.c b/gcc/testsuite/gcc.target/arm/simd/bf16_vstn_1.c index 2657b6f..5c6cdd5 100644 --- a/gcc/testsuite/gcc.target/arm/simd/bf16_vstn_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/bf16_vstn_1.c @@ -1,4 +1,5 @@ /* { dg-do assemble } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ /* { dg-add-options arm_v8_2a_bf16_neon } */ /* { dg-additional-options "-save-temps -O2 -mfloat-abi=hard" } */ From patchwork Tue Mar 23 14:32:47 2021 Content-Type: text/plain; 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[148.251.136.42]) by smtp.gmail.com with ESMTPSA id h62sm3312102wmf.37.2021.03.23.07.32.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Mar 2021 07:32:55 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH 5/8] testsuite/arm: Add arm_hard_ok check in armv8_2-fp16-scalar-2.c Date: Tue, 23 Mar 2021 14:32:47 +0000 Message-Id: <1616509970-26398-6-git-send-email-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616509970-26398-1-git-send-email-christophe.lyon@linaro.org> References: <1616509970-26398-1-git-send-email-christophe.lyon@linaro.org> X-Spam-Status: No, score=-14.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" This test relies on -mfloat-abi=hard to pass (otherwise test_mov_imm_[12] directly build the 1.0 fp16 representation via movw r0, #15360 rather than using vmov.f16 s0, #1.0e+0 as expected by scan-assembler-times) Adding the arm_hard_ok check makes the test unsupported eg. on arm-linux-gnueabi instead of reporting a failure. 2021-03-20 Christophe Lyon gcc/testsuite/ * gcc.target/arm/armv8_2-fp16-scalar-2.c: Add arm_hard_ok. --- gcc/testsuite/gcc.target/arm/armv8_2-fp16-scalar-2.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-scalar-2.c b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-scalar-2.c index fa4828d..de5adf3 100644 --- a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-scalar-2.c +++ b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-scalar-2.c @@ -1,7 +1,9 @@ /* { dg-do compile } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */ /* { dg-options "-O2 -std=c11" } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-additional-options "-mfloat-abi=hard" } */ /* Test compiler use of FP16 instructions. */ #include From patchwork Tue Mar 23 14:32:48 2021 Content-Type: text/plain; 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[148.251.136.42]) by smtp.gmail.com with ESMTPSA id h62sm3312102wmf.37.2021.03.23.07.32.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Mar 2021 07:32:57 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH 6/8] testsuite/arm: Fix -mfloat-abi order in arm_v8_2a_bf16_neon_ok_nocache and arm_v8_2a_i8mm_ok_nocache Date: Tue, 23 Mar 2021 14:32:48 +0000 Message-Id: <1616509970-26398-7-git-send-email-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616509970-26398-1-git-send-email-christophe.lyon@linaro.org> References: <1616509970-26398-1-git-send-email-christophe.lyon@linaro.org> X-Spam-Status: No, score=-14.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Make the order in which we try -mfloat-abi options consistent with the other similar effective targets: try softfp first, then hard. This shows that a few tests implicitly rely on -mfloat-abi=hard, so we now check arm_hard_ok where needed. This makes these tests unsupported rather than fail on arm-linux-gnueabi. 2021-03-19 Christophe Lyon gcc/testsuite/ * lib/target-supports.exp (check_effective_target_arm_v8_2a_i8mm_ok_nocache): Fix -mfloat-abi= options order. (check_effective_target_arm_v8_2a_bf16_neon_ok_nocache): Likewise. * gcc.target/arm/bfloat16_scalar_1_1.c: Add arm_hard_ok effective target and -mfloat-abi=hard additional option. * gcc.target/arm/bfloat16_simd_1_1.c: Likewise. * gcc.target/arm/simd/bf16_ma_1.c: Likewise. * gcc.target/arm/simd/bf16_mmla_1.c: Likewise. * gcc.target/arm/simd/vdot-2-1.c: Likewise. * gcc.target/arm/simd/vdot-2-2.c: Likewise. --- gcc/testsuite/gcc.target/arm/bfloat16_scalar_1_1.c | 3 ++- gcc/testsuite/gcc.target/arm/bfloat16_simd_1_1.c | 3 ++- gcc/testsuite/gcc.target/arm/simd/bf16_ma_1.c | 3 ++- gcc/testsuite/gcc.target/arm/simd/bf16_mmla_1.c | 3 ++- gcc/testsuite/gcc.target/arm/simd/vdot-2-1.c | 3 ++- gcc/testsuite/gcc.target/arm/simd/vdot-2-2.c | 3 ++- gcc/testsuite/lib/target-supports.exp | 4 ++-- 7 files changed, 14 insertions(+), 8 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/bfloat16_scalar_1_1.c b/gcc/testsuite/gcc.target/arm/bfloat16_scalar_1_1.c index efcc561..7a6c177 100644 --- a/gcc/testsuite/gcc.target/arm/bfloat16_scalar_1_1.c +++ b/gcc/testsuite/gcc.target/arm/bfloat16_scalar_1_1.c @@ -1,7 +1,8 @@ /* { dg-do assemble { target { arm*-*-* } } } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ /* { dg-add-options arm_v8_2a_bf16_neon } */ -/* { dg-additional-options "-O3 --save-temps -std=gnu90" } */ +/* { dg-additional-options "-O3 --save-temps -std=gnu90 -mfloat-abi=hard" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/arm/bfloat16_simd_1_1.c b/gcc/testsuite/gcc.target/arm/bfloat16_simd_1_1.c index cad7d54..72b4a1b 100644 --- a/gcc/testsuite/gcc.target/arm/bfloat16_simd_1_1.c +++ b/gcc/testsuite/gcc.target/arm/bfloat16_simd_1_1.c @@ -1,7 +1,8 @@ /* { dg-do assemble { target { arm*-*-* } } } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ /* { dg-add-options arm_v8_2a_bf16_neon } */ -/* { dg-additional-options "-O3 --save-temps -std=gnu90" } */ +/* { dg-additional-options "-O3 --save-temps -std=gnu90 -mfloat-abi=hard" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/arm/simd/bf16_ma_1.c b/gcc/testsuite/gcc.target/arm/simd/bf16_ma_1.c index 6729af7..c043049 100644 --- a/gcc/testsuite/gcc.target/arm/simd/bf16_ma_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/bf16_ma_1.c @@ -1,7 +1,8 @@ /* { dg-do assemble } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ /* { dg-add-options arm_v8_2a_bf16_neon } */ -/* { dg-additional-options "-save-temps -O2" } */ +/* { dg-additional-options "-save-temps -O2 -mfloat-abi=hard" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/arm/simd/bf16_mmla_1.c b/gcc/testsuite/gcc.target/arm/simd/bf16_mmla_1.c index 5f9c85b..cc64e23 100644 --- a/gcc/testsuite/gcc.target/arm/simd/bf16_mmla_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/bf16_mmla_1.c @@ -1,7 +1,8 @@ /* { dg-do assemble } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ /* { dg-add-options arm_v8_2a_bf16_neon } */ -/* { dg-additional-options "-save-temps -O2" } */ +/* { dg-additional-options "-save-temps -O2 -mfloat-abi=hard" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/arm/simd/vdot-2-1.c b/gcc/testsuite/gcc.target/arm/simd/vdot-2-1.c index 4d5f07b..88b80cf 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vdot-2-1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vdot-2-1.c @@ -1,7 +1,8 @@ /* { dg-do assemble { target { arm*-*-* } } } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_2a_i8mm_ok } */ /* { dg-add-options arm_v8_2a_i8mm } */ -/* { dg-additional-options "-O -save-temps" } */ +/* { dg-additional-options "-O -save-temps -mfloat-abi=hard" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/arm/simd/vdot-2-2.c b/gcc/testsuite/gcc.target/arm/simd/vdot-2-2.c index b7b76e2..1c74718 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vdot-2-2.c +++ b/gcc/testsuite/gcc.target/arm/simd/vdot-2-2.c @@ -1,7 +1,8 @@ /* { dg-do assemble { target { arm*-*-* } } } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_2a_i8mm_ok } */ /* { dg-add-options arm_v8_2a_i8mm } */ -/* { dg-additional-options "-O -save-temps -mbig-endian" } */ +/* { dg-additional-options "-O -save-temps -mbig-endian -mfloat-abi=hard" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index a90c375..e42d711 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -5267,7 +5267,7 @@ proc check_effective_target_arm_v8_2a_i8mm_ok_nocache { } { # Iterate through sets of options to find the compiler flags that # need to be added to the -march option. - foreach flags {"" "-mfloat-abi=hard -mfpu=neon-fp-armv8" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" } { + foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8" } { if { [check_no_compiler_messages_nocache \ arm_v8_2a_i8mm_ok object { #include @@ -5352,7 +5352,7 @@ proc check_effective_target_arm_v8_2a_bf16_neon_ok_nocache { } { return 0; } - foreach flags {"" "-mfloat-abi=hard -mfpu=neon-fp-armv8" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" } { + foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8" } { if { [check_no_compiler_messages_nocache arm_v8_2a_bf16_neon_ok object { #include #if !defined (__ARM_FEATURE_BF16_VECTOR_ARITHMETIC) From patchwork Tue Mar 23 14:32:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 1457246 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=w4Zg7ezM; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F4Yky2SX6z9sVS for ; Wed, 24 Mar 2021 01:33:30 +1100 (AEDT) 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[148.251.136.42]) by smtp.gmail.com with ESMTPSA id h62sm3312102wmf.37.2021.03.23.07.32.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Mar 2021 07:32:57 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH 7/8] testsuite/arm: Fix -mfloat-abi order in arm_v8_1m_mve_ok_nocache and arm_v8_1m_mve_fp_ok_nocache Date: Tue, 23 Mar 2021 14:32:49 +0000 Message-Id: <1616509970-26398-8-git-send-email-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616509970-26398-1-git-send-email-christophe.lyon@linaro.org> References: <1616509970-26398-1-git-send-email-christophe.lyon@linaro.org> X-Spam-Status: No, score=-14.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Make the order in which we try -mfloat-abi options consistent with the other similar effective targets: try softfp first, then hard. This shows that a few tests implicitly rely on -mfloat-abi=hard, so we add this option via dg-additional-options so that it comes after any potential -mfloat-abi option that the preceding effective-targets might have added. armv8_1m-fpXX-move-1.c tests don't need arm_hard_ok because they don't include arm_mve.h: adding -mfloat-abi=hard when using a soft/softfp toolchain does not lead to the missing include gnu/stubs-*.h error. This patch makes armv8_1m-fpXX-move-1.c pass on arm-linux-gnueabi, and the other tests become unsupported (instead of fail) on this target. On arm-eabi with default cpu/fpu/mode and a+rm multilibs, the same mve/intrinsics/* tests become unsupported instead of pass because arm_hard_ok fails with "selected processor lacks an FPU". Since we also override the fpu via dg-options, we'd need another effective target (say arm_hard_mve_ok) that would check -mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve.fp at the same time. But we have already so many arm effective targets, it doesn't seem like a good way forward. 2021-03-19 Christophe Lyon gcc/testsuite/ * lib/target-supports.exp (check_effective_target_arm_v8_1m_mve_fp_ok_nocache): Fix -mfloat-abi= options order. (check_effective_target_arm_v8_1m_mve_ok_nocache): Likewise * gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Add arm_hard_ok effective target and -mfloat-abi=hard additional option. * gcc.target/arm/mve/intrinsics/mve_vector_int.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_uint.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_uint1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_uint2.c: Likewise. * gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c: Likewise. * gcc.target/arm/armv8_1m-fp16-move-1.c: Add -mfloat-abi=hard additional option. * gcc.target/arm/armv8_1m-fp32-move-1.c: Likewise. * gcc.target/arm/armv8_1m-fp64-move-1.c: Likewise. --- gcc/testsuite/gcc.target/arm/armv8_1m-fp16-move-1.c | 3 ++- gcc/testsuite/gcc.target/arm/armv8_1m-fp32-move-1.c | 3 ++- gcc/testsuite/gcc.target/arm/armv8_1m-fp64-move-1.c | 3 ++- gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c | 2 ++ gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c | 2 ++ gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c | 2 ++ gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c | 2 ++ gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c | 2 ++ gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c | 3 ++- gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c | 3 ++- gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c | 3 ++- gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c | 3 ++- gcc/testsuite/lib/target-supports.exp | 4 ++-- 13 files changed, 26 insertions(+), 9 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-fp16-move-1.c b/gcc/testsuite/gcc.target/arm/armv8_1m-fp16-move-1.c index 67a9f41..f5ab6e7 100644 --- a/gcc/testsuite/gcc.target/arm/armv8_1m-fp16-move-1.c +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-fp16-move-1.c @@ -1,7 +1,8 @@ /* { dg-do compile } */ -/* { dg-options "-O -mfloat-abi=hard -mfp16-format=ieee" } */ +/* { dg-options "-O -mfp16-format=ieee" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-mfloat-abi=hard" } * /* { dg-final { check-function-bodies "**" "" } } */ /* diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-fp32-move-1.c b/gcc/testsuite/gcc.target/arm/armv8_1m-fp32-move-1.c index 1ecb839..2f62e839 100644 --- a/gcc/testsuite/gcc.target/arm/armv8_1m-fp32-move-1.c +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-fp32-move-1.c @@ -1,7 +1,8 @@ /* { dg-do compile } */ -/* { dg-options "-O -mfloat-abi=hard" } */ +/* { dg-options "-O" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-mfloat-abi=hard" } * /* { dg-final { check-function-bodies "**" "" } } */ /* diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-fp64-move-1.c b/gcc/testsuite/gcc.target/arm/armv8_1m-fp64-move-1.c index 3f81350..d236f08 100644 --- a/gcc/testsuite/gcc.target/arm/armv8_1m-fp64-move-1.c +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-fp64-move-1.c @@ -1,7 +1,8 @@ /* { dg-do compile } */ -/* { dg-options "-O -mfloat-abi=hard" } */ +/* { dg-options "-O" } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-mfloat-abi=hard" } * /* { dg-final { check-function-bodies "**" "" } } */ /* diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c index 35f83c6..6728776 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c @@ -1,5 +1,7 @@ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-mfloat-abi=hard" } */ /* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c index e70cbc1..029e02f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c @@ -1,5 +1,7 @@ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-mfloat-abi=hard" } */ /* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c index 0c4e763..c158100 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c @@ -1,5 +1,7 @@ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-mfloat-abi=hard" } */ /* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c index fce69eb..d30fce0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c @@ -1,5 +1,7 @@ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-mfloat-abi=hard" } */ /* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c index e0d6dcb..ae68914 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c @@ -1,5 +1,7 @@ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-mfloat-abi=hard" } */ /* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c index a7457f8..63b2508 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c @@ -1,7 +1,8 @@ /* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-mfloat-abi=hard -O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c index 3cbbef5..a4b900f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c @@ -1,7 +1,8 @@ /* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-mfloat-abi=hard -O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c index e487b73..430df66 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c @@ -1,7 +1,8 @@ /* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-mfloat-abi=hard -O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c index ae57b9c..0e04012 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c @@ -1,7 +1,8 @@ /* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-require-effective-target arm_hard_ok } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-mfloat-abi=hard -O2" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index e42d711..1af7619 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -5025,7 +5025,7 @@ proc check_effective_target_arm_v8_1m_mve_fp_ok_nocache { } { # Iterate through sets of options to find the compiler flags that # need to be added to the -march option. - foreach flags {"" "-mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve.fp" "-mfloat-abi=softfp -mfpu=auto -march=armv8.1-m.main+mve.fp"} { + foreach flags {"" "-mfloat-abi=softfp -mfpu=auto -march=armv8.1-m.main+mve.fp" "-mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve.fp"} { if { [check_no_compiler_messages_nocache \ arm_v8_1m_mve_fp_ok object { #include @@ -5208,7 +5208,7 @@ proc check_effective_target_arm_v8_1m_mve_ok_nocache { } { # Iterate through sets of options to find the compiler flags that # need to be added to the -march option. - foreach flags {"" "-mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve" "-mfloat-abi=softfp -mfpu=auto -march=armv8.1-m.main+mve"} { + foreach flags {"" "-mfloat-abi=softfp -mfpu=auto -march=armv8.1-m.main+mve" "-mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve"} { if { [check_no_compiler_messages_nocache \ arm_v8_1m_mve_ok object { #if !defined (__ARM_FEATURE_MVE) From patchwork Tue Mar 23 14:32:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 1457247 Return-Path: X-Original-To: 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[148.251.136.42]) by smtp.gmail.com with ESMTPSA id h62sm3312102wmf.37.2021.03.23.07.32.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Mar 2021 07:32:58 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH 8/8] testsuite/arm: Add arm_dsp_ok effective target and use it in arm/acle/dsp_arith.c Date: Tue, 23 Mar 2021 14:32:50 +0000 Message-Id: <1616509970-26398-9-git-send-email-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616509970-26398-1-git-send-email-christophe.lyon@linaro.org> References: <1616509970-26398-1-git-send-email-christophe.lyon@linaro.org> X-Spam-Status: No, score=-14.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" gcc.target/arm/acle/dsp_arith.c uses DSP intrinsics, which arm_acle.h defines only with __ARM_FEATURE_DSP, so make the test check for that property rather than arm_qbit_ok. However, the existing arm_dsp effective target only checks if DSP features are supported with the current multilib rather than trying -march and -mfloat-abi options. Thus we introduce a similar effective target, arm_dsp_ok and associated dg-add-options. This makes dsp_arith.c unsupported rather than failed when no option combination is suitable, for instance when running the tests with -mcpu=cortex-m3. 2021-03-19 Christophe Lyon gcc/ * doc/sourcebuild.texi (arm_dsp_ok, arm_dsp): Document. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_arm_dsp_ok_nocache) (check_effective_target_arm_dsp_ok, add_options_for_arm_dsp): New. * gcc.target/arm/acle/dsp_arith.c: Use arm_dsp_ok effective target and add arm_dsp options. --- gcc/doc/sourcebuild.texi | 11 ++++++++ gcc/testsuite/gcc.target/arm/acle/dsp_arith.c | 4 +-- gcc/testsuite/lib/target-supports.exp | 40 +++++++++++++++++++++++++++ 3 files changed, 53 insertions(+), 2 deletions(-) diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 1fa3656..2bc362b 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2044,6 +2044,12 @@ ARM Target supports options suitable for accessing the Q-bit manipulation intrinsics from @code{arm_acle.h}. Some multilibs may be incompatible with these options. +@item arm_dsp_ok +@anchor{arm_dsp_ok} +ARM Target supports options suitable for accessing the DSP intrinsics +from @code{arm_acle.h}. +Some multilibs may be incompatible with these options. + @item arm_softfp_ok @anchor{arm_softfp_ok} ARM target supports the @code{-mfloat-abi=softfp} option. @@ -2778,6 +2784,11 @@ Add options to enable generation of the @code{VFMAL} and @code{VFMSL} instructions, if this is supported by the target; see the @ref{arm_fp16fml_neon_ok} effective target keyword. +@item arm_dsp +Add options for ARM DSP intrinsics support, if this is supported by +the target; see the @ref{arm_dsp_ok,,arm_dsp_ok effective target +keyword}. + @item bind_pic_locally Add the target-specific flags needed to enable functions to bind locally when using pic/PIC passes in the testsuite. diff --git a/gcc/testsuite/gcc.target/arm/acle/dsp_arith.c b/gcc/testsuite/gcc.target/arm/acle/dsp_arith.c index 9ebd55a..7bf458e 100644 --- a/gcc/testsuite/gcc.target/arm/acle/dsp_arith.c +++ b/gcc/testsuite/gcc.target/arm/acle/dsp_arith.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target arm_qbit_ok } */ -/* { dg-add-options arm_qbit } */ +/* { dg-require-effective-target arm_dsp_ok } */ +/* { dg-add-options arm_dsp } */ #include diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 1af7619..733b6c8 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4200,6 +4200,46 @@ proc add_options_for_arm_qbit { flags } { return "$flags $et_arm_qbit_flags" } +# Return 1 if this is an ARM target supporting the DSP intrinsics from +# arm_acle.h. Some multilibs may be incompatible with these options. +# Also set et_arm_dsp_flags to the best options to add. +# arm_acle.h includes stdint.h which can cause trouble with incompatible +# -mfloat-abi= options. +# check_effective_target_arm_dsp also exists, which checks the current +# multilib, without trying other options. + +proc check_effective_target_arm_dsp_ok_nocache { } { + global et_arm_dsp_flags + set et_arm_dsp_flags "" + foreach flags {"" "-march=armv5te" "-march=armv5te -mfloat-abi=softfp" "-march=armv5te -mfloat-abi=hard"} { + if { [check_no_compiler_messages_nocache et_arm_dsp_ok object { + #include + int dummy; + #ifndef __ARM_FEATURE_DSP + #error not DSP + #endif + } "$flags"] } { + set et_arm_dsp_flags $flags + return 1 + } + } + + return 0 +} + +proc check_effective_target_arm_dsp_ok { } { + return [check_cached_effective_target et_arm_dsp_flags \ + check_effective_target_arm_dsp_ok_nocache] +} + +proc add_options_for_arm_dsp { flags } { + if { ! [check_effective_target_arm_dsp_ok] } { + return "$flags" + } + global et_arm_dsp_flags + return "$flags $et_arm_dsp_flags" +} + # Return 1 if this is an ARM target supporting -mfpu=neon without any # -mfloat-abi= option. Useful in tests where add_options is not # supported (such as lto tests).