From patchwork Mon Mar 22 09:22:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Green Wan X-Patchwork-Id: 1456439 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F3pw04q9Kz9sRf for ; Mon, 22 Mar 2021 20:23:44 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BB4A280462; Mon, 22 Mar 2021 10:23:39 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 8835B80475; Mon, 22 Mar 2021 10:23:38 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.2 Received: from transporter.internal.sifive.com (unknown [64.62.193.209]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5712680200 for ; Mon, 22 Mar 2021 10:23:35 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=green.wan@sifive.com Received: from gamma15.internal.sifive.com (gamma15.internal.sifive.com [10.14.21.64]) by transporter.internal.sifive.com (Postfix) with ESMTPS id D7279200A4; Mon, 22 Mar 2021 02:23:32 -0700 (PDT) Received: from localhost (gamma15.internal.sifive.com [local]) by gamma15.internal.sifive.com (OpenSMTPD) with ESMTPA id 12a910bf; Mon, 22 Mar 2021 09:23:32 +0000 (UTC) From: Green Wan To: Cc: Green Wan , Rick Chen , Paul Walmsley , Pragnesh Patel , Bin Meng , Sean Anderson , Atish Patra , Leo Yu-Chi Liang , Simon Glass , Heinrich Schuchardt , u-boot@lists.denx.de (open list) Subject: [RFC PATCH] arch: riscv: cpu: Add callback to init each core Date: Mon, 22 Mar 2021 02:22:55 -0700 Message-Id: <20210322092255.303362-1-green.wan@sifive.com> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean I am looking for a proper place to add some M-mode code in SPL to configure features of each core as early as possible. Try to start the discussion by sending this RFC. I tried mach_cpu_init() as the start. And not sure whether I used it correctly, it seems executed only by the core wins lottery in ./arch/riscv/cpu/start.S. Is there a proper place to add some inits for each core like CSR in section 7.6 in document of U74-MC Core Complex Manual[1]. There are some alternatives to do it such as a) sending IPI to each cores Have to wait for IPI init for each core. And the boot core have to perform the init by itself and send IPIs to other cores. It might not be straightforward. b) hook callback, (like this patch) c) hard code in ./arch/riscv/cpu/start.c [1] https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf Signed-off-by: Green Wan --- arch/riscv/cpu/start.S | 5 +++++ arch/riscv/lib/spl.c | 4 ++++ board/sifive/unmatched/spl.c | 7 +++++++ 3 files changed, 16 insertions(+) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 8589509e01..2629f7e4cc 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -102,6 +102,11 @@ call_board_init_f_0: mv a0, sp jal board_init_f_alloc_reserve +#if CONFIG_IS_ENABLED(RISCV_MMODE) +call_each_cpu_core: + jal mach_cpu_core_init +#endif + /* * Save global data pointer for later. We don't set it here because it * is not initialized yet. diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c index 8baee07bea..e8261d9c19 100644 --- a/arch/riscv/lib/spl.c +++ b/arch/riscv/lib/spl.c @@ -14,6 +14,10 @@ DECLARE_GLOBAL_DATA_PTR; +__weak void mach_cpu_core_init(void) +{ +} + __weak int spl_board_init_f(void) { return 0; diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c index 5e1333b09a..cc466f703a 100644 --- a/board/sifive/unmatched/spl.c +++ b/board/sifive/unmatched/spl.c @@ -22,6 +22,13 @@ #define MODE_SELECT_SD 0xb #define MODE_SELECT_MASK GENMASK(3, 0) +void mach_cpu_core_init(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile ("csrwi 0x7c1, 0"); +#endif +} + int spl_board_init_f(void) { int ret;