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Mon, 15 Mar 2021 22:30:21 -0700 (PDT) From: Ilya Lipnitskiy To: openwrt-devel@lists.openwrt.org, =?utf-8?q?Petr_=C5=A0tetiar?= , Sander Vanheule Cc: Ilya Lipnitskiy Subject: [PATCH 1/2] kernel: backports: mt7530: fix TRGMII mode after reset Date: Mon, 15 Mar 2021 22:29:55 -0700 Message-Id: <20210316052956.418921-1-ilya.lipnitskiy@gmail.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210316_053024_020475_7C79001A X-CRM114-Status: GOOD ( 18.82 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "desiato.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Backport upstream patch that fixes TRGMII mode now that mt7530 is actually resetting the switch on ramips devices. Patches apply to both Linux 5.4 and 5.10, since TRGMII is broken on both. Fixes: 69551a244292 ("ramips: manage low reset lines") Signed-off-by: Ilya Lipnitskiy --- ...setup-core-clock-even-in-TRGMII-mode.patch | 84 +++++++++++++++++++ ...setup-core-clock-even-in-TRGMII-mo [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:62a listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [ilya.lipnitskiy[at]gmail.com] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org Backport upstream patch that fixes TRGMII mode now that mt7530 is actually resetting the switch on ramips devices. Patches apply to both Linux 5.4 and 5.10, since TRGMII is broken on both. Fixes: 69551a244292 ("ramips: manage low reset lines") Signed-off-by: Ilya Lipnitskiy --- ...setup-core-clock-even-in-TRGMII-mode.patch | 84 +++++++++++++++++++ ...setup-core-clock-even-in-TRGMII-mode.patch | 84 +++++++++++++++++++ ...-net-dsa-mt7530-Support-EEE-features.patch | 6 +- ...-net-dsa-mt7530-Support-EEE-features.patch | 6 +- 4 files changed, 174 insertions(+), 6 deletions(-) create mode 100644 target/linux/generic/backport-5.10/780-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch create mode 100644 target/linux/generic/backport-5.4/780-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch diff --git a/target/linux/generic/backport-5.10/780-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch b/target/linux/generic/backport-5.10/780-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch new file mode 100644 index 000000000000..951ae9c664c3 --- /dev/null +++ b/target/linux/generic/backport-5.10/780-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch @@ -0,0 +1,84 @@ +From c3b8e07909dbe67b0d580416c1a5257643a73be7 Mon Sep 17 00:00:00 2001 +From: Ilya Lipnitskiy +Date: Fri, 12 Mar 2021 00:07:03 -0800 +Subject: [PATCH] net: dsa: mt7530: setup core clock even in TRGMII mode + +A recent change to MIPS ralink reset logic made it so mt7530 actually +resets the switch on platforms such as mt7621 (where bit 2 is the reset +line for the switch). That exposed an issue where the switch would not +function properly in TRGMII mode after a reset. + +Reconfigure core clock in TRGMII mode to fix the issue. + +Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled. + +Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines") +Signed-off-by: Ilya Lipnitskiy +Signed-off-by: David S. Miller +--- + drivers/net/dsa/mt7530.c | 52 +++++++++++++++++++--------------------- + 1 file changed, 25 insertions(+), 27 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -435,34 +435,32 @@ mt7530_pad_clk_setup(struct dsa_switch * + TD_DM_DRVP(8) | TD_DM_DRVN(8)); + + /* Setup core clock for MT7530 */ +- if (!trgint) { +- /* Disable MT7530 core clock */ +- core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); +- +- /* Disable PLL, since phy_device has not yet been created +- * provided for phy_[read,write]_mmd_indirect is called, we +- * provide our own core_write_mmd_indirect to complete this +- * function. +- */ +- core_write_mmd_indirect(priv, +- CORE_GSWPLL_GRP1, +- MDIO_MMD_VEND2, +- 0); +- +- /* Set core clock into 500Mhz */ +- core_write(priv, CORE_GSWPLL_GRP2, +- RG_GSWPLL_POSDIV_500M(1) | +- RG_GSWPLL_FBKDIV_500M(25)); +- +- /* Enable PLL */ +- core_write(priv, CORE_GSWPLL_GRP1, +- RG_GSWPLL_EN_PRE | +- RG_GSWPLL_POSDIV_200M(2) | +- RG_GSWPLL_FBKDIV_200M(32)); +- +- /* Enable MT7530 core clock */ +- core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); +- } ++ /* Disable MT7530 core clock */ ++ core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); ++ ++ /* Disable PLL, since phy_device has not yet been created ++ * provided for phy_[read,write]_mmd_indirect is called, we ++ * provide our own core_write_mmd_indirect to complete this ++ * function. ++ */ ++ core_write_mmd_indirect(priv, ++ CORE_GSWPLL_GRP1, ++ MDIO_MMD_VEND2, ++ 0); ++ ++ /* Set core clock into 500Mhz */ ++ core_write(priv, CORE_GSWPLL_GRP2, ++ RG_GSWPLL_POSDIV_500M(1) | ++ RG_GSWPLL_FBKDIV_500M(25)); ++ ++ /* Enable PLL */ ++ core_write(priv, CORE_GSWPLL_GRP1, ++ RG_GSWPLL_EN_PRE | ++ RG_GSWPLL_POSDIV_200M(2) | ++ RG_GSWPLL_FBKDIV_200M(32)); ++ ++ /* Enable MT7530 core clock */ ++ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); + + /* Setup the MT7530 TRGMII Tx Clock */ + core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); diff --git a/target/linux/generic/backport-5.4/780-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch b/target/linux/generic/backport-5.4/780-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch new file mode 100644 index 000000000000..d48d7972942f --- /dev/null +++ b/target/linux/generic/backport-5.4/780-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch @@ -0,0 +1,84 @@ +From c3b8e07909dbe67b0d580416c1a5257643a73be7 Mon Sep 17 00:00:00 2001 +From: Ilya Lipnitskiy +Date: Fri, 12 Mar 2021 00:07:03 -0800 +Subject: [PATCH] net: dsa: mt7530: setup core clock even in TRGMII mode + +A recent change to MIPS ralink reset logic made it so mt7530 actually +resets the switch on platforms such as mt7621 (where bit 2 is the reset +line for the switch). That exposed an issue where the switch would not +function properly in TRGMII mode after a reset. + +Reconfigure core clock in TRGMII mode to fix the issue. + +Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled. + +Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines") +Signed-off-by: Ilya Lipnitskiy +Signed-off-by: David S. Miller +--- + drivers/net/dsa/mt7530.c | 52 +++++++++++++++++++--------------------- + 1 file changed, 25 insertions(+), 27 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -427,34 +427,32 @@ mt7530_pad_clk_setup(struct dsa_switch * + TD_DM_DRVP(8) | TD_DM_DRVN(8)); + + /* Setup core clock for MT7530 */ +- if (!trgint) { +- /* Disable MT7530 core clock */ +- core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); +- +- /* Disable PLL, since phy_device has not yet been created +- * provided for phy_[read,write]_mmd_indirect is called, we +- * provide our own core_write_mmd_indirect to complete this +- * function. +- */ +- core_write_mmd_indirect(priv, +- CORE_GSWPLL_GRP1, +- MDIO_MMD_VEND2, +- 0); +- +- /* Set core clock into 500Mhz */ +- core_write(priv, CORE_GSWPLL_GRP2, +- RG_GSWPLL_POSDIV_500M(1) | +- RG_GSWPLL_FBKDIV_500M(25)); +- +- /* Enable PLL */ +- core_write(priv, CORE_GSWPLL_GRP1, +- RG_GSWPLL_EN_PRE | +- RG_GSWPLL_POSDIV_200M(2) | +- RG_GSWPLL_FBKDIV_200M(32)); +- +- /* Enable MT7530 core clock */ +- core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); +- } ++ /* Disable MT7530 core clock */ ++ core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); ++ ++ /* Disable PLL, since phy_device has not yet been created ++ * provided for phy_[read,write]_mmd_indirect is called, we ++ * provide our own core_write_mmd_indirect to complete this ++ * function. ++ */ ++ core_write_mmd_indirect(priv, ++ CORE_GSWPLL_GRP1, ++ MDIO_MMD_VEND2, ++ 0); ++ ++ /* Set core clock into 500Mhz */ ++ core_write(priv, CORE_GSWPLL_GRP2, ++ RG_GSWPLL_POSDIV_500M(1) | ++ RG_GSWPLL_FBKDIV_500M(25)); ++ ++ /* Enable PLL */ ++ core_write(priv, CORE_GSWPLL_GRP1, ++ RG_GSWPLL_EN_PRE | ++ RG_GSWPLL_POSDIV_200M(2) | ++ RG_GSWPLL_FBKDIV_200M(32)); ++ ++ /* Enable MT7530 core clock */ ++ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); + + /* Setup the MT7530 TRGMII Tx Clock */ + core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); diff --git a/target/linux/generic/pending-5.10/761-net-dsa-mt7530-Support-EEE-features.patch b/target/linux/generic/pending-5.10/761-net-dsa-mt7530-Support-EEE-features.patch index 3e4413db02f1..3e654f4b047e 100644 --- a/target/linux/generic/pending-5.10/761-net-dsa-mt7530-Support-EEE-features.patch +++ b/target/linux/generic/pending-5.10/761-net-dsa-mt7530-Support-EEE-features.patch @@ -9,7 +9,7 @@ Content-Transfer-Encoding: 8bit Signed-off-by: René van Dorst --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2266,9 +2266,13 @@ static void mt753x_phylink_mac_link_up(s +@@ -2264,9 +2264,13 @@ static void mt753x_phylink_mac_link_up(s switch (speed) { case SPEED_1000: mcr |= PMCR_FORCE_SPEED_1000; @@ -23,7 +23,7 @@ Signed-off-by: René van Dorst break; } if (duplex == DUPLEX_FULL) { -@@ -2509,6 +2513,54 @@ mt753x_phy_write(struct dsa_switch *ds, +@@ -2507,6 +2511,54 @@ mt753x_phy_write(struct dsa_switch *ds, return priv->info->phy_write(ds, port, regnum, val); } @@ -78,7 +78,7 @@ Signed-off-by: René van Dorst static const struct dsa_switch_ops mt7530_switch_ops = { .get_tag_protocol = mtk_get_tag_protocol, .setup = mt753x_setup, -@@ -2537,6 +2589,8 @@ static const struct dsa_switch_ops mt753 +@@ -2535,6 +2587,8 @@ static const struct dsa_switch_ops mt753 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart, .phylink_mac_link_down = mt753x_phylink_mac_link_down, .phylink_mac_link_up = mt753x_phylink_mac_link_up, diff --git a/target/linux/generic/pending-5.4/761-net-dsa-mt7530-Support-EEE-features.patch b/target/linux/generic/pending-5.4/761-net-dsa-mt7530-Support-EEE-features.patch index 1822647ff17b..b9ca691f6f11 100644 --- a/target/linux/generic/pending-5.4/761-net-dsa-mt7530-Support-EEE-features.patch +++ b/target/linux/generic/pending-5.4/761-net-dsa-mt7530-Support-EEE-features.patch @@ -9,7 +9,7 @@ Content-Transfer-Encoding: 8bit Signed-off-by: René van Dorst --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1419,9 +1419,13 @@ static void mt7530_phylink_mac_config(st +@@ -1417,9 +1417,13 @@ static void mt7530_phylink_mac_config(st switch (state->speed) { case SPEED_1000: mcr_new |= PMCR_FORCE_SPEED_1000; @@ -23,7 +23,7 @@ Signed-off-by: René van Dorst break; } if (state->duplex == DUPLEX_FULL) { -@@ -1557,6 +1561,54 @@ mt7530_phylink_mac_link_state(struct dsa +@@ -1555,6 +1559,54 @@ mt7530_phylink_mac_link_state(struct dsa return 1; } @@ -78,7 +78,7 @@ Signed-off-by: René van Dorst static const struct dsa_switch_ops mt7530_switch_ops = { .get_tag_protocol = mtk_get_tag_protocol, .setup = mt7530_setup, -@@ -1584,6 +1636,8 @@ static const struct dsa_switch_ops mt753 +@@ -1582,6 +1634,8 @@ static const struct dsa_switch_ops mt753 .phylink_mac_config = mt7530_phylink_mac_config, .phylink_mac_link_down = mt7530_phylink_mac_link_down, .phylink_mac_link_up = mt7530_phylink_mac_link_up, From patchwork Tue Mar 16 05:29:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Lipnitskiy X-Patchwork-Id: 1453678 X-Patchwork-Delegate: gch981213@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "desiato.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: TRGMII allows to run the CPU switch port 6 and GMAC0 at 1.2 Gb. This change should improve performance. Both ER-X and ER-X-SFP have DDR3 RAM, allowing them to take advantage of TRGMII: https://dl.ubnt.com/datasheets/edgemax/EdgeRouter_X_DS.pdf Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1030 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [ilya.lipnitskiy[at]gmail.com] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org TRGMII allows to run the CPU switch port 6 and GMAC0 at 1.2 Gb. This change should improve performance. Both ER-X and ER-X-SFP have DDR3 RAM, allowing them to take advantage of TRGMII: https://dl.ubnt.com/datasheets/edgemax/EdgeRouter_X_DS.pdf Signed-off-by: Ilya Lipnitskiy --- target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dtsi b/target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dtsi index 04eb49bfa359..abda97807e3e 100644 --- a/target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dtsi +++ b/target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dtsi @@ -22,6 +22,7 @@ &gmac0 { mtd-mac-address = <&factory 0x22>; label = "dsa"; + phy-mode = "trgmii"; }; &switch0 { @@ -58,6 +59,10 @@ mtd-mac-address = <&factory 0x22>; mtd-mac-address-increment = <4>; }; + + port@6 { + phy-mode = "trgmii"; + }; }; };