From patchwork Mon Jan 15 17:10:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 860998 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=googlemail.com header.i=@googlemail.com header.b="O5f6fghL"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zL0H35yphz9t2Q for ; Tue, 16 Jan 2018 04:10:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965779AbeAORKi (ORCPT ); Mon, 15 Jan 2018 12:10:38 -0500 Received: from mail-wr0-f196.google.com ([209.85.128.196]:33330 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965699AbeAORKf (ORCPT ); Mon, 15 Jan 2018 12:10:35 -0500 Received: by mail-wr0-f196.google.com with SMTP id p6so12487397wrd.0 for ; Mon, 15 Jan 2018 09:10:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6xqg0g/QXeIhvVbtEGiaxCGXeNk3j97f6FztZF/vbFc=; b=O5f6fghLaAd5Gvk4Z05ODOPYF8AUpQwEkbaudhsAw3WGT5zL7luMxLH8jHE5F0qBv7 OquaZnsiVRlScpdkjFkgPO3nq8G5uzAJ1MoZE9kALjMcdxI2lx6NYwSgiLjfJnz02lNR LqwDzRIJcIwtXvRC8hAzC3R1z03L2IPSZAuZRC/RzowH+WWTO+xEBR9pQZeaajbicNz9 /sT/fQwjzEk7XVxEkZL/ie3zkaemyf4fVe6FRK5QoubT+jZyg6GYUAl7vlr1LBKX592N cT/0LbECiIUqZIHjg6xddPQ0MHxd3JlBhxX7iLb+llVS19+vg3wYye3I19XEiQWpqw/c p9DA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6xqg0g/QXeIhvVbtEGiaxCGXeNk3j97f6FztZF/vbFc=; b=BM8F08uMwis3mJaUSqXmaqYhPQ/K6MKxT7XxTkZZhQ7DUv85/YQkb5Bgh7ONeQZ5At C0mPv7KzkFJGf77QpFsk6EM1quYEXtsmRcBft9aVQ6Sm6QF7YwQkGAKqed1Q+3ZxM2hd Fm+b5FJSpLO3Qt2S6f+8LR82lD426+Z8pBCNrEgcljIGnpPDkg4+ApKc96N/fkIKLFVC zGaLhhsfTxTh+ZWFe8iFS9emHA0EIKP/O1FPAU4UXxXUr74fmxmTUZi1AEEfnksqNXnk WdnKWbyOh0yLEVk2beUG5mfB8lPS1pwpeWCdVB/jo4qtBPDXpZ0deooKhCbmC6sqt9e5 1KhQ== X-Gm-Message-State: AKwxytdKzQ0RmXYdvZLrJo1eSSvJj5QklbQyC14qf7o5LIcp3clLnMXX XNV5l8W88jNUN57Vf0t9cY4= X-Google-Smtp-Source: ACJfBos89MRAJTMr/gP6CP/xPOxen2x7vhaj0jC+syLiZCpPLsvO1ibqdild85MOmwXmxirfKEKSrw== X-Received: by 10.223.152.150 with SMTP id w22mr2182080wrb.74.1516036233735; Mon, 15 Jan 2018 09:10:33 -0800 (PST) Received: from blackbox.darklights.net (p5DD9BF25.dip0.t-ipconnect.de. [93.217.191.37]) by smtp.googlemail.com with ESMTPSA id c11sm142716wrc.8.2018.01.15.09.10.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jan 2018 09:10:32 -0800 (PST) From: Martin Blumenstingl To: davem@davemloft.net, netdev@vger.kernel.org, ingrassia@epigenesys.com Cc: linus.luessing@c0d3.blue, khilman@baylibre.com, linux-amlogic@lists.infradead.org, jbrunet@baylibre.com, narmstrong@baylibre.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, Martin Blumenstingl Subject: [PATCH net-next v5 1/4] net: stmmac: dwmac-meson8b: only configure the clocks in RGMII mode Date: Mon, 15 Jan 2018 18:10:12 +0100 Message-Id: <20180115171015.1118-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180115171015.1118-1-martin.blumenstingl@googlemail.com> References: <20180115171015.1118-1-martin.blumenstingl@googlemail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Neither the m25_div_clk nor the m250_div_clk or m250_mux_clk are used in RMII mode. The m25_div_clk output is routed to the RGMII PHY's "RGMII clock". This means that we don't need to configure the clocks in RMII mode. The driver however did this - with no effect since the clocks are not routed to the PHY in RMII mode. While here also rename meson8b_init_clk to meson8b_init_rgmii_tx_clk to make it easier to understand the code. Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC") Signed-off-by: Martin Blumenstingl Tested-by: Jerome Brunet --- .../net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 46 ++++++++++------------ 1 file changed, 21 insertions(+), 25 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index 4404650b32c5..c6f87e9c4ccb 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -81,7 +81,7 @@ static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, writel(data, dwmac->regs + reg); } -static int meson8b_init_clk(struct meson8b_dwmac *dwmac) +static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) { struct clk_init_data init; int i, ret; @@ -176,7 +176,6 @@ static int meson8b_init_clk(struct meson8b_dwmac *dwmac) static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) { int ret; - unsigned long clk_rate; u8 tx_dly_val = 0; switch (dwmac->phy_mode) { @@ -191,9 +190,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_TXID: - /* Generate a 25MHz clock for the PHY */ - clk_rate = 25 * 1000 * 1000; - /* enable RGMII mode */ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, PRG_ETH0_RGMII_MODE); @@ -204,12 +200,24 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, tx_dly_val << PRG_ETH0_TXDLY_SHIFT); + + ret = clk_prepare_enable(dwmac->m25_div_clk); + if (ret) { + dev_err(&dwmac->pdev->dev, "failed to enable the PHY clock\n"); + return ret; + } + + /* Generate the 25MHz RGMII clock for the PHY */ + ret = clk_set_rate(dwmac->m25_div_clk, 25 * 1000 * 1000); + if (ret) { + clk_disable_unprepare(dwmac->m25_div_clk); + + dev_err(&dwmac->pdev->dev, "failed to set PHY clock\n"); + return ret; + } break; case PHY_INTERFACE_MODE_RMII: - /* Use the rate of the mux clock for the internal RMII PHY */ - clk_rate = clk_get_rate(dwmac->m250_mux_clk); - /* disable RGMII mode -> enables RMII mode */ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, 0); @@ -231,20 +239,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) return -EINVAL; } - ret = clk_prepare_enable(dwmac->m25_div_clk); - if (ret) { - dev_err(&dwmac->pdev->dev, "failed to enable the PHY clock\n"); - return ret; - } - - ret = clk_set_rate(dwmac->m25_div_clk, clk_rate); - if (ret) { - clk_disable_unprepare(dwmac->m25_div_clk); - - dev_err(&dwmac->pdev->dev, "failed to set PHY clock\n"); - return ret; - } - /* enable TX_CLK and PHY_REF_CLK generator */ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK, PRG_ETH0_TX_AND_PHY_REF_CLK); @@ -294,7 +288,7 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) &dwmac->tx_delay_ns)) dwmac->tx_delay_ns = 2; - ret = meson8b_init_clk(dwmac); + ret = meson8b_init_rgmii_tx_clk(dwmac); if (ret) goto err_remove_config_dt; @@ -311,7 +305,8 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) return 0; err_clk_disable: - clk_disable_unprepare(dwmac->m25_div_clk); + if (phy_interface_mode_is_rgmii(dwmac->phy_mode)) + clk_disable_unprepare(dwmac->m25_div_clk); err_remove_config_dt: stmmac_remove_config_dt(pdev, plat_dat); @@ -322,7 +317,8 @@ static int meson8b_dwmac_remove(struct platform_device *pdev) { struct meson8b_dwmac *dwmac = get_stmmac_bsp_priv(&pdev->dev); - clk_disable_unprepare(dwmac->m25_div_clk); + if (phy_interface_mode_is_rgmii(dwmac->phy_mode)) + clk_disable_unprepare(dwmac->m25_div_clk); return stmmac_pltfr_remove(pdev); } From patchwork Mon Jan 15 17:10:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 861004 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=googlemail.com header.i=@googlemail.com header.b="Fhoxf3r6"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zL0JJ1bfcz9ryQ for ; Tue, 16 Jan 2018 04:11:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965718AbeAORLn (ORCPT ); Mon, 15 Jan 2018 12:11:43 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:44183 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965706AbeAORKh (ORCPT ); Mon, 15 Jan 2018 12:10:37 -0500 Received: by mail-wr0-f195.google.com with SMTP id w50so12437158wrc.11 for ; Mon, 15 Jan 2018 09:10:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5Uetw2131cldpwAFA3KCvcvSkq+k14GYul4Ymrf2Q1M=; b=Fhoxf3r6zo23ve3aIrQyJn5+bPQnClNGflv/soOLv3wCgFVUh7i2M/ygJeheAbaBmW +O2eZ2Qwr57lwiYvZWJ9vQqDWpMb+ZvywNMHauFb0XsRufU3ft5zDrlaq5ZjYhDD+ons OvpCsQ0D/EoS7OxvCiRjD+AiGRb86cTtDNVn7cY+xjtM2Ky1MGKrU9Fnp+WD7+D6i6rr rkEwKNAg9zCeCksJTOcb7srrara8jlUeU9lXTwta+nJ7wzqE2kPDpo1ruXa5KKKcYEmj 5pfgReIZDXUDQzMr3sIGgOB/samJFOgqcZzyj+PsQhTc9hUfwL7Bg8svXS2HPYWeQrEl AgZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5Uetw2131cldpwAFA3KCvcvSkq+k14GYul4Ymrf2Q1M=; b=MlJHrSPS2JLYKV3OCVyV6STWrY0BPomkaUxeBVwtEgWG7iiVZng4pA6tg74ULvh/uN o8FLRWmeIe8ZXQiuTNjj4AjRFa785hwX8xvgjltIESkhyEkIEj3GNJuXHh/P2wrgDxqn XGNIBSyT3+3GEMQkk49Dohsx5CX7Je+BHLAekb5n/zeGZK6n8uZU2vMJhDHvOCJ8GTnr W+bfGRCh7CDJuuDvj6AhCKI6IqhoC+wmcCVsipMu3tcCf9j6ptGIi23sXDnnH0vjJzn4 5z+GRXEaaZ1zH+HzWdtx2hjf6dVD9R/G+9CFCW2KImZwPXP50K8FPim0I/YA2sZtT8cd JUpQ== X-Gm-Message-State: AKwxyte9svA8XJStTVpyMzY21l1uU8bARHZPQPxxn7ycQxsrzkVRfzgm efTOIOzgExwl4uP+04ikdNEs/VSL X-Google-Smtp-Source: ACJfBouKH72dc/vMlWrLY1ikve+4T2CwWcgHOatt/d9jiLa4muFoSxoqimGffx3uAJXZW+neRP15sw== X-Received: by 10.223.139.218 with SMTP id w26mr11572379wra.67.1516036235568; Mon, 15 Jan 2018 09:10:35 -0800 (PST) Received: from blackbox.darklights.net (p5DD9BF25.dip0.t-ipconnect.de. [93.217.191.37]) by smtp.googlemail.com with ESMTPSA id c11sm142716wrc.8.2018.01.15.09.10.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jan 2018 09:10:34 -0800 (PST) From: Martin Blumenstingl To: davem@davemloft.net, netdev@vger.kernel.org, ingrassia@epigenesys.com Cc: linus.luessing@c0d3.blue, khilman@baylibre.com, linux-amlogic@lists.infradead.org, jbrunet@baylibre.com, narmstrong@baylibre.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, Martin Blumenstingl Subject: [PATCH net-next v5 2/4] net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration Date: Mon, 15 Jan 2018 18:10:13 +0100 Message-Id: <20180115171015.1118-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180115171015.1118-1-martin.blumenstingl@googlemail.com> References: <20180115171015.1118-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Tests (using an oscilloscope and an Odroid-C1 board with a RTL8211F RGMII PHY) have shown that the PRG_ETH0 register behaves as follows: - bit 4 is a mux to choose between two parent clocks. according to the public S805 datasheet the only supported parent clock is MPLL2 (this was not verified using the oscilloscope). The public S805/S905 datasheet claims that this bit is reserved. - bits 9:7 control a one-based divider (register value 1 means "divide by 1", etc.) for the input clock. we call this clock the "m250_div" clock because it's value is always supposed to be (close to) 250MHz (see below for an explanation). The description in the public S805/S905 datasheet is a bit cryptic, but it comes down to "input clock = 250MHz * value" (which could also be expressed as "250MHz = input clock / value") - there seems to be an internal fixed divide-by-2 clock which takes the output from the m250_div and divides it by 2. This is not unusual on Amlogic SoCs, since the SDIO (MMC) driver also uses an internal fixed divide-by-2 clock. This is not documented in the public S805/S905 datasheet - bit 10 controls a gate clock which enables or disables the RGMII TX clock (which is an output on the MAC/SoC and an input in the PHY). we call this the "rgmii_tx_en" clock. if this bit is set to "0" the RGMII TX clock output is close to 0 The description for this bit in the public S805/S905 datasheet is "Generate 25MHz clock for PHY". Based on these tests it's believed that this is wrong, and should probably read "Generate the 125MHz RGMII TX clock for the PHY" - the RGMII TX clock has to be set to 125MHz - the IP block adjusts the output (automatically) depending on the line speed (RGMII specifies that Gbit connections use a 125MHz clock, 100Mbit/s connections use a 25MHz clock and 10Mbit/s connections use a 2.5MHz clock. only Gbit and 100Mbit/s were tested with an oscilloscope). Due to the requirement that this clock always has to be set to 125MHz and due to the fixed divide-by-2 parent clock this means that m250_div will always end up with a rate of (close to) 250MHz. - bits 6:5 are the TX delay, which is also named "clock phase" in some of Amlogic's older GPL kernel sources. The PHY also has an XTAL_IN pin where a 25MHz clock has to be provided. Tests with the oscilloscope have shown that this is routed to a crystal right next to the RTL8211F PHY. The same seems to be true on the Khadas VIM2 (which uses a GXM SoC) board - however the 25MHz crystal is on the other side of the PCB there. This updates the clocks in the dwmac-meson8b driver by replacing the "m25_div" with the "rgmii_tx_en" clock and additionally introducing a fixed divide-by-2 clock between "m250_div" and "rgmii_tx_en". Now we also need to set a frequency of 125MHz on the RGMII clock (opposed to the 25MHz we set before, with that non-existing divide-by-5-or-10 divider). Special thanks go to Linus Lüssing for testing the various bits and checking the results with an oscilloscope on his Odroid-C1! Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC") Reported-by: Emiliano Ingrassia Signed-off-by: Martin Blumenstingl Acked-by: Jerome Brunet Tested-by: Jerome Brunet --- .../net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 79 +++++++++++++--------- 1 file changed, 47 insertions(+), 32 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index c6f87e9c4ccb..7930a152dd63 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -40,9 +40,7 @@ #define PRG_ETH0_CLK_M250_DIV_SHIFT 7 #define PRG_ETH0_CLK_M250_DIV_WIDTH 3 -/* divides the result of m25_sel by either 5 (bit unset) or 10 (bit set) */ -#define PRG_ETH0_CLK_M25_DIV_SHIFT 10 -#define PRG_ETH0_CLK_M25_DIV_WIDTH 1 +#define PRG_ETH0_RGMII_TX_CLK_EN 10 #define PRG_ETH0_INVERTED_RMII_CLK BIT(11) #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) @@ -63,8 +61,11 @@ struct meson8b_dwmac { struct clk_divider m250_div; struct clk *m250_div_clk; - struct clk_divider m25_div; - struct clk *m25_div_clk; + struct clk_fixed_factor fixed_div2; + struct clk *fixed_div2_clk; + + struct clk_gate rgmii_tx_en; + struct clk *rgmii_tx_en_clk; u32 tx_delay_ns; }; @@ -89,11 +90,6 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) char clk_name[32]; const char *clk_div_parents[1]; const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; - static const struct clk_div_table clk_25m_div_table[] = { - { .val = 0, .div = 5 }, - { .val = 1, .div = 10 }, - { /* sentinel */ }, - }; /* get the mux parents from DT */ for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { @@ -150,25 +146,40 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) if (WARN_ON(IS_ERR(dwmac->m250_div_clk))) return PTR_ERR(dwmac->m250_div_clk); - /* create the m25_div */ - snprintf(clk_name, sizeof(clk_name), "%s#m25_div", dev_name(dev)); + /* create the fixed_div2 */ + snprintf(clk_name, sizeof(clk_name), "%s#fixed_div2", dev_name(dev)); init.name = devm_kstrdup(dev, clk_name, GFP_KERNEL); - init.ops = &clk_divider_ops; - init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; + init.ops = &clk_fixed_factor_ops; + init.flags = CLK_SET_RATE_PARENT; clk_div_parents[0] = __clk_get_name(dwmac->m250_div_clk); init.parent_names = clk_div_parents; init.num_parents = ARRAY_SIZE(clk_div_parents); - dwmac->m25_div.reg = dwmac->regs + PRG_ETH0; - dwmac->m25_div.shift = PRG_ETH0_CLK_M25_DIV_SHIFT; - dwmac->m25_div.width = PRG_ETH0_CLK_M25_DIV_WIDTH; - dwmac->m25_div.table = clk_25m_div_table; - dwmac->m25_div.hw.init = &init; - dwmac->m25_div.flags = CLK_DIVIDER_ALLOW_ZERO; + dwmac->fixed_div2.mult = 1; + dwmac->fixed_div2.div = 2; + dwmac->fixed_div2.hw.init = &init; - dwmac->m25_div_clk = devm_clk_register(dev, &dwmac->m25_div.hw); - if (WARN_ON(IS_ERR(dwmac->m25_div_clk))) - return PTR_ERR(dwmac->m25_div_clk); + dwmac->fixed_div2_clk = devm_clk_register(dev, &dwmac->fixed_div2.hw); + if (WARN_ON(IS_ERR(dwmac->fixed_div2_clk))) + return PTR_ERR(dwmac->fixed_div2_clk); + + /* create the rgmii_tx_en */ + init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#rgmii_tx_en", + dev_name(dev)); + init.ops = &clk_gate_ops; + init.flags = CLK_SET_RATE_PARENT; + clk_div_parents[0] = __clk_get_name(dwmac->fixed_div2_clk); + init.parent_names = clk_div_parents; + init.num_parents = ARRAY_SIZE(clk_div_parents); + + dwmac->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0; + dwmac->rgmii_tx_en.bit_idx = PRG_ETH0_RGMII_TX_CLK_EN; + dwmac->rgmii_tx_en.hw.init = &init; + + dwmac->rgmii_tx_en_clk = devm_clk_register(dev, + &dwmac->rgmii_tx_en.hw); + if (WARN_ON(IS_ERR(dwmac->rgmii_tx_en_clk))) + return PTR_ERR(dwmac->rgmii_tx_en_clk); return 0; } @@ -201,18 +212,22 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, tx_dly_val << PRG_ETH0_TXDLY_SHIFT); - ret = clk_prepare_enable(dwmac->m25_div_clk); + /* Configure the 125MHz RGMII TX clock, the IP block changes + * the output automatically (= without us having to configure + * a register) based on the line-speed (125MHz for Gbit speeds, + * 25MHz for 100Mbit/s and 2.5MHz for 10Mbit/s). + */ + ret = clk_set_rate(dwmac->rgmii_tx_en_clk, 125 * 1000 * 1000); if (ret) { - dev_err(&dwmac->pdev->dev, "failed to enable the PHY clock\n"); + dev_err(&dwmac->pdev->dev, + "failed to set RGMII TX clock\n"); return ret; } - /* Generate the 25MHz RGMII clock for the PHY */ - ret = clk_set_rate(dwmac->m25_div_clk, 25 * 1000 * 1000); + ret = clk_prepare_enable(dwmac->rgmii_tx_en_clk); if (ret) { - clk_disable_unprepare(dwmac->m25_div_clk); - - dev_err(&dwmac->pdev->dev, "failed to set PHY clock\n"); + dev_err(&dwmac->pdev->dev, + "failed to enable the RGMII TX clock\n"); return ret; } break; @@ -306,7 +321,7 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) err_clk_disable: if (phy_interface_mode_is_rgmii(dwmac->phy_mode)) - clk_disable_unprepare(dwmac->m25_div_clk); + clk_disable_unprepare(dwmac->rgmii_tx_en_clk); err_remove_config_dt: stmmac_remove_config_dt(pdev, plat_dat); @@ -318,7 +333,7 @@ static int meson8b_dwmac_remove(struct platform_device *pdev) struct meson8b_dwmac *dwmac = get_stmmac_bsp_priv(&pdev->dev); if (phy_interface_mode_is_rgmii(dwmac->phy_mode)) - clk_disable_unprepare(dwmac->m25_div_clk); + clk_disable_unprepare(dwmac->rgmii_tx_en_clk); return stmmac_pltfr_remove(pdev); } From patchwork Mon Jan 15 17:10:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 861003 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=googlemail.com header.i=@googlemail.com header.b="Ed/ZmlqC"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zL0J90wqSz9t20 for ; Tue, 16 Jan 2018 04:11:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935033AbeAORLe (ORCPT ); Mon, 15 Jan 2018 12:11:34 -0500 Received: from mail-wr0-f194.google.com ([209.85.128.194]:36816 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965718AbeAORKi (ORCPT ); Mon, 15 Jan 2018 12:10:38 -0500 Received: by mail-wr0-f194.google.com with SMTP id d9so12460106wre.3 for ; Mon, 15 Jan 2018 09:10:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4yf9zNolSiimLFO0jvT7BVE66PrqbzQyVDduVAMpIVQ=; b=Ed/ZmlqCfNPNXOyY9WIFZEvd/gSK5Kwmqc+mu19HQch7kHjNPGgCA8Sz6jXgRBjQ3y 7SZb9DqGX+KY0+jPKAswUbjhqLmBc7Oorr8DygfH2XoHoDN9Mi1Y17pOSck57cuvTQBn uvtyLeZ6GcbDuoXYdoM20rYsH3QXt3KezOWjjFm+1rlsileH39rbWD1xzNCcx5t/r536 Vg1xoJ7s/AkO0tLc/5YDD0OJk/U8QqZQJyJbkqXBIlfvKjpJUGALZgRojujjjN5/frtW 66+TVzqxyBXbeTafwOU6Bi65P5ZcdRVwk48bfg4JDTLV/G7MWRVqsTRbnAsnspz08XJY egjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4yf9zNolSiimLFO0jvT7BVE66PrqbzQyVDduVAMpIVQ=; b=O6s3rAOkC5R74mlr5Ws8kquR+hX7MLI6K+38DkwqEXXE5tlRK+aOybpDQLVpJQcQ2u SwWjFDLlfixfTgDALBBGcIUKYNGPEGj3XVs1QZYnUPE7tBZpIWOvHBpvXRyIShIDrsBe Ftau5c0r98Q4zuv1L8bRmOaX44u3TWBNk6/4h64C0SlIrps2wO5eR2AuGVL3I3NbIwuJ mMk9Db0HGn+pYWTHLzxhRKoy6G3LwHBfJXyRF5990vbX32Qidqn2YXvt2Eo17JefWYUI 1h8mUYH64ktZYEcvnv2Z1ylkYxHKV1J2H8Tihg4LDP0aTyhgxx+ObOccGA0Tec/aJ4ss 3wmw== X-Gm-Message-State: AKGB3mI9fi8X3cF3O3IKZKucjly0z2UogW0uk5SBwSu1De5EJegV3/tN K8EtLlMjCgkJek8NyQSmOISqI9Ao X-Google-Smtp-Source: ACJfBov8roZLt+rFWtf/Z49M+klk1YoKj2CGo5ezzmOyXm5gffTztuZjigen/aasHl0CtfcqOuCdtA== X-Received: by 10.223.162.195 with SMTP id t3mr30114099wra.237.1516036237172; Mon, 15 Jan 2018 09:10:37 -0800 (PST) Received: from blackbox.darklights.net (p5DD9BF25.dip0.t-ipconnect.de. [93.217.191.37]) by smtp.googlemail.com with ESMTPSA id c11sm142716wrc.8.2018.01.15.09.10.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jan 2018 09:10:36 -0800 (PST) From: Martin Blumenstingl To: davem@davemloft.net, netdev@vger.kernel.org, ingrassia@epigenesys.com Cc: linus.luessing@c0d3.blue, khilman@baylibre.com, linux-amlogic@lists.infradead.org, jbrunet@baylibre.com, narmstrong@baylibre.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, Martin Blumenstingl Subject: [PATCH net-next v5 3/4] net: stmmac: dwmac-meson8b: fix setting the RGMII TX clock on Meson8b Date: Mon, 15 Jan 2018 18:10:14 +0100 Message-Id: <20180115171015.1118-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180115171015.1118-1-martin.blumenstingl@googlemail.com> References: <20180115171015.1118-1-martin.blumenstingl@googlemail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Meson8b only supports MPLL2 as clock input. The rate of the MPLL2 clock set by Odroid-C1's u-boot is close to (but not exactly) 500MHz. The exact rate is 500002394Hz, which is calculated in drivers/clk/meson/clk-mpll.c using the following formula: DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, (SDM_DEN * n2) + sdm) Odroid-C1's u-boot configures MPLL2 with the following values: - SDM_DEN = 16384 - SDM = 1638 - N2 = 5 The 250MHz clock (m250_div) inside dwmac-meson8b driver is derived from the MPLL2 clock. Due to MPLL2 running slightly faster than 500MHz the common clock framework chooses a divider which is too big to generate the 250MHz clock (a divider of 2 would be needed, but this is rounded up to a divider of 3). This breaks the RTL8211F RGMII PHY on Odroid-C1 because it requires a (close to) 125MHz RGMII TX clock (on Gbit speeds, the IP block internally divides that down to 25MHz on 100Mbit/s connections and 2.5MHz on 10Mbit/s connections - we don't need any special configuration for that). Round the divider to the closest value to prevent this issue on Meson8b. This means we'll now end up with a clock rate for the RGMII TX clock of 125001197Hz (= 125MHz plus 1197Hz), which is close-enough to 125MHz. This has no effect on the Meson GX SoCs since there fclk_div2 is used as input clock, which has a rate of 1000MHz (and thus is divisible cleanly to 250MHz and 125MHz). Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC") Reported-by: Emiliano Ingrassia Signed-off-by: Martin Blumenstingl Reviewed-by: Jerome Brunet Tested-by: Jerome Brunet --- drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index 7930a152dd63..de01ce75a1b1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -140,7 +140,9 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) dwmac->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT; dwmac->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH; dwmac->m250_div.hw.init = &init; - dwmac->m250_div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; + dwmac->m250_div.flags = CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO | + CLK_DIVIDER_ROUND_CLOSEST; dwmac->m250_div_clk = devm_clk_register(dev, &dwmac->m250_div.hw); if (WARN_ON(IS_ERR(dwmac->m250_div_clk))) From patchwork Mon Jan 15 17:10:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 861000 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=googlemail.com header.i=@googlemail.com header.b="R996h1sp"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zL0HB15LDz9t20 for ; Tue, 16 Jan 2018 04:10:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965868AbeAORKo (ORCPT ); Mon, 15 Jan 2018 12:10:44 -0500 Received: from mail-wr0-f193.google.com ([209.85.128.193]:45498 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965829AbeAORKk (ORCPT ); Mon, 15 Jan 2018 12:10:40 -0500 Received: by mail-wr0-f193.google.com with SMTP id 16so12445543wry.12 for ; Mon, 15 Jan 2018 09:10:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=20VeNrdGT2Lu83qpfbzmtUG1+TZSV7h5zSEiJrjx1lo=; b=R996h1spgP5o7qq18JwuIekbm9V1o802wu9fBjTvM4sBR83pADSfmQ4iYcaOvY6c5D dL3+/XAub+uXdDkRCSWgfollIBYJEFcfAmIDT9d2DfzsjBwEuUNzvZSigDPKXJizOxd+ zI9AMD314Y5W2WxZDtSHUFjjdm+txIS1rQ0qIBYh1lE1EcfFcvfGjoFL/9kqjaz+ehNj W7NEQg173oB3C1qQU9szOwYoVJfZIsjgZzY18zq7e4mEFkxB84200DU7wBo/f+vrqOl8 zn7NZryC3OI8kCTmqkn8M2rQRUw8s+fKDFRRQ5M6yJ+yx6T4q0buxv1wRleP0JNyqs6u ir3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=20VeNrdGT2Lu83qpfbzmtUG1+TZSV7h5zSEiJrjx1lo=; b=B1fxloDahCuKkPNtOUZpoPx17fcML0rnE4JN12Bx2neSyfYjRfgTHuuc6SmYWkPx7g ZYA8YoVYrS0MAJkpMo4yRfxjF15N61rggkM9d9Rq/DvMUpTocv1MXq4Ld2KGRxmn7dG5 2d8lptFnK1R1c44DSmDjFwE1tAuL/ovrHHNYC7DSSL6T3JO5miNrQp/riwExHz3WiB51 njWRHVWP0v8q/T446CPDRlLMwtsFcCyJ0oROXNKbLIiwrH1GufO1hf3jPmHLA7qesxkG +vq145/egbRgYN6g1jMEGGcppIILmxixDiT7G31xpaiGJ6y8eIpIHCWLr23mFBF22uG3 HJXA== X-Gm-Message-State: AKGB3mJA70Pw1Lr+Eu6fDB1E3KtBz1lLpKNowGDzGr6AV8LU/+zEb6Ai DWWYuOrPoimFXm/dF7P3iuE= X-Google-Smtp-Source: ACJfBouToPNjWvceXjugbPGqglyF0iJy78xB4B0DQzab9JtVTe9cpA3zs+RgAVzpGyXgYu60KROJkQ== X-Received: by 10.223.169.116 with SMTP id u107mr25190721wrc.3.1516036239094; Mon, 15 Jan 2018 09:10:39 -0800 (PST) Received: from blackbox.darklights.net (p5DD9BF25.dip0.t-ipconnect.de. [93.217.191.37]) by smtp.googlemail.com with ESMTPSA id c11sm142716wrc.8.2018.01.15.09.10.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jan 2018 09:10:38 -0800 (PST) From: Martin Blumenstingl To: davem@davemloft.net, netdev@vger.kernel.org, ingrassia@epigenesys.com Cc: linus.luessing@c0d3.blue, khilman@baylibre.com, linux-amlogic@lists.infradead.org, jbrunet@baylibre.com, narmstrong@baylibre.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, Martin Blumenstingl Subject: [PATCH net-next v5 4/4] net: stmmac: dwmac-meson8b: propagate rate changes to the parent clock Date: Mon, 15 Jan 2018 18:10:15 +0100 Message-Id: <20180115171015.1118-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180115171015.1118-1-martin.blumenstingl@googlemail.com> References: <20180115171015.1118-1-martin.blumenstingl@googlemail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Meson8b the only valid input clock is MPLL2. The bootloader configures that to run at 500002394Hz which cannot be divided evenly down to 125MHz using the m250_div clock. Currently the common clock framework chooses a m250_div of 2 - with the internal fixed "divide by 10" this results in a RGMII TX clock of 125001197Hz (120Hz above the requested 125MHz). Letting the common clock framework propagate the rate changes up to the parent of m250_mux allows us to get the best possible clock rate. With this patch the common clock framework calculates a rate of very-close-to-250MHz (249999701Hz to be exact) for the MPLL2 clock (which is the mux input). Dividing that by 2 (which is an internal, fixed divider for the RGMII TX clock) gives us an RGMII TX clock of 124999850Hz (which is only 150Hz off the requested 125MHz, compared to 1197Hz based on the MPLL2 rate set by u-boot and the Amlogic GPL kernel sources). SoCs from the Meson GX series are not affected by this change because the input clock is FCLK_DIV2 whose rate cannot be changed (which is fine since it's running at 1GHz, so it's already a multiple of 250MHz and 125MHz). Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC") Suggested-by: Jerome Brunet Signed-off-by: Martin Blumenstingl Reviewed-by: Jerome Brunet Tested-by: Jerome Brunet --- drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index de01ce75a1b1..5270d26f0bc6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -112,7 +112,7 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) snprintf(clk_name, sizeof(clk_name), "%s#m250_sel", dev_name(dev)); init.name = clk_name; init.ops = &clk_mux_ops; - init.flags = 0; + init.flags = CLK_SET_RATE_PARENT; init.parent_names = mux_parent_names; init.num_parents = MUX_CLK_NUM_PARENTS;