From patchwork Mon Jan 15 07:14:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 860667 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zKl5Q6gsXz9s7v for ; Mon, 15 Jan 2018 18:16:26 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932511AbeAOHQD (ORCPT ); Mon, 15 Jan 2018 02:16:03 -0500 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76]:41946 "EHLO wens.csie.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754022AbeAOHO7 (ORCPT ); Mon, 15 Jan 2018 02:14:59 -0500 Received: by wens.csie.org (Postfix, from userid 1000) id 268F36005E; Mon, 15 Jan 2018 15:14:54 +0800 (CST) From: Chen-Yu Tsai To: Maxime Ripard , Russell King Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Nicolas Pitre , Dave Martin Subject: [PATCH v3 6/8] dt-bindings: ARM: sunxi: Document A80 SoC secure SRAM usage by SMP hotplug Date: Mon, 15 Jan 2018 15:14:48 +0800 Message-Id: <20180115071450.18355-7-wens@csie.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180115071450.18355-1-wens@csie.org> References: <20180115071450.18355-1-wens@csie.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On the Allwinner A80 SoC the BROM supports hotplugging the primary core (cpu0) by checking two 32bit values at a specific location within the secure SRAM block. This region needs to be reserved and accessible to the SMP code. Document its usage. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/sunxi/smp-sram.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt diff --git a/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt b/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt new file mode 100644 index 000000000000..082e6a9382d3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt @@ -0,0 +1,44 @@ +Allwinner SRAM for smp bringup: +------------------------------------------------ + +Allwinner's A80 SoC uses part of the secure sram for hotplugging of the +primary core (cpu0). Once the core gets powered up it checks if a magic +value is set at a specific location. If it is then the BROM will jump +to the software entry address, instead of executing a standard boot. + +Therefore a reserved section sub-node has to be added to the mmio-sram +declaration. + +Note that this is separate from the Allwinner SRAM controller found in +../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to +any device. + +Also there are no "secure-only" properties. The implementation should +check if this SRAM is usable first. + +Required sub-node properties: +- compatible : depending on the SoC this should be one of: + "allwinner,sun9i-a80-smp-sram" + +The rest of the properties should follow the generic mmio-sram discription +found in ../../misc/sram.txt + +Example: + + sram_b: sram@20000 { + /* 256 KiB secure SRAM at 0x20000 */ + compatible = "mmio-sram"; + reg = <0x00020000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00020000 0x40000>; + + smp-sram@1000 { + /* + * This is checked by BROM to determine if + * cpu0 should jump to SMP entry vector + */ + compatible = "allwinner,sun9i-a80-smp-sram"; + reg = <0x1000 0x8>; + }; + };