From patchwork Thu Mar 4 22:23:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1447580 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=pZ6S1AEW; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ds5bW48dbz9sSC for ; Fri, 5 Mar 2021 09:47:19 +1100 (AEDT) Received: from localhost ([::1]:56652 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lHwkX-0003oi-Gw for incoming@patchwork.ozlabs.org; Thu, 04 Mar 2021 17:47:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55524) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHwNc-0006a2-8t; Thu, 04 Mar 2021 17:23:36 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:35121) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lHwNa-0002OB-PA; Thu, 04 Mar 2021 17:23:35 -0500 Received: by mail-wr1-x435.google.com with SMTP id l12so29379993wry.2; Thu, 04 Mar 2021 14:23:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sZzqDSzbsexD9Zh3aq/wd1p0b53KS/Yn8zf4kVHZSu8=; b=pZ6S1AEWRk7U9b63+cejO+/j9dwOxzbhBvb/obwzh3d8QeY5JA7h7LT5i53dILRgqi BVTqFHfXSNGXLmcRGw5Hi6i4U6iU9W7CO7nOcC2ohPO1noOUzcj6PoSeQWb6g+gueQO7 3g4z6jr4jKb28VZVuUILRZV7iEnGjGda05d8N89Ay+Cxp4KppuDempl3wlXk4tgZNvJ2 zevCyH7Ny/uYfEK5PxTo4fJ3MQ9DuriYqWJ9yc3p+VQSFk+VfUBwdcTYNRwaPJxpzfd/ LinY5lXzDUN5x7Vk/ejifGcZpYJZQK4k1sstoXZmSBmv+sfv0C7HsfjF2HsFSw8l0QQM GEFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sZzqDSzbsexD9Zh3aq/wd1p0b53KS/Yn8zf4kVHZSu8=; b=O2CYgNKSFFOXrmD/wKNktX7WiUcAn+PONW6Z02u3x5ta8bsNmW+v03gtbCWahFCWHA HIL5ZhJjaXQ5yfbEUpVs0tuDTcAQGR6w09LIhh6YNydAwobnNArdgLlE72gmVB7/WLci KTV+9ZqB/Recy42phEDN3rHvyG7xpy722/Mk/CjJZOVnxbJGPDzug4nrMizAbZ/6thZb WNJfogNvxO9PkIBh/r9xoxmyXHWqSESR/b5tvaUdofR/HZ06zFFvnhim8jnpyG1g4YbJ R6NJiNsnFU3Mlpq8tjJSK64Rv93tFXp0fKxmAnMy18cZ5TCXRmDYn/5pQqA8FGswNYxP npVw== X-Gm-Message-State: AOAM531HlUcW2SYNgU4PlDIC3fYHTX4Uq/87zccerETZkrSp8Eq60hhT 4d40Qw1eC1dfNj9ltGslmwVcLME34+M= X-Google-Smtp-Source: ABdhPJytszF6Gh7yIRnn5zIm8ZcLxWTULeMm+RZerO6Mj2TnpXYLHT76N4M87apDUrJ+R7srJ2unTw== X-Received: by 2002:adf:f889:: with SMTP id u9mr6073330wrp.180.1614896611296; Thu, 04 Mar 2021 14:23:31 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id i26sm1289891wmb.18.2021.03.04.14.23.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 14:23:30 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 1/8] sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG Date: Thu, 4 Mar 2021 23:23:16 +0100 Message-Id: <20210304222323.1954755-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org> References: <20210304222323.1954755-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , qemu-riscv@nongnu.org, Eduardo Habkost , David Hildenbrand , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Cornelia Huck , Richard Henderson , Laurent Vivier , Greg Kurz , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Claudio Fontana , Paolo Bonzini , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Invert the #ifdef'ry to easily restrict tcg_exec_init() declaration to CONFIG_TCG. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand Reviewed-by: Claudio Fontana --- include/sysemu/tcg.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h index 00349fb18a7..fddde2b6b9a 100644 --- a/include/sysemu/tcg.h +++ b/include/sysemu/tcg.h @@ -8,13 +8,15 @@ #ifndef SYSEMU_TCG_H #define SYSEMU_TCG_H +#ifndef CONFIG_TCG +#define tcg_enabled() 0 +#else + void tcg_exec_init(unsigned long tb_size, int splitwx); -#ifdef CONFIG_TCG extern bool tcg_allowed; #define tcg_enabled() (tcg_allowed) -#else -#define tcg_enabled() 0 -#endif + +#endif /* CONFIG_TCG */ #endif From patchwork Thu Mar 4 22:23:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1447565 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=UWQyP0l8; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ds5HV4kFgz9sSC for ; Fri, 5 Mar 2021 09:33:26 +1100 (AEDT) Received: from localhost ([::1]:41114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lHwX6-0002Eg-L9 for incoming@patchwork.ozlabs.org; Thu, 04 Mar 2021 17:33:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55554) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHwNh-0006mN-5B; Thu, 04 Mar 2021 17:23:41 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:54722) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lHwNf-0002Qs-GD; Thu, 04 Mar 2021 17:23:40 -0500 Received: by mail-wm1-x335.google.com with SMTP id u187so9370354wmg.4; Thu, 04 Mar 2021 14:23:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OUZUt6DUDETGfeYoWkRPY1ImgFxPl3GPkcbxoc9krNo=; b=UWQyP0l8uyZKNzmMYvUOIW1n9rnYeebf87oLY66bGNcJPc/WT9d+sCaWgS5LOEasCZ KCQZLazOPSW9RjHHtS8Nnuq4iUGbzC2rSjtt1hRvs9xdL4RvNLN4+kQtbjABSCugpnoO TSnqXY3R26ztLy+AG3I9AJzYoD2HEhJsphdG6OhnVAp2Xlj4GE3h9Mi7x6VsZXoLyQ6z 76lZEtmKUvnt673nEJGgiFYHerS5bq+9vt5Hk9FOK+P4pfYwdGUIoBbgAkstYXmnQ8w1 6JF9AvG/e5MoSDh+q0MF8+tJ5R33fwIdskaXZ+P3Ha4oKozJ9M0+/SLav6vd9xCP/7IO CdJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=OUZUt6DUDETGfeYoWkRPY1ImgFxPl3GPkcbxoc9krNo=; b=GVKflYSjLbp+pyQ3t1NMl1MnDvWlIZIEBLNnIr/6L9JD8a7lX9AoEwkSzI+scEwp/+ gknN0hGeUkdpMGiuKGmR8tMY7Ct/pc47ju57lTRDCMa7hKYXXPmQTPkPa9G2ksZYnnto 5/dIS5Q8DHaqCHi2A5fYSKRMoPYAJOxvwdJN1+YKltOHcrKd0av8U6c1h5HNCbqWdLAM 2zYgsMnT/7DlKtQr8gjrOdRJ1nmnkJ7f0FS3s/YRS5kxz9jtx0xP+BFxN2gvAggNvgEe avHT/02FBTDR0pA9dJlw84eVo3A60nieyhCLED71hVh16KygWwC+Ub+YOZj3A/0jEvz9 wxcg== X-Gm-Message-State: AOAM531WonKrkms0CIevjycthj7YHyZHByphyGFOK9/CctaUYzrk5Wed nkGFSaSpY9r4dzjUbmfXTGpjZK53BQE= X-Google-Smtp-Source: ABdhPJxtwTdTVXcDZSftstwccFkSDRQ/eq3WDttHC5Vx/OfQwqayes3YoV41fMb5TqwzjbWn/uResQ== X-Received: by 2002:a05:600c:4ba2:: with SMTP id e34mr5923244wmp.121.1614896616354; Thu, 04 Mar 2021 14:23:36 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id d13sm1058581wro.23.2021.03.04.14.23.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 14:23:35 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 2/8] sysemu/tcg: Restrict qemu_tcg_mttcg_enabled() to TCG Date: Thu, 4 Mar 2021 23:23:17 +0100 Message-Id: <20210304222323.1954755-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org> References: <20210304222323.1954755-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , qemu-riscv@nongnu.org, Eduardo Habkost , David Hildenbrand , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Cornelia Huck , Richard Henderson , Laurent Vivier , Greg Kurz , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Claudio Fontana , Paolo Bonzini , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" qemu_tcg_mttcg_enabled() shouldn't not be used outside of TCG, restrict its declaration. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Claudio Fontana --- include/hw/core/cpu.h | 9 --------- include/sysemu/tcg.h | 9 +++++++++ accel/tcg/cpu-exec.c | 1 + tcg/tcg.c | 1 + 4 files changed, 11 insertions(+), 9 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index e3648338dfe..1376e496a3f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -454,15 +454,6 @@ static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) } } -/** - * qemu_tcg_mttcg_enabled: - * Check whether we are running MultiThread TCG or not. - * - * Returns: %true if we are in MTTCG mode %false otherwise. - */ -extern bool mttcg_enabled; -#define qemu_tcg_mttcg_enabled() (mttcg_enabled) - /** * cpu_paging_enabled: * @cpu: The CPU whose state is to be inspected. diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h index fddde2b6b9a..c16c13c3c69 100644 --- a/include/sysemu/tcg.h +++ b/include/sysemu/tcg.h @@ -17,6 +17,15 @@ void tcg_exec_init(unsigned long tb_size, int splitwx); extern bool tcg_allowed; #define tcg_enabled() (tcg_allowed) +/** + * qemu_tcg_mttcg_enabled: + * Check whether we are running MultiThread TCG or not. + * + * Returns: %true if we are in MTTCG mode %false otherwise. + */ +extern bool mttcg_enabled; +#define qemu_tcg_mttcg_enabled() (mttcg_enabled) + #endif /* CONFIG_TCG */ #endif diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 16e4fe3ccd8..7e67ade35b9 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -39,6 +39,7 @@ #include "hw/i386/apic.h" #endif #include "sysemu/cpus.h" +#include "sysemu/tcg.h" #include "exec/cpu-all.h" #include "sysemu/cpu-timers.h" #include "sysemu/replay.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index 63a12b197bf..4a4dac0bb3e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -65,6 +65,7 @@ #include "elf.h" #include "exec/log.h" #include "sysemu/sysemu.h" +#include "sysemu/tcg.h" /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ From patchwork Thu Mar 4 22:23:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1447569 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=mhBQEJUj; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ds5MP1NLzz9sSC for ; Fri, 5 Mar 2021 09:36:49 +1100 (AEDT) Received: from localhost ([::1]:50404 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lHwaN-0006BM-3E for incoming@patchwork.ozlabs.org; Thu, 04 Mar 2021 17:36:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55580) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHwNl-0006yk-PO; Thu, 04 Mar 2021 17:23:45 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:41027) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lHwNk-0002T2-4D; Thu, 04 Mar 2021 17:23:45 -0500 Received: by mail-wr1-x42c.google.com with SMTP id f12so25577162wrx.8; Thu, 04 Mar 2021 14:23:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Sy2H6EddRIKWB1GSb3aR2E61qw1Oji422a4IED5nUFk=; b=mhBQEJUjEnB/YIfFNMe++iCNWz0lJM5t4I45IW7gGw6pz4iPRjTY1kAOLOwqDZL7ot Wx6nDJEaMvdheasiN9HYKocpqofzOsYa6I9yN1m8YReMdvKynY8+wujDG65Dj6IX098p k6JYfFDivampkjG3tsfEA1KmoNyGSfrG/M8MigxnAEPnhKwY4+/zP1jjPXo7acXe4AYA TOwZP3ZM17VgTe1jvAEzCBdzewFmVfSuRLmAClJ3jCN6LTWOnBm1hmpgbip1RqQ0BYyP xBrgN+hVJKOAwXYAwIDNGgunDGyGfP/KSz6SAnwFUq9yzlHIYY38BES3bHNHoQAUNUie JDhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Sy2H6EddRIKWB1GSb3aR2E61qw1Oji422a4IED5nUFk=; b=Fz/DDcWMhweGUFdmSLt7LsB/jHx2aHgkno7ggjMuG9ODQ99TwU0wv28DtIXkYllBc0 xX65c+8M+5sD8pjdEQvrP/tq1MKKoqzb8RAkGbGxf0L1xihT8q6N4799ydlBBsDkVHiK Axtch0q+lEqu+If+GUpywVkoYwlXctQ0LFIiV30N4azJSoetHu/8wJoraWadsMSafBqQ STUYdpCx/VEv5gQaDCDFTrlPs0c4BgwNjp7GzvjEJWF7lo9LNjoDlt3SzzCHNng6WoUt ZRO9BZmUxaE3wLeZgIfD2ldI3ojS9YQw+xuSkQt929qXOUrD0+6us1DEaE56KEMMN9np yQ2Q== X-Gm-Message-State: AOAM533cGBz1ZW97vwhl7YNSaC6wYmuEx9GE+/VQFGrfoIPKHCrH1Tlt FGCTBv/gnrq6v13buW4No0/7RD1COx8= X-Google-Smtp-Source: ABdhPJwlQm7jfaSajGyc50qshmJurkslHzterzoVGYe4xgchSIPRbdA//wesm2yYXPzLC2j1BiGmUg== X-Received: by 2002:adf:ed49:: with SMTP id u9mr6088176wro.337.1614896621247; Thu, 04 Mar 2021 14:23:41 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id y9sm907051wrm.88.2021.03.04.14.23.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 14:23:40 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 3/8] target/arm: Directly use arm_cpu_has_work instead of CPUClass::has_work Date: Thu, 4 Mar 2021 23:23:18 +0100 Message-Id: <20210304222323.1954755-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org> References: <20210304222323.1954755-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , qemu-riscv@nongnu.org, Eduardo Habkost , David Hildenbrand , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Cornelia Huck , Richard Henderson , Laurent Vivier , Greg Kurz , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Claudio Fontana , Paolo Bonzini , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" There is only one CPUClass::has_work() ARM handler: arm_cpu_has_work(). Avoid a dereference by declaring it in "internals.h" and call it directly in the WFI helper. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Claudio Fontana --- target/arm/internals.h | 1 + target/arm/cpu.c | 2 +- target/arm/op_helper.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 05cebc8597c..1930be08828 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -172,6 +172,7 @@ static inline int r14_bank_number(int mode) void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); +bool arm_cpu_has_work(CPUState *cs); #ifdef CONFIG_TCG void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); #endif /* CONFIG_TCG */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5e018b2a732..6d2d9f2100f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -76,7 +76,7 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, } #endif /* CONFIG_TCG */ -static bool arm_cpu_has_work(CPUState *cs) +bool arm_cpu_has_work(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 65cb37d088f..a4da6f4fde8 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -289,7 +289,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) CPUState *cs = env_cpu(env); int target_el = check_wfx_trap(env, false); - if (cpu_has_work(cs)) { + if (arm_cpu_has_work(cs)) { /* Don't bother to go into our "low power state" if * we would just wake up immediately. */ From patchwork Thu Mar 4 22:23:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1447576 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=OOdbFZ3A; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ds5Vz5TFmz9sW1 for ; Fri, 5 Mar 2021 09:43:23 +1100 (AEDT) Received: from localhost ([::1]:44944 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lHwgi-00079m-JZ for incoming@patchwork.ozlabs.org; Thu, 04 Mar 2021 17:43:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHwNr-0007CJ-4W; Thu, 04 Mar 2021 17:23:51 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:33643) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lHwNp-0002VC-GQ; Thu, 04 Mar 2021 17:23:50 -0500 Received: by mail-wm1-x32a.google.com with SMTP id w203-20020a1c49d40000b029010c706d0642so5202401wma.0; Thu, 04 Mar 2021 14:23:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+rqeUSg2fiW/MftHzeY++j7Aj9yk8dsEiDYp+lRnH1c=; b=OOdbFZ3AqgZkXVIv+J10pQn1XsyaoAYbkMORcRS7S/KbOJ4VSw3ZqOa1gcj+mFkYT5 CeTJC7kMsKIUKqtrc1cLSs6ag0pKQhWPXeeMcMCS1lLITsEV9RHZqjiY9Op/96wgtTNK tZGghF+IwTdq8Y15SeAXpDmHCfMruYiMABL1XpvuU0w1twQWFe/dlMy7YYBP5WDTtaQw 2yRhfHQX2R60nsIyMO1UBSAdOKL23MyEnKqe9fgZ4hs/5KLUXXObr7VJXjhl3qVumlTU eu34/v9omzWDN4/dDT++xEXPKyAz6IzjVIa1qytss59q5pBSZqFhgtu/btW0SUsQRze0 oL2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=+rqeUSg2fiW/MftHzeY++j7Aj9yk8dsEiDYp+lRnH1c=; b=QkkWBC95NVSsixsankuNPXZBRZtasGXTdpF8tWxBpnmMOQG4ZjEbY4Bktk2LEIzg2x DBtV+PWRuCZzkgHuP4AFEcOTLOVs5twf5ceXufcYJIwf4vWFHauOw6fR4mFcOBrSs69J Fpx+MAZqIBqOoQbltD2NXjwqY5zOL9OLaJsrhQeNFK6pEobOocWO9v7VCJjlawBT02Wz Kbux95BlCs116a0wWk3EWxSdz0jYGNHkgfsW8aRb9JHddcAC6ss28JEgCx6ljdj5/jIR pCgJEwp04rdKeCyqKmAED6CaDxB5dSDmqpIKcJDwebInXUpuWFUhy2Tjsnldj7Q8cfPu LQUA== X-Gm-Message-State: AOAM530OsSXntBZA5jGIpMdjtA/sNXwFxsITuc8OxRnBJQtcXsTrUIgR SejtO6KM9v1VFWUbGSrGyo1wbEWZdH4= X-Google-Smtp-Source: ABdhPJzOo7zZJspFMey4e0BrxmgD6sGrw/fGdi9w+8Brl5uG9ELjlvTZp8m6kGMO6R1vYn8QLdFc4A== X-Received: by 2002:a05:600c:2f08:: with SMTP id r8mr5905655wmn.95.1614896626435; Thu, 04 Mar 2021 14:23:46 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id 3sm1162274wry.72.2021.03.04.14.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 14:23:45 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 4/8] target/s390x: Move s390_cpu_has_work to excp_helper.c Date: Thu, 4 Mar 2021 23:23:19 +0100 Message-Id: <20210304222323.1954755-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org> References: <20210304222323.1954755-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , qemu-riscv@nongnu.org, Eduardo Habkost , David Hildenbrand , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Cornelia Huck , Richard Henderson , Laurent Vivier , Greg Kurz , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Claudio Fontana , Paolo Bonzini , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We will restrict the s390_cpu_has_work() function to TCG. First declare it in "internal.h" and move it to excp_helper.c. Reviewed-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daudé --- target/s390x/internal.h | 1 + target/s390x/cpu.c | 17 ----------------- target/s390x/excp_helper.c | 18 ++++++++++++++++++ 3 files changed, 19 insertions(+), 17 deletions(-) diff --git a/target/s390x/internal.h b/target/s390x/internal.h index 11515bb6173..7184e38631c 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -263,6 +263,7 @@ ObjectClass *s390_cpu_class_by_name(const char *name); /* excp_helper.c */ +bool s390_cpu_has_work(CPUState *cs); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index feaf2a6d08f..d57f69e7f7d 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -56,23 +56,6 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.psw.addr = value; } -static bool s390_cpu_has_work(CPUState *cs) -{ - S390CPU *cpu = S390_CPU(cs); - - /* STOPPED cpus can never wake up */ - if (s390_cpu_get_state(cpu) != S390_CPU_STATE_LOAD && - s390_cpu_get_state(cpu) != S390_CPU_STATE_OPERATING) { - return false; - } - - if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { - return false; - } - - return s390_cpu_has_int(cpu); -} - #if !defined(CONFIG_USER_ONLY) /* S390CPUClass::load_normal() */ static void s390_cpu_load_normal(CPUState *s) diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index ce16af394b1..64923ffb83a 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -28,12 +28,30 @@ #include "hw/s390x/ioinst.h" #include "exec/address-spaces.h" #include "tcg_s390x.h" +#include "qapi/qapi-types-machine.h" #ifndef CONFIG_USER_ONLY #include "sysemu/sysemu.h" #include "hw/s390x/s390_flic.h" #include "hw/boards.h" #endif +bool s390_cpu_has_work(CPUState *cs) +{ + S390CPU *cpu = S390_CPU(cs); + + /* STOPPED cpus can never wake up */ + if (s390_cpu_get_state(cpu) != S390_CPU_STATE_LOAD && + s390_cpu_get_state(cpu) != S390_CPU_STATE_OPERATING) { + return false; + } + + if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { + return false; + } + + return s390_cpu_has_int(cpu); +} + void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra) { From patchwork Thu Mar 4 22:23:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1447578 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=ZEreaPaF; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ds5Wb2J8fz9sSC for ; Fri, 5 Mar 2021 09:43:55 +1100 (AEDT) Received: from localhost ([::1]:47428 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lHwhF-00089f-7p for incoming@patchwork.ozlabs.org; Thu, 04 Mar 2021 17:43:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55608) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHwNv-0007Ot-VN; Thu, 04 Mar 2021 17:23:56 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:54715) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lHwNu-0002XD-Ax; Thu, 04 Mar 2021 17:23:55 -0500 Received: by mail-wm1-x32c.google.com with SMTP id u187so9370741wmg.4; Thu, 04 Mar 2021 14:23:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D6LLQzNZyfmEhNL83oc33kVYOp47IlGJ59yVOiNpnRg=; b=ZEreaPaFQBeiuBRNQ2OdnjMAh9JP6F2sp+ucDXyAI7serdBvnEP0GeJdpO1aAGOIeI mIVkrONeWtvTb1SMlHLcC3sGhPN3obe0dPFCNXlQDxIXdWO3p3i0+75JNV1bSQ3SXq+Z YHhbanE6DrpECs+Gf7JQFnk1TcIRvJF8JXp6USUYHyeIUAUv1YMCAxZOBy6LY6sh2+vb v4Nd21MM9wbNeiCvo7RmagK5R3DNdDj4WFkWsU+1u17WCATCjnuqddqsP8euBUJlYwbE 4lHfmE2bwxDXaii4j1U2dCT4sO84hu9SR1qdIVEDLB0K9amKQ6g8RbArTEXXP6kLsuc7 n2GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=D6LLQzNZyfmEhNL83oc33kVYOp47IlGJ59yVOiNpnRg=; b=F2ZmQdebd5vNEMytEvMB1FAyZA36eEpW3JXsKtyIhN3NwW/h5oAwQiBun4ZSAjS+5E D6xEmxar9W8ZjFej5OZ7XSopbWePHVOfB5Gy31wKaLPji3ogNbr9Z3z9l3QKJcaAgvjg eZRa7amZb+uEkC1kv5R2s8dmW35fZRY/yaO6qzlZuNvCCL9AGwAwqFEWwLgrvHeT/u6D YcQbsT/O0d3aYu3ZEl2VvFEv4PcqlG9+HHW7w2JArpzUGQK+oYz4ClUhmz+RamION8A4 ewu4zmWT+TNUCmUe66tSJ6L7GN57wKD/pBIjdu9NG6OYUhhaapir6cnVcetvXrzurEAS ONYA== X-Gm-Message-State: AOAM530gdtcI8/4CRLgNdNiKgspZISNVEglmeDF/jEWkSNLe6MZ+yWIg slaYyUpjvGdfKPtgAHdwGYkWJAEVoQw= X-Google-Smtp-Source: ABdhPJwnMQsUEYN2vxJhPn71ExiDnnAWuGzag6QAtfQlcdTNm3SuZmB5gnJwAeak8v++6xxILl5L3w== X-Received: by 2002:a1c:6309:: with SMTP id x9mr5873815wmb.62.1614896631437; Thu, 04 Mar 2021 14:23:51 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id m9sm1035239wro.52.2021.03.04.14.23.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 14:23:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 5/8] target/ppc: Duplicate the TCGCPUOps structure for POWER CPUs Date: Thu, 4 Mar 2021 23:23:20 +0100 Message-Id: <20210304222323.1954755-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org> References: <20210304222323.1954755-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , qemu-riscv@nongnu.org, Eduardo Habkost , David Hildenbrand , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Cornelia Huck , Richard Henderson , Laurent Vivier , Greg Kurz , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Claudio Fontana , Paolo Bonzini , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" POWER CPUs have specific CPUClass::has_work() handlers. In preparation of moving this field to TCGCPUOps, we need to duplicate the current ppc_tcg_ops structure for the POWER cpus. Signed-off-by: Philippe Mathieu-Daudé Acked-by: David Gibson --- target/ppc/translate_init.c.inc | 69 +++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index 80239077e0b..fe76d0b3773 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -48,6 +48,11 @@ /* #define PPC_DUMP_SPR_ACCESSES */ /* #define USE_APPLE_GDB */ +static const struct TCGCPUOps power7_tcg_ops; +static const struct TCGCPUOps power8_tcg_ops; +static const struct TCGCPUOps power9_tcg_ops; +static const struct TCGCPUOps power10_tcg_ops; + /* * Generic callbacks: * do nothing but store/retrieve spr value @@ -8685,6 +8690,9 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; +#ifdef CONFIG_TCG + cc->tcg_ops = &power7_tcg_ops; +#endif /* CONFIG_TCG */ } static void init_proc_POWER8(CPUPPCState *env) @@ -8863,6 +8871,9 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; +#ifdef CONFIG_TCG + cc->tcg_ops = &power8_tcg_ops; +#endif /* CONFIG_TCG */ } #ifdef CONFIG_SOFTMMU @@ -9081,6 +9092,9 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; +#ifdef CONFIG_TCG + cc->tcg_ops = &power9_tcg_ops; +#endif /* CONFIG_TCG */ } #ifdef CONFIG_SOFTMMU @@ -9292,6 +9306,9 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; +#ifdef CONFIG_TCG + cc->tcg_ops = &power10_tcg_ops; +#endif /* CONFIG_TCG */ } #if !defined(CONFIG_USER_ONLY) @@ -10851,6 +10868,58 @@ static const struct TCGCPUOps ppc_tcg_ops = { .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .tlb_fill = ppc_cpu_tlb_fill, +#ifndef CONFIG_USER_ONLY + .do_interrupt = ppc_cpu_do_interrupt, + .cpu_exec_enter = ppc_cpu_exec_enter, + .cpu_exec_exit = ppc_cpu_exec_exit, + .do_unaligned_access = ppc_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + +static const struct TCGCPUOps power7_tcg_ops = { + .initialize = ppc_translate_init, + .cpu_exec_interrupt = ppc_cpu_exec_interrupt, + .tlb_fill = ppc_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = ppc_cpu_do_interrupt, + .cpu_exec_enter = ppc_cpu_exec_enter, + .cpu_exec_exit = ppc_cpu_exec_exit, + .do_unaligned_access = ppc_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + +static const struct TCGCPUOps power8_tcg_ops = { + .initialize = ppc_translate_init, + .cpu_exec_interrupt = ppc_cpu_exec_interrupt, + .tlb_fill = ppc_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = ppc_cpu_do_interrupt, + .cpu_exec_enter = ppc_cpu_exec_enter, + .cpu_exec_exit = ppc_cpu_exec_exit, + .do_unaligned_access = ppc_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + +static const struct TCGCPUOps power9_tcg_ops = { + .initialize = ppc_translate_init, + .cpu_exec_interrupt = ppc_cpu_exec_interrupt, + .tlb_fill = ppc_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = ppc_cpu_do_interrupt, + .cpu_exec_enter = ppc_cpu_exec_enter, + .cpu_exec_exit = ppc_cpu_exec_exit, + .do_unaligned_access = ppc_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + +static const struct TCGCPUOps power10_tcg_ops = { + .initialize = ppc_translate_init, + .cpu_exec_interrupt = ppc_cpu_exec_interrupt, + .tlb_fill = ppc_cpu_tlb_fill, + #ifndef CONFIG_USER_ONLY .do_interrupt = ppc_cpu_do_interrupt, .cpu_exec_enter = ppc_cpu_exec_enter, From patchwork Thu Mar 4 22:23:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1447582 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=hvqFY9/8; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ds5hQ6p2Yz9sW8 for ; Fri, 5 Mar 2021 09:51:34 +1100 (AEDT) Received: from localhost ([::1]:37314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lHwoe-0007s6-Pu for incoming@patchwork.ozlabs.org; Thu, 04 Mar 2021 17:51:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55620) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHwO0-0007SI-PO; Thu, 04 Mar 2021 17:24:01 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:39820) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lHwNz-0002Za-D1; Thu, 04 Mar 2021 17:24:00 -0500 Received: by mail-wr1-x434.google.com with SMTP id b18so22907486wrn.6; Thu, 04 Mar 2021 14:23:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zTTkw6DpezJcV9ta0hw/wRNRNKjGMDk4hmoteXF2Vxs=; b=hvqFY9/8x2pQ3MdLFvz9iIu5R1VUd7sy7YKrg48MftwYJzQStGNpMagbf/ibcJtbsS XwMp3hHqRmtfVrMPBBQDd1vlpCwXpxjWamEvUSlS/G7NT4eCaEshL3K+OwE40c3588/m 50TiCJYqL7y8Ez0+9t43ZY3RJpwiVrGzZ7u94im5FDNBfSmpjkGTH5KiQuIF5Yc6Z2Bc WsUOkX/KedqBhzkGeO2/xO1TKURwjQ6X91NvLNkZ0/WhdN5Ws1MQ3DmWzQVdQE6HPb0x OdYsOgznLGyHSDXvKBheVqDG15OBVEpabtX2QNTIBCPgXltANzN1n/5VYgNPLFdlMPQr hZEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=zTTkw6DpezJcV9ta0hw/wRNRNKjGMDk4hmoteXF2Vxs=; b=NpAB2+MR4nGVogjCPU9nOdgQrFvTBRO0lBCjL6rWrt8fXMsjRHLHqI6zERNWSVf2ux tnZkq1s63wSs+E5YnxrPwX/Jpx7zY8r+6OTmwyB2cA8dFwScJeynW0WOUyvOUc35RRy9 rPUHBSwFXk1cQBpE819IyxRwqf5sxFJQJckwvB0joe5tdrRbeuTC/wzqm8BxSZnHcT63 PqgL1f9st7r+fvcVR7iJ910FRHDCfuURJZ8fHP4g9sKJEGa8JzwQOi13dhbvcvGtGk8r 0Z64EnbZigRDJHXEqhS69yyG2QM9LgMyQaIHN4sXH80OYj4bT1TmPQQ6nfkqhAYkSQn9 c/cw== X-Gm-Message-State: AOAM532KYUNSZsK6exDlDPhDIEyZxYQNEMokgqHawOKSoDjR9Oyvnt7o 5C3VtbMZFKElY2I239Ns0FmQiZgbMPY= X-Google-Smtp-Source: ABdhPJx8klgY2qVo7VdLbu0491Gt8xseOQ7+EflJJtemygc1y7YGsLshyoZBnw2q0r4/3MVoDqd5BQ== X-Received: by 2002:a5d:400f:: with SMTP id n15mr5930136wrp.89.1614896636541; Thu, 04 Mar 2021 14:23:56 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id j12sm1165596wrt.27.2021.03.04.14.23.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 14:23:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 6/8] cpu: Declare cpu_has_work() in 'sysemu/tcg.h' Date: Thu, 4 Mar 2021 23:23:21 +0100 Message-Id: <20210304222323.1954755-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org> References: <20210304222323.1954755-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , qemu-riscv@nongnu.org, Eduardo Habkost , David Hildenbrand , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Cornelia Huck , Richard Henderson , Laurent Vivier , Greg Kurz , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Claudio Fontana , Paolo Bonzini , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We can only check if a vCPU has work with TCG. Move the cpu_has_work() prototype to "sysemu/tcg.h". Signed-off-by: Philippe Mathieu-Daudé --- RFC: could another accelerator do that? can we rename this tcg_vcpu_has_work()? --- include/hw/core/cpu.h | 16 ---------------- include/sysemu/tcg.h | 11 +++++++++++ accel/tcg/cpu-exec.c | 7 +++++++ softmmu/cpus.c | 1 + 4 files changed, 19 insertions(+), 16 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 1376e496a3f..66109bcca35 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -670,22 +670,6 @@ CPUState *cpu_create(const char *typename); */ const char *parse_cpu_option(const char *cpu_option); -/** - * cpu_has_work: - * @cpu: The vCPU to check. - * - * Checks whether the CPU has work to do. - * - * Returns: %true if the CPU has work, %false otherwise. - */ -static inline bool cpu_has_work(CPUState *cpu) -{ - CPUClass *cc = CPU_GET_CLASS(cpu); - - g_assert(cc->has_work); - return cc->has_work(cpu); -} - /** * qemu_cpu_is_self: * @cpu: The vCPU to check against. diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h index c16c13c3c69..3d46b0a7a93 100644 --- a/include/sysemu/tcg.h +++ b/include/sysemu/tcg.h @@ -10,6 +10,7 @@ #ifndef CONFIG_TCG #define tcg_enabled() 0 +#define cpu_has_work(cpu) false #else void tcg_exec_init(unsigned long tb_size, int splitwx); @@ -26,6 +27,16 @@ extern bool tcg_allowed; extern bool mttcg_enabled; #define qemu_tcg_mttcg_enabled() (mttcg_enabled) +/** + * cpu_has_work: + * @cpu: The vCPU to check. + * + * Checks whether the CPU has work to do. + * + * Returns: %true if the CPU has work, %false otherwise. + */ +bool cpu_has_work(CPUState *cpu); + #endif /* CONFIG_TCG */ #endif diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 7e67ade35b9..b9ce36e59e2 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -447,6 +447,13 @@ static inline TranslationBlock *tb_find(CPUState *cpu, return tb; } +bool cpu_has_work(CPUState *cpu) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + + return cc->has_work(cpu); +} + static inline bool cpu_handle_halt(CPUState *cpu) { if (cpu->halted) { diff --git a/softmmu/cpus.c b/softmmu/cpus.c index a7ee431187a..548ab9236f1 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -42,6 +42,7 @@ #include "sysemu/runstate.h" #include "sysemu/cpu-timers.h" #include "sysemu/whpx.h" +#include "sysemu/tcg.h" #include "hw/boards.h" #include "hw/hw.h" From patchwork Thu Mar 4 22:23:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1447579 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=I3dGCnIM; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ds5bN6nL4z9sSC for ; Fri, 5 Mar 2021 09:47:12 +1100 (AEDT) Received: from localhost ([::1]:55874 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lHwkQ-0003UJ-SN for incoming@patchwork.ozlabs.org; Thu, 04 Mar 2021 17:47:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55632) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHwO9-0007nu-AY; Thu, 04 Mar 2021 17:24:09 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:38145) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lHwO6-0002cp-GL; Thu, 04 Mar 2021 17:24:09 -0500 Received: by mail-wm1-x32e.google.com with SMTP id h7so1846291wmf.3; Thu, 04 Mar 2021 14:24:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nHP7+H+pUpBFPq7GhPyMRNWKOjnIMPvaEGxuyNvHJzs=; b=I3dGCnIMFZALivYxWDyIIZvhm8Lr/tUBMUiRV+I2DYDZ+ri/NKGJesaPU4RimErCNZ bp7OB4m0wdRpmsWyaGzrcZBAczwWqP5jbtOYLAzvm/4yexC0ZKvC//m8hdOJr+kBSgGM 1FfSRwiKihAD7hk9GT50rvMAEh3+7qhyW7xiJ4cQpLFde4Ma7runXu0WIgeG7k+ndLTS 1dLkIySzW0pfquwAdwywSFQ+AcqY/HdNSqlXCPgotq+sEeBgeO0w+uzR56Glm7eMtqBy cTubW6Qa45wbPyPTU8JlpVVEMH7pk/mGmPjeW4keIKv+Z0szWlaYENOT/2wwicP8kV3N aFdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=nHP7+H+pUpBFPq7GhPyMRNWKOjnIMPvaEGxuyNvHJzs=; b=EBF2oc1kJQrkUk0dOjhqRg9MNBFzloqqmdsV7/bI2QMvya6kTsEM8ZbAZ3J92aVo6e SmLMlHuAuhLpbZ0973RLvmVjjjTk1NZDbU3t7iRfPqlQpm7cVGPz+9TrN38y+Yu/L8sl p3t+BJYK7aD8mUbDY7fQfjWUOVN3Wi7PbwYSayXOE+xpfEhYSs9R47FhNq9rPAcZCZen fA1YBpNzlrNhPRnw0YgHw5Ke0ollzW/+0clNwvixI+atzyfGWwe4tcwHAJnIrH1Ct9li wLrwGvzxJEfHCDYS8EE7bBPaduW1q312Sh+G5t5Y3Zd/b41IOxJmjLDHS1CxecOPHB0G Sqow== X-Gm-Message-State: AOAM533WR60qJpNV462niXcgLpTLUnZEy/W8HpntGldLreCM2bys77K+ +Tktf/fNFPJ1UVMQtr/lBpg8gi8Id8o= X-Google-Smtp-Source: ABdhPJxsxA17v1Gnk1btW5Iksqs5ErEa/VKmfoXpmRBTcwvAgs1B6TGV/Jbl7FGEmLku5rGipnyNTg== X-Received: by 2002:a1c:4b0a:: with SMTP id y10mr5736938wma.141.1614896642933; Thu, 04 Mar 2021 14:24:02 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id m132sm1400938wmf.45.2021.03.04.14.24.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 14:24:02 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 7/8] cpu: Move CPUClass::has_work() to TCGCPUOps Date: Thu, 4 Mar 2021 23:23:22 +0100 Message-Id: <20210304222323.1954755-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org> References: <20210304222323.1954755-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Sarah Harris , Chris Wulff , Sagar Karandikar , David Hildenbrand , Anthony Green , Mark Cave-Ayland , Aleksandar Rikalo , Laurent Vivier , Max Filippov , Taylor Simpson , Alistair Francis , "Edgar E. Iglesias" , Guan Xuetao , Marek Vasut , Yoshinori Sato , Claudio Fontana , Palmer Dabbelt , Artyom Tarasenko , Thomas Huth , Eduardo Habkost , Richard Henderson , Greg Kurz , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Michael Rolnik , Stafford Horne , David Gibson , qemu-riscv@nongnu.org, Bastian Koppelmann , Cornelia Huck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Michael Walle , qemu-ppc@nongnu.org, Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We can only check if a vCPU has work with TCG. Restrict the has_work() handler to TCG by moving it to the TCGCPUOps structure, and adapt all the targets. cpu_common_has_work() is removed as being inlined in cpu_has_work(). Reviewed-by: Taylor Simpson Signed-off-by: Philippe Mathieu-Daudé Acked-by: David Gibson --- v2: - finished PPC - check cc->tcg_ops->has_work non-null (thuth) --- include/hw/core/cpu.h | 2 -- include/hw/core/tcg-cpu-ops.h | 4 ++++ accel/tcg/cpu-exec.c | 6 +++++- hw/core/cpu.c | 6 ------ target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 3 ++- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 7 +------ target/i386/tcg/tcg-cpu.c | 6 ++++++ target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tilegx/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 10 +++++----- 29 files changed, 44 insertions(+), 42 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 66109bcca35..8efea289e7e 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -86,7 +86,6 @@ struct AccelCPUClass; * instantiatable CPU type. * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. - * @has_work: Callback for checking if there is work to do. * @virtio_is_big_endian: Callback to return %true if a CPU which supports * runtime configurable endianness is currently big-endian. Non-configurable * CPUs can use the default implementation of this method. This method should @@ -149,7 +148,6 @@ struct CPUClass { void (*parse_features)(const char *typename, char *str, Error **errp); int reset_dump_flags; - bool (*has_work)(CPUState *cpu); bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 72d791438c2..f5d44ba59f3 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -19,6 +19,10 @@ struct TCGCPUOps { * Called when the first CPU is realized. */ void (*initialize)(void); + /** + * @has_work: Callback for checking if there is work to do + */ + bool (*has_work)(CPUState *cpu); /** * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock * diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index b9ce36e59e2..4e73550f981 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -451,7 +451,11 @@ bool cpu_has_work(CPUState *cpu) { CPUClass *cc = CPU_GET_CLASS(cpu); - return cc->has_work(cpu); + if (cc->tcg_ops->has_work) { + return cc->tcg_ops->has_work(cpu); + } + + return false; } static inline bool cpu_handle_halt(CPUState *cpu) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 00330ba07de..3110867c3a3 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -261,11 +261,6 @@ static void cpu_common_reset(DeviceState *dev) } } -static bool cpu_common_has_work(CPUState *cs) -{ - return false; -} - ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model) { CPUClass *cc = CPU_CLASS(object_class_by_name(typename)); @@ -397,7 +392,6 @@ static void cpu_class_init(ObjectClass *klass, void *data) k->parse_features = cpu_common_parse_features; k->get_arch_id = cpu_common_get_arch_id; - k->has_work = cpu_common_has_work; k->get_paging_enabled = cpu_common_get_paging_enabled; k->get_memory_mapping = cpu_common_get_memory_mapping; k->write_elf32_qemunote = cpu_common_write_elf32_qemunote; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index e50ae7bef06..57e88bbe7fd 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -210,6 +210,7 @@ static void alpha_cpu_initfn(Object *obj) static const struct TCGCPUOps alpha_tcg_ops = { .initialize = alpha_translate_init, + .has_work = alpha_cpu_has_work, .cpu_exec_interrupt = alpha_cpu_exec_interrupt, .tlb_fill = alpha_cpu_tlb_fill, @@ -230,7 +231,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) &acc->parent_realize); cc->class_by_name = alpha_cpu_class_by_name; - cc->has_work = alpha_cpu_has_work; cc->dump_state = alpha_cpu_dump_state; cc->set_pc = alpha_cpu_set_pc; cc->gdb_read_register = alpha_cpu_gdb_read_register; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6d2d9f2100f..7181deee84a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2263,6 +2263,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) #ifdef CONFIG_TCG static const struct TCGCPUOps arm_tcg_ops = { .initialize = arm_translate_init, + .has_work = arm_cpu_has_work, .synchronize_from_tb = arm_cpu_synchronize_from_tb, .cpu_exec_interrupt = arm_cpu_exec_interrupt, .tlb_fill = arm_cpu_tlb_fill, @@ -2291,7 +2292,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); cc->class_by_name = arm_cpu_class_by_name; - cc->has_work = arm_cpu_has_work; cc->dump_state = arm_cpu_dump_state; cc->set_pc = arm_cpu_set_pc; cc->gdb_read_register = arm_cpu_gdb_read_register; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 7d0ab606ae1..7416aa805d0 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -188,6 +188,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) static const struct TCGCPUOps avr_tcg_ops = { .initialize = avr_cpu_tcg_init, + .has_work = avr_cpu_has_work, .synchronize_from_tb = avr_cpu_synchronize_from_tb, .cpu_exec_interrupt = avr_cpu_exec_interrupt, .tlb_fill = avr_cpu_tlb_fill, @@ -208,7 +209,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = avr_cpu_class_by_name; - cc->has_work = avr_cpu_has_work; cc->dump_state = avr_cpu_dump_state; cc->set_pc = avr_cpu_set_pc; cc->memory_rw_debug = avr_cpu_memory_rw_debug; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 4586302ba39..eef76a211f1 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -197,6 +197,7 @@ static void cris_cpu_initfn(Object *obj) static const struct TCGCPUOps crisv10_tcg_ops = { .initialize = cris_initialize_crisv10_tcg, + .has_work = cris_cpu_has_work, .cpu_exec_interrupt = cris_cpu_exec_interrupt, .tlb_fill = cris_cpu_tlb_fill, @@ -207,6 +208,7 @@ static const struct TCGCPUOps crisv10_tcg_ops = { static const struct TCGCPUOps crisv32_tcg_ops = { .initialize = cris_initialize_tcg, + .has_work = cris_cpu_has_work, .cpu_exec_interrupt = cris_cpu_exec_interrupt, .tlb_fill = cris_cpu_tlb_fill, @@ -286,7 +288,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset); cc->class_by_name = cris_cpu_class_by_name; - cc->has_work = cris_cpu_has_work; cc->dump_state = cris_cpu_dump_state; cc->set_pc = cris_cpu_set_pc; cc->gdb_read_register = cris_cpu_gdb_read_register; diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index a13a941ed5b..cda63537d32 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -268,6 +268,7 @@ static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size, static const struct TCGCPUOps hexagon_tcg_ops = { .initialize = hexagon_translate_init, + .has_work = hexagon_cpu_has_work, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, .tlb_fill = hexagon_tlb_fill, }; @@ -284,7 +285,6 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_reset(dc, hexagon_cpu_reset, &mcc->parent_reset); cc->class_by_name = hexagon_cpu_class_by_name; - cc->has_work = hexagon_cpu_has_work; cc->dump_state = hexagon_dump_state; cc->set_pc = hexagon_cpu_set_pc; cc->gdb_read_register = hexagon_gdb_read_register; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 5f1822b5fe6..b9437f4c534 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -135,6 +135,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) static const struct TCGCPUOps hppa_tcg_ops = { .initialize = hppa_translate_init, + .has_work = hppa_cpu_has_work, .synchronize_from_tb = hppa_cpu_synchronize_from_tb, .cpu_exec_interrupt = hppa_cpu_exec_interrupt, .tlb_fill = hppa_cpu_tlb_fill, @@ -155,7 +156,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) &acc->parent_realize); cc->class_by_name = hppa_cpu_class_by_name; - cc->has_work = hppa_cpu_has_work; cc->dump_state = hppa_cpu_dump_state; cc->set_pc = hppa_cpu_set_pc; cc->gdb_read_register = hppa_cpu_gdb_read_register; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 50008431c35..464e136a072 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7171,6 +7171,7 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.eip = value; } +/* FIXME TCG only? */ int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) { X86CPU *cpu = X86_CPU(cs); @@ -7213,11 +7214,6 @@ int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) return 0; } -static bool x86_cpu_has_work(CPUState *cs) -{ - return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; -} - static void x86_disas_set_info(CPUState *cs, disassemble_info *info) { X86CPU *cpu = X86_CPU(cs); @@ -7404,7 +7400,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->class_by_name = x86_cpu_class_by_name; cc->parse_features = x86_cpu_parse_featurestr; - cc->has_work = x86_cpu_has_work; #ifdef CONFIG_TCG tcg_cpu_common_class_init(cc); diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 6a35aa664dc..fee8487135d 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -57,10 +57,16 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, cpu->env.eip = tb->pc - tb->cs_base; } +static bool x86_cpu_has_work(CPUState *cs) +{ + return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; +} + #include "hw/core/tcg-cpu-ops.h" static const struct TCGCPUOps x86_tcg_ops = { .initialize = tcg_x86_init, + .has_work = x86_cpu_has_work, .synchronize_from_tb = x86_cpu_synchronize_from_tb, .cpu_exec_enter = x86_cpu_exec_enter, .cpu_exec_exit = x86_cpu_exec_exit, diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 4ad253a50ec..5d18255ac83 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -214,6 +214,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model) static const struct TCGCPUOps lm32_tcg_ops = { .initialize = lm32_translate_init, + .has_work = lm32_cpu_has_work, .cpu_exec_interrupt = lm32_cpu_exec_interrupt, .tlb_fill = lm32_cpu_tlb_fill, .debug_excp_handler = lm32_debug_excp_handler, @@ -234,7 +235,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, lm32_cpu_reset, &lcc->parent_reset); cc->class_by_name = lm32_cpu_class_by_name; - cc->has_work = lm32_cpu_has_work; cc->dump_state = lm32_cpu_dump_state; cc->set_pc = lm32_cpu_set_pc; cc->gdb_read_register = lm32_cpu_gdb_read_register; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 9b2f651213b..9c38138215f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -506,6 +506,7 @@ static const VMStateDescription vmstate_m68k_cpu = { static const struct TCGCPUOps m68k_tcg_ops = { .initialize = m68k_tcg_init, + .has_work = m68k_cpu_has_work, .cpu_exec_interrupt = m68k_cpu_exec_interrupt, .tlb_fill = m68k_cpu_tlb_fill, @@ -526,7 +527,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_reset(dc, m68k_cpu_reset, &mcc->parent_reset); cc->class_by_name = m68k_cpu_class_by_name; - cc->has_work = m68k_cpu_has_work; cc->dump_state = m68k_cpu_dump_state; cc->set_pc = m68k_cpu_set_pc; cc->gdb_read_register = m68k_cpu_gdb_read_register; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 4e086ab5465..809f42b5e0d 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -356,6 +356,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model) static const struct TCGCPUOps mb_tcg_ops = { .initialize = mb_tcg_init, + .has_work = mb_cpu_has_work, .synchronize_from_tb = mb_cpu_synchronize_from_tb, .cpu_exec_interrupt = mb_cpu_exec_interrupt, .tlb_fill = mb_cpu_tlb_fill, @@ -378,7 +379,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset); cc->class_by_name = mb_cpu_class_by_name; - cc->has_work = mb_cpu_has_work; cc->dump_state = mb_cpu_dump_state; cc->set_pc = mb_cpu_set_pc; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 81030c5c407..a189710904a 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -688,6 +688,7 @@ static Property mips_cpu_properties[] = { */ static const struct TCGCPUOps mips_tcg_ops = { .initialize = mips_tcg_init, + .has_work = mips_cpu_has_work, .synchronize_from_tb = mips_cpu_synchronize_from_tb, .cpu_exec_interrupt = mips_cpu_exec_interrupt, .tlb_fill = mips_cpu_tlb_fill, @@ -713,7 +714,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) device_class_set_props(dc, mips_cpu_properties); cc->class_by_name = mips_cpu_class_by_name; - cc->has_work = mips_cpu_has_work; cc->dump_state = mips_cpu_dump_state; cc->set_pc = mips_cpu_set_pc; cc->gdb_read_register = mips_cpu_gdb_read_register; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index c3de71b82fe..942804de21b 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -98,6 +98,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model) static const struct TCGCPUOps moxie_tcg_ops = { .initialize = moxie_translate_init, + .has_work = moxie_cpu_has_work, .tlb_fill = moxie_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY @@ -117,7 +118,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = moxie_cpu_class_by_name; - cc->has_work = moxie_cpu_has_work; cc->dump_state = moxie_cpu_dump_state; cc->set_pc = moxie_cpu_set_pc; #ifndef CONFIG_USER_ONLY diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 0de93cdd98f..cfd9f002436 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -211,6 +211,7 @@ static Property nios2_properties[] = { static const struct TCGCPUOps nios2_tcg_ops = { .initialize = nios2_tcg_init, + .has_work = nios2_cpu_has_work, .cpu_exec_interrupt = nios2_cpu_exec_interrupt, .tlb_fill = nios2_cpu_tlb_fill, @@ -232,7 +233,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset); cc->class_by_name = nios2_cpu_class_by_name; - cc->has_work = nios2_cpu_has_work; cc->dump_state = nios2_cpu_dump_state; cc->set_pc = nios2_cpu_set_pc; cc->disas_set_info = nios2_cpu_disas_set_info; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 52aef277232..674e1ac0d23 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -178,6 +178,7 @@ static void openrisc_any_initfn(Object *obj) static const struct TCGCPUOps openrisc_tcg_ops = { .initialize = openrisc_translate_init, + .has_work = openrisc_cpu_has_work, .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, .tlb_fill = openrisc_cpu_tlb_fill, @@ -197,7 +198,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset); cc->class_by_name = openrisc_cpu_class_by_name; - cc->has_work = openrisc_cpu_has_work; cc->dump_state = openrisc_cpu_dump_state; cc->set_pc = openrisc_cpu_set_pc; cc->gdb_read_register = openrisc_cpu_gdb_read_register; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6f9822bc0a1..a5de166bb3f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -584,6 +584,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) static const struct TCGCPUOps riscv_tcg_ops = { .initialize = riscv_translate_init, + .has_work = riscv_cpu_has_work, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .tlb_fill = riscv_cpu_tlb_fill, @@ -607,7 +608,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); cc->class_by_name = riscv_cpu_class_by_name; - cc->has_work = riscv_cpu_has_work; cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc; cc->gdb_read_register = riscv_cpu_gdb_read_register; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 28d2becc32c..f5f967ff509 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -177,6 +177,7 @@ static void rx_cpu_init(Object *obj) static const struct TCGCPUOps rx_tcg_ops = { .initialize = rx_translate_init, + .has_work = rx_cpu_has_work, .synchronize_from_tb = rx_cpu_synchronize_from_tb, .cpu_exec_interrupt = rx_cpu_exec_interrupt, .tlb_fill = rx_cpu_tlb_fill, @@ -198,7 +199,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data) &rcc->parent_reset); cc->class_by_name = rx_cpu_class_by_name; - cc->has_work = rx_cpu_has_work; cc->dump_state = rx_cpu_dump_state; cc->set_pc = rx_cpu_set_pc; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d57f69e7f7d..d2f897bf41a 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -465,6 +465,7 @@ static void s390_cpu_reset_full(DeviceState *dev) static const struct TCGCPUOps s390_tcg_ops = { .initialize = s390x_translate_init, + .has_work = s390_cpu_has_work, .tlb_fill = s390_cpu_tlb_fill, #if !defined(CONFIG_USER_ONLY) @@ -493,7 +494,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) #endif scc->reset = s390_cpu_reset; cc->class_by_name = s390_cpu_class_by_name, - cc->has_work = s390_cpu_has_work; cc->dump_state = s390_cpu_dump_state; cc->set_pc = s390_cpu_set_pc; cc->gdb_read_register = s390_cpu_gdb_read_register; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 9d77f9cfdae..8bac001bfa4 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -227,6 +227,7 @@ static const VMStateDescription vmstate_sh_cpu = { static const struct TCGCPUOps superh_tcg_ops = { .initialize = sh4_translate_init, + .has_work = superh_cpu_has_work, .synchronize_from_tb = superh_cpu_synchronize_from_tb, .cpu_exec_interrupt = superh_cpu_exec_interrupt, .tlb_fill = superh_cpu_tlb_fill, @@ -250,7 +251,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset); cc->class_by_name = superh_cpu_class_by_name; - cc->has_work = superh_cpu_has_work; cc->dump_state = superh_cpu_dump_state; cc->set_pc = superh_cpu_set_pc; cc->gdb_read_register = superh_cpu_gdb_read_register; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ccabe189c4a..761813ce96b 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -853,6 +853,7 @@ static Property sparc_cpu_properties[] = { static const struct TCGCPUOps sparc_tcg_ops = { .initialize = sparc_tcg_init, + .has_work = sparc_cpu_has_work, .synchronize_from_tb = sparc_cpu_synchronize_from_tb, .cpu_exec_interrupt = sparc_cpu_exec_interrupt, .tlb_fill = sparc_cpu_tlb_fill, @@ -879,7 +880,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = sparc_cpu_class_by_name; cc->parse_features = sparc_cpu_parse_features; - cc->has_work = sparc_cpu_has_work; cc->dump_state = sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) cc->memory_rw_debug = sparc_cpu_memory_rw_debug; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index c7f8a898caf..3bc89e736b3 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -138,6 +138,7 @@ static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) static const struct TCGCPUOps tilegx_tcg_ops = { .initialize = tilegx_tcg_init, + .has_work = tilegx_cpu_has_work, .cpu_exec_interrupt = tilegx_cpu_exec_interrupt, .tlb_fill = tilegx_cpu_tlb_fill, @@ -158,7 +159,6 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, tilegx_cpu_reset, &tcc->parent_reset); cc->class_by_name = tilegx_cpu_class_by_name; - cc->has_work = tilegx_cpu_has_work; cc->dump_state = tilegx_cpu_dump_state; cc->set_pc = tilegx_cpu_set_pc; cc->gdb_num_core_regs = 0; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 5b500b575bd..b493e3ede85 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -146,6 +146,7 @@ static void tc27x_initfn(Object *obj) static const struct TCGCPUOps tricore_tcg_ops = { .initialize = tricore_tcg_init, + .has_work = tricore_cpu_has_work, .synchronize_from_tb = tricore_cpu_synchronize_from_tb, .tlb_fill = tricore_cpu_tlb_fill, }; @@ -161,7 +162,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_reset(dc, tricore_cpu_reset, &mcc->parent_reset); cc->class_by_name = tricore_cpu_class_by_name; - cc->has_work = tricore_cpu_has_work; cc->gdb_read_register = tricore_cpu_gdb_read_register; cc->gdb_write_register = tricore_cpu_gdb_write_register; diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index a732b08748d..55569018296 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -124,6 +124,7 @@ static const VMStateDescription vmstate_uc32_cpu = { static const struct TCGCPUOps uc32_tcg_ops = { .initialize = uc32_translate_init, + .has_work = uc32_cpu_has_work, .cpu_exec_interrupt = uc32_cpu_exec_interrupt, .tlb_fill = uc32_cpu_tlb_fill, @@ -142,7 +143,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data) &ucc->parent_realize); cc->class_by_name = uc32_cpu_class_by_name; - cc->has_work = uc32_cpu_has_work; cc->dump_state = uc32_cpu_dump_state; cc->set_pc = uc32_cpu_set_pc; cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index badc3a26aa2..849a664a679 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -185,6 +185,7 @@ static const VMStateDescription vmstate_xtensa_cpu = { static const struct TCGCPUOps xtensa_tcg_ops = { .initialize = xtensa_translate_init, + .has_work = xtensa_cpu_has_work, .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, .tlb_fill = xtensa_cpu_tlb_fill, .debug_excp_handler = xtensa_breakpoint_handler, @@ -208,7 +209,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset); cc->class_by_name = xtensa_cpu_class_by_name; - cc->has_work = xtensa_cpu_has_work; cc->dump_state = xtensa_cpu_dump_state; cc->set_pc = xtensa_cpu_set_pc; cc->gdb_read_register = xtensa_cpu_gdb_read_register; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index fe76d0b3773..1558de804c9 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -8633,7 +8633,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER7; pcc->check_pow = check_pow_nocheck; - cc->has_work = cpu_has_work_POWER7; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -8806,7 +8805,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER8; pcc->check_pow = check_pow_nocheck; - cc->has_work = cpu_has_work_POWER8; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -9026,7 +9024,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER9; pcc->check_pow = check_pow_nocheck; - cc->has_work = cpu_has_work_POWER9; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -9241,7 +9238,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER10; pcc->check_pow = check_pow_nocheck; - cc->has_work = cpu_has_work_POWER10; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -10865,6 +10861,7 @@ static Property ppc_cpu_properties[] = { static const struct TCGCPUOps ppc_tcg_ops = { .initialize = ppc_translate_init, + .has_work = ppc_cpu_has_work, .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .tlb_fill = ppc_cpu_tlb_fill, @@ -10878,6 +10875,7 @@ static const struct TCGCPUOps ppc_tcg_ops = { static const struct TCGCPUOps power7_tcg_ops = { .initialize = ppc_translate_init, + .has_work = cpu_has_work_POWER7, .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .tlb_fill = ppc_cpu_tlb_fill, @@ -10891,6 +10889,7 @@ static const struct TCGCPUOps power7_tcg_ops = { static const struct TCGCPUOps power8_tcg_ops = { .initialize = ppc_translate_init, + .has_work = cpu_has_work_POWER8, .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .tlb_fill = ppc_cpu_tlb_fill, @@ -10904,6 +10903,7 @@ static const struct TCGCPUOps power8_tcg_ops = { static const struct TCGCPUOps power9_tcg_ops = { .initialize = ppc_translate_init, + .has_work = cpu_has_work_POWER9, .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .tlb_fill = ppc_cpu_tlb_fill, @@ -10917,6 +10917,7 @@ static const struct TCGCPUOps power9_tcg_ops = { static const struct TCGCPUOps power10_tcg_ops = { .initialize = ppc_translate_init, + .has_work = cpu_has_work_POWER10, .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .tlb_fill = ppc_cpu_tlb_fill, @@ -10946,7 +10947,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); cc->class_by_name = ppc_cpu_class_by_name; - cc->has_work = ppc_cpu_has_work; cc->dump_state = ppc_cpu_dump_state; cc->dump_statistics = ppc_cpu_dump_statistics; cc->set_pc = ppc_cpu_set_pc; From patchwork Thu Mar 4 22:23:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1447581 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=NmsARctx; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ds5gP67qjz9sSC for ; Fri, 5 Mar 2021 09:50:40 +1100 (AEDT) Received: from localhost ([::1]:34880 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lHwnm-0006g1-HL for incoming@patchwork.ozlabs.org; Thu, 04 Mar 2021 17:50:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55644) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHwOC-0007wL-61; Thu, 04 Mar 2021 17:24:12 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:36738) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lHwOA-0002eR-K7; Thu, 04 Mar 2021 17:24:11 -0500 Received: by mail-wm1-x334.google.com with SMTP id k66so11160338wmf.1; Thu, 04 Mar 2021 14:24:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fX6hEXkHOn0EDIH5ppgTAZxEG1tZNK4v7KhIUlmGx5M=; b=NmsARctxdUkxORvwpGrzrQBVLeNzc5ZUXeZNDaRJMDGsGYiiepheAAeenQx8XJkWG0 V6DQv6qOlw9kCHbaM40nZ95uRgDrFEM74p3NtTXaUFxeYzPtYEY+/8buH8VD1g6Z64z9 Y1/j5YnIRV8TWYzbnM/G+CHCU0nnPlfO6OYaqxsPrCdpPwwHEJOD8EWrxWcxdemXwK9D JnXOiRmTvl6H4cteMVFBQ3+TLc0ueTbXcQSZKsK/wQALoWndsvwOe4023JDnq+Lioxxk W94rxO+oT/+zmHb+qDgrOD8V6m0EzWs6IeHb8lETIoqONVLMTDwHxelhMvZjiMlKN24u XLlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fX6hEXkHOn0EDIH5ppgTAZxEG1tZNK4v7KhIUlmGx5M=; b=tjCpmOptBw+P7gP+iKY8nolbZFbIdxfvqO8YL86JBHXRH2+UJahEUa7OULBOvY+Xvv TqfkmGcVu8DO7DMivKBeEM7rv9TDhrcXazKTwzoJTikeOiLHhiRI/7nDEE3trL5oncNg J3FAtXn6x5DCgJKjgFP25zitQKiyi87qwg+P7bQIACKEJ3m1q/lfHRun66eTmYhAKMfT AEy0Yof283c8gFkt8RxPDFZ1dmDRZ3pB4DToaPmE8FokrtWN+6P7GjCzDFOcSgqfu4YE cpwPUgX5gFgpzaNA0BtXqwfCz/pYuvCV6JrVn/uFIZxmrN5BS9MU39YLdf91ksTWKxCw Zi7w== X-Gm-Message-State: AOAM533VrFtl1trLUZdZ6m7/eNBd0qDrPDwRBzdIFNz10al4P01n1o7U 8DYr8wPySsBSq3u3OwZfbx4V4se1w9E= X-Google-Smtp-Source: ABdhPJzosXqnrg30Glb/e8pVNWp2DurBv7xYuCw8ER1o1ANc+KLu/D+uVw2qnceBEynPCG5A6WFV0A== X-Received: by 2002:a7b:c5cc:: with SMTP id n12mr5768799wmk.123.1614896647799; Thu, 04 Mar 2021 14:24:07 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id n66sm1250102wmn.25.2021.03.04.14.24.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 14:24:07 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 8/8] target/arm: Restrict arm_cpu_has_work() to TCG Date: Thu, 4 Mar 2021 23:23:23 +0100 Message-Id: <20210304222323.1954755-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org> References: <20210304222323.1954755-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x334.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , qemu-riscv@nongnu.org, Eduardo Habkost , David Hildenbrand , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Cornelia Huck , Richard Henderson , Laurent Vivier , Greg Kurz , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Claudio Fontana , Paolo Bonzini , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" arm_cpu_has_work() is only used from TCG. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 2 +- target/arm/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1930be08828..db81db9bf57 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -172,8 +172,8 @@ static inline int r14_bank_number(int mode) void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); -bool arm_cpu_has_work(CPUState *cs); #ifdef CONFIG_TCG +bool arm_cpu_has_work(CPUState *cs); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); #endif /* CONFIG_TCG */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7181deee84a..02db969c00f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -74,7 +74,6 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, env->regs[15] = tb->pc; } } -#endif /* CONFIG_TCG */ bool arm_cpu_has_work(CPUState *cs) { @@ -86,6 +85,7 @@ bool arm_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_EXITTB); } +#endif /* CONFIG_TCG */ void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque)