From patchwork Mon Mar 1 17:08:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Codrin Ciubotariu X-Patchwork-Id: 1445700 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=BD+UbIaL; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Dq6N20k3Cz9sS8 for ; Tue, 2 Mar 2021 04:15:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237235AbhCAROx (ORCPT ); Mon, 1 Mar 2021 12:14:53 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:12062 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237306AbhCARLR (ORCPT ); Mon, 1 Mar 2021 12:11:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1614618675; x=1646154675; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9Dw+kwhMQDbH+M3mWnOXIqZENc4i58L5DgTTWewcxdU=; b=BD+UbIaL2btEe12JWHVj31dAgTW5E1+zQ5ty4ywIziyk4O7naWZo0VCo kZ+M6PJTtEKunjZT4IaA0LKViZZZFxiRYWEPdNs+vTmMY6tG1XOF+zPUs DdUqt1nu0xe1KDGyveK2nr3hsethv/kaDhGWEKOMA0YVlbkmQQoc4yV63 W5kBjMSk+aJSKg5DckwQQZwdCS59G9wAQRq4MB04rFg8GsAcrtatdz15N 8NtiHR8GbGPZtTOqczJ3Gj4+FpwklvsadTtKyRmHiFtwaQN32ymJex4fy 2tyvT0l1wBmBYdtCH1r3gNnYNvTyswfIOsT35T/xFF0gNGNTBpsS6oJyS g==; IronPort-SDR: KUIfx+c87XzXmqdIZUjC7INv++N9JoD8Vn+raEsJ7CxoEifIYuw6S4RjEiXU8gczsv0CczRSdQ jEVeGdfGSsfDymW2DgPxo6roOOfH/hYr5TwjX7nTs2r3keiKgZSzi88Exi6Lz6EGfauvoilmnb fQBCrzUNcr5YXqriGeJGsCdFEQkgiDmhAvQviccNf4lXiJwQ1Is3KSnBbpeaLTG5phHTS+GUTz lqOcyeUDZybU4p2zhDCBXmecgOrvGeKfigyV05nn3BkpAVzZmpxRAYriCAZvtb4nKA+mkpAz6W N0w= X-IronPort-AV: E=Sophos;i="5.81,215,1610434800"; d="scan'208";a="111511618" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Mar 2021 10:09:38 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 1 Mar 2021 10:09:38 -0700 Received: from rob-ult-m19940.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 1 Mar 2021 10:09:34 -0700 From: Codrin Ciubotariu To: , , , CC: , , , , , , , , "Codrin Ciubotariu" Subject: [PATCH v2 1/7] dt-bindings: mchp,i2s-mcc: Add SAMA7G5 to binding Date: Mon, 1 Mar 2021 19:08:59 +0200 Message-ID: <20210301170905.835091-2-codrin.ciubotariu@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210301170905.835091-1-codrin.ciubotariu@microchip.com> References: <20210301170905.835091-1-codrin.ciubotariu@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SAMA7G5 includes an updated version of the I2S-MCC driver, that includes 3 more DIN/DOUT pin pairs for multi-channel. Signed-off-by: Codrin Ciubotariu --- Changes in v2: - changes are done to mchp-i2s-mcc.txt insted of mchp,i2s-mcc.yaml Documentation/devicetree/bindings/sound/mchp-i2s-mcc.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/mchp-i2s-mcc.txt b/Documentation/devicetree/bindings/sound/mchp-i2s-mcc.txt index 91ec83a6faed..2180dbd9ea81 100644 --- a/Documentation/devicetree/bindings/sound/mchp-i2s-mcc.txt +++ b/Documentation/devicetree/bindings/sound/mchp-i2s-mcc.txt @@ -1,7 +1,8 @@ * Microchip I2S Multi-Channel Controller Required properties: -- compatible: Should be "microchip,sam9x60-i2smcc". +- compatible: Should be "microchip,sam9x60-i2smcc" or + "microchip,sama7g5-i2smcc". - reg: Should be the physical base address of the controller and the length of memory mapped region. - interrupts: Should contain the interrupt for the controller. From patchwork Mon Mar 1 17:09:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Codrin Ciubotariu X-Patchwork-Id: 1445705 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=MK47i3J7; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Dq6T26xF9z9sS8 for ; Tue, 2 Mar 2021 04:19:50 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237799AbhCART2 (ORCPT ); Mon, 1 Mar 2021 12:19:28 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:32429 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233180AbhCARQE (ORCPT ); Mon, 1 Mar 2021 12:16:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1614618961; x=1646154961; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JAZW71oGr+uPsf05sRgZbONv7U3epY8nJsk/yvQb0aY=; b=MK47i3J7DRIzlHog6SdxOcVJOOWeLDZHVmymNweL17ygHJdtNH4Di4Xf RkkqBd7nSXrWsFpFsKZrfAqK0yASxTa1lAVYlFoLAvbW2tMxuAwdbEMFW xNHlY0hen7Jy2zAP7ri2fJ8awSzrfrrxhv/1bAmT2vQeYqsUqO1qU+4/N u4K6SyjkhyVZatvDBrFsZBDSZ7tDJljdrGlo1wm6y3XRwFafJ9maI18wM Fx60v9OmoT11dro+GQldUcQcn6J6YJsI5G4Zgt1tjIzwxLdB4iUp2AhVj SsQ/HyCQzuBOKJVOzCM5WVTpKWexnuUB/5Qp2+Ef+TEs0eVF0lHAF5r0v A==; IronPort-SDR: OPDsas62esXmTkEDESjLiHXRHblwzIfU0ueGzYrZIw/dOcdPD2yx1XgAlDHFc2xTpHZsz43RJ3 4yLsRplyaAbjqUvgsXWihaeNVctgWBHvQQQh4Lk+0hIzWXevUNmHs3VAUe6904MDuzz2lru7YM 9+wYMXjSPg1Qfo0F1KclMNWMm7zQm/iq720ZtIagfmthg6Le49RxCYKyMD1ERJ0szF2H+4FovP XxtY5Fz00L96swuHseNSjUh+fG3KQNciR9kHY4xB775oQBdvN9TnJ250SXMj7uW+ThTqjaa65S 6Zo= X-IronPort-AV: E=Sophos;i="5.81,215,1610434800"; d="scan'208";a="111511738" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Mar 2021 10:09:54 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 1 Mar 2021 10:09:49 -0700 Received: from rob-ult-m19940.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 1 Mar 2021 10:09:46 -0700 From: Codrin Ciubotariu To: , , , CC: , , , , , , , , "Codrin Ciubotariu" Subject: [PATCH v2 4/7] dt-bindings: mchp,i2s-mcc: Add property to specify pin pair for TDM Date: Mon, 1 Mar 2021 19:09:02 +0200 Message-ID: <20210301170905.835091-5-codrin.ciubotariu@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210301170905.835091-1-codrin.ciubotariu@microchip.com> References: <20210301170905.835091-1-codrin.ciubotariu@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SAMA7G5's I2S-MCC has 4 pairs of DIN/DOUT pins. Since TDM only uses a single pair of pins for synchronous capture and playback, the controller needs to be told which of the pair is connected. This can be mentioned using the new "microchip,tdm-data-pair" property. The property is optional, needed only if TDM is used, and if it's missing DIN/DOUT 0 pins will be used by default. Signed-off-by: Codrin Ciubotariu --- Changes in v2: - changes are done to mchp-i2s-mcc.txt insted of mchp,i2s-mcc.yaml Documentation/devicetree/bindings/sound/mchp-i2s-mcc.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/mchp-i2s-mcc.txt b/Documentation/devicetree/bindings/sound/mchp-i2s-mcc.txt index 2180dbd9ea81..af8fe3e657df 100644 --- a/Documentation/devicetree/bindings/sound/mchp-i2s-mcc.txt +++ b/Documentation/devicetree/bindings/sound/mchp-i2s-mcc.txt @@ -19,7 +19,12 @@ Required properties: Optional properties: - pinctrl-0: Should specify pin control groups used for this controller. - princtrl-names: Should contain only one value - "default". - +- microchip,tdm-data-pair: 8 bit value that represents the DIN/DOUT pair pins + which are used to receive/send TDM data. It is optional + and it is only needed if the controller uses the TDM + mode. Not available for "microchip,sam9x60-i2smcc" + compatible. If it's not present, the default value is 0, + so the DIN/DOUT 0 pins are used. (1) : Only the peripheral clock is required. The generated clock is optional and should be set mostly when Master Mode is required. From patchwork Mon Mar 1 17:09:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Codrin Ciubotariu X-Patchwork-Id: 1445702 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=mKByZ5ID; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Dq6NZ5rWkz9sVw for ; Tue, 2 Mar 2021 04:15:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237324AbhCARPR (ORCPT ); Mon, 1 Mar 2021 12:15:17 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:47375 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236649AbhCARLX (ORCPT ); Mon, 1 Mar 2021 12:11:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1614618681; x=1646154681; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KkYmeABURUpBJilVSbLXGkupR/elTsE8JTUDxIe7uI8=; b=mKByZ5IDLh8lfoVPZC2gP9jY7ywe50lPkMRFFACojll8oYxIveluABtj XO6qimZ05GOYYEyqRIrQECXizQJQmrLl+ajFJe//fnLFf1bYXne5qh0Fc yoMSQyWUdkRwq4Y39Rkx2JmOkecU4xOQvshRb8+ecthR5DnSv68pgKP7F /V7uc/L223cylo7zziuzrpcp4Ci1E9JQd0itMe43MRrsfq+zTe+t74gq7 jEaLdNaaIyWZ5QAo7vIF2TSWBY5l+u5wye8Sqs3SqhbOjeDjw8vpxMxLW 3MY/poT64a/cUIbVWeBGa9J4lydgB25RosXybGqrEBjy773dz3bx6unTN A==; IronPort-SDR: RUAQQuKc8bU+YvOwwXbRPj8k/kX57It6Egh4uEsWodeZ68DE42ZAwMEEJBE2FVOVHFdouYL7t2 5x72jHGkCUI+JTzJMU3bDwoEo7Pe9FT7ox5vudm3IP/AFnb8thbuoZN0NkbEkxgqXbyyi7i1lZ MF1WbASYralZrx3FQB8N6VmQsie6S3cmQBiLuXCJ38JuBFq2HXbYvBejPzqOkcC9fVo6Ptm/wR j16+A/4RJxrBM+G0Bgri0NC890cqI/t5gntUIU9tmJP9UK7iALBN1aRvQPj228mQryYEcofSXb BGE= X-IronPort-AV: E=Sophos;i="5.81,215,1610434800"; d="scan'208";a="108323788" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Mar 2021 10:10:02 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 1 Mar 2021 10:10:00 -0700 Received: from rob-ult-m19940.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 1 Mar 2021 10:09:57 -0700 From: Codrin Ciubotariu To: , , , CC: , , , , , , , , "Codrin Ciubotariu" Subject: [PATCH v2 7/7] ASoC: convert Microchip I2SMCC binding to yaml Date: Mon, 1 Mar 2021 19:09:05 +0200 Message-ID: <20210301170905.835091-8-codrin.ciubotariu@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210301170905.835091-1-codrin.ciubotariu@microchip.com> References: <20210301170905.835091-1-codrin.ciubotariu@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch converts the Microchip I2SMCC bindings to DT schema format using json-schema. Signed-off-by: Codrin Ciubotariu Reviewed-by: Rob Herring --- Changes in v2: - moved from the beginning to the end of the patch series; - includes the changes (to yaml) from the rest of the patches that update the DT binding; .../bindings/sound/mchp,i2s-mcc.yaml | 108 ++++++++++++++++++ .../bindings/sound/mchp-i2s-mcc.txt | 49 -------- 2 files changed, 108 insertions(+), 49 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/mchp,i2s-mcc.yaml delete mode 100644 Documentation/devicetree/bindings/sound/mchp-i2s-mcc.txt diff --git a/Documentation/devicetree/bindings/sound/mchp,i2s-mcc.yaml b/Documentation/devicetree/bindings/sound/mchp,i2s-mcc.yaml new file mode 100644 index 000000000000..0481315cb5f2 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mchp,i2s-mcc.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mchp,i2s-mcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip I2S Multi-Channel Controller + +maintainers: + - Codrin Ciubotariu + +description: + The I2SMCC complies with the Inter-IC Sound (I2S) bus specification and + supports a Time Division Multiplexed (TDM) interface with external + multi-channel audio codecs. It consists of a receiver, a transmitter and a + common clock generator that can be enabled separately to provide Adapter, + Client or Controller modes with receiver and/or transmitter active. + On later I2SMCC versions (starting with Microchip's SAMA7G5) I2S + multi-channel is supported by using multiple data pins, output and + input, without TDM. + +properties: + "#sound-dai-cells": + const: 0 + + compatible: + enum: + - microchip,sam9x60-i2smcc + - microchip,sama7g5-i2smcc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Peripheral Bus Clock + - description: Generic Clock (Optional). Should be set mostly when Master + Mode is required. + minItems: 1 + + clock-names: + items: + - const: pclk + - const: gclk + minItems: 1 + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + + microchip,tdm-data-pair: + description: + Represents the DIN/DOUT pair pins that are used to receive/send + TDM data. It is optional and it is only needed if the controller + uses the TDM mode. + $ref: /schemas/types.yaml#/definitions/uint8 + enum: [0, 1, 2, 3] + default: 0 + +if: + properties: + compatible: + const: microchip,sam9x60-i2smcc +then: + properties: + microchip,tdm-data-pair: false + +required: + - "#sound-dai-cells" + - compatible + - reg + - interrupts + - clocks + - clock-names + - dmas + - dma-names + +additionalProperties: false + +examples: + - | + #include + #include + + i2s@f001c000 { + #sound-dai-cells = <0>; + compatible = "microchip,sam9x60-i2smcc"; + reg = <0xf001c000 0x100>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(36))>, + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(37))>; + dma-names = "tx", "rx"; + clocks = <&i2s_clk>, <&i2s_gclk>; + clock-names = "pclk", "gclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_default>; + }; diff --git a/Documentation/devicetree/bindings/sound/mchp-i2s-mcc.txt b/Documentation/devicetree/bindings/sound/mchp-i2s-mcc.txt deleted file mode 100644 index af8fe3e657df..000000000000 --- a/Documentation/devicetree/bindings/sound/mchp-i2s-mcc.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Microchip I2S Multi-Channel Controller - -Required properties: -- compatible: Should be "microchip,sam9x60-i2smcc" or - "microchip,sama7g5-i2smcc". -- reg: Should be the physical base address of the controller and the - length of memory mapped region. -- interrupts: Should contain the interrupt for the controller. -- dmas: Should be one per channel name listed in the dma-names property, - as described in atmel-dma.txt and dma.txt files. -- dma-names: Identifier string for each DMA request line in the dmas property. - Two dmas have to be defined, "tx" and "rx". -- clocks: Must contain an entry for each entry in clock-names. - Please refer to clock-bindings.txt. -- clock-names: Should be one of each entry matching the clocks phandles list: - - "pclk" (peripheral clock) Required. - - "gclk" (generated clock) Optional (1). - -Optional properties: -- pinctrl-0: Should specify pin control groups used for this controller. -- princtrl-names: Should contain only one value - "default". -- microchip,tdm-data-pair: 8 bit value that represents the DIN/DOUT pair pins - which are used to receive/send TDM data. It is optional - and it is only needed if the controller uses the TDM - mode. Not available for "microchip,sam9x60-i2smcc" - compatible. If it's not present, the default value is 0, - so the DIN/DOUT 0 pins are used. - -(1) : Only the peripheral clock is required. The generated clock is optional - and should be set mostly when Master Mode is required. - -Example: - - i2s@f001c000 { - compatible = "microchip,sam9x60-i2smcc"; - reg = <0xf001c000 0x100>; - interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(36))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(37))>; - dma-names = "tx", "rx"; - clocks = <&i2s_clk>, <&i2s_gclk>; - clock-names = "pclk", "gclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s_default>; - };