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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 01/50] target/i386: Split out gen_exception_gpf Date: Sun, 28 Feb 2021 15:22:32 -0800 Message-Id: <20210228232321.322053-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 68 ++++++++++++++++++++----------------- 1 file changed, 37 insertions(+), 31 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 6ecbbfa6c1..6af8bd219b 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -1276,6 +1276,12 @@ static void gen_illegal_opcode(DisasContext *s) gen_exception(s, EXCP06_ILLOP, s->pc_start - s->cs_base); } +/* Generate #GP for the current instruction. */ +static void gen_exception_gpf(DisasContext *s) +{ + gen_exception(s, EXCP0D_GPF, s->pc_start - s->cs_base); +} + /* if d == OR_TMP0, it means memory operand (address in A0) */ static void gen_op(DisasContext *s1, int op, MemOp ot, int d) { @@ -4502,7 +4508,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) s->vex_l = 0; s->vex_v = 0; if (sigsetjmp(s->jmpbuf, 0) != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); return s->pc; } @@ -6561,7 +6567,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) set_cc_op(s, CC_OP_EFLAGS); } else if (s->vm86) { if (s->iopl != 3) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1)); set_cc_op(s, CC_OP_EFLAGS); @@ -6683,7 +6689,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x9c: /* pushf */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF); if (s->vm86 && s->iopl != 3) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_update_cc_op(s); gen_helper_read_eflags(s->T0, cpu_env); @@ -6693,7 +6699,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x9d: /* popf */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); if (s->vm86 && s->iopl != 3) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { ot = gen_pop_T0(s); if (s->cpl == 0) { @@ -7055,7 +7061,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xcd: /* int N */ val = x86_ldub_code(env, s); if (s->vm86 && s->iopl != 3) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base); } @@ -7078,13 +7084,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (s->cpl <= s->iopl) { gen_helper_cli(cpu_env); } else { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } } else { if (s->iopl == 3) { gen_helper_cli(cpu_env); } else { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } } break; @@ -7095,7 +7101,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_jmp_im(s, s->pc - s->cs_base); gen_eob_inhibit_irq(s, true); } else { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } break; case 0x62: /* bound */ @@ -7188,7 +7194,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x130: /* wrmsr */ case 0x132: /* rdmsr */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); @@ -7220,7 +7226,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) goto illegal_op; if (!s->pe) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_helper_sysenter(cpu_env); gen_eob(s); @@ -7231,7 +7237,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) goto illegal_op; if (!s->pe) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_helper_sysexit(cpu_env, tcg_const_i32(dflag - 1)); gen_eob(s); @@ -7250,7 +7256,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0x107: /* sysret */ if (!s->pe) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1)); /* condition codes are modified only in long mode */ @@ -7272,7 +7278,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xf4: /* hlt */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); @@ -7298,7 +7304,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!s->pe || s->vm86) goto illegal_op; if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); @@ -7319,7 +7325,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!s->pe || s->vm86) goto illegal_op; if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); @@ -7435,7 +7441,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX], @@ -7452,7 +7458,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_update_cc_op(s); @@ -7477,7 +7483,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_update_cc_op(s); @@ -7490,7 +7496,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_update_cc_op(s); @@ -7505,7 +7511,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_update_cc_op(s); @@ -7519,7 +7525,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_update_cc_op(s); @@ -7543,7 +7549,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_update_cc_op(s); @@ -7553,7 +7559,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) CASE_MODRM_MEM_OP(2): /* lgdt */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_WRITE); @@ -7570,7 +7576,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) CASE_MODRM_MEM_OP(3): /* lidt */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_WRITE); @@ -7616,7 +7622,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; CASE_MODRM_OP(6): /* lmsw */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); @@ -7628,7 +7634,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) CASE_MODRM_MEM_OP(7): /* invlpg */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_update_cc_op(s); @@ -7643,7 +7649,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) #ifdef TARGET_X86_64 if (CODE64(s)) { if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { tcg_gen_mov_tl(s->T0, cpu_seg_base[R_GS]); tcg_gen_ld_tl(cpu_seg_base[R_GS], cpu_env, @@ -7679,7 +7685,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x108: /* invd */ case 0x109: /* wbinvd */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); /* nothing to do */ @@ -8003,7 +8009,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x120: /* mov reg, crN */ case 0x122: /* mov crN, reg */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { modrm = x86_ldub_code(env, s); /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). @@ -8057,7 +8063,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x121: /* mov reg, drN */ case 0x123: /* mov drN, reg */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { #ifndef CONFIG_USER_ONLY modrm = x86_ldub_code(env, s); @@ -8093,7 +8099,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0x106: /* clts */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); gen_helper_clts(cpu_env); From patchwork Sun Feb 28 23:22:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445338 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=pAinsol7; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DpfcG1V92z9sRN for ; Mon, 1 Mar 2021 10:24:30 +1100 (AEDT) Received: from localhost ([::1]:53608 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVQK-0005MI-6E for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:24:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPM-0005Jq-Gz for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:28 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:39147) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPK-0007f5-Ip for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:28 -0500 Received: by mail-pj1-x1033.google.com with SMTP id d2so10478375pjs.4 for ; Sun, 28 Feb 2021 15:23:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b3o7BcKxUNswRMMyWGLBg72LcoS575qjgZJ5bfz0nIY=; b=pAinsol7G6Kh3BQpjUgMQ4Sicddteb+5xsn/m7+ZSILHuSqaC7Bc67oevkfUc6N/Hm pRyaEaCE9fZKVxCcide+rkz2nsqOon1YZSRqRKyvLkIlM6yjMS7h+KPvn+5/I0c6DCcr cgUQ2AmdK/22Ijejn3k+7QqQ4VvJ+mcGzxHSeKDqF3Cgbvb67QW2B9nZh8O8NztZJZP3 GRbuZi0/KQ5EiikYff8BbnlqbOQOrT3xfyZyrVZKKuhzxZKd3d0oJDMPIaJ6CgOd+0I/ vtL1EwtfkDwts1SLar9N+jb7z/+2qhnfmL1wWPdnt5d+NbjyPpbNZTSJS1XK5ISbAjCe N9DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b3o7BcKxUNswRMMyWGLBg72LcoS575qjgZJ5bfz0nIY=; b=PXjAT50H2qOVbcELdeDtylniH0LyEVZz6n5tSakF/CoNZO6X5XwWHzWqnmhR4RdQDi UCvKaSrPrlEXKxH1DkA8HDPnhJSDvky4EL/leCXDXg0wZCaKDWR1xv+mWxjThITkkw1m GgYCZy1bCpA4tQQlJf2YzgKlMUu8/hZboXd39/xCitR7N8O/TFiUvdy5Wm1B8notidm3 BCZykg7qQufO65GjrlF1Jqmq2lVz3mVe5ISl31xToERpsvDaOMCttlPzp56Uc0Vcwrkh 5gPn8LbL2xFNtAWSw4BCwJVVdx7Jx5Lk5v/XucUk8CRf2lKo1k0m7qIzsMRRqhjoIFCV eDQQ== X-Gm-Message-State: AOAM533BiO4C8WKtWHLl/4bcuy2V9e497Z9KJD6zNZJLrZLTAquvJUxL Q35frBzx/qq8a0EQOE+h7nx4a/+NeA4JLw== X-Google-Smtp-Source: ABdhPJyDaZXnXm3iDVK031rlnWYbrZoi2iPLzHEzv5DVObDgm7UljGj2/grz6A9WlEXb3FhYBPf2tA== X-Received: by 2002:a17:902:cecb:b029:e4:182e:a2e4 with SMTP id d11-20020a170902cecbb02900e4182ea2e4mr12822457plg.48.1614554605075; Sun, 28 Feb 2021 15:23:25 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 02/50] target/i386: Split out check_cpl0 Date: Sun, 28 Feb 2021 15:22:33 -0800 Message-Id: <20210228232321.322053-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Split out the check for CPL != 0 and the raising of #GP. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 79 ++++++++++++++----------------------- 1 file changed, 30 insertions(+), 49 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 6af8bd219b..5703b253a1 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -1282,6 +1282,16 @@ static void gen_exception_gpf(DisasContext *s) gen_exception(s, EXCP0D_GPF, s->pc_start - s->cs_base); } +/* Check for cpl == 0; if not, raise #GP and return false. */ +static bool check_cpl0(DisasContext *s) +{ + if (s->cpl == 0) { + return true; + } + gen_exception_gpf(s); + return false; +} + /* if d == OR_TMP0, it means memory operand (address in A0) */ static void gen_op(DisasContext *s1, int op, MemOp ot, int d) { @@ -7193,9 +7203,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0x130: /* wrmsr */ case 0x132: /* rdmsr */ - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); if (b & 2) { @@ -7277,9 +7285,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_helper_cpuid(cpu_env); break; case 0xf4: /* hlt */ - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); @@ -7303,9 +7309,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 2: /* lldt */ if (!s->pe || s->vm86) goto illegal_op; - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); @@ -7324,9 +7328,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 3: /* ltr */ if (!s->pe || s->vm86) goto illegal_op; - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); @@ -7440,8 +7442,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) | PREFIX_REPZ | PREFIX_REPNZ))) { goto illegal_op; } - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX], @@ -7457,8 +7458,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!(s->flags & HF_SVME_MASK) || !s->pe) { goto illegal_op; } - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_update_cc_op(s); @@ -7482,8 +7482,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!(s->flags & HF_SVME_MASK) || !s->pe) { goto illegal_op; } - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_update_cc_op(s); @@ -7495,8 +7494,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!(s->flags & HF_SVME_MASK) || !s->pe) { goto illegal_op; } - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_update_cc_op(s); @@ -7510,8 +7508,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) || !s->pe) { goto illegal_op; } - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_update_cc_op(s); @@ -7524,8 +7521,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!(s->flags & HF_SVME_MASK) || !s->pe) { goto illegal_op; } - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_update_cc_op(s); @@ -7548,8 +7544,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!(s->flags & HF_SVME_MASK) || !s->pe) { goto illegal_op; } - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_update_cc_op(s); @@ -7558,8 +7553,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; CASE_MODRM_MEM_OP(2): /* lgdt */ - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_WRITE); @@ -7575,8 +7569,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; CASE_MODRM_MEM_OP(3): /* lidt */ - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_WRITE); @@ -7621,8 +7614,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_helper_wrpkru(cpu_env, s->tmp2_i32, s->tmp1_i64); break; CASE_MODRM_OP(6): /* lmsw */ - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); @@ -7633,8 +7625,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; CASE_MODRM_MEM_OP(7): /* invlpg */ - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_update_cc_op(s); @@ -7648,9 +7639,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xf8: /* swapgs */ #ifdef TARGET_X86_64 if (CODE64(s)) { - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { tcg_gen_mov_tl(s->T0, cpu_seg_base[R_GS]); tcg_gen_ld_tl(cpu_seg_base[R_GS], cpu_env, offsetof(CPUX86State, kernelgsbase)); @@ -7684,9 +7673,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x108: /* invd */ case 0x109: /* wbinvd */ - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); /* nothing to do */ } @@ -8008,9 +7995,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0x120: /* mov reg, crN */ case 0x122: /* mov crN, reg */ - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { modrm = x86_ldub_code(env, s); /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). * AMD documentation (24594.pdf) and testing of @@ -8062,9 +8047,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0x121: /* mov reg, drN */ case 0x123: /* mov drN, reg */ - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { #ifndef CONFIG_USER_ONLY modrm = x86_ldub_code(env, s); /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). @@ -8098,9 +8081,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) } break; case 0x106: /* clts */ - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); gen_helper_clts(cpu_env); /* abort block because static cpu state changed */ From patchwork Sun Feb 28 23:22:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445344 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=vo7vwJnO; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpfkd0C6Tz9sR4 for ; Mon, 1 Mar 2021 10:29:59 +1100 (AEDT) Received: from localhost ([::1]:42350 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVVc-0003zV-Sn for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:29:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43298) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPN-0005KD-0S for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:29 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:34756) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPL-0007fD-AP for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:28 -0500 Received: by mail-pf1-x434.google.com with SMTP id m6so10282315pfk.1 for ; Sun, 28 Feb 2021 15:23:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SbL2dW1QfQ+CyQTDJgcTi/qLjMFE5Hm5ssvxBaiakag=; b=vo7vwJnOUBy3AXHollETtSZd5+/BQ42mggGxVn8fmG5zj0kCbooLCIMF+qKcPZ1x3N U1IOa+/2ON7stQY+I6LOcwSsI6QBCwQCQRvx/th7JnB5/KRYy42nrHyZumKjULMktzxM UdrgI88gpkqe2Tzgvg7U8D6+5ytIUkksLNLM1ZNn3OFbdVO3hEiXe4c1etufq2KNQfBF NpPzIRvSEGT6QgH8uz0oGV8FXvSQw+urxzIT9ZD2wQY6YZRLqlHuEyomTe+r/0/oyufw TtFgs/wdGGANqYBiYBkzxXCpinrRw6rc790hl+rJEkfeHJ/TjvJCz/QaoGHwsyMGbiPa upLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SbL2dW1QfQ+CyQTDJgcTi/qLjMFE5Hm5ssvxBaiakag=; b=KSXRn3UUEi4oDK4ogDxZl21u4AvPmzHbm0IENJeakIMG3hnKkjdCUV/aM5Dfdj9Ilu XZVIatU+ze9FB7rSE63PuhHbN8PiIrG8blBJxy/Dy7ctpIU0S0KMSX1ghNG8PWSfsZwu biUvZdGZ6kFbwCm9IWGuRC+hU8rRk8WAqNTA9PW80+ZNtmdqf1idWTPBT4tXlmaMjqxG W0gauoYrKPJoPTgm30IGfptxPbNpi7QeOb9QE1PUPTMolzmkcT5xgRKRTHIpMnObGWZ6 8KCx4eznM2BK8Q/x4eodOprRXTZqdgt0vRXlTE/l2YmSSvXFK7Ew0Om+tFoW6lrpT9+q PMdA== X-Gm-Message-State: AOAM530zsqLaEbELxEinw/y9OOqsp8W2hCI55e9EA120gf7OoMSi42SI GlICtUrUgySzcUc+Kkse+9gX1J0oVU1M8A== X-Google-Smtp-Source: ABdhPJyAmQaHnt9l79V+oBc3hrpBgeD+sfELKy5qaA801RN+ip4qrGVGQPT7207zwWYAKkUe+I9VYg== X-Received: by 2002:a63:36c4:: with SMTP id d187mr10068396pga.168.1614554605926; Sun, 28 Feb 2021 15:23:25 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 03/50] target/i386: Unify code paths for IRET Date: Sun, 28 Feb 2021 15:22:34 -0800 Message-Id: <20210228232321.322053-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" In vm86 mode, we use the same helper as real-mode, but with an extra check for IOPL. All non-exceptional paths set EFLAGS. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 5703b253a1..59c1212625 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -6571,22 +6571,18 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto do_lret; case 0xcf: /* iret */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); - if (!s->pe) { - /* real mode */ - gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1)); - set_cc_op(s, CC_OP_EFLAGS); - } else if (s->vm86) { - if (s->iopl != 3) { + if (!s->pe || s->vm86) { + /* real mode or vm86 mode */ + if (s->vm86 && s->iopl != 3) { gen_exception_gpf(s); - } else { - gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1)); - set_cc_op(s, CC_OP_EFLAGS); + break; } + gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1)); } else { gen_helper_iret_protected(cpu_env, tcg_const_i32(dflag - 1), tcg_const_i32(s->pc - s->cs_base)); - set_cc_op(s, CC_OP_EFLAGS); } + set_cc_op(s, CC_OP_EFLAGS); gen_eob(s); break; case 0xe8: /* call im */ From patchwork Sun Feb 28 23:22:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445343 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=ofqfcp14; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpfgf6lTdz9sR4 for ; Mon, 1 Mar 2021 10:27:26 +1100 (AEDT) Received: from localhost ([::1]:34212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVTA-0000gr-TO for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:27:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43402) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPV-0005N0-Ez for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:39 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:53176) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPL-0007fI-Rg for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:37 -0500 Received: by mail-pj1-x102c.google.com with SMTP id e9so7196681pjs.2 for ; Sun, 28 Feb 2021 15:23:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZE0p78tg8cxpd5a+CooQGkZB6FVAM4mBBizGWXSKr3w=; b=ofqfcp149fg+tXklZk1tvv3QW/MRO1c0i5ZYWuW0YVC1ybeE9AhgrUg6Ojv0cbav+2 14JV9Gd8j5MOoE4v9KpxMlNf07L18PDJBpWkvK8Sq3efLDf6DaYXgYJU5MBuO94+GpDO A4s10xhYuMLDSQKdGA7UAu+aZuh7GcsiRshi8ftt+YQ9IOEpS6e7YSLDKt0Aq2OlDO/u ZxoLAwM1V3N8CYQ9nUhGT5t0nffZrK5DEtPpuXFzS4MfmIDH5ExG283H8tiDIzFt3Lru 5TvgtXHA4tNWm+H0aDdys9c/6uZvKVWy23RVdGLV8AuvDnjsJcS3ObPHhco/Zkl1+yoL 3IHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZE0p78tg8cxpd5a+CooQGkZB6FVAM4mBBizGWXSKr3w=; b=TM0poSvyDWljEkOp2CcnaPVJdv/EIrgelobUXcalFJb+y+sb6zd08V8YJ2lYezEr0z y2ZtzUwaq8eDecJRKMR6eZt5aRA46fPzsaHXQxQZWcEgYEXnNJRaX7Sc4erelRJ7ulZ9 yypCEUSJim+8DFJUVaImL8baSvP4U50PqEXCjSWVYaq07zpF9HfAH30IO+D3ca9y/Q0f CVSFeXY+PriSkXf64NAz5Wi1Muh4v/2EElnc6PuWguumuX8IJGZSKQNlFStQKqtMhYQt 6l8JhNaf+IS93/l8X9DMNc/iYEOEAmoqL3mLcMAV78NVD/iOmZr4CtKoDjDk6fdJr8tU BwCw== X-Gm-Message-State: AOAM533w6ax6QiLDKmq0qd/AjRb5k2dnfIohCW2pxeWeSSDica/zpmtB I5hTYrI7w8+WYsZp8kOcnuqaX2o+f0QOFQ== X-Google-Smtp-Source: ABdhPJx5whSrabdrhNhhoxuObVC2W/XiM5rGSKPwTKDN7lohyvtFS6pRzZ2jIsl1zSM3H5E/Zs2RGw== X-Received: by 2002:a17:90b:253:: with SMTP id fz19mr7557602pjb.160.1614554606591; Sun, 28 Feb 2021 15:23:26 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 04/50] target/i386: Split out check_vm86_iopl Date: Sun, 28 Feb 2021 15:22:35 -0800 Message-Id: <20210228232321.322053-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 59c1212625..75ee87fe84 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -1292,6 +1292,16 @@ static bool check_cpl0(DisasContext *s) return false; } +/* If vm86, check for iopl == 3; if not, raise #GP and return false. */ +static bool check_vm86_iopl(DisasContext *s) +{ + if (!s->vm86 || s->iopl == 3) { + return true; + } + gen_exception_gpf(s); + return false; +} + /* if d == OR_TMP0, it means memory operand (address in A0) */ static void gen_op(DisasContext *s1, int op, MemOp ot, int d) { @@ -6573,8 +6583,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); if (!s->pe || s->vm86) { /* real mode or vm86 mode */ - if (s->vm86 && s->iopl != 3) { - gen_exception_gpf(s); + if (!check_vm86_iopl(s)) { break; } gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1)); @@ -6694,9 +6703,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /* flags */ case 0x9c: /* pushf */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF); - if (s->vm86 && s->iopl != 3) { - gen_exception_gpf(s); - } else { + if (check_vm86_iopl(s)) { gen_update_cc_op(s); gen_helper_read_eflags(s->T0, cpu_env); gen_push_v(s, s->T0); @@ -6704,9 +6711,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0x9d: /* popf */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); - if (s->vm86 && s->iopl != 3) { - gen_exception_gpf(s); - } else { + if (check_vm86_iopl(s)) { ot = gen_pop_T0(s); if (s->cpl == 0) { if (dflag != MO_16) { @@ -7066,9 +7071,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xcd: /* int N */ val = x86_ldub_code(env, s); - if (s->vm86 && s->iopl != 3) { - gen_exception_gpf(s); - } else { + if (check_vm86_iopl(s)) { gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base); } break; From patchwork Sun Feb 28 23:22:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445337 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 05/50] target/i386: Split out check_iopl Date: Sun, 28 Feb 2021 15:22:36 -0800 Message-Id: <20210228232321.322053-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 75ee87fe84..176c95c02b 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -1302,6 +1302,16 @@ static bool check_vm86_iopl(DisasContext *s) return false; } +/* Check for iopl allowing access; if not, raise #GP and return false. */ +static bool check_iopl(DisasContext *s) +{ + if (s->vm86 ? s->iopl == 3 : s->cpl <= s->iopl) { + return true; + } + gen_exception_gpf(s); + return false; +} + /* if d == OR_TMP0, it means memory operand (address in A0) */ static void gen_op(DisasContext *s1, int op, MemOp ot, int d) { @@ -7089,28 +7099,16 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; #endif case 0xfa: /* cli */ - if (!s->vm86) { - if (s->cpl <= s->iopl) { - gen_helper_cli(cpu_env); - } else { - gen_exception_gpf(s); - } - } else { - if (s->iopl == 3) { - gen_helper_cli(cpu_env); - } else { - gen_exception_gpf(s); - } + if (check_iopl(s)) { + gen_helper_cli(cpu_env); } break; case 0xfb: /* sti */ - if (s->vm86 ? s->iopl == 3 : s->cpl <= s->iopl) { + if (check_iopl(s)) { gen_helper_sti(cpu_env); /* interruptions are enabled only the first insn after sti */ gen_jmp_im(s, s->pc - s->cs_base); gen_eob_inhibit_irq(s, true); - } else { - gen_exception_gpf(s); } break; case 0x62: /* bound */ From patchwork Sun Feb 28 23:22:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445346 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=TwpxD/N2; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpfkn0bznz9sR4 for ; Mon, 1 Mar 2021 10:30:09 +1100 (AEDT) Received: from localhost ([::1]:42508 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVVl-00043v-Bd for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:30:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43478) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPd-0005OH-5d for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:45 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:39150) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPO-0007gH-6A for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:43 -0500 Received: by mail-pj1-x1036.google.com with SMTP id d2so10478421pjs.4 for ; Sun, 28 Feb 2021 15:23:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PE0gONUgFUTslg2sgwOR+ancA+fjobnB/g6thC/v3Pc=; b=TwpxD/N2n8QZgvzAwqji763qycaXWiAjzAR/QJL38Ni/Gv2CtoCd5/dHH0CCeS/C3x ipH/nMUpEhNEP05DBYO3LQOcdxKDg5RGb2Ya89aSHka7H1+JQhrRrwbVf1bQ6zcXv68G T99aPgd00X0d6zxjtidDuVm7EGvhWQ2ikauyBJ9mzhzX2lMD5k+0EK4opyCs0+wp7ZrQ QaqzsLzKT/n60ztrbNDJxyl7UMr4wisAJJeUHzDM5no5K9kv5m89k3sHUOSwE5tsgP4/ M2YQf0pUDLOrp9G+tDiWEZfq0LXjI/FrBQYmW0jMPuPO0VDp034ZG1dW8UcUEnecLWlW 6BGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PE0gONUgFUTslg2sgwOR+ancA+fjobnB/g6thC/v3Pc=; b=e9ffMN79mojlCDMZun1EDTXjUH9j2sIsZcTqkiZ/CyxONvr/SbqrpZ4rt9MnPB0ebL ma+lgRtYNlquIM80Ysp+GXc0Kd1RVhR6ZuRD/HliiXeSt/icuq5uTTv95jM5Is9DDdER OfXoPvKNL9uxILDSteCcRfKup5t04bYcDoWbkz30wRGP0n/HgxOO1jxGr4Ghqs1CZve+ Nke5+OwOm1UVM3cA+AFzkhi5U72BZzoky2j4CmUN0Ryo5QbZTVOaG3MS3pzA0XreZpr9 Gjw2312vTJKCSebGCAGS/RhlvvL85MRxFK+jqZThEo9Klw2BrU8gt8/Ediauf6maxvzW Hyug== X-Gm-Message-State: AOAM533ruvacrdecK3ROvcGPwqp/WHkSBAdApO6U25VspGy6OJ0SrE0Q 8Iv/l13UeiX8kYhYM9PtCDyZyNkQmOqCpw== X-Google-Smtp-Source: ABdhPJx3b/s1DImTgfpX/Wxf6WNG72VbOz+xYkRIwMOVgpz2P5H2kRKxkk18RXER9aM5/ETqBuxBOQ== X-Received: by 2002:a17:90a:7309:: with SMTP id m9mr14266921pjk.23.1614554608592; Sun, 28 Feb 2021 15:23:28 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 06/50] target/i386: Assert PE is set for user-only Date: Sun, 28 Feb 2021 15:22:37 -0800 Message-Id: <20210228232321.322053-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" A user-mode executable is never in real-mode. Since we're adding an accessor macro, pull the value directly out of flags for sysemu. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 69 +++++++++++++++++++------------------ 1 file changed, 36 insertions(+), 33 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 176c95c02b..8477797798 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -94,7 +94,6 @@ typedef struct DisasContext { target_ulong pc; /* pc = eip + cs_base */ /* current block context */ target_ulong cs_base; /* base of CS segment */ - int pe; /* protected mode */ int code32; /* 32 bit code segment */ #ifdef TARGET_X86_64 int lma; /* long mode active */ @@ -146,6 +145,13 @@ typedef struct DisasContext { sigjmp_buf jmpbuf; } DisasContext; +/* The environment in which user-only runs is constrained. */ +#ifdef CONFIG_USER_ONLY +#define PE(S) true +#else +#define PE(S) (((S)->flags & HF_PE_MASK) != 0) +#endif + static void gen_eob(DisasContext *s); static void gen_jr(DisasContext *s, TCGv dest); static void gen_jmp(DisasContext *s, target_ulong eip); @@ -617,7 +623,7 @@ static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip, { target_ulong next_eip; - if (s->pe && (s->cpl > s->iopl || s->vm86)) { + if (PE(s) && (s->cpl > s->iopl || s->vm86)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); switch (ot) { case MO_8: @@ -2345,7 +2351,7 @@ static inline void gen_op_movl_seg_T0_vm(DisasContext *s, X86Seg seg_reg) call this function with seg_reg == R_CS */ static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg) { - if (s->pe && !s->vm86) { + if (PE(s) && !s->vm86) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), s->tmp2_i32); /* abort translation because the addseg value may change or @@ -5105,7 +5111,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_add_A0_im(s, 1 << ot); gen_op_ld_v(s, MO_16, s->T0, s->A0); do_lcall: - if (s->pe && !s->vm86) { + if (PE(s) && !s->vm86) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_lcall_protected(cpu_env, s->tmp2_i32, s->T1, tcg_const_i32(dflag - 1), @@ -5132,7 +5138,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_add_A0_im(s, 1 << ot); gen_op_ld_v(s, MO_16, s->T0, s->A0); do_ljmp: - if (s->pe && !s->vm86) { + if (PE(s) && !s->vm86) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_ljmp_protected(cpu_env, s->tmp2_i32, s->T1, tcg_const_tl(s->pc - s->cs_base)); @@ -6565,7 +6571,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xca: /* lret im */ val = x86_ldsw_code(env, s); do_lret: - if (s->pe && !s->vm86) { + if (PE(s) && !s->vm86) { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1), @@ -6591,7 +6597,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto do_lret; case 0xcf: /* iret */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); - if (!s->pe || s->vm86) { + if (!PE(s) || s->vm86) { /* real mode or vm86 mode */ if (!check_vm86_iopl(s)) { break; @@ -7230,7 +7236,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /* For Intel SYSENTER is valid on 64-bit */ if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) goto illegal_op; - if (!s->pe) { + if (!PE(s)) { gen_exception_gpf(s); } else { gen_helper_sysenter(cpu_env); @@ -7241,7 +7247,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /* For Intel SYSEXIT is valid on 64-bit */ if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) goto illegal_op; - if (!s->pe) { + if (!PE(s)) { gen_exception_gpf(s); } else { gen_helper_sysexit(cpu_env, tcg_const_i32(dflag - 1)); @@ -7260,7 +7266,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_eob_worker(s, false, true); break; case 0x107: /* sysret */ - if (!s->pe) { + if (!PE(s)) { gen_exception_gpf(s); } else { gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1)); @@ -7295,7 +7301,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) op = (modrm >> 3) & 7; switch(op) { case 0: /* sldt */ - if (!s->pe || s->vm86) + if (!PE(s) || s->vm86) goto illegal_op; gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); tcg_gen_ld32u_tl(s->T0, cpu_env, @@ -7304,7 +7310,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; case 2: /* lldt */ - if (!s->pe || s->vm86) + if (!PE(s) || s->vm86) goto illegal_op; if (check_cpl0(s)) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); @@ -7314,7 +7320,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) } break; case 1: /* str */ - if (!s->pe || s->vm86) + if (!PE(s) || s->vm86) goto illegal_op; gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); tcg_gen_ld32u_tl(s->T0, cpu_env, @@ -7323,7 +7329,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; case 3: /* ltr */ - if (!s->pe || s->vm86) + if (!PE(s) || s->vm86) goto illegal_op; if (check_cpl0(s)) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); @@ -7334,7 +7340,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 4: /* verr */ case 5: /* verw */ - if (!s->pe || s->vm86) + if (!PE(s) || s->vm86) goto illegal_op; gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); gen_update_cc_op(s); @@ -7452,7 +7458,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xd8: /* VMRUN */ - if (!(s->flags & HF_SVME_MASK) || !s->pe) { + if (!(s->flags & HF_SVME_MASK) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7476,7 +7482,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xda: /* VMLOAD */ - if (!(s->flags & HF_SVME_MASK) || !s->pe) { + if (!(s->flags & HF_SVME_MASK) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7488,7 +7494,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xdb: /* VMSAVE */ - if (!(s->flags & HF_SVME_MASK) || !s->pe) { + if (!(s->flags & HF_SVME_MASK) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7502,7 +7508,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xdc: /* STGI */ if ((!(s->flags & HF_SVME_MASK) && !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) - || !s->pe) { + || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7515,7 +7521,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xdd: /* CLGI */ - if (!(s->flags & HF_SVME_MASK) || !s->pe) { + if (!(s->flags & HF_SVME_MASK) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7529,7 +7535,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xde: /* SKINIT */ if ((!(s->flags & HF_SVME_MASK) && !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) - || !s->pe) { + || !PE(s)) { goto illegal_op; } gen_update_cc_op(s); @@ -7538,7 +7544,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xdf: /* INVLPGA */ - if (!(s->flags & HF_SVME_MASK) || !s->pe) { + if (!(s->flags & HF_SVME_MASK) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7705,7 +7711,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) TCGLabel *label1; TCGv t0, t1, t2, a0; - if (!s->pe || s->vm86) + if (!PE(s) || s->vm86) goto illegal_op; t0 = tcg_temp_local_new(); t1 = tcg_temp_local_new(); @@ -7753,7 +7759,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) { TCGLabel *label1; TCGv t0; - if (!s->pe || s->vm86) + if (!PE(s) || s->vm86) goto illegal_op; ot = dflag != MO_16 ? MO_32 : MO_16; modrm = x86_ldub_code(env, s); @@ -8455,9 +8461,13 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) DisasContext *dc = container_of(dcbase, DisasContext, base); CPUX86State *env = cpu->env_ptr; uint32_t flags = dc->base.tb->flags; - target_ulong cs_base = dc->base.tb->cs_base; - dc->pe = (flags >> HF_PE_SHIFT) & 1; + dc->cs_base = dc->base.tb->cs_base; + dc->flags = flags; + + /* We make some simplifying assumptions; validate they're correct. */ + g_assert(PE(dc) == ((flags & HF_PE_MASK) != 0)); + dc->code32 = (flags >> HF_CS32_SHIFT) & 1; dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; @@ -8468,7 +8478,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->tf = (flags >> TF_SHIFT) & 1; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; - dc->cs_base = cs_base; dc->popl_esp_hack = 0; /* select memory access functions */ dc->mem_index = 0; @@ -8485,7 +8494,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->lma = (flags >> HF_LMA_SHIFT) & 1; dc->code64 = (flags >> HF_CS64_SHIFT) & 1; #endif - dc->flags = flags; dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)); /* Do not optimize repz jumps at all in icount mode, because @@ -8499,11 +8507,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) additional step for ecx=0 when icount is enabled. */ dc->repz_opt = !dc->jmp_opt && !(tb_cflags(dc->base.tb) & CF_USE_ICOUNT); -#if 0 - /* check addseg logic */ - if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) - printf("ERROR addseg\n"); -#endif dc->T0 = tcg_temp_new(); dc->T1 = tcg_temp_new(); From patchwork Sun Feb 28 23:22:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445348 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 07/50] target/i386: Assert CPL is 3 for user-only Date: Sun, 28 Feb 2021 15:22:38 -0800 Message-Id: <20210228232321.322053-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" A user-mode executable always runs in ring 3. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 8477797798..50dc693edc 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -94,6 +94,11 @@ typedef struct DisasContext { target_ulong pc; /* pc = eip + cs_base */ /* current block context */ target_ulong cs_base; /* base of CS segment */ + +#ifndef CONFIG_USER_ONLY + uint8_t cpl; /* code priv level */ +#endif + int code32; /* 32 bit code segment */ #ifdef TARGET_X86_64 int lma; /* long mode active */ @@ -111,7 +116,6 @@ typedef struct DisasContext { int addseg; /* non zero if either DS/ES/SS have a non zero base */ int f_st; /* currently unused */ int vm86; /* vm86 mode */ - int cpl; int iopl; int tf; /* TF cpu flag */ int jmp_opt; /* use direct block chaining for direct jumps */ @@ -148,8 +152,10 @@ typedef struct DisasContext { /* The environment in which user-only runs is constrained. */ #ifdef CONFIG_USER_ONLY #define PE(S) true +#define CPL(S) 3 #else #define PE(S) (((S)->flags & HF_PE_MASK) != 0) +#define CPL(S) ((S)->cpl) #endif static void gen_eob(DisasContext *s); @@ -623,7 +629,7 @@ static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip, { target_ulong next_eip; - if (PE(s) && (s->cpl > s->iopl || s->vm86)) { + if (PE(s) && (CPL(s) > s->iopl || s->vm86)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); switch (ot) { case MO_8: @@ -1291,7 +1297,7 @@ static void gen_exception_gpf(DisasContext *s) /* Check for cpl == 0; if not, raise #GP and return false. */ static bool check_cpl0(DisasContext *s) { - if (s->cpl == 0) { + if (CPL(s) == 0) { return true; } gen_exception_gpf(s); @@ -1311,7 +1317,7 @@ static bool check_vm86_iopl(DisasContext *s) /* Check for iopl allowing access; if not, raise #GP and return false. */ static bool check_iopl(DisasContext *s) { - if (s->vm86 ? s->iopl == 3 : s->cpl <= s->iopl) { + if (s->vm86 ? s->iopl == 3 : CPL(s) <= s->iopl) { return true; } gen_exception_gpf(s); @@ -6729,7 +6735,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); if (check_vm86_iopl(s)) { ot = gen_pop_T0(s); - if (s->cpl == 0) { + if (CPL(s) == 0) { if (dflag != MO_16) { gen_helper_write_eflags(cpu_env, s->T0, tcg_const_i32((TF_MASK | AC_MASK | @@ -6744,7 +6750,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) & 0xffff)); } } else { - if (s->cpl <= s->iopl) { + if (CPL(s) <= s->iopl) { if (dflag != MO_16) { gen_helper_write_eflags(cpu_env, s->T0, tcg_const_i32((TF_MASK | @@ -7374,7 +7380,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xc8: /* monitor */ - if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || s->cpl != 0) { + if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || CPL(s) != 0) { goto illegal_op; } gen_update_cc_op(s); @@ -7386,7 +7392,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xc9: /* mwait */ - if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || s->cpl != 0) { + if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || CPL(s) != 0) { goto illegal_op; } gen_update_cc_op(s); @@ -7397,7 +7403,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xca: /* clac */ if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) - || s->cpl != 0) { + || CPL(s) != 0) { goto illegal_op; } gen_helper_clac(cpu_env); @@ -7407,7 +7413,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xcb: /* stac */ if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) - || s->cpl != 0) { + || CPL(s) != 0) { goto illegal_op; } gen_helper_stac(cpu_env); @@ -8461,19 +8467,23 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) DisasContext *dc = container_of(dcbase, DisasContext, base); CPUX86State *env = cpu->env_ptr; uint32_t flags = dc->base.tb->flags; + int cpl = (flags >> HF_CPL_SHIFT) & 3; dc->cs_base = dc->base.tb->cs_base; dc->flags = flags; +#ifndef CONFIG_USER_ONLY + dc->cpl = cpl; +#endif /* We make some simplifying assumptions; validate they're correct. */ g_assert(PE(dc) == ((flags & HF_PE_MASK) != 0)); + g_assert(CPL(dc) == cpl); dc->code32 = (flags >> HF_CS32_SHIFT) & 1; dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; dc->f_st = 0; dc->vm86 = (flags >> VM_SHIFT) & 1; - dc->cpl = (flags >> HF_CPL_SHIFT) & 3; dc->iopl = (flags >> IOPL_SHIFT) & 3; dc->tf = (flags >> TF_SHIFT) & 1; dc->cc_op = CC_OP_DYNAMIC; From patchwork Sun Feb 28 23:22:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445342 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=gHbr/9FO; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpfgf1jFpz9sRN for ; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 08/50] target/i386: Assert IOPL is 0 for user-only Date: Sun, 28 Feb 2021 15:22:39 -0800 Message-Id: <20210228232321.322053-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" On real hardware, the linux kernel has the iopl(2) syscall which can set IOPL to 3, to allow e.g. the xserver to briefly disable interrupts while programming the graphics card. However, QEMU cannot and does not implement this syscall, so the IOPL is never changed from 0. Which means that all of the checks vs CPL <= IOPL are false for user-only. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 50dc693edc..5f24615826 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -97,6 +97,7 @@ typedef struct DisasContext { #ifndef CONFIG_USER_ONLY uint8_t cpl; /* code priv level */ + uint8_t iopl; /* i/o priv level */ #endif int code32; /* 32 bit code segment */ @@ -116,7 +117,6 @@ typedef struct DisasContext { int addseg; /* non zero if either DS/ES/SS have a non zero base */ int f_st; /* currently unused */ int vm86; /* vm86 mode */ - int iopl; int tf; /* TF cpu flag */ int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ @@ -153,9 +153,11 @@ typedef struct DisasContext { #ifdef CONFIG_USER_ONLY #define PE(S) true #define CPL(S) 3 +#define IOPL(S) 0 #else #define PE(S) (((S)->flags & HF_PE_MASK) != 0) #define CPL(S) ((S)->cpl) +#define IOPL(S) ((S)->iopl) #endif static void gen_eob(DisasContext *s); @@ -629,7 +631,7 @@ static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip, { target_ulong next_eip; - if (PE(s) && (CPL(s) > s->iopl || s->vm86)) { + if (PE(s) && (CPL(s) > IOPL(s) || s->vm86)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); switch (ot) { case MO_8: @@ -1307,7 +1309,7 @@ static bool check_cpl0(DisasContext *s) /* If vm86, check for iopl == 3; if not, raise #GP and return false. */ static bool check_vm86_iopl(DisasContext *s) { - if (!s->vm86 || s->iopl == 3) { + if (!s->vm86 || IOPL(s) == 3) { return true; } gen_exception_gpf(s); @@ -1317,7 +1319,7 @@ static bool check_vm86_iopl(DisasContext *s) /* Check for iopl allowing access; if not, raise #GP and return false. */ static bool check_iopl(DisasContext *s) { - if (s->vm86 ? s->iopl == 3 : CPL(s) <= s->iopl) { + if (s->vm86 ? IOPL(s) == 3 : CPL(s) <= IOPL(s)) { return true; } gen_exception_gpf(s); @@ -6750,7 +6752,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) & 0xffff)); } } else { - if (CPL(s) <= s->iopl) { + if (CPL(s) <= IOPL(s)) { if (dflag != MO_16) { gen_helper_write_eflags(cpu_env, s->T0, tcg_const_i32((TF_MASK | @@ -8468,23 +8470,25 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) CPUX86State *env = cpu->env_ptr; uint32_t flags = dc->base.tb->flags; int cpl = (flags >> HF_CPL_SHIFT) & 3; + int iopl = (flags >> IOPL_SHIFT) & 3; dc->cs_base = dc->base.tb->cs_base; dc->flags = flags; #ifndef CONFIG_USER_ONLY dc->cpl = cpl; + dc->iopl = iopl; #endif /* We make some simplifying assumptions; validate they're correct. */ g_assert(PE(dc) == ((flags & HF_PE_MASK) != 0)); g_assert(CPL(dc) == cpl); + g_assert(IOPL(dc) == iopl); dc->code32 = (flags >> HF_CS32_SHIFT) & 1; dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; dc->f_st = 0; dc->vm86 = (flags >> VM_SHIFT) & 1; - dc->iopl = (flags >> IOPL_SHIFT) & 3; dc->tf = (flags >> TF_SHIFT) & 1; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; From patchwork Sun Feb 28 23:22:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445351 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=fgeJQVQj; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpfmq394cz9sR4 for ; Mon, 1 Mar 2021 10:31:55 +1100 (AEDT) Received: from localhost ([::1]:50960 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVXV-0007fa-Bf for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:31:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43502) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPe-0005Ob-IV for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:48 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:46691) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPR-0007hC-DB for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:45 -0500 Received: by mail-pl1-x62c.google.com with SMTP id u11so8744801plg.13 for ; Sun, 28 Feb 2021 15:23:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=87aQkAhQ1r5VYsTamlPm4Aatahw/X8GlcsAtVHfX6hU=; b=fgeJQVQjAOGjUDxXpoJ1t2v126QVJbgIb/VY1+lbR3slO0bxnkEX5FRezfg0V838Tw pp5yIwLCuEiXplxJT5UnEinblJnV0YOaHC7YayHdB8+f6zebF9iDVtk0+ZLZnA2T2L/z KFoFT2el6ds9PBaBU55pkfAfwM1c49eYsp6zND71gZYQx/oi68yXMPHfHSEXNzj1wZC9 WcmBdMrBh2Fti8TgXytU9X9hT+/GSdRAVb4b0qu+LScmaxYK09UE52jWn8Xy3AM8qnKu dToaTKAHqgIRKsAw4imh5j4+BYziqieXfM3FDFI+YeNjQdD6Fa7puaJfTOLoN8IS8IMn 6YWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=87aQkAhQ1r5VYsTamlPm4Aatahw/X8GlcsAtVHfX6hU=; b=nsXHCOfPPJKzapBe0EjVUeIb9NTyCLoN28ytFLaY1AUEz+NTLkpVxSijoxuM7PybHT mXOS85bTUOW21YNvEjrVa9O0D6uRC2ayi7eENR0fn2bh/Qmly5BGEDXgZQNQqJG/VTNq PySQKoEdpMg5SCKcwoUuFtxfuePTinIFAujf5lvHF0JMuWPO+etqWeh3d8NHzrc+TvEt DgutmJhLYtgF11Iuu/N8lGigNFxGWFvtSNV9IbIuEQ9iwDT6Iq6rVqF8eLxQQ39Jmetq zR6YJyfLwwaKH+Nuqb+hJT57b+1do5ch0Fji+cYg+RrBb+DB8+0zXOHCgFg4fe9Vj1Zx pOeQ== X-Gm-Message-State: AOAM531G4J76rEY4T81ugw/oQcSoOH16TsYPwJqld0Ezk84o1G+Rswxa rj7MSxkMbIjD5tljkCIOdxROI5K2ExabXQ== X-Google-Smtp-Source: ABdhPJwoo6t23IErhSAZk3FGrFqSLjeszoBHRddXWfHtLvIE7AowgB/pRK3cS8cCnFVsqzSok94dcQ== X-Received: by 2002:a17:902:b609:b029:e3:4b8d:994 with SMTP id b9-20020a170902b609b02900e34b8d0994mr12687770pls.44.1614554611662; Sun, 28 Feb 2021 15:23:31 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 09/50] target/i386: Assert !VM86 for x86_64 user-only Date: Sun, 28 Feb 2021 15:22:40 -0800 Message-Id: <20210228232321.322053-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" For i386-linux-user, we can enter vm86 mode via the vm86(2) syscall. That syscall explicitly returns to 32-bit mode, and the syscall does not exist for a 64-bit x86_64 executable. Since we're adding an accessor macro, pull the value directly out of flags otherwise. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 40 ++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 18 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 5f24615826..0e4f34f201 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -116,7 +116,6 @@ typedef struct DisasContext { #endif int addseg; /* non zero if either DS/ES/SS have a non zero base */ int f_st; /* currently unused */ - int vm86; /* vm86 mode */ int tf; /* TF cpu flag */ int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ @@ -159,6 +158,11 @@ typedef struct DisasContext { #define CPL(S) ((S)->cpl) #define IOPL(S) ((S)->iopl) #endif +#if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64) +#define VM86(S) false +#else +#define VM86(S) (((S)->flags & HF_VM_MASK) != 0) +#endif static void gen_eob(DisasContext *s); static void gen_jr(DisasContext *s, TCGv dest); @@ -631,7 +635,7 @@ static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip, { target_ulong next_eip; - if (PE(s) && (CPL(s) > IOPL(s) || s->vm86)) { + if (PE(s) && (CPL(s) > IOPL(s) || VM86(s))) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); switch (ot) { case MO_8: @@ -1309,7 +1313,7 @@ static bool check_cpl0(DisasContext *s) /* If vm86, check for iopl == 3; if not, raise #GP and return false. */ static bool check_vm86_iopl(DisasContext *s) { - if (!s->vm86 || IOPL(s) == 3) { + if (!VM86(s) || IOPL(s) == 3) { return true; } gen_exception_gpf(s); @@ -1319,7 +1323,7 @@ static bool check_vm86_iopl(DisasContext *s) /* Check for iopl allowing access; if not, raise #GP and return false. */ static bool check_iopl(DisasContext *s) { - if (s->vm86 ? IOPL(s) == 3 : CPL(s) <= IOPL(s)) { + if (VM86(s) ? IOPL(s) == 3 : CPL(s) <= IOPL(s)) { return true; } gen_exception_gpf(s); @@ -2359,7 +2363,7 @@ static inline void gen_op_movl_seg_T0_vm(DisasContext *s, X86Seg seg_reg) call this function with seg_reg == R_CS */ static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg) { - if (PE(s) && !s->vm86) { + if (PE(s) && !VM86(s)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), s->tmp2_i32); /* abort translation because the addseg value may change or @@ -4615,7 +4619,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xc4: /* 3-byte VEX */ /* VEX prefixes cannot be used except in 32-bit mode. Otherwise the instruction is LES or LDS. */ - if (s->code32 && !s->vm86) { + if (s->code32 && !VM86(s)) { static const int pp_prefix[4] = { 0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ }; @@ -5119,7 +5123,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_add_A0_im(s, 1 << ot); gen_op_ld_v(s, MO_16, s->T0, s->A0); do_lcall: - if (PE(s) && !s->vm86) { + if (PE(s) && !VM86(s)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_lcall_protected(cpu_env, s->tmp2_i32, s->T1, tcg_const_i32(dflag - 1), @@ -5146,7 +5150,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_add_A0_im(s, 1 << ot); gen_op_ld_v(s, MO_16, s->T0, s->A0); do_ljmp: - if (PE(s) && !s->vm86) { + if (PE(s) && !VM86(s)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_ljmp_protected(cpu_env, s->tmp2_i32, s->T1, tcg_const_tl(s->pc - s->cs_base)); @@ -6579,7 +6583,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xca: /* lret im */ val = x86_ldsw_code(env, s); do_lret: - if (PE(s) && !s->vm86) { + if (PE(s) && !VM86(s)) { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1), @@ -6605,7 +6609,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto do_lret; case 0xcf: /* iret */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); - if (!PE(s) || s->vm86) { + if (!PE(s) || VM86(s)) { /* real mode or vm86 mode */ if (!check_vm86_iopl(s)) { break; @@ -7309,7 +7313,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) op = (modrm >> 3) & 7; switch(op) { case 0: /* sldt */ - if (!PE(s) || s->vm86) + if (!PE(s) || VM86(s)) goto illegal_op; gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); tcg_gen_ld32u_tl(s->T0, cpu_env, @@ -7318,7 +7322,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; case 2: /* lldt */ - if (!PE(s) || s->vm86) + if (!PE(s) || VM86(s)) goto illegal_op; if (check_cpl0(s)) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); @@ -7328,7 +7332,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) } break; case 1: /* str */ - if (!PE(s) || s->vm86) + if (!PE(s) || VM86(s)) goto illegal_op; gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); tcg_gen_ld32u_tl(s->T0, cpu_env, @@ -7337,7 +7341,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; case 3: /* ltr */ - if (!PE(s) || s->vm86) + if (!PE(s) || VM86(s)) goto illegal_op; if (check_cpl0(s)) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); @@ -7348,7 +7352,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 4: /* verr */ case 5: /* verw */ - if (!PE(s) || s->vm86) + if (!PE(s) || VM86(s)) goto illegal_op; gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); gen_update_cc_op(s); @@ -7719,7 +7723,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) TCGLabel *label1; TCGv t0, t1, t2, a0; - if (!PE(s) || s->vm86) + if (!PE(s) || VM86(s)) goto illegal_op; t0 = tcg_temp_local_new(); t1 = tcg_temp_local_new(); @@ -7767,7 +7771,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) { TCGLabel *label1; TCGv t0; - if (!PE(s) || s->vm86) + if (!PE(s) || VM86(s)) goto illegal_op; ot = dflag != MO_16 ? MO_32 : MO_16; modrm = x86_ldub_code(env, s); @@ -8483,12 +8487,12 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(PE(dc) == ((flags & HF_PE_MASK) != 0)); g_assert(CPL(dc) == cpl); g_assert(IOPL(dc) == iopl); + g_assert(VM86(dc) == ((flags & HF_VM_MASK) != 0)); dc->code32 = (flags >> HF_CS32_SHIFT) & 1; dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; dc->f_st = 0; - dc->vm86 = (flags >> VM_SHIFT) & 1; dc->tf = (flags >> TF_SHIFT) & 1; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; From patchwork Sun Feb 28 23:22:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445345 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=eTrsJ5SE; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpfkl1njqz9sR4 for ; Mon, 1 Mar 2021 10:30:07 +1100 (AEDT) Received: from localhost ([::1]:42580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVVl-00045h-83 for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:30:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43520) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPg-0005PL-Ev for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:49 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:54396) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPT-0007hL-55 for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:48 -0500 Received: by mail-pj1-x102b.google.com with SMTP id i14so8243628pjz.4 for ; Sun, 28 Feb 2021 15:23:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QDVFGxFwrmBHnWFNAj8HT9b7D+hlCMSrCwvbH/K9RpM=; b=eTrsJ5SEEQaChT2lpyshsSNqlRY7I1a33ZXbSVZnnTCJb29YbYx7IU9F7QT4t4uPk/ M10VwZR+11DGTWU9pKNMoxIcDhZ8RDktkwtst/0k8fAovKg9aQwcp9V/Y9YiSeNSUOka MBliu/BzdOBSI3Z8WM4uYTgJl8205tqSrvNIrZD8sKkBpsJL2yiTUjEAW7rIS03/MBRO ihb7pq9ILvRA/cORK59aNqBEIgwBpfa6zK5C6x8vmZFqX3Ei+mV5E7H3suHxcB56BQTE ZtTcVmNHhHLEu4T23QZxNN5zEFwnui1EzHqKrq+kPQvcHtav387RuHN/t9IIFKk3CoB9 s57A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QDVFGxFwrmBHnWFNAj8HT9b7D+hlCMSrCwvbH/K9RpM=; b=L+BP5F1twExyNBzeIIDDMFaOuYwGD/WuOByBVYg6PvKKJbjNiWdhoo9sGhOXjW0xOV z8eH7LVzfYC4ialNQQdqAwfnayOrbvqw4GH0ebP+Iyh2gbbkagZjFB5RYAj8nVdFurER OynrgWnLE6SAtQGG0ihxw2aO/tz+ug9R0XOt3h3WKDDYAGx6jx4WSxzBflY00E/SuIhN 68M6bzi26gM1iRolY81KZLE4N8JEFTtAfD2Zckt78Ey7pMByLq7KvNnTmnM/B6r+K9VZ PVWcpVFjJxxjzkVxwJRuvmjGGki1cfS1U231NpG+ddSHmbzPZUmVRFOtyR1dhm0f4qtQ Kgpg== X-Gm-Message-State: AOAM531mxMbpityjhjd/bWmrFV8CJUN8OvGQAPyl11vtpZEnyX5F3r9h 610FYq6x0F0NITRoucc9XGr8+0I3yOeSbg== X-Google-Smtp-Source: ABdhPJzFsJ3nnNEikzn0XOGNoQ55s0nTOOioM9eRcBMrze09UYIiVmecO5JYZvhQ9mzwQv6NHd3htA== X-Received: by 2002:a17:902:ab8f:b029:e1:8334:c845 with SMTP id f15-20020a170902ab8fb02900e18334c845mr12859210plr.55.1614554612450; Sun, 28 Feb 2021 15:23:32 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 10/50] target/i386: Assert CODE32 for x86_64 user-only Date: Sun, 28 Feb 2021 15:22:41 -0800 Message-Id: <20210228232321.322053-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" For user-only, CODE32 == !VM86, because we are never in real-mode. Since we cannot enter vm86 mode for x86_64 user-only, CODE32 is always set. Since we're adding an accessor macro, pull the value directly out of flags otherwise. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 0e4f34f201..d46ebc1dc2 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -100,7 +100,6 @@ typedef struct DisasContext { uint8_t iopl; /* i/o priv level */ #endif - int code32; /* 32 bit code segment */ #ifdef TARGET_X86_64 int lma; /* long mode active */ int code64; /* 64 bit code segment */ @@ -160,8 +159,10 @@ typedef struct DisasContext { #endif #if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64) #define VM86(S) false +#define CODE32(S) true #else #define VM86(S) (((S)->flags & HF_VM_MASK) != 0) +#define CODE32(S) (((S)->flags & HF_CS32_MASK) != 0) #endif static void gen_eob(DisasContext *s); @@ -2370,7 +2371,7 @@ static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg) because ss32 may change. For R_SS, translation must always stop as a special handling must be done to disable hardware interrupts for the next instruction */ - if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) { + if (seg_reg == R_SS || (CODE32(s) && seg_reg < R_FS)) { s->base.is_jmp = DISAS_TOO_MANY; } } else { @@ -4619,7 +4620,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xc4: /* 3-byte VEX */ /* VEX prefixes cannot be used except in 32-bit mode. Otherwise the instruction is LES or LDS. */ - if (s->code32 && !VM86(s)) { + if (CODE32(s) && !VM86(s)) { static const int pp_prefix[4] = { 0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ }; @@ -4686,13 +4687,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64); } else { /* In 16/32-bit mode, 0x66 selects the opposite data size. */ - if (s->code32 ^ ((prefixes & PREFIX_DATA) != 0)) { + if (CODE32(s) ^ ((prefixes & PREFIX_DATA) != 0)) { dflag = MO_32; } else { dflag = MO_16; } /* In 16/32-bit mode, 0x67 selects the opposite addressing. */ - if (s->code32 ^ ((prefixes & PREFIX_ADR) != 0)) { + if (CODE32(s) ^ ((prefixes & PREFIX_ADR) != 0)) { aflag = MO_32; } else { aflag = MO_16; @@ -8488,8 +8489,8 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(CPL(dc) == cpl); g_assert(IOPL(dc) == iopl); g_assert(VM86(dc) == ((flags & HF_VM_MASK) != 0)); + g_assert(CODE32(dc) == ((flags & HF_CS32_MASK) != 0)); - dc->code32 = (flags >> HF_CS32_SHIFT) & 1; dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; dc->f_st = 0; From patchwork Sun Feb 28 23:22:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445339 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=MXw/ZsZ2; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DpfcH09vXz9sS8 for ; Mon, 1 Mar 2021 10:24:30 +1100 (AEDT) Received: from localhost ([::1]:53714 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVQK-0005Ph-M0 for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:24:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43480) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPd-0005OI-7N for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:45 -0500 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:38491) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPT-0007i1-9c for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:45 -0500 Received: by mail-pf1-x42c.google.com with SMTP id 201so10276111pfw.5 for ; Sun, 28 Feb 2021 15:23:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XZsGfWtTysVo81uFFzyXKZud5EEc/xMwJHVIKqPG4Tc=; b=MXw/ZsZ2bAwnR+WKLo9j+BVs7UxHxdRNumqkPaalXdzy50zZVSd9cvc0QSipPlHh5m ez/IrigcdTWBiwzW9WowngQzRevxFMSZ9QcdyVMxmVkr45cuWkq75OQ735+d7DdwsGMB EmWomuqIPM68LxFpTSFHQXUZpWP29t6UeFferIeE+IUrL6/9p+Z1hYuKGHl734sKw0oG BT23bsQRGkoQzLyQNXc6F5s82/16lKBbzTKneLKSzW1BSUQ3uD8Xy6SeuNEOOOfidORg TEFROJEIyE3mMGrumMbhkfMuTGVZglode1uBxWKYM4HpjC2SqPLGnxdEo0mlmviF3pLo AiDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XZsGfWtTysVo81uFFzyXKZud5EEc/xMwJHVIKqPG4Tc=; b=sEm/OHoZYKlmq9K24zQn8jVo8qyfNghWatb1NSp/0FliU/Ay2WyHezGiAPTP9dCKdF L2wZfPtpb41HEeQAbMuCmx+6JRMSahj3thlJyWB2DzWPpp78x1KfNql56hmM1vWMn5xP 9BV+3eiO5SoK7ZzlC79yKLOt7LrEudmURRzkJ4JV2nhU8keD3FJA/JB356iO2asOjgV4 mBfUG8b4blO18SYHy4RTrYYdBTMDUQlL0JM6kWhE7PIuOJudi013UgRo8DQFKDyNl5DD UU1bhpbTIUnuyWAl13HpuEvmYNtTso3/6f8359dwO0l6JkC/Hx9yI5GIGmkb8fs1AARw BhIg== X-Gm-Message-State: AOAM5334cZ/0onlD7uhrcPfCVkbez6CnDQhhJ8UpZWze0RcxoX7c/GBN X/+hHm289/2EBaKZwJIz36+kFoXuII+2lQ== X-Google-Smtp-Source: ABdhPJxbs6hf64FvGKB6grWS62QGLnq0Ay69lDgL0QPe2OyO2dbXQGc8OSkjE7Pm+IuJ+yu+aTgayQ== X-Received: by 2002:aa7:9514:0:b029:1ee:1397:701 with SMTP id b20-20020aa795140000b02901ee13970701mr12360027pfp.19.1614554613122; Sun, 28 Feb 2021 15:23:33 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 11/50] target/i386: Assert SS32 for x86_64 user-only Date: Sun, 28 Feb 2021 15:22:42 -0800 Message-Id: <20210228232321.322053-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" For user-only, SS32 == !VM86, because we are never in real-mode. Since we cannot enter vm86 mode for x86_64 user-only, SS32 is always set. Since we're adding an accessor macro, pull the value directly out of flags otherwise. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index d46ebc1dc2..ede6e4c5cd 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -107,7 +107,6 @@ typedef struct DisasContext { #endif int vex_l; /* vex vector length */ int vex_v; /* vex vvvv register, without 1's complement. */ - int ss32; /* 32 bit stack segment */ CCOp cc_op; /* current CC operation */ bool cc_op_dirty; #ifdef TARGET_X86_64 @@ -160,9 +159,11 @@ typedef struct DisasContext { #if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64) #define VM86(S) false #define CODE32(S) true +#define SS32(S) true #else #define VM86(S) (((S)->flags & HF_VM_MASK) != 0) #define CODE32(S) (((S)->flags & HF_CS32_MASK) != 0) +#define SS32(S) (((S)->flags & HF_SS32_MASK) != 0) #endif static void gen_eob(DisasContext *s); @@ -352,7 +353,7 @@ static inline MemOp mo_pushpop(DisasContext *s, MemOp ot) /* Select the size of the stack pointer. */ static inline MemOp mo_stacksize(DisasContext *s) { - return CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16; + return CODE64(s) ? MO_64 : SS32(s) ? MO_32 : MO_16; } /* Select only size 64 else 32. Used for SSE operand sizes. */ @@ -2451,12 +2452,12 @@ static inline void gen_pop_update(DisasContext *s, MemOp ot) static inline void gen_stack_A0(DisasContext *s) { - gen_lea_v_seg(s, s->ss32 ? MO_32 : MO_16, cpu_regs[R_ESP], R_SS, -1); + gen_lea_v_seg(s, SS32(s) ? MO_32 : MO_16, cpu_regs[R_ESP], R_SS, -1); } static void gen_pusha(DisasContext *s) { - MemOp s_ot = s->ss32 ? MO_32 : MO_16; + MemOp s_ot = SS32(s) ? MO_32 : MO_16; MemOp d_ot = s->dflag; int size = 1 << d_ot; int i; @@ -2472,7 +2473,7 @@ static void gen_pusha(DisasContext *s) static void gen_popa(DisasContext *s) { - MemOp s_ot = s->ss32 ? MO_32 : MO_16; + MemOp s_ot = SS32(s) ? MO_32 : MO_16; MemOp d_ot = s->dflag; int size = 1 << d_ot; int i; @@ -2494,7 +2495,7 @@ static void gen_popa(DisasContext *s) static void gen_enter(DisasContext *s, int esp_addend, int level) { MemOp d_ot = mo_pushpop(s, s->dflag); - MemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16; + MemOp a_ot = CODE64(s) ? MO_64 : SS32(s) ? MO_32 : MO_16; int size = 1 << d_ot; /* Push BP; compute FrameTemp into T1. */ @@ -8490,8 +8491,8 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(IOPL(dc) == iopl); g_assert(VM86(dc) == ((flags & HF_VM_MASK) != 0)); g_assert(CODE32(dc) == ((flags & HF_CS32_MASK) != 0)); + g_assert(SS32(dc) == ((flags & HF_SS32_MASK) != 0)); - dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; dc->f_st = 0; dc->tf = (flags >> TF_SHIFT) & 1; From patchwork Sun Feb 28 23:22:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445349 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Ife5a/pG; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpfmn5h8lz9sR4 for ; Mon, 1 Mar 2021 10:31:53 +1100 (AEDT) Received: from localhost ([::1]:50868 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVXT-0007dP-KZ for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:31:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43580) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPk-0005RQ-7y for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:54 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:51547) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPT-0007i5-9e for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:51 -0500 Received: by mail-pj1-x1033.google.com with SMTP id jx13so6380620pjb.1 for ; Sun, 28 Feb 2021 15:23:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pjuG897ecqPHqn9o+8GNgZG7OZ+sBrEQD+MOGdNWOSM=; b=Ife5a/pGxobkc9E1YaiZhO7HeDjFqjeNL/e/lqINvKnP7JxM60vdvUebBdsuHh11pQ LIWhRGQ5/B8E/n0z36jyrI+4EyY6+qo7412l2PlwjJqxdqK25IOnNatsc+EtXvUQe6i5 T7T2GfJLRH2P8zKeSrduhTTVC+070o6TVhYK+8sM4yobwz/1RyI/PLzH41kwQi50eQjB IEUMgZ0B6d+SUpUmlxvq4C/atgxJx1Tq/E1Y2I57gwMHJOvQ/KFXs95XOCPiwUlUzYVW dgB0lwyQQbSxLpVClecc8lzvJi67qCoSxqIWlhASGLU1d49BAJad7a303E+VJIcnWqZ3 qibw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pjuG897ecqPHqn9o+8GNgZG7OZ+sBrEQD+MOGdNWOSM=; b=pD3CBayX7Mnt5L7WRHtBDUJds3cFwECvoNLbKi/253t4H09rBW89bLO9vsryjo3yj/ 6rs+C77OjKq2cbTvy/LWupVNt8ZmGe7TjnoZ9NmHp8khGJJqlYiGNMkGaATSrgwuNQR4 O8ij6Vf90FNrdIgJXitdtwhFXB58zCAOTu+AIEkbq63ICEHQmDfzFwHzvKBBA39osUJU vHEj8ebD4mlJQU246bDQI/67feGgkmgZkGaIZX5ZGABZUzlG1EkOFJtUTeOuOs7fU0py 6dc66w8GHOxb90hLGFEOxba4p4Lj6US9AZsYbXASuoI9TndUb+etRkxPjNFp4QzpeAVB AEOw== X-Gm-Message-State: AOAM5335/R0BCr8X9F2Hi92mMr8N3I00Qrve+aUnwqpzelmVUPPc8rUX RRN+rET3m3XBACZFuBWDTvQ909VJ+NGOCA== X-Google-Smtp-Source: ABdhPJzxu+VbnsyzNA/gbuNOSm2cvF6KCugBEHaMcpEFgyI2b2yfobbcEAOGxg+c6BI8zyLNL0n+qQ== X-Received: by 2002:a17:902:b206:b029:e3:f546:2f70 with SMTP id t6-20020a170902b206b02900e3f5462f70mr12815869plr.63.1614554614091; Sun, 28 Feb 2021 15:23:34 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 12/50] target/i386: Assert CODE64 for x86_64 user-only Date: Sun, 28 Feb 2021 15:22:43 -0800 Message-Id: <20210228232321.322053-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" For x86_64 user-only, there is no way to leave 64-bit mode. Without x86_64, there is no way to enter 64-bit mode. There is an existing macro to aid with that; simply place it in the right place in the ifdef chain. Since we're adding an accessor macro, pull the value directly out of flags when we're not assuming a constant. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index ede6e4c5cd..e7f4392d55 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -41,11 +41,9 @@ #define PREFIX_VEX 0x20 #ifdef TARGET_X86_64 -#define CODE64(s) ((s)->code64) #define REX_X(s) ((s)->rex_x) #define REX_B(s) ((s)->rex_b) #else -#define CODE64(s) 0 #define REX_X(s) 0 #define REX_B(s) 0 #endif @@ -102,7 +100,6 @@ typedef struct DisasContext { #ifdef TARGET_X86_64 int lma; /* long mode active */ - int code64; /* 64 bit code segment */ int rex_x, rex_b; #endif int vex_l; /* vex vector length */ @@ -165,6 +162,13 @@ typedef struct DisasContext { #define CODE32(S) (((S)->flags & HF_CS32_MASK) != 0) #define SS32(S) (((S)->flags & HF_SS32_MASK) != 0) #endif +#if !defined(TARGET_X86_64) +#define CODE64(S) false +#elif defined(CONFIG_USER_ONLY) +#define CODE64(S) true +#else +#define CODE64(S) (((S)->flags & HF_CS64_MASK) != 0) +#endif static void gen_eob(DisasContext *s); static void gen_jr(DisasContext *s, TCGv dest); @@ -8491,6 +8495,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(IOPL(dc) == iopl); g_assert(VM86(dc) == ((flags & HF_VM_MASK) != 0)); g_assert(CODE32(dc) == ((flags & HF_CS32_MASK) != 0)); + g_assert(CODE64(dc) == ((flags & HF_CS64_MASK) != 0)); g_assert(SS32(dc) == ((flags & HF_SS32_MASK) != 0)); dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; @@ -8512,7 +8517,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->cpuid_xsave_features = env->features[FEAT_XSAVE]; #ifdef TARGET_X86_64 dc->lma = (flags >> HF_LMA_SHIFT) & 1; - dc->code64 = (flags >> HF_CS64_SHIFT) & 1; #endif dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)); From patchwork Sun Feb 28 23:22:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445352 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 13/50] target/i386: Assert LMA for x86_64 user-only Date: Sun, 28 Feb 2021 15:22:44 -0800 Message-Id: <20210228232321.322053-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" LMA is a pre-requisite for CODE64, so there is no way to disable it for x86_64-linux-user, and there is no way to enable it for i386. Since we're adding an accessor macro, pull the value directly out of flags when we're not assuming a constant. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index e7f4392d55..c8728397d0 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -99,7 +99,6 @@ typedef struct DisasContext { #endif #ifdef TARGET_X86_64 - int lma; /* long mode active */ int rex_x, rex_b; #endif int vex_l; /* vex vector length */ @@ -164,10 +163,13 @@ typedef struct DisasContext { #endif #if !defined(TARGET_X86_64) #define CODE64(S) false +#define LMA(S) false #elif defined(CONFIG_USER_ONLY) #define CODE64(S) true +#define LMA(S) true #else #define CODE64(S) (((S)->flags & HF_CS64_MASK) != 0) +#define LMA(S) (((S)->flags & HF_LMA_MASK) != 0) #endif static void gen_eob(DisasContext *s); @@ -7289,7 +7291,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) } else { gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1)); /* condition codes are modified only in long mode */ - if (s->lma) { + if (LMA(s)) { set_cc_op(s, CC_OP_EFLAGS); } /* TF handling for the sysret insn is different. The TF bit is @@ -8497,6 +8499,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(CODE32(dc) == ((flags & HF_CS32_MASK) != 0)); g_assert(CODE64(dc) == ((flags & HF_CS64_MASK) != 0)); g_assert(SS32(dc) == ((flags & HF_SS32_MASK) != 0)); + g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0)); dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; dc->f_st = 0; @@ -8515,9 +8518,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX]; dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX]; dc->cpuid_xsave_features = env->features[FEAT_XSAVE]; -#ifdef TARGET_X86_64 - dc->lma = (flags >> HF_LMA_SHIFT) & 1; -#endif dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)); /* Do not optimize repz jumps at all in icount mode, because From patchwork Sun Feb 28 23:22:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445359 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=agasLxkV; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpfy93r2tz9sVw for ; Mon, 1 Mar 2021 10:40:01 +1100 (AEDT) Received: from localhost ([::1]:39778 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVfL-0006aO-Fc for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:39:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPn-0005To-GK for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:55 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:39294) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPV-0007iI-6R for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:55 -0500 Received: by mail-pl1-x632.google.com with SMTP id k22so8761988pll.6 for ; Sun, 28 Feb 2021 15:23:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eWU48+PmRMax2TIUlWmTbNBZGlHPNyOmd8zQuonIrmY=; b=agasLxkVbDR2asl2wYEV9qXQy61UhPH+QOMW8JBVAz9VnXgzopRJBvuDY7l1VOVvLT 5m9n7DwQMOSg6xfUmSN+UOsl4dRHQblPw/ZZ5ktqO33ixAdu2Yvx7A9r77jzY4imslt2 +vPftpDlVud0JtGW5F0aEJL51hgGY89nULz5xUjP0pepn2zymjPkYcnZF3PsjmEsIeHC vD4kQcpcDV5doWRD9qokSm9gGVfh0ab6hRfJFdaMwUD0UM8EM5ivvDkKdt4W3b5J3gB9 K7yuByw+Y2xbwqzz2qnmZYs2D6IpBAL9j3jxR8tWj7KobvdDE/RLF7hqJWqU7/Cads63 rc1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eWU48+PmRMax2TIUlWmTbNBZGlHPNyOmd8zQuonIrmY=; b=BdOEBuusa7/jjoaSkPBfRWM/8fmx6K7mdXfdFcWSvlgYoZZrRpMRHPDBU58SUn31k4 WR8XJdV3GGd4G3ZDdfQW3ijk/yWihyEA4D1t8AXI6BjNyTCG9K7TenCUMZEm4oy7Utbw 9S9PovH3/tdXobwjizkyvnZw6P/LppxvaqUOruhRCu7nhe4Q/FNNvSpFcHBydlkKQ2zu PiTRQfc+cD7Bg+otT2EXyiJYfJllfnBq86/ZstWsZyc9hIRnD2xdohJmRrYj4RJwo7fr Q8gOH5Fn65+a/AT1v0SFdp1nFi2kYK592Q5Wc5VTvR2mJitmQL0X3pXTjcC2BdlTI00Y D7+A== X-Gm-Message-State: AOAM5329ZRqRZsWYV3+Qqe3cuczRUQuXiAr5DS58OBVGN1mzt38FS24b QN0QsSlBqLFWOti97AkmxcQ/aMWPjmhB5g== X-Google-Smtp-Source: ABdhPJx4QcD3Yf2h7PGzGzyCYRVX4BooUam4YC+zOO1Q1KDuLoqtHaMwttdytq/7exiQ7hM0RRv70g== X-Received: by 2002:a17:90a:5d14:: with SMTP id s20mr6464631pji.6.1614554615721; Sun, 28 Feb 2021 15:23:35 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 14/50] target/i386: Assert !ADDSEG for x86_64 user-only Date: Sun, 28 Feb 2021 15:22:45 -0800 Message-Id: <20210228232321.322053-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" LMA disables traditional segmentation, exposing a flat address space. This means that ADDSEG is off. Since we're adding an accessor macro, pull the value directly out of flags otherwise. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index c8728397d0..33da97d0a6 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -108,7 +108,6 @@ typedef struct DisasContext { #ifdef TARGET_X86_64 bool x86_64_hregs; #endif - int addseg; /* non zero if either DS/ES/SS have a non zero base */ int f_st; /* currently unused */ int tf; /* TF cpu flag */ int jmp_opt; /* use direct block chaining for direct jumps */ @@ -156,10 +155,12 @@ typedef struct DisasContext { #define VM86(S) false #define CODE32(S) true #define SS32(S) true +#define ADDSEG(S) false #else #define VM86(S) (((S)->flags & HF_VM_MASK) != 0) #define CODE32(S) (((S)->flags & HF_CS32_MASK) != 0) #define SS32(S) (((S)->flags & HF_SS32_MASK) != 0) +#define ADDSEG(S) (((S)->flags & HF_ADDSEG_MASK) != 0) #endif #if !defined(TARGET_X86_64) #define CODE64(S) false @@ -492,7 +493,7 @@ static void gen_lea_v_seg(DisasContext *s, MemOp aflag, TCGv a0, #endif case MO_32: /* 32 bit address */ - if (ovr_seg < 0 && s->addseg) { + if (ovr_seg < 0 && ADDSEG(s)) { ovr_seg = def_seg; } if (ovr_seg < 0) { @@ -505,7 +506,7 @@ static void gen_lea_v_seg(DisasContext *s, MemOp aflag, TCGv a0, tcg_gen_ext16u_tl(s->A0, a0); a0 = s->A0; if (ovr_seg < 0) { - if (s->addseg) { + if (ADDSEG(s)) { ovr_seg = def_seg; } else { return; @@ -2429,7 +2430,7 @@ static void gen_push_v(DisasContext *s, TCGv val) tcg_gen_subi_tl(s->A0, cpu_regs[R_ESP], size); if (!CODE64(s)) { - if (s->addseg) { + if (ADDSEG(s)) { new_esp = s->tmp4; tcg_gen_mov_tl(new_esp, s->A0); } @@ -8500,8 +8501,8 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(CODE64(dc) == ((flags & HF_CS64_MASK) != 0)); g_assert(SS32(dc) == ((flags & HF_SS32_MASK) != 0)); g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0)); + g_assert(ADDSEG(dc) == ((flags & HF_ADDSEG_MASK) != 0)); - dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; dc->f_st = 0; dc->tf = (flags >> TF_SHIFT) & 1; dc->cc_op = CC_OP_DYNAMIC; From patchwork Sun Feb 28 23:22:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445356 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 15/50] target/i386: Introduce REX_PREFIX Date: Sun, 28 Feb 2021 15:22:46 -0800 Message-Id: <20210228232321.322053-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The existing flag, x86_64_hregs, does not accurately describe its setting. It is true if and only if a REX prefix has been seen. Yes, that affects the "h" regs, but that's secondary. Add PREFIX_REX and include this bit in s->prefix. Add REX_PREFIX so that the check folds away when x86_64 is compiled out. Fold away the reg >= 8 check, because bit 3 of the register number comes from the REX prefix in the first place. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 29 +++++++++++------------------ 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 33da97d0a6..31b128d4fe 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -39,6 +39,7 @@ #define PREFIX_DATA 0x08 #define PREFIX_ADR 0x10 #define PREFIX_VEX 0x20 +#define PREFIX_REX 0x40 #ifdef TARGET_X86_64 #define REX_X(s) ((s)->rex_x) @@ -105,9 +106,6 @@ typedef struct DisasContext { int vex_v; /* vex vvvv register, without 1's complement. */ CCOp cc_op; /* current CC operation */ bool cc_op_dirty; -#ifdef TARGET_X86_64 - bool x86_64_hregs; -#endif int f_st; /* currently unused */ int tf; /* TF cpu flag */ int jmp_opt; /* use direct block chaining for direct jumps */ @@ -173,6 +171,12 @@ typedef struct DisasContext { #define LMA(S) (((S)->flags & HF_LMA_MASK) != 0) #endif +#ifdef TARGET_X86_64 +#define REX_PREFIX(S) (((S)->prefix & PREFIX_REX) != 0) +#else +#define REX_PREFIX(S) false +#endif + static void gen_eob(DisasContext *s); static void gen_jr(DisasContext *s, TCGv dest); static void gen_jmp(DisasContext *s, target_ulong eip); @@ -336,14 +340,10 @@ static void gen_update_cc_op(DisasContext *s) */ static inline bool byte_reg_is_xH(DisasContext *s, int reg) { - if (reg < 4) { + /* Any time the REX prefix is present, byte registers are uniform */ + if (reg < 4 || REX_PREFIX(s)) { return false; } -#ifdef TARGET_X86_64 - if (reg >= 8 || s->x86_64_hregs) { - return false; - } -#endif return true; } @@ -4559,7 +4559,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) #ifdef TARGET_X86_64 s->rex_x = 0; s->rex_b = 0; - s->x86_64_hregs = false; #endif s->rip_offset = 0; /* for relative ip address */ s->vex_l = 0; @@ -4614,12 +4613,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x40 ... 0x4f: if (CODE64(s)) { /* REX prefix */ + prefixes |= PREFIX_REX; rex_w = (b >> 3) & 1; rex_r = (b & 0x4) << 1; s->rex_x = (b & 0x2) << 2; REX_B(s) = (b & 0x1) << 3; - /* select uniform byte register addressing */ - s->x86_64_hregs = true; goto next_byte; } break; @@ -4643,14 +4641,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */ if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ - | PREFIX_LOCK | PREFIX_DATA)) { + | PREFIX_LOCK | PREFIX_DATA | PREFIX_REX)) { goto illegal_op; } -#ifdef TARGET_X86_64 - if (s->x86_64_hregs) { - goto illegal_op; - } -#endif rex_r = (~vex2 >> 4) & 8; if (b == 0xc5) { /* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode byte */ From patchwork Sun Feb 28 23:22:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445355 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 16/50] target/i386: Tidy REX_B, REX_X definition Date: Sun, 28 Feb 2021 15:22:47 -0800 Message-Id: <20210228232321.322053-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Change the storage from int to uint8_t since the value is in {0,8}. For x86_64 add 0 in the macros to (1) promote the type back to int, and (2) make the macro an rvalue. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 31b128d4fe..605b80229a 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -41,14 +41,6 @@ #define PREFIX_VEX 0x20 #define PREFIX_REX 0x40 -#ifdef TARGET_X86_64 -#define REX_X(s) ((s)->rex_x) -#define REX_B(s) ((s)->rex_b) -#else -#define REX_X(s) 0 -#define REX_B(s) 0 -#endif - #ifdef TARGET_X86_64 # define ctztl ctz64 # define clztl clz64 @@ -100,7 +92,8 @@ typedef struct DisasContext { #endif #ifdef TARGET_X86_64 - int rex_x, rex_b; + uint8_t rex_x; + uint8_t rex_b; #endif int vex_l; /* vex vector length */ int vex_v; /* vex vvvv register, without 1's complement. */ @@ -173,8 +166,12 @@ typedef struct DisasContext { #ifdef TARGET_X86_64 #define REX_PREFIX(S) (((S)->prefix & PREFIX_REX) != 0) +#define REX_X(S) ((S)->rex_x + 0) +#define REX_B(S) ((S)->rex_b + 0) #else #define REX_PREFIX(S) false +#define REX_X(S) 0 +#define REX_B(S) 0 #endif static void gen_eob(DisasContext *s); @@ -4617,7 +4614,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) rex_w = (b >> 3) & 1; rex_r = (b & 0x4) << 1; s->rex_x = (b & 0x2) << 2; - REX_B(s) = (b & 0x1) << 3; + s->rex_b = (b & 0x1) << 3; goto next_byte; } break; From patchwork Sun Feb 28 23:22:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445354 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=XviND/Lm; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpftf5JWbz9sRR for ; Mon, 1 Mar 2021 10:36:58 +1100 (AEDT) Received: from localhost ([::1]:59094 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVcN-0002vj-Kv for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:36:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43666) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPp-0005Z3-Ok for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:57 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:36925) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPZ-0007ir-0q for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:57 -0500 Received: by mail-pj1-x102d.google.com with SMTP id u12so10241318pjr.2 for ; Sun, 28 Feb 2021 15:23:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5sMrPCvBvZcRNI0f+4NGvi10dnGYsatk73CQtS7iOqk=; b=XviND/LmawhHzDOwdpfeeRqtWUdkMKvIRPzJqSSovblGu50Vzhz4TCToSwuLGapPmj hazn1ycqqVY/3+WluzsgajCZKQuZLdIyXwXgNMiKR/mLZBWGngmEk58tp1iT5IXq4o/9 p3UPrpYkfZSmy2z8AUwWqpQkwWX1qBSdaG4gdQSImhIiqTTCC98zhx14cuLhO5W+F0jc 8lfLsWBzXFAsH/k7oyc866++pGl2/suRmkQ2dXItVyG4WNX9LeLw1OpIYScfdrZBlGGn 74scrtcPglEWHdUAFactSfw9+qVc2s4F188hxwf3jfcMUV2FdgqbzyBCB5Pv1XYzdjy2 6JDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5sMrPCvBvZcRNI0f+4NGvi10dnGYsatk73CQtS7iOqk=; b=baCzIsBxmVWJQUvxsW8nnz61W8v8b8vNyUT/Y4eDgVzuCUNZKKebvlADw3hysvWqKh shB6eB6Im3An3BBQiDFFSal3+EFm0ugNuOfgbbfPA0ofgKeiANeyvMnbUgB8AJmWax8V aUFqZyg3kpafCzi21DRNcFiqc05EcVsbYeBycvzo3Tci2Mx6QcIhG322I+KspWHvbw7F gpKMJ2U87KLKQm1W8Ba/rmx+/9MoMRPxolgCm6UeA6tPNye8gt830GfPH/Cq4+Tl81eO c7VSmajTAyl4TUGCwadu66L2gB4KLWNCDMj/gkj61BQZEfCTC65S9ZPZdCSSGWjhl8L9 kaUA== X-Gm-Message-State: AOAM532hRoAXA03BhThiX5WEjHBKvSc78BxVakynN5QYsfEG7PGYywOy z6uJoSKs44Gp/Xdbn1ek18W7fnCh5cnYrg== X-Google-Smtp-Source: ABdhPJyOFyVK+r2ER6kRssMHJT7b549YyQPrQd2qKlv4Mnau93dVnbZOnbOFJ70uPaSarCF/63dWJA== X-Received: by 2002:a17:903:248f:b029:de:c703:9839 with SMTP id p15-20020a170903248fb02900dec7039839mr13020757plw.42.1614554618432; Sun, 28 Feb 2021 15:23:38 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 17/50] target/i386: Move rex_r into DisasContext Date: Sun, 28 Feb 2021 15:22:48 -0800 Message-Id: <20210228232321.322053-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Treat this flag exactly like we treat rex_b and rex_x. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 84 ++++++++++++++++++++----------------- 1 file changed, 45 insertions(+), 39 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 605b80229a..aa10d0ba99 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -92,6 +92,7 @@ typedef struct DisasContext { #endif #ifdef TARGET_X86_64 + uint8_t rex_r; uint8_t rex_x; uint8_t rex_b; #endif @@ -166,10 +167,12 @@ typedef struct DisasContext { #ifdef TARGET_X86_64 #define REX_PREFIX(S) (((S)->prefix & PREFIX_REX) != 0) +#define REX_R(S) ((S)->rex_r + 0) #define REX_X(S) ((S)->rex_x + 0) #define REX_B(S) ((S)->rex_b + 0) #else #define REX_PREFIX(S) false +#define REX_R(S) 0 #define REX_X(S) 0 #define REX_B(S) 0 #endif @@ -3094,7 +3097,7 @@ static const struct SSEOpHelper_eppi sse_op_table7[256] = { }; static void gen_sse(CPUX86State *env, DisasContext *s, int b, - target_ulong pc_start, int rex_r) + target_ulong pc_start) { int b1, op1_offset, op2_offset, is_xmm, val; int modrm, mod, rm, reg; @@ -3164,8 +3167,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, modrm = x86_ldub_code(env, s); reg = ((modrm >> 3) & 7); - if (is_xmm) - reg |= rex_r; + if (is_xmm) { + reg |= REX_R(s); + } mod = (modrm >> 6) & 3; if (sse_fn_epp == SSE_SPECIAL) { b |= (b1 << 8); @@ -3699,7 +3703,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, tcg_gen_ld16u_tl(s->T0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val))); } - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); gen_op_mov_reg_v(s, ot, reg, s->T0); break; case 0x1d6: /* movq ea, xmm */ @@ -3743,7 +3747,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, offsetof(CPUX86State, fpregs[rm].mmx)); gen_helper_pmovmskb_mmx(s->tmp2_i32, cpu_env, s->ptr0); } - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); tcg_gen_extu_i32_tl(cpu_regs[reg], s->tmp2_i32); break; @@ -3755,7 +3759,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } modrm = x86_ldub_code(env, s); rm = modrm & 7; - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; if (b1 >= 2) { goto unknown_op; @@ -3831,7 +3835,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, /* Various integer extensions at 0f 38 f[0-f]. */ b = modrm | (b1 << 8); modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); switch (b) { case 0x3f0: /* crc32 Gd,Eb */ @@ -4185,7 +4189,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, b = modrm; modrm = x86_ldub_code(env, s); rm = modrm & 7; - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; if (b1 >= 2) { goto unknown_op; @@ -4205,7 +4209,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, rm = (modrm & 7) | REX_B(s); if (mod != 3) gen_lea_modrm(env, s, modrm); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); val = x86_ldub_code(env, s); switch (b) { case 0x14: /* pextrb */ @@ -4374,7 +4378,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, /* Various integer extensions at 0f 3a f[0-f]. */ b = modrm | (b1 << 8); modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); switch (b) { case 0x3f0: /* rorx Gy,Ey, Ib */ @@ -4548,12 +4552,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) MemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; - int rex_w, rex_r; + int rex_w; target_ulong pc_start = s->base.pc_next; s->pc_start = s->pc = pc_start; s->override = -1; #ifdef TARGET_X86_64 + s->rex_r = 0; s->rex_x = 0; s->rex_b = 0; #endif @@ -4567,7 +4572,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) prefixes = 0; rex_w = -1; - rex_r = 0; next_byte: b = x86_ldub_code(env, s); @@ -4612,7 +4616,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /* REX prefix */ prefixes |= PREFIX_REX; rex_w = (b >> 3) & 1; - rex_r = (b & 0x4) << 1; + s->rex_r = (b & 0x4) << 1; s->rex_x = (b & 0x2) << 2; s->rex_b = (b & 0x1) << 3; goto next_byte; @@ -4641,7 +4645,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) | PREFIX_LOCK | PREFIX_DATA | PREFIX_REX)) { goto illegal_op; } - rex_r = (~vex2 >> 4) & 8; +#ifdef TARGET_X86_64 + s->rex_r = (~vex2 >> 4) & 8; +#endif if (b == 0xc5) { /* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode byte */ vex3 = vex2; @@ -4731,7 +4737,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) switch(f) { case 0: /* OP Ev, Gv */ modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); if (mod != 3) { @@ -4753,7 +4759,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 1: /* OP Gv, Ev */ modrm = x86_ldub_code(env, s); mod = (modrm >> 6) & 3; - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); rm = (modrm & 7) | REX_B(s); if (mod != 3) { gen_lea_modrm(env, s, modrm); @@ -5173,7 +5179,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) ot = mo_b_d(b, dflag); modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_op_mov_v_reg(s, ot, s->T1, reg); @@ -5245,7 +5251,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x6b: ot = dflag; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); if (b == 0x69) s->rip_offset = insn_const_size(ot); else if (b == 0x6b) @@ -5297,7 +5303,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x1c1: /* xadd Ev, Gv */ ot = mo_b_d(b, dflag); modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; gen_op_mov_v_reg(s, ot, s->T0, reg); if (mod == 3) { @@ -5329,7 +5335,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) ot = mo_b_d(b, dflag); modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; oldv = tcg_temp_new(); newv = tcg_temp_new(); @@ -5551,7 +5557,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x89: /* mov Gv, Ev */ ot = mo_b_d(b, dflag); modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); /* generate a generic store */ gen_ldst_modrm(env, s, modrm, ot, reg, 1); @@ -5577,7 +5583,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x8b: /* mov Ev, Gv */ ot = mo_b_d(b, dflag); modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_op_mov_reg_v(s, ot, reg, s->T0); @@ -5627,7 +5633,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) s_ot = b & 8 ? MO_SIGN | ot : ot; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); @@ -5666,7 +5672,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) mod = (modrm >> 6) & 3; if (mod == 3) goto illegal_op; - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); { AddressParts a = gen_lea_modrm_0(env, s, modrm); TCGv ea = gen_lea_modrm_1(s, a); @@ -5748,7 +5754,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x87: /* xchg Ev, Gv */ ot = mo_b_d(b, dflag); modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; if (mod == 3) { rm = (modrm & 7) | REX_B(s); @@ -5785,7 +5791,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) do_lxx: ot = dflag != MO_16 ? MO_32 : MO_16; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; if (mod == 3) goto illegal_op; @@ -5868,7 +5874,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) modrm = x86_ldub_code(env, s); mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); if (mod != 3) { gen_lea_modrm(env, s, modrm); opreg = OR_TMP0; @@ -6722,7 +6728,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) } ot = dflag; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); gen_cmovcc1(env, s, ot, b, modrm, reg); break; @@ -6868,7 +6874,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) do_btx: ot = dflag; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); gen_op_mov_v_reg(s, MO_32, s->T1, reg); @@ -6973,7 +6979,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x1bd: /* bsr / lzcnt */ ot = dflag; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_extu(ot, s->T0); @@ -7700,7 +7706,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) d_ot = dflag; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); @@ -7774,7 +7780,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; ot = dflag != MO_16 ? MO_32 : MO_16; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); t0 = tcg_temp_local_new(); gen_update_cc_op(s); @@ -7815,7 +7821,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) modrm = x86_ldub_code(env, s); if (s->flags & HF_MPX_EN_MASK) { mod = (modrm >> 6) & 3; - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); if (prefixes & PREFIX_REPZ) { /* bndcl */ if (reg >= 4 @@ -7905,7 +7911,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) modrm = x86_ldub_code(env, s); if (s->flags & HF_MPX_EN_MASK) { mod = (modrm >> 6) & 3; - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); if (mod != 3 && (prefixes & PREFIX_REPZ)) { /* bndmk */ if (reg >= 4 @@ -8017,7 +8023,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) * are assumed to be 1's, regardless of actual values. */ rm = (modrm & 7) | REX_B(s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); if (CODE64(s)) ot = MO_64; else @@ -8070,7 +8076,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) * are assumed to be 1's, regardless of actual values. */ rm = (modrm & 7) | REX_B(s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); if (CODE64(s)) ot = MO_64; else @@ -8112,7 +8118,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) mod = (modrm >> 6) & 3; if (mod == 3) goto illegal_op; - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); /* generate a generic store */ gen_ldst_modrm(env, s, modrm, ot, reg, 1); break; @@ -8344,7 +8350,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); if (s->prefix & PREFIX_DATA) { ot = MO_16; @@ -8372,7 +8378,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x1c2: case 0x1c4 ... 0x1c6: case 0x1d0 ... 0x1fe: - gen_sse(env, s, b, pc_start, rex_r); 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 18/50] target/i386: Move rex_w into DisasContext Date: Sun, 28 Feb 2021 15:22:49 -0800 Message-Id: <20210228232321.322053-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Treat this flag exactly like we treat the other rex bits. The -1 initialization is unused; the two tests are > 0 and == 1, so the value can be reduced to a bool. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index aa10d0ba99..deb1e43430 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -95,6 +95,7 @@ typedef struct DisasContext { uint8_t rex_r; uint8_t rex_x; uint8_t rex_b; + bool rex_w; #endif int vex_l; /* vex vector length */ int vex_v; /* vex vvvv register, without 1's complement. */ @@ -167,11 +168,13 @@ typedef struct DisasContext { #ifdef TARGET_X86_64 #define REX_PREFIX(S) (((S)->prefix & PREFIX_REX) != 0) +#define REX_W(S) ((S)->rex_w) #define REX_R(S) ((S)->rex_r + 0) #define REX_X(S) ((S)->rex_x + 0) #define REX_B(S) ((S)->rex_b + 0) #else #define REX_PREFIX(S) false +#define REX_W(S) false #define REX_R(S) 0 #define REX_X(S) 0 #define REX_B(S) 0 @@ -4552,12 +4555,12 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) MemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; - int rex_w; target_ulong pc_start = s->base.pc_next; s->pc_start = s->pc = pc_start; s->override = -1; #ifdef TARGET_X86_64 + s->rex_w = false; s->rex_r = 0; s->rex_x = 0; s->rex_b = 0; @@ -4571,7 +4574,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) } prefixes = 0; - rex_w = -1; next_byte: b = x86_ldub_code(env, s); @@ -4615,7 +4617,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (CODE64(s)) { /* REX prefix */ prefixes |= PREFIX_REX; - rex_w = (b >> 3) & 1; + s->rex_w = (b >> 3) & 1; s->rex_r = (b & 0x4) << 1; s->rex_x = (b & 0x2) << 2; s->rex_b = (b & 0x1) << 3; @@ -4654,12 +4656,12 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) b = x86_ldub_code(env, s) | 0x100; } else { /* 3-byte VEX prefix: RXBmmmmm wVVVVlpp */ + vex3 = x86_ldub_code(env, s); #ifdef TARGET_X86_64 s->rex_x = (~vex2 >> 3) & 8; s->rex_b = (~vex2 >> 2) & 8; + s->rex_w = (vex3 >> 7) & 1; #endif - vex3 = x86_ldub_code(env, s); - rex_w = (vex3 >> 7) & 1; switch (vex2 & 0x1f) { case 0x01: /* Implied 0f leading opcode bytes. */ b = x86_ldub_code(env, s) | 0x100; @@ -4686,7 +4688,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /* In 64-bit mode, the default data size is 32-bit. Select 64-bit data with rex_w, and 16-bit data with 0x66; rex_w takes precedence over 0x66 if both are present. */ - dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_16 : MO_32); + dflag = (REX_W(s) ? MO_64 : prefixes & PREFIX_DATA ? MO_16 : MO_32); /* In 64-bit mode, 0x67 selects 32-bit addressing. */ aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64); } else { @@ -5082,7 +5084,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /* operand size for jumps is 64 bit */ ot = MO_64; } else if (op == 3 || op == 5) { - ot = dflag != MO_16 ? MO_32 + (rex_w == 1) : MO_16; + ot = dflag != MO_16 ? MO_32 + REX_W(s) : MO_16; } else if (op == 6) { /* default push size is 64 bit */ ot = mo_pushpop(s, dflag); From patchwork Sun Feb 28 23:22:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445341 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=SnP2my/S; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpfgf1JHsz9sR4 for ; Mon, 1 Mar 2021 10:27:26 +1100 (AEDT) Received: from localhost ([::1]:34092 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVTA-0000e5-5g for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:27:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43642) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPo-0005V0-EC for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:56 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:42628) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPa-0007jO-AU for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:56 -0500 Received: by mail-pl1-x62a.google.com with SMTP id s16so8756376plr.9 for ; Sun, 28 Feb 2021 15:23:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zJUfAY1VyGRTYaSFMvv3X+jRgCoxyXqIhxTpwb/I4ZE=; b=SnP2my/SyyHg3NsXQyEdUTKs4QJqM50Fo9IeYmtNhTIEqE0a1bh/8h5HxFEB/je+Xi sm/M9dKyBYgcLr/Ylmok4KoLGKPliatvD3yt7ECAUArfICECYy+EOu7ciZNrCWNLMS7h 3+MGpo4xpRrFu0wTolhKUk7K805O9nrlR4Fjrh6rAQz0ilqOfbexE9O0j3UqAM/PN0qZ smpqEES6cdn3HJFttA7cgo111SQACwuHcAwaD1kJNYcjuDvBNc9aSj4VKQOMuxt0VUoE BZgp4UXzQlaeVBjaVhcFi7QbkJAGTxSAF9AfnD6SbouHlY1EObIgg8Y/qR/cqTusEP5R wGVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zJUfAY1VyGRTYaSFMvv3X+jRgCoxyXqIhxTpwb/I4ZE=; b=OPE6hTRsudWpvuvIJ/IfREZw74mKDr7khugdbMCVJ/4qRPVe+m1xBBRja87bkrMfS+ mcbyPiS5J4WN60gX7q/eOdBTlfBVbYdtUmQArfda3NBvqdBcKQlxAIAe7ThSgdGtpo7b hilKv8wF/OlWyJvl34bql3WPqwjywJr1EXmPtrQL4+wtFMj9tK/5Te8We6J/e4Wm1yGR IbfPEKCB9S02Yewd7r41pnWnCjU2ncpZIEbdUhpH4SeGhJs2HBvWGZGxWSRhX9vVDhT1 9aCVq3/BnRCnRQgnHIM35Xgl6nNwOn07VA32YU5ULVzSBOr0YDjrgxzBzdi4g/aH9u95 W96A== X-Gm-Message-State: AOAM532L09L7CjzQjAR7j4ZvEnJTAUM94MBinV2P4I+aR9SnKvJWTfGy ZLK2mnx85BL4Aq8y5oMd0+o2RwXJ3WoYmg== X-Google-Smtp-Source: ABdhPJzWRv3zLm/o+rH7ByBSfTqOsrvETMordxooxUBJ0KnSw1AwAuiD8lsESjrqzFvNholfwZpmdg== X-Received: by 2002:a17:90a:4888:: with SMTP id b8mr14238696pjh.106.1614554620049; Sun, 28 Feb 2021 15:23:40 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 19/50] target/i386: Remove DisasContext.f_st as unused Date: Sun, 28 Feb 2021 15:22:50 -0800 Message-Id: <20210228232321.322053-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index deb1e43430..f4af92886f 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -101,7 +101,6 @@ typedef struct DisasContext { int vex_v; /* vex vvvv register, without 1's complement. */ CCOp cc_op; /* current CC operation */ bool cc_op_dirty; - int f_st; /* currently unused */ int tf; /* TF cpu flag */ int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ @@ -8501,7 +8500,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0)); g_assert(ADDSEG(dc) == ((flags & HF_ADDSEG_MASK) != 0)); - dc->f_st = 0; dc->tf = (flags >> TF_SHIFT) & 1; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; From patchwork Sun Feb 28 23:22:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445377 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 20/50] target/i386: Reduce DisasContext.flags to uint32_t Date: Sun, 28 Feb 2021 15:22:51 -0800 Message-Id: <20210228232321.322053-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The value comes from tb->flags, which is uint32_t. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index f4af92886f..39af69585f 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -105,7 +105,7 @@ typedef struct DisasContext { int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ int mem_index; /* select memory access functions */ - uint64_t flags; /* all execution flags */ + uint32_t flags; /* all execution flags */ int popl_esp_hack; /* for correct popl with esp base handling */ int rip_offset; /* only used in x86_64, but left for simplicity */ int cpuid_features; From patchwork Sun Feb 28 23:22:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=QKytV8i7; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpg4z5wJhz9sRR for ; Mon, 1 Mar 2021 10:45:55 +1100 (AEDT) Received: from localhost ([::1]:56598 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVl3-000571-OK for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:45:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43648) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPo-0005WK-R0 for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:56 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:36349) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPc-0007jb-D2 for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:56 -0500 Received: by mail-pj1-x1036.google.com with SMTP id s23so10488953pji.1 for ; Sun, 28 Feb 2021 15:23:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bk2/HEa3eVWiJHWySA58FMUKA4eJmzbnbZ4nVyAtnoo=; b=QKytV8i7zTEWOmiupA63yM8h7zzF7CsT8MQoFZQBv4PWJHI1ALn4AZhlAkN+7AXAKB xW/VEblDOQ+QEiriNJBDimgr7advnYf0PX2ai4UEcq1HHW5Zk5oPO5/YoMa/fcsMpZa8 pPejVjC45IrU9s0wFnLfTnlMC8SKV8n5xnLtHKRn7Tj6OT588EHyQIxbaE5Q8Q2sDdpg mg3YjY8OL2kTKWDV8gOPRWWKJy2iAAcZ/vO980myMnakikXrZpzeKmYsbDJpcVk2njwg 5KXmWy6HB24kkgCgRaegO8eLHcJadOygxBC/ARL8ea0BfdQlCGHoxrwIsA8plKox8kNN ew5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bk2/HEa3eVWiJHWySA58FMUKA4eJmzbnbZ4nVyAtnoo=; b=j3Jve7UAXv3j4klGlB7n8yaIHooomrXGCNc9d/e2dA87zqz1V0UHMGKpu5SlyxBqYf Xg58DOyS6o1GMA6sDV+QAO33rEewyLVs4XujIT56ib1UF1ZKaFMkiqDMXKuxFv/R9Acq Xsx3SEkwbSry32gz7paDvh6nGyaRnha/kOUmS5PvDXZ/yvIDcKc7AbgluHEpQ7Eoivc6 GnO+U5gtGzIG0JywvHW5ZuP3onO+wXQ4NpQ9nE8anbF60JlLnOdqXLQHu0zIQ4/7MPX8 9p4D9/O6RyfIFiihrd9tMcJkM0sC1b3mnQ3TSgXevtSRljWnI0IueiyQZ7Kwy+s4Ehyk QaSQ== X-Gm-Message-State: AOAM530r4krrWxbwX9du7cFFnvhi6WAaND6JHelqQrLUwgrIDz/dzCC+ FljFt+2oLidKf6DhuGBb3C8enSrDdZGVhg== X-Google-Smtp-Source: ABdhPJz9QsVhmvm2bXwXKE1kA/+OP6w6V3aKZT1YQrAjdxtV5L3KMbLjMUAA15xkLOksosDnWa3uQg== X-Received: by 2002:a17:902:369:b029:e4:b5f1:cfb4 with SMTP id 96-20020a1709020369b02900e4b5f1cfb4mr1184184pld.60.1614554622071; Sun, 28 Feb 2021 15:23:42 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 21/50] target/i386: Reduce DisasContext.override to int8_t Date: Sun, 28 Feb 2021 15:22:52 -0800 Message-Id: <20210228232321.322053-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The range of values is -1 (none) to 5 (R_GS). Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 39af69585f..19c2034344 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -77,7 +77,7 @@ typedef struct DisasContext { DisasContextBase base; /* current insn context */ - int override; /* -1 if no override */ + int8_t override; /* -1 if no override, else R_CS, R_DS, etc */ int prefix; MemOp aflag; MemOp dflag; From patchwork Sun Feb 28 23:22:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445362 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=vZHpIMGm; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpg2M4HtNz9sSC for ; Mon, 1 Mar 2021 10:43:39 +1100 (AEDT) Received: from localhost ([::1]:48232 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVir-0001iV-FF for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:43:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43690) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPq-0005bt-PN for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:58 -0500 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:37159) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPc-0007kH-VQ for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:58 -0500 Received: by mail-pg1-x52c.google.com with SMTP id o10so10361881pgg.4 for ; Sun, 28 Feb 2021 15:23:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=s1JQvNSusTUc8RlPgZx0OC+J+/b+DyOZSi+hnuBILZY=; b=vZHpIMGmN/SeRh7r4Y1pJYGmUo6iUtClj6aXZ888DkxIXK3hC1g/cNpHd/z26GAuKN b3BlCJkv8xZL/6pjDQq2DJIRcJU6ZgheNIQTy/pxw1OEFqBg4AfJpnlIcN2KXa+YqyRh b31kvPn3kol3u4yA5IfiyCz5XazfSNP7zxp6gRwnp8PdqiGmAXfUEwt8n6SFoL2jspOb kG43PRXEfdhQ6S7Yo18S0Sgd8Rwk3PeOssImAZ7kKQ9es5yorVlXGeKZpM/6QSDtx5Up 6q9hqS68uTubItmvKEoVLgHOluqw1H2OEaRmaLophD78e836llBD2qcMhnXvB42YoGcR iBJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=s1JQvNSusTUc8RlPgZx0OC+J+/b+DyOZSi+hnuBILZY=; b=WgUqxWQVSongAruGJtKMCO3Rd/RaHwdN6tdeWgTTJqBPqxOjlixtLCK+cat8oKgMqK LwapS1T09e03ONgmccNOVXfxewWHnh+WP5VJHi6neOPa930sRb93a2i+lvreD5YlQuUJ Bhx8o0AJXIt9nA9hX/Pc1k9Vd6jUSHHUp3U+31udwTL1M17jcagIgxbAdPEemFM0Gpf9 B3ERL3VjbJUhabeLbIGOjHVSYn8G37FPuYoIatOCf2g86psLEY5FAaNgJGJMITQ42gvN rVcBF4hrpiNGftG/3HCGeR9CrklQx8Fp23E/umRaeF4Sf30Du6Pu0VLlR4VibrCL0m5u 6nPg== X-Gm-Message-State: AOAM5308gDeaIU5JJZZNvRtIqo3G/QPUBHs/4YA+qPBM4uzpWOE1G0df cEprquFIjM66D1Z2ImVUlZDKqFPoSIwY5w== X-Google-Smtp-Source: ABdhPJy0yZNP9AVsdKSXP7+a/X1JjagavCbBf8gYOGjqGZ5kkUkO2ptbfDrfCnUjYU76EBK6jACXZA== X-Received: by 2002:a63:f808:: with SMTP id n8mr11330443pgh.115.1614554623109; Sun, 28 Feb 2021 15:23:43 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 22/50] target/i386: Reduce DisasContext.prefix to uint8_t Date: Sun, 28 Feb 2021 15:22:53 -0800 Message-Id: <20210228232321.322053-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The highest bit in this set is 0x40 (PREFIX_REX). Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 19c2034344..79f987b2cf 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -78,7 +78,7 @@ typedef struct DisasContext { /* current insn context */ int8_t override; /* -1 if no override, else R_CS, R_DS, etc */ - int prefix; + uint8_t prefix; MemOp aflag; MemOp dflag; target_ulong pc_start; From patchwork Sun Feb 28 23:22:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445347 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=zKgIOFah; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpfkq0jHbz9sR4 for ; Mon, 1 Mar 2021 10:30:11 +1100 (AEDT) Received: from localhost ([::1]:42674 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVVp-00047p-2F for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:30:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPq-0005bi-NR for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:58 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:42631) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPe-0007kN-A9 for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:58 -0500 Received: by mail-pl1-x62d.google.com with SMTP id s16so8756434plr.9 for ; Sun, 28 Feb 2021 15:23:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aU/KCKVa2SU1U8PQpzFTQgYauXXz+N+xlij7JLFYI1g=; b=zKgIOFahQwgy6IOU5DDM3U2miwmiLkjx/29S+LjB0+9n1ug37B0r98e+Fq4Z73B1gE AyIUfmC8yXfW9e6aJHIE84zgQgd6TuKgalQYNkSSvfrSymb8WwfhGkar2wH35eQmIQge OorpSJaBMzvKeuC/B3+5afWmVOgzdbEeP3wxM3J/j594t8ca5Ws8KUy5nNNUY5GhGtsN UZ7T4Udt4raHNjAQH2UCwlnBCkX5NBzCE9vuwnduVcYy+Dl3pU8kQ8qNEGxaoPYFOhNg DTroNQly/ACL2Q6HuNF1MJX6Tvm72yH+/RtFshiZJ8W6CYnJP8Up+Lpq2F1Ih59IsyF+ AJ5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aU/KCKVa2SU1U8PQpzFTQgYauXXz+N+xlij7JLFYI1g=; b=gLs0S9Jep0RMgl2A7npA+fOWWgQfb0Z54BYEwpe08eSY8LqbhytvfpXh+88rtgM8Rj 6PB8Z0Ql/UD8VOEcnE7JYloNvmwvYi+QLahJ8rLrw6MteTRIggPvs84CWYtWio/d6Y5V pZbkXzinBIfocKkkCvym2RfQ6xDMrcT3NK3lnEoEUHTfj7bbrnljJYTPITXxG0r/pi/o d4Gw/TYoJDqyZ+z4WlunJjenRQ1ZAk3C51/WKjndwArgJ5jVer6prbQtUGrtocGLnxZV u5sCJNZ1mrxTJdTOFNp+gYLjywogFDVioQkL1BfFfiWUGqNMveK0jav76eXH28k7bGel valg== X-Gm-Message-State: AOAM5329GrYxQvWWMxjLBHL23PaeONupDly9fYKv99siZGDg2lZL7EtG YvoViJIwcEpciDYrPmcyfOo0DMM3TRZImg== X-Google-Smtp-Source: ABdhPJxjWOI7uLbtX2KIuTC+NIS7ylHNcbyBrJ4w3726+3J2IGIkZjOnMMT/V42/7QJ4Z6+ZMJ881w== X-Received: by 2002:a17:902:bd96:b029:e3:73aa:e14f with SMTP id q22-20020a170902bd96b02900e373aae14fmr12957571pls.9.1614554624117; Sun, 28 Feb 2021 15:23:44 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 23/50] target/i386: Reduce DisasContext.vex_[lv] to uint8_t Date: Sun, 28 Feb 2021 15:22:54 -0800 Message-Id: <20210228232321.322053-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Currently, vex_l is either {0,1}; if in the future we implement AVX-512, the max value will be 2. In vex_v we store a register number. This is 0-15 for SSE, and 0-31 for AVX-512. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/i386/tcg/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 79f987b2cf..3b7660a019 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -97,8 +97,8 @@ typedef struct DisasContext { uint8_t rex_b; bool rex_w; #endif - int vex_l; /* vex vector length */ - int vex_v; /* vex vvvv register, without 1's complement. */ + uint8_t vex_l; /* vex vector length */ + uint8_t vex_v; /* vex vvvv register, without 1's complement. */ CCOp cc_op; /* current CC operation */ bool cc_op_dirty; int tf; /* TF cpu flag */ From patchwork Sun Feb 28 23:22:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445380 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=rf0/9ezE; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DpgDz2mHTz9sRR for ; Mon, 1 Mar 2021 10:52:51 +1100 (AEDT) Received: from localhost ([::1]:48596 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVrl-00056N-A2 for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:52:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43678) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPq-0005a7-4t for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:58 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:38892) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPe-0007kX-Ak for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:57 -0500 Received: by mail-pj1-x102c.google.com with SMTP id l18so10481623pji.3 for ; Sun, 28 Feb 2021 15:23:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Jp1oxTR2VzQtOn8Dm1XpEq+MbBttOBriYtfiWssZL7A=; b=rf0/9ezECXmoPiHX5kVLdBBVzD2E9xwLtlRNcb0qVJE3Dbsz/XaS/yTwEQ+hwi/t8m vmKnQFGJ+euKvNQUofZjQSxDTx3pWXgxj3VPTxBgoeQbgVozd+K+dsy6+MO5mZTCGA3a Yp6aX9/yrRwYs1aN6hX+w3t3ccF6LVVYO6K9p/1BeSpy2Nz2vwAlHghTfQoU1yTGTn4G Pm1AD2LSkF4J9nxxj9VfBMujam+n7D0kUsnyJq0haQWtxdTWnLuY4t7glNnpnfFuCzGG eo9hlzPsfyDTicXisG0kCz4U4/cgMogx69WtTBn8KmK9a9WBD8pFHoQ38vsRsp/jXTQk NaJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jp1oxTR2VzQtOn8Dm1XpEq+MbBttOBriYtfiWssZL7A=; b=deF8If7+Opl7EuapU1BMwgpINSlYvEQkZgKsAnJF934jZD64IVLlS2VPFPkK6k3ywS gMELiKspqvrMW3JCIPYEcftMgogj+Iq+Is5jVW1bsgGiyq8lfXuWhgeqBgR/NBCUE7vX +OmWZ2oN0Q6SZnP4u3Va/m3Tl24tB9ZDv5zZbYqvhpkxeCfncMDXC/QKDsCP1cRYk6Ue Rs1W0GUA9+So9hHpbpq939/iPk48V0ltft4Hfwv9AWnh/yZk6Kzfik5TI4LFpWmS5fWC BNJHGKhfg32YAw8DOcXwKDenh3iHJMTxQTWC2MwX58DTWfhvuuLbjcdncqEqyxFv0YIZ uOYg== X-Gm-Message-State: AOAM533oPbqo5U0uomUXB8+GN042Ab+yYV3xJfEXtVGRZnhnZW/fU7nG QKxxE4VMjRAfyjFS2jj9SakgED8V5i2tXA== X-Google-Smtp-Source: ABdhPJyUCvv5C62S1XdvxXLWqjTh7c+3ArmnVWLOnlPWAvpOgBXE6GDLr9Rqfeg7QF2nFTEussicjQ== X-Received: by 2002:a17:902:eb11:b029:e4:a5c3:42e8 with SMTP id l17-20020a170902eb11b02900e4a5c342e8mr3857985plb.26.1614554624942; Sun, 28 Feb 2021 15:23:44 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 24/50] target/i386: Reduce DisasContext popl_esp_hack and rip_offset to uint8_t Date: Sun, 28 Feb 2021 15:22:55 -0800 Message-Id: <20210228232321.322053-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Both of these fields store the size of a single memory access, so the range of values is 0-8. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 3b7660a019..9004f83c52 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -106,8 +106,8 @@ typedef struct DisasContext { int repz_opt; /* optimize jumps within repz instructions */ int mem_index; /* select memory access functions */ uint32_t flags; /* all execution flags */ - int popl_esp_hack; /* for correct popl with esp base handling */ - int rip_offset; /* only used in x86_64, but left for simplicity */ + uint8_t popl_esp_hack; /* for correct popl with esp base handling */ + uint8_t rip_offset; /* only used in x86_64, but left for simplicity */ int cpuid_features; int cpuid_ext_features; int cpuid_ext2_features; From patchwork Sun Feb 28 23:22:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445360 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=mwRcCD0G; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpg2M2McWz9sRR for ; Mon, 1 Mar 2021 10:43:38 +1100 (AEDT) Received: from localhost ([::1]:48122 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGViq-0001ft-6W for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:43:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43718) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPr-0005f3-TC for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:59 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:37207) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPg-0007ke-6w for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:59 -0500 Received: by mail-pl1-x62b.google.com with SMTP id p5so8770754plo.4 for ; Sun, 28 Feb 2021 15:23:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4uX9QPl9X+aFdcuNr9JmvACrJ855sGkXtJeh0OS686U=; b=mwRcCD0GtXiR+UlHBamF9ejU1dExxzLTl+TeQZ/tqyFxumc7e8dKwgan3tbPpiziCH QfMrAO5yJu/AK36SRyErnKhEVCchw0zf+DUKJwcrtzzmKYlEi8WbA+1cyeOIqb0govku MxjU0QHGCKjkGGFdRQHefekfGhy8AGplxULNhV1CswCtis9haAmJbOdRsbQqhqwfobI4 ozlBy31pQWuRnIH8o8NROr31luF900E8XZnT7Oq5GbU0n0+FZu3itCb21jPCzXuRClDp Ssbz0MIwzffvMcpAluxlgdouE90lsYJQGzdn+P4kdXjLbvR1MvnlEh9QlJtBwaFLHOET 4zuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4uX9QPl9X+aFdcuNr9JmvACrJ855sGkXtJeh0OS686U=; b=eR47mGjrZs9NvHH8ubx8s45d5md33WCHaMM1I3j1otrUEG0t+oer1QgIfmpV2OX2m1 lU/v2v2GARjM0oAnIO4NIj4g4Ap51FpUWFFGsp56lpbKwqK1i/XM2nIvipIEKXIEkjlR ylOrxF5aFKo54LICn2jBcMCSzDoH8PQF906AzeD2i2yP9gddhSZ58kcj9LrOp6kJRmf0 Zl0w/Gu7dHbBET4TMF22DkF06JmtCpn7uqg/zwpI391aMFhXIUDmosnV4LIWiTCCNlo2 /ssJwB6QWCogNfN3VdsqQPylGZ0vClGfHsxJm1VEFBrea4ELmw1ZXKSv7Mi1yowB/G4u PHcg== X-Gm-Message-State: AOAM5318ttfe+usfLmjsdKeSZjtSyLoutOrCoQUpSwEfsuhsk3XKc/NS qd26jK+Xab9HdefE0ZUdmf/ttuZNwKyajw== X-Google-Smtp-Source: ABdhPJzzM2JcFoH+H0+TTgIBGdQ1OwSiPjdtuEttTvEUnxE9caaULRuwAEgzWk89YjERKp6O6viqMQ== X-Received: by 2002:a17:90b:1045:: with SMTP id gq5mr14615356pjb.101.1614554625595; Sun, 28 Feb 2021 15:23:45 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 25/50] target/i386: Leave TF in DisasContext.flags Date: Sun, 28 Feb 2021 15:22:56 -0800 Message-Id: <20210228232321.322053-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" It's just as easy to clear the flag with AND than assignment. In two cases the test for the bit can be folded together with the test for HF_INHIBIT_IRQ_MASK. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 9004f83c52..92669bc142 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -101,7 +101,6 @@ typedef struct DisasContext { uint8_t vex_v; /* vex vvvv register, without 1's complement. */ CCOp cc_op; /* current CC operation */ bool cc_op_dirty; - int tf; /* TF cpu flag */ int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ int mem_index; /* select memory access functions */ @@ -2656,7 +2655,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr) } else if (recheck_tf) { gen_helper_rechecking_single_step(cpu_env); tcg_gen_exit_tb(NULL, 0); - } else if (s->tf) { + } else if (s->flags & HF_TF_MASK) { gen_helper_single_step(cpu_env); } else if (jr) { tcg_gen_lookup_and_goto_ptr(); @@ -5534,7 +5533,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (s->base.is_jmp) { gen_jmp_im(s, s->pc - s->cs_base); if (reg == R_SS) { - s->tf = 0; + s->flags &= ~HF_TF_MASK; gen_eob_inhibit_irq(s, true); } else { gen_eob(s); @@ -5600,7 +5599,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (s->base.is_jmp) { gen_jmp_im(s, s->pc - s->cs_base); if (reg == R_SS) { - s->tf = 0; + s->flags &= ~HF_TF_MASK; gen_eob_inhibit_irq(s, true); } else { gen_eob(s); @@ -8500,7 +8499,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0)); g_assert(ADDSEG(dc) == ((flags & HF_ADDSEG_MASK) != 0)); - dc->tf = (flags >> TF_SHIFT) & 1; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; dc->popl_esp_hack = 0; @@ -8515,8 +8513,8 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX]; dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX]; dc->cpuid_xsave_features = env->features[FEAT_XSAVE]; - dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled || - (flags & HF_INHIBIT_IRQ_MASK)); + dc->jmp_opt = !(dc->base.singlestep_enabled || + (flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK))); /* Do not optimize repz jumps at all in icount mode, because rep movsS instructions are execured with different paths in !repz_opt and repz_opt modes. The first one was used @@ -8591,7 +8589,7 @@ static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) pc_next = disas_insn(dc, cpu); - if (dc->tf || (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { + if (dc->flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)) { /* if single step mode, we generate only one instruction and generate an exception */ /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear From patchwork Sun Feb 28 23:22:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445358 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=XZKBH8AK; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpfy84qgmz9sVv for ; Mon, 1 Mar 2021 10:40:00 +1100 (AEDT) Received: from localhost ([::1]:39490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVfK-0006Te-Hg for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:39:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPr-0005d1-7k for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:59 -0500 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:42515) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPg-0007ko-6x for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:23:58 -0500 Received: by mail-pf1-x42a.google.com with SMTP id w18so10270080pfu.9 for ; Sun, 28 Feb 2021 15:23:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b7j9ch8PyL7hMB8yDFIrEz2hIViL6J2USSPBmhNlSXg=; b=XZKBH8AKwbjJOjaFxM4SDPh9/MCElHqUa2/NTqpZEySoAFoDv9PzxjDD1rZuI18viB 8N4UkAjWGXgR2gJPvYdUG0/ZnKACEvJXfa3aii0FAyMJSD5cmWRBW0UgwODZeR8qvsF+ KOzGMlPzmrMMUOz2q2gMgiNIXheDkvHyZ11aXVZtxKULtWAfuhIU/PaAeqAUG1DtY+EV NitwgPTjhL4KLqveEeiVg9pey9AC9yxQ9FRVYsaA6NFmpYF6eA2XEHjm7CyPZ9XKHjm7 tQKYBo80dczJ4wqIcyCi/43MiCq6DNlbCY2gchAUpHfSxeJfAOF3UXAG5k7br9xmt3z+ LEBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b7j9ch8PyL7hMB8yDFIrEz2hIViL6J2USSPBmhNlSXg=; b=n5hZn0jexNfPZLFtsfB2K+Ii3dNZX/fWHdtSVmdxdGboDOvroOA0ELkJcJZXgIWMmb 918BmjEiWP/0NxhTgvsJ4vUvCzYHOL4scjN9xcfQ4HzKP7pR4guNJXkKu0O1CXNjCoUN /ke4MPVs1QJ2rAtP97J6zepq4rd20LBdYPZUHg+Jb49khehCVp9W4pSDlsJNJJzt76jL cDH9xMvHvyYJSGiTUAQ/oDcy+Q3Oi+ZzpPj/GpG30NyjKXDjZpOFHYw+rWxjw34MvEB2 SIUvKARLDTFnqn7pjx535wLHHFyZyU8kt726aYsNCUdG3JIf1zr3QR1tMVIOSQpOT+1t fW6A== X-Gm-Message-State: AOAM533+YRepJ2uZUip6M+LmwUDGbk9VZzG1Wy5o1H6jEhcjZRr9lzzh k0MShNBlJiEuxNBrJrjpbZE2sb7fc/3ODg== X-Google-Smtp-Source: ABdhPJx6XDlvdS/TU6YGpUy3XGggVhV6cKbYSHRkYkyGPp3sDHbT20QHfLlu9xJDiSfOQBPQuWAuBQ== X-Received: by 2002:a62:bd05:0:b029:1ab:6d2:5edf with SMTP id a5-20020a62bd050000b02901ab06d25edfmr12208904pff.32.1614554626271; Sun, 28 Feb 2021 15:23:46 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 26/50] target/i386: Reduce DisasContext jmp_opt, repz_opt to bool Date: Sun, 28 Feb 2021 15:22:57 -0800 Message-Id: <20210228232321.322053-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 92669bc142..6877873bee 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -101,8 +101,8 @@ typedef struct DisasContext { uint8_t vex_v; /* vex vvvv register, without 1's complement. */ CCOp cc_op; /* current CC operation */ bool cc_op_dirty; - int jmp_opt; /* use direct block chaining for direct jumps */ - int repz_opt; /* optimize jumps within repz instructions */ + bool jmp_opt; /* use direct block chaining for direct jumps */ + bool repz_opt; /* optimize jumps within repz instructions */ int mem_index; /* select memory access functions */ uint32_t flags; /* all execution flags */ uint8_t popl_esp_hack; /* for correct popl with esp base handling */ From patchwork Sun Feb 28 23:22:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445383 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 27/50] target/i386: Fix the comment for repz_opt Date: Sun, 28 Feb 2021 15:22:58 -0800 Message-Id: <20210228232321.322053-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" After fixing a typo in the comment, fixup for CODING_STYLE. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 6877873bee..36dee5c0c7 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -8515,15 +8515,16 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->cpuid_xsave_features = env->features[FEAT_XSAVE]; dc->jmp_opt = !(dc->base.singlestep_enabled || (flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK))); - /* Do not optimize repz jumps at all in icount mode, because - rep movsS instructions are execured with different paths - in !repz_opt and repz_opt modes. The first one was used - always except single step mode. And this setting - disables jumps optimization and control paths become - equivalent in run and single step modes. - Now there will be no jump optimization for repz in - record/replay modes and there will always be an - additional step for ecx=0 when icount is enabled. + /* + * Do not optimize repz jumps at all in icount mode, because + * rep movsS instructions are executed with different paths + * in !repz_opt and repz_opt modes. The first one was used + * always except single step mode. And this setting + * disables jumps optimization and control paths become + * equivalent in run and single step modes. + * Now there will be no jump optimization for repz in + * record/replay modes and there will always be an + * additional step for ecx=0 when icount is enabled. */ dc->repz_opt = !dc->jmp_opt && !(tb_cflags(dc->base.tb) & CF_USE_ICOUNT); From patchwork Sun Feb 28 23:22:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445385 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Dm5Nkehu; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DpgMs3rDLz9sRR for ; Mon, 1 Mar 2021 10:58:49 +1100 (AEDT) Received: from localhost ([::1]:35664 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVxX-00033q-8g for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:58:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43758) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPs-0005ij-Tr for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:00 -0500 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:35878) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPi-0007lc-37 for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:00 -0500 Received: by mail-pg1-x52e.google.com with SMTP id t26so10374621pgv.3 for ; Sun, 28 Feb 2021 15:23:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LaK3xHS/fvHJ2f1smHUqdXOOyUpc8PJcLS6WrecJURU=; b=Dm5NkehuYLOzmdU35O0j/RlAwZGbXA3HZbrc2uDP37KDD59aaKRSxGpsRJH+1B50Zv 5/r7FZl5v0/eYA+hW3zCqYEd/kfpSjtUcAvMN9ak7ds+WtzS8EKe/hr0fMN2fKUgqUiP XZoNh4qEeNDUzT0FQm3i5Lit7eEvQS1sbojm764jvFf4CBeAOgP5wuDsY1nld50A56c2 APBn0j3dDoIzhuJiSHuOQ4HX8lNo+feoHbozfFkRdEdnhBR/9zG5dg71T6W0Svj+fEgp YM2nrg5v2CjjYpnhuZigK6yMsztrjSOGWNzIAgKDkIGTJQjfM3zHEeS8w5Q3eUZdvlIA PiGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LaK3xHS/fvHJ2f1smHUqdXOOyUpc8PJcLS6WrecJURU=; b=bqJnkd+NsToL3zLdxaRAtaMrrj3v8IRKwlRjt8Khy4ZW7d1PGImm4LOevIpDiLmPX/ KsqnhSMgnTEGHj88XomaeHSxzD1NibfBYleKBGdsxcRgv33UVBmWBc9QbEhc9TzGDwod AXLftsxXRwC4rPQHBDTa5pkcXUD0Zp6wkFxu9dinsbAXXF3P4h90oIdtJVM76hnU5Pyq MlvWtCTDvG2Sx9WDG+yHpXtPfqO9YLc2tuknZI/b1b5Ulq2kIv+CzUUcq48DDg+XdgUk jApwBxlW7u7dfflSjyRMGhARCE9LDGDTcHPEajg+tjDinNLBk9GhN8mPAYH6gIe+ya0Q bK+w== X-Gm-Message-State: AOAM531atkIJ7UVcqwzT1RUf/nESK57OBTCDXJuDZSmjt/dEmVM1Lxvx 8Bp0gaIZVPxJGFsG3n42KrbQMNa5F5BBnQ== X-Google-Smtp-Source: ABdhPJxmDozFzDShtOATNWajLr5I1OIqOmI62Lo1GHSkSF+mS8qwoOrxTBhkI/m8ecPCTSrcvt5LzQ== X-Received: by 2002:a65:4088:: with SMTP id t8mr11463969pgp.296.1614554627590; Sun, 28 Feb 2021 15:23:47 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 28/50] target/i386: Reorder DisasContext members Date: Sun, 28 Feb 2021 15:22:59 -0800 Message-Id: <20210228232321.322053-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Sort all of the single-byte members to the same area of the structure, eliminating 8 bytes of padding. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 36dee5c0c7..f0bc2df98c 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -76,20 +76,24 @@ static TCGv_i64 cpu_bndu[4]; typedef struct DisasContext { DisasContextBase base; - /* current insn context */ - int8_t override; /* -1 if no override, else R_CS, R_DS, etc */ - uint8_t prefix; + target_ulong pc; /* pc = eip + cs_base */ + target_ulong pc_start; /* pc at TB entry */ + target_ulong cs_base; /* base of CS segment */ + MemOp aflag; MemOp dflag; - target_ulong pc_start; - target_ulong pc; /* pc = eip + cs_base */ - /* current block context */ - target_ulong cs_base; /* base of CS segment */ + + int8_t override; /* -1 if no override, else R_CS, R_DS, etc */ + uint8_t prefix; #ifndef CONFIG_USER_ONLY uint8_t cpl; /* code priv level */ uint8_t iopl; /* i/o priv level */ #endif + uint8_t vex_l; /* vex vector length */ + uint8_t vex_v; /* vex vvvv register, without 1's complement. */ + uint8_t popl_esp_hack; /* for correct popl with esp base handling */ + uint8_t rip_offset; /* only used in x86_64, but left for simplicity */ #ifdef TARGET_X86_64 uint8_t rex_r; @@ -97,16 +101,13 @@ typedef struct DisasContext { uint8_t rex_b; bool rex_w; #endif - uint8_t vex_l; /* vex vector length */ - uint8_t vex_v; /* vex vvvv register, without 1's complement. */ - CCOp cc_op; /* current CC operation */ - bool cc_op_dirty; bool jmp_opt; /* use direct block chaining for direct jumps */ bool repz_opt; /* optimize jumps within repz instructions */ + bool cc_op_dirty; + + CCOp cc_op; /* current CC operation */ int mem_index; /* select memory access functions */ uint32_t flags; /* all execution flags */ - uint8_t popl_esp_hack; /* for correct popl with esp base handling */ - uint8_t rip_offset; /* only used in x86_64, but left for simplicity */ int cpuid_features; int cpuid_ext_features; int cpuid_ext2_features; From patchwork Sun Feb 28 23:23:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445365 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=u+B0cgxX; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpg504zzkz9sRR for ; Mon, 1 Mar 2021 10:45:56 +1100 (AEDT) Received: from localhost ([::1]:56638 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVl4-00057j-Jo for incoming@patchwork.ozlabs.org; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 29/50] target/i386: Add stub generator for helper_set_dr Date: Sun, 28 Feb 2021 15:23:00 -0800 Message-Id: <20210228232321.322053-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This removes an ifdef from the middle of disas_insn, and ensures that the branch is not reachable. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index f0bc2df98c..42b96a2669 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -179,6 +179,19 @@ typedef struct DisasContext { #define REX_B(S) 0 #endif +/* + * Many sysemu-only helpers are not reachable for user-only. + * Define stub generators here, so that we need not either sprinkle + * ifdefs through the translator, nor provide the helper function. + */ +#define STUB_HELPER(NAME, ...) \ + static inline void gen_helper_##NAME(__VA_ARGS__) \ + { qemu_build_not_reached(); } + +#ifdef CONFIG_USER_ONLY +STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) +#endif + static void gen_eob(DisasContext *s); static void gen_jr(DisasContext *s, TCGv dest); static void gen_jmp(DisasContext *s, target_ulong eip); @@ -8069,7 +8082,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x121: /* mov reg, drN */ case 0x123: /* mov drN, reg */ if (check_cpl0(s)) { -#ifndef CONFIG_USER_ONLY modrm = x86_ldub_code(env, s); /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). * AMD documentation (24594.pdf) and testing of @@ -8098,7 +8110,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_helper_get_dr(s->T0, cpu_env, s->tmp2_i32); gen_op_mov_reg_v(s, ot, rm, s->T0); } -#endif /* !CONFIG_USER_ONLY */ } break; case 0x106: /* clts */ From patchwork Sun Feb 28 23:23:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445386 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=rP7XhgRg; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DpgRB1DHTz9sRR for ; Mon, 1 Mar 2021 11:01:41 +1100 (AEDT) Received: from localhost ([::1]:38958 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGW0I-0004fK-SP for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 19:01:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPt-0005kx-Ft for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:01 -0500 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:45413) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPi-0007lo-3V for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:01 -0500 Received: by mail-pg1-x533.google.com with SMTP id p21so10339005pgl.12 for ; Sun, 28 Feb 2021 15:23:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N1nE08dhMaE5XVBv3v7IRuYZmIZeZZ0rBWSjMoXgkIQ=; b=rP7XhgRgkA4+uZZcM8FeE04eXJkln/OiJufdc1c6+i+RwZVXyaF34XA97NuYnlJMpY 5AQ9TTce/daVaJkQz6LjaW+7ewqVHqSHPbXPx9UA+PTDHGOgWKc0/yPC3S7UPA0AZOg1 euR9dE+0E+jYcB7+oBIVZk9fPbmlcVVuyKKp8ROFB//bBM/HOhEQ0vinLJ7J84Mio2q1 mcavoGT2jSzJwC48a/ZolgFRDloZQNZHyhIE9jFdkzy4eb5UoxASCwQoyaITmnU4vNbq sp+q16/ERJ2HqvAy1dgVbibvObnJncKDSroherex3nJXJStkz51udhD7bjOIFs9RM+qa +7NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N1nE08dhMaE5XVBv3v7IRuYZmIZeZZ0rBWSjMoXgkIQ=; b=Rn8Weq0ATBwNQlRRjfGfxxYUKD0EN+zgRku+L+mJ1ggPXdNLh/X8uHiJq7LVY/sXul xfoyb7BifxxXiUX57vl/TZX/mRsqdcKlSJBCkDlq0Fjo1RBEaxS/7dx4+whykxvf70sj z9k+avn9+VRSgLlFMte5qGUCxgbbYUQqfSRRoUDrnmX5O/biAtTmosFspqJ1xHljYX6m w9ENvZzqFWDfgS4Uds2MQGqM7CyAYeiBABr2tc4ytc8cRHhn0NEsiaZxLwR1T+w0RQ0X 5D2DWdhdVbomOML1XMoVW1yuTNPfBIuFOT6kgw0DDP6DcfwyvL/1mRKrGj+GkPrgK/PX hXow== X-Gm-Message-State: AOAM530UI6+uQ+hAN9hfRY6X+Qi88maqKNHGNtE7DdFXgVkh+xF02Pf6 +SLBdJDv8agtRIqBOzY6zIvtbS47ff2Sjg== X-Google-Smtp-Source: ABdhPJyNl1fDZEv02AzlsXCK7f2nRWsGfNFlJT3mi95ApmFl4l2lL509ElQvwDzduDWSHg76iRO3Cw== X-Received: by 2002:a62:2c58:0:b029:1ee:1afa:432b with SMTP id s85-20020a622c580000b02901ee1afa432bmr12718906pfs.42.1614554628826; Sun, 28 Feb 2021 15:23:48 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 30/50] target/i386: Assert !SVME for user-only Date: Sun, 28 Feb 2021 15:23:01 -0800 Message-Id: <20210228232321.322053-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Most of the VMM instructions are already disabled for user-only, by being usable only from ring 0. The spec is intentionally loose for VMMCALL, allowing the VMM to define syscalls for user-only. However, linux does not do so; VMMCALL is illegal. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 42b96a2669..3779da9042 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -138,10 +138,12 @@ typedef struct DisasContext { #define PE(S) true #define CPL(S) 3 #define IOPL(S) 0 +#define SVME(S) false #else #define PE(S) (((S)->flags & HF_PE_MASK) != 0) #define CPL(S) ((S)->cpl) #define IOPL(S) ((S)->iopl) +#define SVME(S) (((S)->flags & HF_SVME_MASK) != 0) #endif #if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64) #define VM86(S) false @@ -7489,7 +7491,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xd8: /* VMRUN */ - if (!(s->flags & HF_SVME_MASK) || !PE(s)) { + if (!SVME(s) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7504,7 +7506,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xd9: /* VMMCALL */ - if (!(s->flags & HF_SVME_MASK)) { + if (!SVME(s)) { goto illegal_op; } gen_update_cc_op(s); @@ -7513,7 +7515,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xda: /* VMLOAD */ - if (!(s->flags & HF_SVME_MASK) || !PE(s)) { + if (!SVME(s) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7525,7 +7527,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xdb: /* VMSAVE */ - if (!(s->flags & HF_SVME_MASK) || !PE(s)) { + if (!SVME(s) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7537,8 +7539,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xdc: /* STGI */ - if ((!(s->flags & HF_SVME_MASK) - && !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) + if ((!SVME(s) && !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || !PE(s)) { goto illegal_op; } @@ -7552,7 +7553,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xdd: /* CLGI */ - if (!(s->flags & HF_SVME_MASK) || !PE(s)) { + if (!SVME(s) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7564,8 +7565,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xde: /* SKINIT */ - if ((!(s->flags & HF_SVME_MASK) - && !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) + if ((!SVME(s) && !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || !PE(s)) { goto illegal_op; } @@ -7575,7 +7575,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xdf: /* INVLPGA */ - if (!(s->flags & HF_SVME_MASK) || !PE(s)) { + if (!SVME(s) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -8510,6 +8510,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(SS32(dc) == ((flags & HF_SS32_MASK) != 0)); g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0)); g_assert(ADDSEG(dc) == ((flags & HF_ADDSEG_MASK) != 0)); + g_assert(SVME(dc) == ((flags & HF_SVME_MASK) != 0)); dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; From patchwork Sun Feb 28 23:23:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445350 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 31/50] target/i386: Assert !GUEST for user-only Date: Sun, 28 Feb 2021 15:23:02 -0800 Message-Id: <20210228232321.322053-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" For user-only, we do not need to check for VMM intercept. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 3779da9042..cd376a2c07 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -139,11 +139,13 @@ typedef struct DisasContext { #define CPL(S) 3 #define IOPL(S) 0 #define SVME(S) false +#define GUEST(S) false #else #define PE(S) (((S)->flags & HF_PE_MASK) != 0) #define CPL(S) ((S)->cpl) #define IOPL(S) ((S)->iopl) #define SVME(S) (((S)->flags & HF_SVME_MASK) != 0) +#define GUEST(S) (((S)->flags & HF_GUEST_MASK) != 0) #endif #if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64) #define VM86(S) false @@ -677,7 +679,7 @@ static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip, tcg_abort(); } } - if(s->flags & HF_GUEST_MASK) { + if (GUEST(s)) { gen_update_cc_op(s); gen_jmp_im(s, cur_eip); svm_flags |= (1 << (4 + ot)); @@ -2417,8 +2419,9 @@ gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, uint32_t type, uint64_t param) { /* no SVM activated; fast case */ - if (likely(!(s->flags & HF_GUEST_MASK))) + if (likely(!GUEST(s))) { return; + } gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_svm_check_intercept_param(cpu_env, tcg_const_i32(type), @@ -8511,6 +8514,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0)); g_assert(ADDSEG(dc) == ((flags & HF_ADDSEG_MASK) != 0)); g_assert(SVME(dc) == ((flags & HF_SVME_MASK) != 0)); + g_assert(GUEST(dc) == ((flags & HF_GUEST_MASK) != 0)); dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; From patchwork Sun Feb 28 23:23:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445353 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 32/50] target/i386: Implement skinit in translate.c Date: Sun, 28 Feb 2021 15:23:03 -0800 Message-Id: <20210228232321.322053-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Our sysemu implementation is a stub. We can already intercept instructions for vmexit, and raising #UD is trivial. Signed-off-by: Richard Henderson --- target/i386/helper.h | 1 - target/i386/tcg/sysemu/svm_helper.c | 7 ------- target/i386/tcg/translate.c | 7 +++---- target/i386/tcg/user/svm_stubs.c | 4 ---- 4 files changed, 3 insertions(+), 16 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index 095520f81f..7a09efd55b 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -117,7 +117,6 @@ DEF_HELPER_2(vmload, void, env, int) DEF_HELPER_2(vmsave, void, env, int) DEF_HELPER_1(stgi, void, env) DEF_HELPER_1(clgi, void, env) -DEF_HELPER_1(skinit, void, env) DEF_HELPER_2(invlpga, void, env, int) /* x86 FPU */ diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c index 5b9c6f18be..ca5a781a7e 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -423,13 +423,6 @@ void helper_clgi(CPUX86State *env) env->hflags2 &= ~HF2_GIF_MASK; } -void helper_skinit(CPUX86State *env) -{ - cpu_svm_check_intercept_param(env, SVM_EXIT_SKINIT, 0, GETPC()); - /* XXX: not implemented */ - raise_exception(env, EXCP06_ILLOP); -} - void helper_invlpga(CPUX86State *env, int aflag) { X86CPU *cpu = env_archcpu(env); diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index cd376a2c07..92e85e1872 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -7572,10 +7572,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) || !PE(s)) { goto illegal_op; } - gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); - gen_helper_skinit(cpu_env); - break; + gen_svm_check_intercept(s, pc_start, SVM_EXIT_SKINIT); + /* If not intercepted, not implemented -- raise #UD. */ + goto illegal_op; case 0xdf: /* INVLPGA */ if (!SVME(s) || !PE(s)) { diff --git a/target/i386/tcg/user/svm_stubs.c b/target/i386/tcg/user/svm_stubs.c index 97528b56ad..63b37f0de6 100644 --- a/target/i386/tcg/user/svm_stubs.c +++ b/target/i386/tcg/user/svm_stubs.c @@ -46,10 +46,6 @@ void helper_clgi(CPUX86State *env) { } -void helper_skinit(CPUX86State *env) -{ -} - void helper_invlpga(CPUX86State *env, int aflag) { } From patchwork Sun Feb 28 23:23:04 2021 Content-Type: text/plain; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 33/50] target/i386: Eliminate SVM helpers for user-only Date: Sun, 28 Feb 2021 15:23:04 -0800 Message-Id: <20210228232321.322053-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Use STUB_HELPER to ensure that such calls are always eliminated. Signed-off-by: Richard Henderson --- target/i386/helper.h | 3 +-- target/i386/tcg/translate.c | 9 ++++++++ target/i386/tcg/user/svm_stubs.c | 38 -------------------------------- 3 files changed, 10 insertions(+), 40 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index 7a09efd55b..d0f7f07c6c 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -107,8 +107,6 @@ DEF_HELPER_2(inl, tl, env, i32) #ifndef CONFIG_USER_ONLY DEF_HELPER_FLAGS_4(bpt_io, TCG_CALL_NO_WG, void, env, i32, i32, tl) -#endif /* !CONFIG_USER_ONLY */ - DEF_HELPER_3(svm_check_intercept_param, void, env, i32, i64) DEF_HELPER_4(svm_check_io, void, env, i32, i32, i32) DEF_HELPER_3(vmrun, void, env, int, int) @@ -118,6 +116,7 @@ DEF_HELPER_2(vmsave, void, env, int) DEF_HELPER_1(stgi, void, env) DEF_HELPER_1(clgi, void, env) DEF_HELPER_2(invlpga, void, env, int) +#endif /* !CONFIG_USER_ONLY */ /* x86 FPU */ diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 92e85e1872..8c77c9cbe6 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -193,7 +193,16 @@ typedef struct DisasContext { { qemu_build_not_reached(); } #ifdef CONFIG_USER_ONLY +STUB_HELPER(clgi, TCGv_env env) +STUB_HELPER(invlpga, TCGv_env env, TCGv_i32 aflag) STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) +STUB_HELPER(stgi, TCGv_env env) +STUB_HELPER(svm_check_intercept_param, TCGv_env env, TCGv_i32 t, TCGv_i64 p) +STUB_HELPER(svm_check_io, TCGv_env env, TCGv_i32 port, TCGv_i32 p, TCGv_i32 a) +STUB_HELPER(vmload, TCGv_env env, TCGv_i32 aflag) +STUB_HELPER(vmmcall, TCGv_env env) +STUB_HELPER(vmrun, TCGv_env env, TCGv_i32 aflag, TCGv_i32 pc_ofs) +STUB_HELPER(vmsave, TCGv_env env, TCGv_i32 aflag) #endif static void gen_eob(DisasContext *s); diff --git a/target/i386/tcg/user/svm_stubs.c b/target/i386/tcg/user/svm_stubs.c index 63b37f0de6..48a43bdcea 100644 --- a/target/i386/tcg/user/svm_stubs.c +++ b/target/i386/tcg/user/svm_stubs.c @@ -22,51 +22,13 @@ #include "exec/helper-proto.h" #include "tcg/helper-tcg.h" -void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) -{ -} - -void helper_vmmcall(CPUX86State *env) -{ -} - -void helper_vmload(CPUX86State *env, int aflag) -{ -} - -void helper_vmsave(CPUX86State *env, int aflag) -{ -} - -void helper_stgi(CPUX86State *env) -{ -} - -void helper_clgi(CPUX86State *env) -{ -} - -void helper_invlpga(CPUX86State *env, int aflag) -{ -} - void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1, uintptr_t retaddr) { assert(0); } -void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, - uint64_t param) -{ -} - void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, uint64_t param, uintptr_t retaddr) { } - -void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param, - uint32_t next_eip_addend) -{ -} From patchwork Sun Feb 28 23:23:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445387 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=LoOpO9qh; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 34/50] target/i386: Mark some helpers as noreturn Date: Sun, 28 Feb 2021 15:23:05 -0800 Message-Id: <20210228232321.322053-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Any helper that always raises an exception or interrupt, or simply exits to the main loop, can be so marked. Signed-off-by: Richard Henderson --- target/i386/helper.h | 18 +++++++++--------- target/i386/tcg/bpt_helper.c | 2 +- target/i386/tcg/excp_helper.c | 18 ++++++++++-------- target/i386/tcg/misc_helper.c | 14 +++++++------- target/i386/tcg/translate.c | 3 ++- 5 files changed, 29 insertions(+), 26 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index d0f7f07c6c..f794d1c7c7 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -60,14 +60,14 @@ DEF_HELPER_2(sysexit, void, env, int) DEF_HELPER_2(syscall, void, env, int) DEF_HELPER_2(sysret, void, env, int) #endif -DEF_HELPER_2(hlt, void, env, int) -DEF_HELPER_2(monitor, void, env, tl) -DEF_HELPER_2(mwait, void, env, int) -DEF_HELPER_2(pause, void, env, int) -DEF_HELPER_1(debug, void, env) +DEF_HELPER_FLAGS_2(hlt, TCG_CALL_NO_WG, noreturn, env, int) +DEF_HELPER_FLAGS_2(monitor, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_2(mwait, TCG_CALL_NO_WG, noreturn, env, int) +DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int) +DEF_HELPER_FLAGS_1(debug, TCG_CALL_NO_WG, noreturn, env) DEF_HELPER_1(reset_rf, void, env) -DEF_HELPER_3(raise_interrupt, void, env, int, int) -DEF_HELPER_2(raise_exception, void, env, int) +DEF_HELPER_FLAGS_3(raise_interrupt, TCG_CALL_NO_WG, noreturn, env, int, int) +DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, int) DEF_HELPER_1(cli, void, env) DEF_HELPER_1(sti, void, env) DEF_HELPER_1(clac, void, env) @@ -86,12 +86,12 @@ DEF_HELPER_2(cmpxchg8b, void, env, tl) DEF_HELPER_2(cmpxchg16b_unlocked, void, env, tl) DEF_HELPER_2(cmpxchg16b, void, env, tl) #endif -DEF_HELPER_1(single_step, void, env) +DEF_HELPER_FLAGS_1(single_step, TCG_CALL_NO_WG, noreturn, env) DEF_HELPER_1(rechecking_single_step, void, env) DEF_HELPER_1(cpuid, void, env) DEF_HELPER_1(rdtsc, void, env) DEF_HELPER_1(rdtscp, void, env) -DEF_HELPER_1(rdpmc, void, env) +DEF_HELPER_FLAGS_1(rdpmc, TCG_CALL_NO_WG, noreturn, env) DEF_HELPER_1(rdmsr, void, env) DEF_HELPER_1(wrmsr, void, env) diff --git a/target/i386/tcg/bpt_helper.c b/target/i386/tcg/bpt_helper.c index fb2a65ac9c..83cd89581e 100644 --- a/target/i386/tcg/bpt_helper.c +++ b/target/i386/tcg/bpt_helper.c @@ -22,7 +22,7 @@ #include "exec/helper-proto.h" #include "helper-tcg.h" -void helper_single_step(CPUX86State *env) +void QEMU_NORETURN helper_single_step(CPUX86State *env) { #ifndef CONFIG_USER_ONLY check_hw_breakpoints(env, true); diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c index 0183f3932e..bdae887d0a 100644 --- a/target/i386/tcg/excp_helper.c +++ b/target/i386/tcg/excp_helper.c @@ -25,12 +25,13 @@ #include "exec/helper-proto.h" #include "helper-tcg.h" -void helper_raise_interrupt(CPUX86State *env, int intno, int next_eip_addend) +void QEMU_NORETURN helper_raise_interrupt(CPUX86State *env, int intno, + int next_eip_addend) { raise_interrupt(env, intno, 1, 0, next_eip_addend); } -void helper_raise_exception(CPUX86State *env, int exception_index) +void QEMU_NORETURN helper_raise_exception(CPUX86State *env, int exception_index) { raise_exception(env, exception_index); } @@ -116,24 +117,25 @@ void QEMU_NORETURN raise_interrupt(CPUX86State *env, int intno, int is_int, raise_interrupt2(env, intno, is_int, error_code, next_eip_addend, 0); } -void raise_exception_err(CPUX86State *env, int exception_index, - int error_code) +void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, + int error_code) { raise_interrupt2(env, exception_index, 0, error_code, 0, 0); } -void raise_exception_err_ra(CPUX86State *env, int exception_index, - int error_code, uintptr_t retaddr) +void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, + int error_code, uintptr_t retaddr) { raise_interrupt2(env, exception_index, 0, error_code, 0, retaddr); } -void raise_exception(CPUX86State *env, int exception_index) +void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index) { raise_interrupt2(env, exception_index, 0, 0, 0, 0); } -void raise_exception_ra(CPUX86State *env, int exception_index, uintptr_t retaddr) +void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, + uintptr_t retaddr) { raise_interrupt2(env, exception_index, 0, 0, 0, retaddr); } diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index 82fb7037ac..1ca9ace3dc 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -96,7 +96,7 @@ void helper_rdtscp(CPUX86State *env) env->regs[R_ECX] = (uint32_t)(env->tsc_aux); } -void helper_rdpmc(CPUX86State *env) +void QEMU_NORETURN helper_rdpmc(CPUX86State *env) { if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) { raise_exception_ra(env, EXCP0D_GPF, GETPC()); @@ -108,7 +108,7 @@ void helper_rdpmc(CPUX86State *env) raise_exception_err(env, EXCP06_ILLOP, 0); } -static void do_pause(X86CPU *cpu) +static QEMU_NORETURN void do_pause(X86CPU *cpu) { CPUState *cs = CPU(cpu); @@ -117,7 +117,7 @@ static void do_pause(X86CPU *cpu) cpu_loop_exit(cs); } -static void do_hlt(X86CPU *cpu) +static QEMU_NORETURN void do_hlt(X86CPU *cpu) { CPUState *cs = CPU(cpu); CPUX86State *env = &cpu->env; @@ -128,7 +128,7 @@ static void do_hlt(X86CPU *cpu) cpu_loop_exit(cs); } -void helper_hlt(CPUX86State *env, int next_eip_addend) +void QEMU_NORETURN helper_hlt(CPUX86State *env, int next_eip_addend) { X86CPU *cpu = env_archcpu(env); @@ -147,7 +147,7 @@ void helper_monitor(CPUX86State *env, target_ulong ptr) cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0, GETPC()); } -void helper_mwait(CPUX86State *env, int next_eip_addend) +void QEMU_NORETURN helper_mwait(CPUX86State *env, int next_eip_addend) { CPUState *cs = env_cpu(env); X86CPU *cpu = env_archcpu(env); @@ -166,7 +166,7 @@ void helper_mwait(CPUX86State *env, int next_eip_addend) } } -void helper_pause(CPUX86State *env, int next_eip_addend) +void QEMU_NORETURN helper_pause(CPUX86State *env, int next_eip_addend) { X86CPU *cpu = env_archcpu(env); @@ -176,7 +176,7 @@ void helper_pause(CPUX86State *env, int next_eip_addend) do_pause(cpu); } -void helper_debug(CPUX86State *env) +void QEMU_NORETURN helper_debug(CPUX86State *env) { CPUState *cs = env_cpu(env); diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 8c77c9cbe6..c2bc3c4b22 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -7276,6 +7276,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_rdpmc(cpu_env); + s->base.is_jmp = DISAS_NORETURN; break; case 0x134: /* sysenter */ /* For Intel SYSENTER is valid on 64-bit */ @@ -7437,7 +7438,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - pc_start)); - gen_eob(s); + s->base.is_jmp = DISAS_NORETURN; break; case 0xca: /* clac */ From patchwork Sun Feb 28 23:23:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445375 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=xNvpwiuV; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 35/50] target/i386: Simplify gen_debug usage Date: Sun, 28 Feb 2021 15:23:06 -0800 Message-Id: <20210228232321.322053-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Both invocations pass the start of the current instruction, which is available as s->base.pc_next. The function sets is_jmp, so we can eliminate a second setting. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index c2bc3c4b22..c135be9063 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2614,10 +2614,10 @@ static void gen_interrupt(DisasContext *s, int intno, s->base.is_jmp = DISAS_NORETURN; } -static void gen_debug(DisasContext *s, target_ulong cur_eip) +static void gen_debug(DisasContext *s) { gen_update_cc_op(s); - gen_jmp_im(s, cur_eip); + gen_jmp_im(s, s->base.pc_next - s->cs_base); gen_helper_debug(cpu_env); s->base.is_jmp = DISAS_NORETURN; } @@ -7146,7 +7146,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) #ifdef WANT_ICEBP case 0xf1: /* icebp (undocumented, exits to external debugger) */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP); - gen_debug(s, pc_start - s->cs_base); + gen_debug(s); break; #endif case 0xfa: /* cli */ @@ -8586,8 +8586,7 @@ static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, /* If RF is set, suppress an internally generated breakpoint. */ int flags = dc->base.tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY; if (bp->flags & flags) { - gen_debug(dc, dc->base.pc_next - dc->cs_base); - dc->base.is_jmp = DISAS_NORETURN; + gen_debug(dc); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that From patchwork Sun Feb 28 23:23:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445390 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=G8KiXVnV; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DpgfK34Ckz9sVS for ; Mon, 1 Mar 2021 11:11:21 +1100 (AEDT) Received: from localhost ([::1]:49440 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGW9f-0000xb-Ev for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 19:11:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43854) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPw-0005tB-HD for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:04 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:54016) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPm-0007mT-35 for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:04 -0500 Received: by mail-pj1-x1031.google.com with SMTP id c19so9855786pjq.3 for ; Sun, 28 Feb 2021 15:23:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=49Cd1j1K/38NZkLjnlIs6/b9Bf5vlKLKhEhBcwBUlbI=; b=G8KiXVnVwc3anNnMfOFv0bZwkZzyOaS1MmlWqccK/HmJz+/A4QBsDQVzwqoH9y9lON lLds6AOv4XJvqZWQ/fdCT3oquu+bgPHuyEATk7bXwteC4g4awRpy9HibgqyCF+c2ipY5 PgDRW7CWZ+mqA9/Ez/exNu2wd+DB29tBFv2aAK/Gz2b5qt0KRkOVEi3fYtPvlKgikBYd tpeVBSPhIHo7nGajUfye7DdXBddIeU51yHZiskz8w6Li2b8O6Lq1z3897Knx4wNvs8KQ XxhqWLfoAqpH8F7ZceagK91CEM6I0e8mF7CqvJYTUvdXFBYgtpXtSbR44gvMY/usM/Yr 9hBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=49Cd1j1K/38NZkLjnlIs6/b9Bf5vlKLKhEhBcwBUlbI=; b=Zu42kCsIYdHRHWdCXmYgkLnuconpGTkkpYmdnBMWoTP+YkOnPGLSIvd1+8I/pXi5KX yQctwQ3VMx4nLbgLZ412UlMCyqJem/GBTa0HgI2O/A0tIjA8A9aw+GKLDZnCgI3MeqfD QYHwW/tZxoJLOG+nU7swBk3hNJunYL/CYeZBAFCBzluUCRNSe2Udv5bZGmQ36Dwvt2ST Hoqnuhk4TmYS6aJW73B4JjqN6bTjVx2K9Vfg5tih2NGTI2TsAMRZg+lAgyvvcQk9S3E1 M94utAiLVUtDB24EJglQJXnOCrTT/DUYL7GCDpqfYirjTS/JfRplqnNeN+fZglLeaki+ pvIQ== X-Gm-Message-State: AOAM530zr+fR+rFwx5xX0wZXn2aI/KbF3lF74MuiqseL+OVRPJl+kLHB qrFQ/WsYeL4fF4egjLM0n3fgi/YuFTufxg== X-Google-Smtp-Source: ABdhPJwdZfK82X6M5KwWc9IDQhMFnJo5JEfSWuOUfAJ8kPTaALlNXayaU3MSFLXLzz4609qWNvDfBw== X-Received: by 2002:a17:90a:ce0c:: with SMTP id f12mr3133064pju.11.1614554632778; Sun, 28 Feb 2021 15:23:52 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 36/50] target/i386: Tidy svm_check_intercept from tcg Date: Sun, 28 Feb 2021 15:23:07 -0800 Message-Id: <20210228232321.322053-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The param argument to helper_svm_check_intercept_param is always 0; eliminate it and rename to helper_svm_check_intercept. Fold gen_sve_check_intercept_param into gen_svm_check_intercept. Signed-off-by: Richard Henderson --- target/i386/helper.h | 2 +- target/i386/tcg/sysemu/svm_helper.c | 5 ++--- target/i386/tcg/translate.c | 16 ++++------------ 3 files changed, 7 insertions(+), 16 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index f794d1c7c7..86484a4ec4 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -107,7 +107,7 @@ DEF_HELPER_2(inl, tl, env, i32) #ifndef CONFIG_USER_ONLY DEF_HELPER_FLAGS_4(bpt_io, TCG_CALL_NO_WG, void, env, i32, i32, tl) -DEF_HELPER_3(svm_check_intercept_param, void, env, i32, i64) +DEF_HELPER_2(svm_check_intercept, void, env, i32) DEF_HELPER_4(svm_check_io, void, env, i32, i32, i32) DEF_HELPER_3(vmrun, void, env, int, int) DEF_HELPER_1(vmmcall, void, env) diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c index ca5a781a7e..86a0b3c4be 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -517,10 +517,9 @@ void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, } } -void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, - uint64_t param) +void helper_svm_check_intercept(CPUX86State *env, uint32_t type) { - cpu_svm_check_intercept_param(env, type, param, GETPC()); + cpu_svm_check_intercept_param(env, type, 0, GETPC()); } void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param, diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index c135be9063..cbc0cc3ccc 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -197,7 +197,7 @@ STUB_HELPER(clgi, TCGv_env env) STUB_HELPER(invlpga, TCGv_env env, TCGv_i32 aflag) STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) STUB_HELPER(stgi, TCGv_env env) -STUB_HELPER(svm_check_intercept_param, TCGv_env env, TCGv_i32 t, TCGv_i64 p) +STUB_HELPER(svm_check_intercept, TCGv_env env, TCGv_i32 type) STUB_HELPER(svm_check_io, TCGv_env env, TCGv_i32 port, TCGv_i32 p, TCGv_i32 a) STUB_HELPER(vmload, TCGv_env env, TCGv_i32 aflag) STUB_HELPER(vmmcall, TCGv_env env) @@ -2423,9 +2423,8 @@ static inline int svm_is_rep(int prefixes) return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); } -static inline void -gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, - uint32_t type, uint64_t param) +static void gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, + uint32_t type) { /* no SVM activated; fast case */ if (likely(!GUEST(s))) { @@ -2433,14 +2432,7 @@ gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, } gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); - gen_helper_svm_check_intercept_param(cpu_env, tcg_const_i32(type), - tcg_const_i64(param)); -} - -static inline void -gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type) -{ - gen_svm_check_intercept_param(s, pc_start, type, 0); + gen_helper_svm_check_intercept(cpu_env, tcg_constant_i32(type)); } static inline void gen_stack_update(DisasContext *s, int addend) From patchwork Sun Feb 28 23:23:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445389 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=ZYejGaGN; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpgcd2dLMz9sSC for ; Mon, 1 Mar 2021 11:09:53 +1100 (AEDT) Received: from localhost ([::1]:46800 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGW8F-0008DX-42 for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 19:09:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43850) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPw-0005sY-8x for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:04 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:44602) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPn-0007mY-8o for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:04 -0500 Received: by mail-pl1-x630.google.com with SMTP id a24so8747929plm.11 for ; Sun, 28 Feb 2021 15:23:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jOmn4vLtGuk+9owXg8+vXu4xydwRiHW7SfVMSLAig3M=; b=ZYejGaGNaC4uSzAM2cLSwVp1FhT/TByoXTAAivyX6P2Ks+z7CyDyhvZX6d0YagujFM qufJK6X3QlE7FMzGPWyBBUAMRL5G1LNTvKD89In89EBrPLcLsXtz4Oc5wffh3Rie00ED Yb300w2cVNenJYJGiHxKaLfZn9s8cfUsY7Z+MFch1MnqAuiA95yhsvhDllgWdVaGzZZ8 YqeVSrUywAvFWi+pENtGX+SFTq+qs9YgWXRLY8optW3BywG+0l9SITyPTN1vfxSMryWZ VKXYEUXmT4/sldoTDluywf9b6QQpaH2LcAMiLLn4yczXiIVNuYsc7aFdipDItqfBu/PW 7elw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jOmn4vLtGuk+9owXg8+vXu4xydwRiHW7SfVMSLAig3M=; b=Oc8UCQFL/ownEmtxQmkHCrsCq8/cEaAP9kxvVRN/eXjineFAUNlWl1KGjOCJpBuEzF WTdw1B7lCjOWbrhkqoHm5anfVEfZi+1jij3mz4CfyK7/eTYFWhquSPLZ5A4cie2NxmhZ vg7Fixi8BhRUhpD2j4xvB7hqCwoWoDuIS+Tzpl4AyphZDXru3pCTsBjk0YWTkovmXoWC VGEwrugEn3qzBu+zq6SE4PvHPJ28/Yv0yVhyGEDm5C41g34k1kc6ltODiEEyc5HcpieY MxusUnarGHzvV/zZl9NRMWe5dxofrC8PniSeF0LXb6pRI6pMFSC2zOGL5iJUaA2pGz3U LNMQ== X-Gm-Message-State: AOAM531yemc92712gS7F5mboZLUTwKG8KWIeRI+oWY8mggU/MAg+fxhr 8XZwKeXU58cKLk4wEhyLaFm8L8b0ZqVuXA== X-Google-Smtp-Source: ABdhPJxA913xnunNgwXbay9Ubi74pksC30W1AmmgVqjV7JEdjgaVN31zlTCk/7PV7Q/UGEXmXVo34w== X-Received: by 2002:a17:902:768b:b029:e3:fb85:1113 with SMTP id m11-20020a170902768bb02900e3fb851113mr13115655pll.3.1614554633433; Sun, 28 Feb 2021 15:23:53 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 37/50] target/i386: Remove pc_start argument to gen_svm_check_intercept Date: Sun, 28 Feb 2021 15:23:08 -0800 Message-Id: <20210228232321.322053-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" When exiting helper_svm_check_intercept via exception, cpu_vmexit calls cpu_restore_state, which will recover eip and cc_op via unwind. Therefore we do not need to store eip or cc_op before the call. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 45 +++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 24 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index cbc0cc3ccc..33faffe00f 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2423,15 +2423,12 @@ static inline int svm_is_rep(int prefixes) return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); } -static void gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, - uint32_t type) +static void gen_svm_check_intercept(DisasContext *s, uint32_t type) { /* no SVM activated; fast case */ if (likely(!GUEST(s))) { return; } - gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); gen_helper_svm_check_intercept(cpu_env, tcg_constant_i32(type)); } @@ -6633,7 +6630,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) val = 0; goto do_lret; case 0xcf: /* iret */ - gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); + gen_svm_check_intercept(s, SVM_EXIT_IRET); if (!PE(s) || VM86(s)) { /* real mode or vm86 mode */ if (!check_vm86_iopl(s)) { @@ -6755,7 +6752,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /************************/ /* flags */ case 0x9c: /* pushf */ - gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF); + gen_svm_check_intercept(s, SVM_EXIT_PUSHF); if (check_vm86_iopl(s)) { gen_update_cc_op(s); gen_helper_read_eflags(s->T0, cpu_env); @@ -6763,7 +6760,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) } break; case 0x9d: /* popf */ - gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); + gen_svm_check_intercept(s, SVM_EXIT_POPF); if (check_vm86_iopl(s)) { ot = gen_pop_T0(s); if (CPL(s) == 0) { @@ -7137,7 +7134,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; #ifdef WANT_ICEBP case 0xf1: /* icebp (undocumented, exits to external debugger) */ - gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP); + gen_svm_check_intercept(s, SVM_EXIT_ICEBP); gen_debug(s); break; #endif @@ -7341,7 +7338,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0: /* sldt */ if (!PE(s) || VM86(s)) goto illegal_op; - gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); + gen_svm_check_intercept(s, SVM_EXIT_LDTR_READ); tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, ldt.selector)); ot = mod == 3 ? dflag : MO_16; @@ -7351,7 +7348,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!PE(s) || VM86(s)) goto illegal_op; if (check_cpl0(s)) { - gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); + gen_svm_check_intercept(s, SVM_EXIT_LDTR_WRITE); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_lldt(cpu_env, s->tmp2_i32); @@ -7360,7 +7357,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 1: /* str */ if (!PE(s) || VM86(s)) goto illegal_op; - gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); + gen_svm_check_intercept(s, SVM_EXIT_TR_READ); tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, tr.selector)); ot = mod == 3 ? dflag : MO_16; @@ -7370,7 +7367,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!PE(s) || VM86(s)) goto illegal_op; if (check_cpl0(s)) { - gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); + gen_svm_check_intercept(s, SVM_EXIT_TR_WRITE); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_ltr(cpu_env, s->tmp2_i32); @@ -7398,7 +7395,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) modrm = x86_ldub_code(env, s); switch (modrm) { CASE_MODRM_MEM_OP(0): /* sgdt */ - gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); + gen_svm_check_intercept(s, SVM_EXIT_GDTR_READ); gen_lea_modrm(env, s, modrm); tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, gdt.limit)); @@ -7454,7 +7451,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; CASE_MODRM_MEM_OP(1): /* sidt */ - gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); + gen_svm_check_intercept(s, SVM_EXIT_IDTR_READ); gen_lea_modrm(env, s, modrm); tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, idt.limit)); gen_op_st_v(s, MO_16, s->T0, s->A0); @@ -7574,7 +7571,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) || !PE(s)) { goto illegal_op; } - gen_svm_check_intercept(s, pc_start, SVM_EXIT_SKINIT); + gen_svm_check_intercept(s, SVM_EXIT_SKINIT); /* If not intercepted, not implemented -- raise #UD. */ goto illegal_op; @@ -7594,7 +7591,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!check_cpl0(s)) { break; } - gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_WRITE); + gen_svm_check_intercept(s, SVM_EXIT_GDTR_WRITE); gen_lea_modrm(env, s, modrm); gen_op_ld_v(s, MO_16, s->T1, s->A0); gen_add_A0_im(s, 2); @@ -7610,7 +7607,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!check_cpl0(s)) { break; } - gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_WRITE); + gen_svm_check_intercept(s, SVM_EXIT_IDTR_WRITE); gen_lea_modrm(env, s, modrm); gen_op_ld_v(s, MO_16, s->T1, s->A0); gen_add_A0_im(s, 2); @@ -7623,7 +7620,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; CASE_MODRM_OP(4): /* smsw */ - gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); + gen_svm_check_intercept(s, SVM_EXIT_READ_CR0); tcg_gen_ld_tl(s->T0, cpu_env, offsetof(CPUX86State, cr[0])); /* * In 32-bit mode, the higher 16 bits of the destination @@ -7655,7 +7652,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!check_cpl0(s)) { break; } - gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); + gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); gen_helper_lmsw(cpu_env, s->T0); gen_jmp_im(s, s->pc - s->cs_base); @@ -7712,7 +7709,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x108: /* invd */ case 0x109: /* wbinvd */ if (check_cpl0(s)) { - gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); + gen_svm_check_intercept(s, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); /* nothing to do */ } break; @@ -8102,14 +8099,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (b & 2) { - gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); + gen_svm_check_intercept(s, SVM_EXIT_WRITE_DR0 + reg); gen_op_mov_v_reg(s, ot, s->T0, rm); tcg_gen_movi_i32(s->tmp2_i32, reg); gen_helper_set_dr(cpu_env, s->tmp2_i32, s->T0); gen_jmp_im(s, s->pc - s->cs_base); gen_eob(s); } else { - gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg); + gen_svm_check_intercept(s, SVM_EXIT_READ_DR0 + reg); tcg_gen_movi_i32(s->tmp2_i32, reg); gen_helper_get_dr(s->T0, cpu_env, s->tmp2_i32); gen_op_mov_reg_v(s, ot, rm, s->T0); @@ -8118,7 +8115,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0x106: /* clts */ if (check_cpl0(s)) { - gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); + gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0); gen_helper_clts(cpu_env); /* abort block because static cpu state changed */ gen_jmp_im(s, s->pc - s->cs_base); @@ -8345,7 +8342,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_nop_modrm(env, s, modrm); break; case 0x1aa: /* rsm */ - gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM); + gen_svm_check_intercept(s, SVM_EXIT_RSM); if (!(s->flags & HF_SMM_MASK)) goto illegal_op; #ifdef CONFIG_USER_ONLY From patchwork Sun Feb 28 23:23:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445388 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=S13mTC+S; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DpgZk6xlWz9sSC for ; Mon, 1 Mar 2021 11:08:14 +1100 (AEDT) Received: from localhost ([::1]:44426 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGW6c-0007Ev-6U for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 19:08:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43844) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPw-0005s5-3I for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:04 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:38496) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPn-0007mf-EW for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:03 -0500 Received: by mail-pf1-x430.google.com with SMTP id 201so10276447pfw.5 for ; Sun, 28 Feb 2021 15:23:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lNlZW0IHz764sQsnKZvud5t74gVw8oF3THem8nh74y4=; b=S13mTC+SP4xsr5wKupFpRYuL/fh4s8qzR+iNDi7qhxm8pNLf3Y1VO+Lnljm3lSQ/Fb +FYvjUP5yzTEDPeSKHJCX/asnSnft38CLB0NgTnkm1laNYFBxYoAIikZGxBY6sMT3thp E4ru1oupGRnloK5yKENFNtc2Iokmz/FdBhVtrOWRrXvWb2D5nBAwHLVv/EzS3GKtjpPp e1hd5CU67BPLdVNBSfnLTjIRdo7jG1GswhRckgZSsUi2znW9Wkw8IOsTQ5tZTGLTEU+6 72v+gZTE+xnsvBz4Z1qp6kkHgX2v8Vzs+OmbE48vaQ72Z0n1z03p3Elgeudcm27n98I/ jNyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lNlZW0IHz764sQsnKZvud5t74gVw8oF3THem8nh74y4=; b=ml/XaXHQkcAWbZP2nM1S52I67mBT1Q51EbgQn8zZ9vc9JSQsM6eYeVDxzPYzzJ8EEn rseaQ8ZGTDtXN8+3UI1xiL4DRYJA2XQIu/BPia0jPZvLTfPVbNZ08pUl/WPKY153YY2k 4g4oVd+oIncs5bsCn92MRV7U6GtRdZDkH3QGn8e7EfGqjrdInzZoAfYpEoHTuIsEDZ4T ReWfYkhH+YvEdw9Xaxvwki+VbZpsMcHvHFaOnD0ZL38bRbDcClpmAbJ3HYVw1z310AkG hAHRVqkVvDdjEKB5DVUUS8TS8mvCxqJr83bQlBE58cVI0wHckqB9Q+5H/SSO87ZBKpnQ iqyw== X-Gm-Message-State: AOAM532DKlVokwsORCGAp5E+AA3vpzwK0V3r5NG+s36fzaCS0hoD3suN IK3pTKRsW0gbwyzVNNgAPqSmAsmYieZUXQ== X-Google-Smtp-Source: ABdhPJy98X4RNJBQVP0nWjv1y8Fmt7sMYZ95EUGTKImLsgo45sUqOrLZHy+lHHXewelERjZS5jgRXQ== X-Received: by 2002:a65:5288:: with SMTP id y8mr10558188pgp.105.1614554634087; Sun, 28 Feb 2021 15:23:54 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 38/50] target/i386: Remove user stub for cpu_vmexit Date: Sun, 28 Feb 2021 15:23:09 -0800 Message-Id: <20210228232321.322053-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This function is only called from tcg/sysemu/. There is no need for a stub in tcg/user/. Signed-off-by: Richard Henderson --- target/i386/tcg/helper-tcg.h | 4 +++- target/i386/tcg/user/svm_stubs.c | 6 ------ 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 3d47cb83cd..e848c3b4b9 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -81,10 +81,12 @@ extern const uint8_t parity_table[256]; /* misc_helper.c */ void cpu_load_eflags(CPUX86State *env, int eflags, int update_mask); -/* svm_helper.c */ +/* sysemu/svm_helper.c */ +#ifndef CONFIG_USER_ONLY void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1, uintptr_t retaddr); void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); +#endif /* seg_helper.c */ void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); diff --git a/target/i386/tcg/user/svm_stubs.c b/target/i386/tcg/user/svm_stubs.c index 48a43bdcea..db818f89a8 100644 --- a/target/i386/tcg/user/svm_stubs.c +++ b/target/i386/tcg/user/svm_stubs.c @@ -22,12 +22,6 @@ #include "exec/helper-proto.h" #include "tcg/helper-tcg.h" -void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1, - uintptr_t retaddr) -{ - assert(0); -} - void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, uint64_t param, uintptr_t retaddr) { From patchwork Sun Feb 28 23:23:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445391 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=ZOiYeKUY; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpggl4DJHz9sSC for ; Mon, 1 Mar 2021 11:12:35 +1100 (AEDT) Received: from localhost ([::1]:51574 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGWAr-0001p6-Ik for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 19:12:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43858) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVPx-0005wi-OL for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:05 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:39296) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVPo-0007mj-2Z for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:05 -0500 Received: by mail-pl1-x633.google.com with SMTP id k22so8762250pll.6 for ; Sun, 28 Feb 2021 15:23:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aqZMZKuCD0f1nXNgNRszgNxoe0OlJvCa7ALxkvWMb0k=; b=ZOiYeKUYxZ/hbs3HDy3JLBRKGPfckQydXWaFWMxKL2sBtv9jCu3fLaiYE2ctqGqA5T frkMsdM16w2EUDvBkPwAuglrY34UZvbM1LFL7OLRd/9Z1+AGUQOmkGEQU2M9IvOwmjJQ nC+BsLEUXUsDSF4zy6xsrPDRWknBcB3f6f7l0UgmM9ky07fXaBHa7yGhLZk9mes5zUgt hNaKCduezRmmjWyUh5/PPasFGox6Rb4te79Jknk+hS4sebhCFgZDVE18YvT9MAe7pVgQ 3DUANngDR1F8TrR6GUefXLW8zhdkW09gCVBwdMhfnQoneNp5TOnuSN9bPqyGqQt/fT5e JVRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aqZMZKuCD0f1nXNgNRszgNxoe0OlJvCa7ALxkvWMb0k=; b=nt1n0cP/efRkPbUDU1UW1Pd4fgkhUrHEj2ikz1XopUnztDyyrxQadkpOBcbQRQfU8I JQzIJplhpQJCQzU6atJwYWMZOyoLK6ULHWgKJRvtJpjAMtZIsXJ7S2l4m44mivwfigQ0 JD46r0qbORoOp1nwJ+uhOCRxMqn2b3lmXGin/2UwL7eQ0Li5e+rkAWOL2SBXh9WupjEI itJ7uBahyHoaVQSdRZ/ljl9j2C9qHZHf3EqUJKP2NRMaE81FoTQ+TBo2jzYHyVX/OLyU QYW/8Qw11Wig7m81DRDKomZlb78MO9I+D/FdewWnnMxz+tkIy3nuRk1dfviFE2IgLG+x WBTQ== X-Gm-Message-State: AOAM532di0EwHDjqn3By236WctCZM9VqPfSfmnGro1wNmQmNbOhpiSpJ ppGoXIpapnEywL2BXn/QnJGfwfxgCkb3rw== X-Google-Smtp-Source: ABdhPJxLDY7O/EeWbHyI9fDfZJ540gCLF2Z70eFgrwhv7wbWtO2p9LPtFRJgYazLndecP8rcrGS85Q== X-Received: by 2002:a17:90a:114f:: with SMTP id d15mr14556061pje.1.1614554634828; Sun, 28 Feb 2021 15:23:54 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 39/50] target/i386: Cleanup read_crN, write_crN, lmsw Date: Sun, 28 Feb 2021 15:23:10 -0800 Message-Id: <20210228232321.322053-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Pull the svm intercept check into the translator. Pull the entire implementation of lmsw into the translator. Push the check for CR8LEG into the regno validation switch. Unify the gen_io_start check between read/write. Signed-off-by: Richard Henderson --- target/i386/helper.h | 5 +- target/i386/tcg/misc_helper.c | 8 --- target/i386/tcg/sysemu/misc_helper.c | 2 - target/i386/tcg/translate.c | 97 +++++++++++++++------------- 4 files changed, 54 insertions(+), 58 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index 86484a4ec4..ebfaca66dd 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -42,9 +42,8 @@ DEF_HELPER_5(lcall_protected, void, env, int, tl, int, tl) DEF_HELPER_2(iret_real, void, env, int) DEF_HELPER_3(iret_protected, void, env, int, int) DEF_HELPER_3(lret_protected, void, env, int, int) -DEF_HELPER_2(read_crN, tl, env, int) -DEF_HELPER_3(write_crN, void, env, int, tl) -DEF_HELPER_2(lmsw, void, env, tl) +DEF_HELPER_FLAGS_2(read_crN, TCG_CALL_NO_RWG, tl, env, int) +DEF_HELPER_FLAGS_3(write_crN, TCG_CALL_NO_RWG, void, env, int, tl) DEF_HELPER_1(clts, void, env) #ifndef CONFIG_USER_ONLY diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index 1ca9ace3dc..b0d3c61f13 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -60,14 +60,6 @@ void helper_cpuid(CPUX86State *env) env->regs[R_EDX] = edx; } -void helper_lmsw(CPUX86State *env, target_ulong t0) -{ - /* only 4 lower bits of CR0 are modified. PE cannot be set to zero - if already set to one. */ - t0 = (env->cr[0] & ~0xe) | (t0 & 0xf); - helper_write_crN(env, 0, t0); -} - void helper_invlpg(CPUX86State *env, target_ulong addr) { X86CPU *cpu = env_archcpu(env); diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index 6a88840cf2..ebf15e3dde 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -65,7 +65,6 @@ target_ulong helper_read_crN(CPUX86State *env, int reg) { target_ulong val; - cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0, GETPC()); switch (reg) { default: val = env->cr[reg]; @@ -83,7 +82,6 @@ target_ulong helper_read_crN(CPUX86State *env, int reg) void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) { - cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0, GETPC()); switch (reg) { case 0: cpu_x86_update_cr0(env, t0); diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 33faffe00f..708059ac15 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -7648,13 +7648,22 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]); gen_helper_wrpkru(cpu_env, s->tmp2_i32, s->tmp1_i64); break; + CASE_MODRM_OP(6): /* lmsw */ if (!check_cpl0(s)) { break; } gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); - gen_helper_lmsw(cpu_env, s->T0); + /* + * Only the 4 lower bits of CR0 are modified. + * PE cannot be set to zero if already set to one. + */ + tcg_gen_ld_tl(s->T1, cpu_env, offsetof(CPUX86State, cr[0])); + tcg_gen_andi_tl(s->T0, s->T0, 0xf); + tcg_gen_andi_tl(s->T1, s->T1, ~0xe); + tcg_gen_or_tl(s->T0, s->T0, s->T1); + gen_helper_write_crN(cpu_env, tcg_constant_i32(0), s->T0); gen_jmp_im(s, s->pc - s->cs_base); gen_eob(s); break; @@ -8028,58 +8037,56 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) modrm = x86_ldub_code(env, s); gen_nop_modrm(env, s, modrm); break; + case 0x120: /* mov reg, crN */ case 0x122: /* mov crN, reg */ - if (check_cpl0(s)) { - modrm = x86_ldub_code(env, s); - /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). - * AMD documentation (24594.pdf) and testing of - * intel 386 and 486 processors all show that the mod bits - * are assumed to be 1's, regardless of actual values. - */ - rm = (modrm & 7) | REX_B(s); - reg = ((modrm >> 3) & 7) | REX_R(s); - if (CODE64(s)) - ot = MO_64; - else - ot = MO_32; - if ((prefixes & PREFIX_LOCK) && (reg == 0) && + if (!check_cpl0(s)) { + break; + } + modrm = x86_ldub_code(env, s); + /* + * Ignore the mod bits (assume (modrm&0xc0)==0xc0). + * AMD documentation (24594.pdf) and testing of Intel 386 and 486 + * processors all show that the mod bits are assumed to be 1's, + * regardless of actual values. + */ + rm = (modrm & 7) | REX_B(s); + reg = ((modrm >> 3) & 7) | REX_R(s); + switch (reg) { + case 0: + if ((prefixes & PREFIX_LOCK) && (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) { reg = 8; } - switch(reg) { - case 0: - case 2: - case 3: - case 4: - case 8: - gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); - if (b & 2) { - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_op_mov_v_reg(s, ot, s->T0, rm); - gen_helper_write_crN(cpu_env, tcg_const_i32(reg), - s->T0); - gen_jmp_im(s, s->pc - s->cs_base); - gen_eob(s); - } else { - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_read_crN(s->T0, cpu_env, tcg_const_i32(reg)); - gen_op_mov_reg_v(s, ot, rm, s->T0); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_jmp(s, s->pc - s->cs_base); - } - } - break; - default: - goto unknown_op; + break; + case 2: + case 3: + case 4: + break; + default: + goto unknown_op; + } + ot = (CODE64(s) ? MO_64 : MO_32); + + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + if (b & 2) { + gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0 + reg); + gen_op_mov_v_reg(s, ot, s->T0, rm); + gen_helper_write_crN(cpu_env, tcg_constant_i32(reg), s->T0); + gen_jmp_im(s, s->pc - s->cs_base); + gen_eob(s); + } else { + gen_svm_check_intercept(s, SVM_EXIT_READ_CR0 + reg); + gen_helper_read_crN(s->T0, cpu_env, tcg_constant_i32(reg)); + gen_op_mov_reg_v(s, ot, rm, s->T0); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_jmp(s, s->pc - s->cs_base); } } break; + case 0x121: /* mov reg, drN */ case 0x123: /* mov drN, reg */ if (check_cpl0(s)) { From patchwork Sun Feb 28 23:23:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445392 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=gS92BZqZ; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpghp4yqBz9sSC for ; Mon, 1 Mar 2021 11:13:30 +1100 (AEDT) Received: from localhost ([::1]:53786 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGWBj-0002iU-L3 for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 19:13:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43978) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVQK-0006X1-Ps for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:28 -0500 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:35215) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVQJ-00081U-4R for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:28 -0500 Received: by mail-pj1-x102f.google.com with SMTP id e9so10494567pjj.0 for ; Sun, 28 Feb 2021 15:24:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+JUyBjkTS0UwwOaXD6FMEo6z2JEb+NRx/8D4N91CKuI=; b=gS92BZqZpv8FCTHgF945XbCi0fH2L9DoKaIJjUPceeI816AvbtlRSVGvccwDM8bwZZ j7tDFxBDJX0L9MH48GsBGUrpqPwIHqH+l9wmANk0nva4OEAKHMGH+5l3Ld0K4EXczT2r k/RxCLd8+TIT1eITiRCUX+hD2kLyFPlJL5yx1/OBmtQHYiK6sMID3QpgoR5vZSfKkxM5 1srXaXuLpSgekK7DbLC9gdog4GJf748Ci4P74uBmNOosF1RYw2xr5nMxsfIjNUbOBLYH F/lYkcfVkCTc+/p3QCboQZy66Wrq2YQlPO4XIAPFMVFvOVKrKg2uCv9ayGdDsoixHLfl ZsBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+JUyBjkTS0UwwOaXD6FMEo6z2JEb+NRx/8D4N91CKuI=; b=cDBN1+gG1Ni/wdKR6BYxEUwncLWBJ0HU2tHgXrYTuUx91u4WERwuhld/MgW7MPHS59 oGFVqqHtf5Z6gB2a9pXqu24SuaERA/Yj90RefYJAypFC8FZTZfzXddG/J25fVyaTHfQ6 lJgeRWqf4heZW3ibp0B20ZqivWc0YCiH/Agr9bwfEHgsXlsBglOUvf/58sMb7ZnG61mO l+G46okVucWeFd2HBOmqkJLoQFlLoXtp2UIAaGwBsUYr7Xhj3eER3uZfI/58nkzKHzWI DQ5alEGAZ5jwqc9gfv5II+OyFJ8PLWDncN0WBWfTB0LwqiCjYZVBVKXyHgXGI9ZG5qhq 1q8g== X-Gm-Message-State: AOAM531xitsSpnVFU3i4ASeBKVFATKAKo5SYHd5w5pgPOrLTlXHDNRbJ BUl9ryORgfZ2P+oDL0EC0eEa+Qzpa13rxA== X-Google-Smtp-Source: ABdhPJxQo3Bw9HV7p6vQHoHrv5U/JUFx9KCkrMF9yxynTUEm1sUTQi4AA6DPT9WhnpobCro8GSFYUA== X-Received: by 2002:a17:90a:f2d2:: with SMTP id gt18mr6469378pjb.210.1614554665846; Sun, 28 Feb 2021 15:24:25 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id b10sm14164049pgm.76.2021.02.28.15.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:24:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 40/50] target/i386: Pass env to do_pause and do_hlt Date: Sun, 28 Feb 2021 15:23:11 -0800 Message-Id: <20210228232321.322053-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Having the callers upcast to X86CPU is a waste, since we don't need it. We even have to recover env in do_hlt. Signed-off-by: Richard Henderson --- target/i386/tcg/misc_helper.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index b0d3c61f13..20bf4771e7 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -100,19 +100,18 @@ void QEMU_NORETURN helper_rdpmc(CPUX86State *env) raise_exception_err(env, EXCP06_ILLOP, 0); } -static QEMU_NORETURN void do_pause(X86CPU *cpu) +static void QEMU_NORETURN do_pause(CPUX86State *env) { - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); /* Just let another CPU run. */ cs->exception_index = EXCP_INTERRUPT; cpu_loop_exit(cs); } -static QEMU_NORETURN void do_hlt(X86CPU *cpu) +static void QEMU_NORETURN do_hlt(CPUX86State *env) { - CPUState *cs = CPU(cpu); - CPUX86State *env = &cpu->env; + CPUState *cs = env_cpu(env); env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */ cs->halted = 1; @@ -122,12 +121,10 @@ static QEMU_NORETURN void do_hlt(X86CPU *cpu) void QEMU_NORETURN helper_hlt(CPUX86State *env, int next_eip_addend) { - X86CPU *cpu = env_archcpu(env); - cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC()); env->eip += next_eip_addend; - do_hlt(cpu); + do_hlt(env); } void helper_monitor(CPUX86State *env, target_ulong ptr) @@ -142,7 +139,6 @@ void helper_monitor(CPUX86State *env, target_ulong ptr) void QEMU_NORETURN helper_mwait(CPUX86State *env, int next_eip_addend) { CPUState *cs = env_cpu(env); - X86CPU *cpu = env_archcpu(env); if ((uint32_t)env->regs[R_ECX] != 0) { raise_exception_ra(env, EXCP0D_GPF, GETPC()); @@ -152,20 +148,18 @@ void QEMU_NORETURN helper_mwait(CPUX86State *env, int next_eip_addend) /* XXX: not complete but not completely erroneous */ if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) { - do_pause(cpu); + do_pause(env); } else { - do_hlt(cpu); + do_hlt(env); } } void QEMU_NORETURN helper_pause(CPUX86State *env, int next_eip_addend) { - X86CPU *cpu = env_archcpu(env); - cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0, GETPC()); env->eip += next_eip_addend; - do_pause(cpu); + do_pause(env); } void QEMU_NORETURN helper_debug(CPUX86State *env) From patchwork Sun Feb 28 23:23:12 2021 Content-Type: text/plain; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id b10sm14164049pgm.76.2021.02.28.15.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:24:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 41/50] target/i386: Move invlpg, hlt, monitor, mwait to sysemu Date: Sun, 28 Feb 2021 15:23:12 -0800 Message-Id: <20210228232321.322053-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" These instructions are all privileged. Signed-off-by: Richard Henderson --- target/i386/helper.h | 8 ++-- target/i386/tcg/helper-tcg.h | 1 + target/i386/tcg/misc_helper.c | 55 +--------------------------- target/i386/tcg/sysemu/misc_helper.c | 53 +++++++++++++++++++++++++++ target/i386/tcg/translate.c | 4 ++ 5 files changed, 63 insertions(+), 58 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index ebfaca66dd..ab72eba52a 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -51,7 +51,6 @@ DEF_HELPER_FLAGS_3(set_dr, TCG_CALL_NO_WG, void, env, int, tl) #endif /* !CONFIG_USER_ONLY */ DEF_HELPER_FLAGS_2(get_dr, TCG_CALL_NO_WG, tl, env, int) -DEF_HELPER_2(invlpg, void, env, tl) DEF_HELPER_1(sysenter, void, env) DEF_HELPER_2(sysexit, void, env, int) @@ -59,9 +58,6 @@ DEF_HELPER_2(sysexit, void, env, int) DEF_HELPER_2(syscall, void, env, int) DEF_HELPER_2(sysret, void, env, int) #endif -DEF_HELPER_FLAGS_2(hlt, TCG_CALL_NO_WG, noreturn, env, int) -DEF_HELPER_FLAGS_2(monitor, TCG_CALL_NO_WG, void, env, tl) -DEF_HELPER_FLAGS_2(mwait, TCG_CALL_NO_WG, noreturn, env, int) DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int) DEF_HELPER_FLAGS_1(debug, TCG_CALL_NO_WG, noreturn, env) DEF_HELPER_1(reset_rf, void, env) @@ -115,6 +111,10 @@ DEF_HELPER_2(vmsave, void, env, int) DEF_HELPER_1(stgi, void, env) DEF_HELPER_1(clgi, void, env) DEF_HELPER_2(invlpga, void, env, int) +DEF_HELPER_2(invlpg, void, env, tl) +DEF_HELPER_FLAGS_2(hlt, TCG_CALL_NO_WG, noreturn, env, int) +DEF_HELPER_FLAGS_2(monitor, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_2(mwait, TCG_CALL_NO_WG, noreturn, env, int) #endif /* !CONFIG_USER_ONLY */ /* x86 FPU */ diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index e848c3b4b9..cce350aa0b 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -80,6 +80,7 @@ extern const uint8_t parity_table[256]; /* misc_helper.c */ void cpu_load_eflags(CPUX86State *env, int eflags, int update_mask); +void do_pause(CPUX86State *env) QEMU_NORETURN; /* sysemu/svm_helper.c */ #ifndef CONFIG_USER_ONLY diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index 20bf4771e7..180bed9021 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -60,14 +60,6 @@ void helper_cpuid(CPUX86State *env) env->regs[R_EDX] = edx; } -void helper_invlpg(CPUX86State *env, target_ulong addr) -{ - X86CPU *cpu = env_archcpu(env); - - cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC()); - tlb_flush_page(CPU(cpu), addr); -} - void helper_rdtsc(CPUX86State *env) { uint64_t val; @@ -100,7 +92,7 @@ void QEMU_NORETURN helper_rdpmc(CPUX86State *env) raise_exception_err(env, EXCP06_ILLOP, 0); } -static void QEMU_NORETURN do_pause(CPUX86State *env) +void QEMU_NORETURN do_pause(CPUX86State *env) { CPUState *cs = env_cpu(env); @@ -109,51 +101,6 @@ static void QEMU_NORETURN do_pause(CPUX86State *env) cpu_loop_exit(cs); } -static void QEMU_NORETURN do_hlt(CPUX86State *env) -{ - CPUState *cs = env_cpu(env); - - env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */ - cs->halted = 1; - cs->exception_index = EXCP_HLT; - cpu_loop_exit(cs); -} - -void QEMU_NORETURN helper_hlt(CPUX86State *env, int next_eip_addend) -{ - cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC()); - env->eip += next_eip_addend; - - do_hlt(env); -} - -void helper_monitor(CPUX86State *env, target_ulong ptr) -{ - if ((uint32_t)env->regs[R_ECX] != 0) { - raise_exception_ra(env, EXCP0D_GPF, GETPC()); - } - /* XXX: store address? */ - cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0, GETPC()); -} - -void QEMU_NORETURN helper_mwait(CPUX86State *env, int next_eip_addend) -{ - CPUState *cs = env_cpu(env); - - if ((uint32_t)env->regs[R_ECX] != 0) { - raise_exception_ra(env, EXCP0D_GPF, GETPC()); - } - cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0, GETPC()); - env->eip += next_eip_addend; - - /* XXX: not complete but not completely erroneous */ - if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) { - do_pause(env); - } else { - do_hlt(env); - } -} - void QEMU_NORETURN helper_pause(CPUX86State *env, int next_eip_addend) { cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0, GETPC()); diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index ebf15e3dde..1d8b651212 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -434,3 +434,56 @@ void helper_rdmsr(CPUX86State *env) env->regs[R_EAX] = (uint32_t)(val); env->regs[R_EDX] = (uint32_t)(val >> 32); } + +void helper_invlpg(CPUX86State *env, target_ulong addr) +{ + X86CPU *cpu = env_archcpu(env); + + cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC()); + tlb_flush_page(CPU(cpu), addr); +} + +static void QEMU_NORETURN do_hlt(CPUX86State *env) +{ + CPUState *cs = env_cpu(env); + + env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */ + cs->halted = 1; + cs->exception_index = EXCP_HLT; + cpu_loop_exit(cs); +} + +void QEMU_NORETURN helper_hlt(CPUX86State *env, int next_eip_addend) +{ + cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC()); + env->eip += next_eip_addend; + + do_hlt(env); +} + +void helper_monitor(CPUX86State *env, target_ulong ptr) +{ + if ((uint32_t)env->regs[R_ECX] != 0) { + raise_exception_ra(env, EXCP0D_GPF, GETPC()); + } + /* XXX: store address? */ + cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0, GETPC()); +} + +void QEMU_NORETURN helper_mwait(CPUX86State *env, int next_eip_addend) +{ + CPUState *cs = env_cpu(env); + + if ((uint32_t)env->regs[R_ECX] != 0) { + raise_exception_ra(env, EXCP0D_GPF, GETPC()); + } + cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0, GETPC()); + env->eip += next_eip_addend; + + /* XXX: not complete but not completely erroneous */ + if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) { + do_pause(env); + } else { + do_hlt(env); + } +} diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 708059ac15..aa6a8c4813 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -194,7 +194,11 @@ typedef struct DisasContext { #ifdef CONFIG_USER_ONLY STUB_HELPER(clgi, TCGv_env env) +STUB_HELPER(hlt, TCGv_env env, TCGv_i32 pc_ofs) STUB_HELPER(invlpga, TCGv_env env, TCGv_i32 aflag) +STUB_HELPER(invlpg, TCGv_env env, TCGv addr) +STUB_HELPER(monitor, TCGv_env env, TCGv addr) +STUB_HELPER(mwait, TCGv_env env, TCGv_i32 pc_ofs) STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) STUB_HELPER(stgi, TCGv_env env) STUB_HELPER(svm_check_intercept, TCGv_env env, TCGv_i32 type) From patchwork Sun Feb 28 23:23:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445376 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=p6wYkpOU; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpg9f19twz9sRR for ; Mon, 1 Mar 2021 10:49:58 +1100 (AEDT) Received: from localhost ([::1]:39994 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVoy-0001WT-3H for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:49:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44012) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVQM-0006b9-He for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:30 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:34836) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVQK-00082B-Bo for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:30 -0500 Received: by mail-pl1-x631.google.com with SMTP id g20so8775706plo.2 for ; Sun, 28 Feb 2021 15:24:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6nFM7mvFhUXE7Fg3oMPfO4xBFJLP9Mt7B9tvDexHBR0=; b=p6wYkpOUEiQcwZBfLF2/Wh0H06s8bT0jSUOswYH5H9q/fshKkZDdk0nQWmHQnBUi5w CFn8MnvbiCngeGKdMScNXmdlx0S4HZThLzz6yMKrvGSfAdGS6ETEo7uw1/vf50TAQXS4 TR/c/qpszGzBzh7ChUiqwvfAqXB5JCOfSSzmb4GZeTDOS1Kj6pOaedHXXhTlrRXB6GJx Z96/bAunEzLMMcSX91b1oisyu++os2tMmv7D7Qb6eAJU3cZz/WuLvaqpBtIfaSd/7xcp v4RHCJneoKAPvuaN50FklPHuQ7KIRoPN5eJmFIpBqdLHfuCZFzPn5QqMQj2JiUB/fqe3 DQFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6nFM7mvFhUXE7Fg3oMPfO4xBFJLP9Mt7B9tvDexHBR0=; b=RuEiDzgXYlIJS26jwXYkL6PrsWyi23rGu48Sgzrlu7N5uq8IjY03LbpcwKvH8IALCz CVITqhleLKclHsLdqcfJO/lOn5L6rRb7lNoKkzncVIkyQZJAxDtzZfMl9sYPDmPrgeuR CViTucGBSXTRFXp1dgjnFJWXaEPjKV3pXRteCwu9tDvA30XXTaO4NURpkv/WC10ZDfN4 VoObqHAh7LTlxAYzRuo1yLQM3iP5JcP7Nv44d3FD6pf7k47P36F1onB9Ra/Kj4oo6KEF an+ak3L/CLQH2eoaYWIE+nYBnIzeTfapmiAmeZCZ3AD/VDB3YWtYHtAzPyK6D6YnTWht dMHw== X-Gm-Message-State: AOAM53178dVOQJG+K1DCqQ1gwabFgCbHMdBfIUkVP/maHpYdx4+OGcCB PgS/JwhJhawXjsN6U6BkvbnuP/GEjx/8aw== X-Google-Smtp-Source: ABdhPJwhIHMikooVxOXybogxB4/C87I9PXNtGoPXDzoNgjAM3p4THLaWCouN5M+vx/JLnnWecnU1Hw== X-Received: by 2002:a17:90a:7c0c:: with SMTP id v12mr14095219pjf.63.1614554667155; Sun, 28 Feb 2021 15:24:27 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id b10sm14164049pgm.76.2021.02.28.15.24.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:24:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 42/50] target/i386: Unify invlpg, invlpga Date: Sun, 28 Feb 2021 15:23:13 -0800 Message-Id: <20210228232321.322053-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Use a single helper, flush_page, to do the work. Use gen_svm_check_intercept. Perform the zero-extension for invlpga inline. Signed-off-by: Richard Henderson --- target/i386/helper.h | 3 +-- target/i386/tcg/sysemu/misc_helper.c | 7 ++----- target/i386/tcg/sysemu/svm_helper.c | 18 ------------------ target/i386/tcg/translate.c | 20 ++++++++++++-------- 4 files changed, 15 insertions(+), 33 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index ab72eba52a..0264fba335 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -110,8 +110,7 @@ DEF_HELPER_2(vmload, void, env, int) DEF_HELPER_2(vmsave, void, env, int) DEF_HELPER_1(stgi, void, env) DEF_HELPER_1(clgi, void, env) -DEF_HELPER_2(invlpga, void, env, int) -DEF_HELPER_2(invlpg, void, env, tl) +DEF_HELPER_FLAGS_2(flush_page, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(hlt, TCG_CALL_NO_WG, noreturn, env, int) DEF_HELPER_FLAGS_2(monitor, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_FLAGS_2(mwait, TCG_CALL_NO_WG, noreturn, env, int) diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index 1d8b651212..b7146092f1 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -435,12 +435,9 @@ void helper_rdmsr(CPUX86State *env) env->regs[R_EDX] = (uint32_t)(val >> 32); } -void helper_invlpg(CPUX86State *env, target_ulong addr) +void helper_flush_page(CPUX86State *env, target_ulong addr) { - X86CPU *cpu = env_archcpu(env); - - cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC()); - tlb_flush_page(CPU(cpu), addr); + tlb_flush_page(env_cpu(env), addr); } static void QEMU_NORETURN do_hlt(CPUX86State *env) diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c index 86a0b3c4be..a8a671aa33 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -423,24 +423,6 @@ void helper_clgi(CPUX86State *env) env->hflags2 &= ~HF2_GIF_MASK; } -void helper_invlpga(CPUX86State *env, int aflag) -{ - X86CPU *cpu = env_archcpu(env); - target_ulong addr; - - cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0, GETPC()); - - if (aflag == 2) { - addr = env->regs[R_EAX]; - } else { - addr = (uint32_t)env->regs[R_EAX]; - } - - /* XXX: could use the ASID to see if it is needed to do the - flush */ - tlb_flush_page(CPU(cpu), addr); -} - void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, uint64_t param, uintptr_t retaddr) { diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index aa6a8c4813..9d2171aa3a 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -194,9 +194,8 @@ typedef struct DisasContext { #ifdef CONFIG_USER_ONLY STUB_HELPER(clgi, TCGv_env env) +STUB_HELPER(flush_page, TCGv_env env, TCGv addr) STUB_HELPER(hlt, TCGv_env env, TCGv_i32 pc_ofs) -STUB_HELPER(invlpga, TCGv_env env, TCGv_i32 aflag) -STUB_HELPER(invlpg, TCGv_env env, TCGv addr) STUB_HELPER(monitor, TCGv_env env, TCGv addr) STUB_HELPER(mwait, TCGv_env env, TCGv_i32 pc_ofs) STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) @@ -7586,9 +7585,15 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!check_cpl0(s)) { break; } - gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); - gen_helper_invlpga(cpu_env, tcg_const_i32(s->aflag - 1)); + gen_svm_check_intercept(s, SVM_EXIT_INVLPGA); + if (s->aflag == MO_64) { + tcg_gen_mov_tl(s->A0, cpu_regs[R_EAX]); + } else { + tcg_gen_ext32u_tl(s->A0, cpu_regs[R_EAX]); + } + gen_helper_flush_page(cpu_env, s->A0); + gen_jmp_im(s, s->pc - s->cs_base); + gen_eob(s); break; CASE_MODRM_MEM_OP(2): /* lgdt */ @@ -7676,10 +7681,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!check_cpl0(s)) { break; } - gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); + gen_svm_check_intercept(s, SVM_EXIT_INVLPG); gen_lea_modrm(env, s, modrm); - gen_helper_invlpg(cpu_env, s->A0); + gen_helper_flush_page(cpu_env, s->A0); gen_jmp_im(s, s->pc - s->cs_base); gen_eob(s); break; From patchwork Sun Feb 28 23:23:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445379 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id b10sm14164049pgm.76.2021.02.28.15.24.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:24:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 43/50] target/i386: Inline user cpu_svm_check_intercept_param Date: Sun, 28 Feb 2021 15:23:14 -0800 Message-Id: <20210228232321.322053-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The user-version is a no-op. This lets us completely remove tcg/user/svm_stubs.c. Signed-off-by: Richard Henderson --- target/i386/cpu.h | 8 ++++++++ target/i386/tcg/user/svm_stubs.c | 28 ---------------------------- target/i386/tcg/user/meson.build | 1 - 3 files changed, 8 insertions(+), 29 deletions(-) delete mode 100644 target/i386/tcg/user/svm_stubs.c diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a1268abe9f..70b26991dd 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2129,8 +2129,16 @@ static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) void helper_lock_init(void); /* svm_helper.c */ +#ifdef CONFIG_USER_ONLY +static inline void +cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, + uint64_t param, uintptr_t retaddr) +{ /* no-op */ } +#else void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, uint64_t param, uintptr_t retaddr); +#endif + /* apic.c */ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, diff --git a/target/i386/tcg/user/svm_stubs.c b/target/i386/tcg/user/svm_stubs.c deleted file mode 100644 index db818f89a8..0000000000 --- a/target/i386/tcg/user/svm_stubs.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * x86 SVM helpers (user-mode) - * - * Copyright (c) 2003 Fabrice Bellard - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "exec/helper-proto.h" -#include "tcg/helper-tcg.h" - -void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, - uint64_t param, uintptr_t retaddr) -{ -} diff --git a/target/i386/tcg/user/meson.build b/target/i386/tcg/user/meson.build index 345294c096..16a0be1ae6 100644 --- a/target/i386/tcg/user/meson.build +++ b/target/i386/tcg/user/meson.build @@ -2,6 +2,5 @@ i386_user_ss.add(when: ['CONFIG_TCG', 'CONFIG_USER_ONLY'], if_true: files( 'excp_helper.c', 'misc_stubs.c', 'fpu_helper.c', - 'svm_stubs.c', 'seg_helper.c', )) From patchwork Sun Feb 28 23:23:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445361 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=jA3QfZNe; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpg2M3Vssz9sS8 for ; Mon, 1 Mar 2021 10:43:39 +1100 (AEDT) Received: from localhost ([::1]:48066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVir-0001eZ-Dv for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:43:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44038) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVQN-0006dh-KK for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:31 -0500 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:37162) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVQL-00082z-OS for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:31 -0500 Received: by mail-pg1-x52c.google.com with SMTP id o10so10362572pgg.4 for ; Sun, 28 Feb 2021 15:24:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LwDKrp05e40VoqkSfurI/uNTqGwd7yQc3l2JK2S828k=; b=jA3QfZNeRNP478mdVidjuVrkCYa6QeutoPFaqhpZxbtgYMmFfpccSJ3LCnXY5NG8NQ H/jSOBNXJ9WiwtFBiMrXOSJcu0IlZQcWtQZY1dqhL7X88ZXYmeFbpcy9ldcrZsBFCfCT EKcHg6lTWfDYFSDCv3E9ij9obLmXpZsmf0nDeoldPyFSmwlhtvMQ58dnXxwRowWOVlWD vbOzwjQN4inbk+GSsr7vcQmt9BAgAeXZdgryDNJcqira4skDWnHeGd5ILLA4/aVkIVhs QdFksS/ILxZrG4wy67V/mfFUElFbae3WMcI2yHK1jQe4J5DircdOLV76cmhXZ75jMsf7 3s3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LwDKrp05e40VoqkSfurI/uNTqGwd7yQc3l2JK2S828k=; b=FK7g7K+f0LmpxeXnf28OxsPqCWwEI0BYeIKplATZWT5HLswR7/ZMat7RRDZt1Clvgl B+MpUa9DcVSeQHwtB7TkQFNXpgyM6Tn8+CrMaKmkaM5WIHPIt4RiZiDnQ6GVcXmT+vok VR6VfUeDc/ffp57o8DZgrwvh2u3/L7UaSNiiLxg3zgWODqb/01VQK3g2QrgMwkokjK70 cmTlEgkcqoI3aiBvkIL9WbwWAjjHmxpkW9Nhp9ui2u+WZ+zDXr0JuwQzXoWuYxJYV7yQ HFggaDzZGMmQsI4PcSpskradJsn1wSkKD4IsXwk/CtCiTSxNV2jUa3Bv7IknH9MLUa3B sVow== X-Gm-Message-State: AOAM5312N1t7nkkaVHswKYHyS7w51PFylX4rrhF49xxPGSSJkHWZCswk KPVISDqpEw6qjZwPo31fRIKzrWtknk3T6Q== X-Google-Smtp-Source: ABdhPJwwNEnkeGecLQn0lJX6z1TrvHz4TpDFcDdIXwRBT5WkXdLks6/wOf+E8qzFErS4592KidhhWw== X-Received: by 2002:a62:5344:0:b029:1c7:eeea:8bad with SMTP id h65-20020a6253440000b02901c7eeea8badmr12659627pfb.1.1614554668418; Sun, 28 Feb 2021 15:24:28 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id b10sm14164049pgm.76.2021.02.28.15.24.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:24:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 44/50] target/i386: Eliminate user stubs for read/write_crN, rd/wrmsr Date: Sun, 28 Feb 2021 15:23:15 -0800 Message-Id: <20210228232321.322053-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/i386/helper.h | 8 ++++---- target/i386/tcg/translate.c | 4 ++++ target/i386/tcg/user/misc_stubs.c | 20 -------------------- 3 files changed, 8 insertions(+), 24 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index 0264fba335..1d85f033df 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -42,8 +42,6 @@ DEF_HELPER_5(lcall_protected, void, env, int, tl, int, tl) DEF_HELPER_2(iret_real, void, env, int) DEF_HELPER_3(iret_protected, void, env, int, int) DEF_HELPER_3(lret_protected, void, env, int, int) -DEF_HELPER_FLAGS_2(read_crN, TCG_CALL_NO_RWG, tl, env, int) -DEF_HELPER_FLAGS_3(write_crN, TCG_CALL_NO_RWG, void, env, int, tl) DEF_HELPER_1(clts, void, env) #ifndef CONFIG_USER_ONLY @@ -87,8 +85,6 @@ DEF_HELPER_1(cpuid, void, env) DEF_HELPER_1(rdtsc, void, env) DEF_HELPER_1(rdtscp, void, env) DEF_HELPER_FLAGS_1(rdpmc, TCG_CALL_NO_WG, noreturn, env) -DEF_HELPER_1(rdmsr, void, env) -DEF_HELPER_1(wrmsr, void, env) DEF_HELPER_2(check_iob, void, env, i32) DEF_HELPER_2(check_iow, void, env, i32) @@ -114,6 +110,10 @@ DEF_HELPER_FLAGS_2(flush_page, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(hlt, TCG_CALL_NO_WG, noreturn, env, int) DEF_HELPER_FLAGS_2(monitor, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_FLAGS_2(mwait, TCG_CALL_NO_WG, noreturn, env, int) +DEF_HELPER_1(rdmsr, void, env) +DEF_HELPER_1(wrmsr, void, env) +DEF_HELPER_FLAGS_2(read_crN, TCG_CALL_NO_RWG, tl, env, int) +DEF_HELPER_FLAGS_3(write_crN, TCG_CALL_NO_RWG, void, env, int, tl) #endif /* !CONFIG_USER_ONLY */ /* x86 FPU */ diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 9d2171aa3a..2493d39f0b 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -198,6 +198,8 @@ STUB_HELPER(flush_page, TCGv_env env, TCGv addr) STUB_HELPER(hlt, TCGv_env env, TCGv_i32 pc_ofs) STUB_HELPER(monitor, TCGv_env env, TCGv addr) STUB_HELPER(mwait, TCGv_env env, TCGv_i32 pc_ofs) +STUB_HELPER(rdmsr, TCGv_env env) +STUB_HELPER(read_crN, TCGv ret, TCGv_env env, TCGv_i32 reg) STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) STUB_HELPER(stgi, TCGv_env env) STUB_HELPER(svm_check_intercept, TCGv_env env, TCGv_i32 type) @@ -206,6 +208,8 @@ STUB_HELPER(vmload, TCGv_env env, TCGv_i32 aflag) STUB_HELPER(vmmcall, TCGv_env env) STUB_HELPER(vmrun, TCGv_env env, TCGv_i32 aflag, TCGv_i32 pc_ofs) STUB_HELPER(vmsave, TCGv_env env, TCGv_i32 aflag) +STUB_HELPER(write_crN, TCGv_env env, TCGv_i32 reg, TCGv val) +STUB_HELPER(wrmsr, TCGv_env env) #endif static void gen_eob(DisasContext *s); diff --git a/target/i386/tcg/user/misc_stubs.c b/target/i386/tcg/user/misc_stubs.c index 84df4e65ff..df38b44d6e 100644 --- a/target/i386/tcg/user/misc_stubs.c +++ b/target/i386/tcg/user/misc_stubs.c @@ -53,23 +53,3 @@ target_ulong helper_inl(CPUX86State *env, uint32_t port) g_assert_not_reached(); return 0; } - -target_ulong helper_read_crN(CPUX86State *env, int reg) -{ - g_assert_not_reached(); -} - -void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) -{ - g_assert_not_reached(); -} - -void helper_wrmsr(CPUX86State *env) -{ - g_assert_not_reached(); -} - -void helper_rdmsr(CPUX86State *env) -{ - g_assert_not_reached(); -} From patchwork Sun Feb 28 23:23:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445393 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id b10sm14164049pgm.76.2021.02.28.15.24.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:24:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 45/50] target/i386: Exit tb after wrmsr Date: Sun, 28 Feb 2021 15:23:16 -0800 Message-Id: <20210228232321.322053-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" At minimum, wrmsr can change efer, which affects HF_LMA. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 2493d39f0b..dc31d8667f 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -7254,6 +7254,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_helper_rdmsr(cpu_env); } else { gen_helper_wrmsr(cpu_env); + gen_jmp_im(s, s->pc - s->cs_base); + gen_eob(s); } } break; From patchwork Sun Feb 28 23:23:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445366 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=VcE8XUVq; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dpg501k6bz9sS8 for ; Mon, 1 Mar 2021 10:45:56 +1100 (AEDT) Received: from localhost ([::1]:56626 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lGVl4-00057R-3w for incoming@patchwork.ozlabs.org; Sun, 28 Feb 2021 18:45:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44066) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lGVQP-0006gv-6P for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:33 -0500 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:41128) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lGVQN-00083t-7Q for qemu-devel@nongnu.org; Sun, 28 Feb 2021 18:24:32 -0500 Received: by mail-pf1-x42c.google.com with SMTP id q20so10260753pfu.8 for ; Sun, 28 Feb 2021 15:24:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8AxLxL20h1MLfwKywJHFZQ2Ei3N+Q0xu9o2GbD1OO+c=; b=VcE8XUVqFoyj/SlnJg8BpfSepscrQDSWNAyA2DjZTKlmg2Sa7X2Q1h69BJCSJn5SGe G2Pq5oTM5a9aF2B/chmJr8PGH4bo8Z8e4elbDu+W3b8tOjlnh3KkdH2rWBC1gW6kMDNx 6TdK/CTOZTy+bUyyPvFH969EE4E3MrQ64QXymNGXxWg3q9TZ/GDTyIBdrdQWPvYATZ0n BG2WXbWLbmzqGE5lYsFAdBtZg9dEQzrzZcw4iEPAqSL0p+iWXXD/UI4RLZ8mJnJWl3ab GYHPanTT8ic5p9KAD3DNMrKqRu0q5cWwKkhw4AgUHFq3UmM0fxIwX5KwhP2DLNjIUdE1 HHgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8AxLxL20h1MLfwKywJHFZQ2Ei3N+Q0xu9o2GbD1OO+c=; b=K5fMnmqW/lEeFQdlh6Ke9f1GRs3i7h4BnbUC97gxzEZ50kRkeSH9ffp2c6ywBb8AP+ Pt0GyeIkkUhROCLNNm3byLHS9fSzyD9mmA8aPWsfjBnVn3wSqeSvTFCct4o+INO2q/Wp fj5yZu7H0BEhJ+OkeUiexzzuHyPw5YGM9pGvw6p6fAVzFAkKD3wq6wL/7wIUwksAOaKI jGmcrN3R9Mez0hSl+kxb9dZdK2Jl1N9hNwmaCkOs9zb70OWPgsQQR+MxmIdtQT/cOmcn byLSm4/U2w8s5rtNbY5cWjJaZ7ULlh48UwAmCJYlqMGgIBcAegyAai/6fa5CfktUrDNu 0CQw== X-Gm-Message-State: AOAM532BCG2WNRm+oqZBzUI8moqI4EevujvK/UUwnIURZNFZ6sdJWP0+ ZrCzKkA2PZQw4p9QNzDDhjwSstr6pFyJTA== X-Google-Smtp-Source: ABdhPJyDBtn2t1rsh0iA15zTYZ2+pGczm0RGL2jTn+zwPzkXQylZQJMZO/XaLOVfk5E0qhyHWQUuBQ== X-Received: by 2002:a63:4e44:: with SMTP id o4mr11480066pgl.46.1614554669887; Sun, 28 Feb 2021 15:24:29 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id b10sm14164049pgm.76.2021.02.28.15.24.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:24:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 46/50] target/i386: Tidy gen_check_io Date: Sun, 28 Feb 2021 15:23:17 -0800 Message-Id: <20210228232321.322053-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Get cur_eip from DisasContext. Do not require the caller to use svm_is_rep; get prefix from DisasContext. Use the proper symbolic constants for SVM_IOIO_*. While we're touching all call sites, return bool in preparation for gen_check_io raising #GP. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 57 +++++++++++++++++++------------------ 1 file changed, 30 insertions(+), 27 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index dc31d8667f..83bcf5cccc 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -674,13 +674,10 @@ static void gen_helper_out_func(MemOp ot, TCGv_i32 v, TCGv_i32 n) } } -static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip, - uint32_t svm_flags) +static bool gen_check_io(DisasContext *s, MemOp ot, uint32_t svm_flags) { - target_ulong next_eip; - + tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); if (PE(s) && (CPL(s) > IOPL(s) || VM86(s))) { - tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); switch (ot) { case MO_8: gen_helper_check_iob(cpu_env, s->tmp2_i32); @@ -696,15 +693,20 @@ static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip, } } if (GUEST(s)) { + target_ulong cur_eip = s->base.pc_next - s->cs_base; + target_ulong next_eip = s->pc - s->cs_base; + gen_update_cc_op(s); gen_jmp_im(s, cur_eip); - svm_flags |= (1 << (4 + ot)); - next_eip = s->pc - s->cs_base; - tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); + if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { + svm_flags |= SVM_IOIO_REP_MASK; + } + svm_flags |= 1 << (SVM_IOIO_SIZE_SHIFT + ot); gen_helper_svm_check_io(cpu_env, s->tmp2_i32, - tcg_const_i32(svm_flags), - tcg_const_i32(next_eip - cur_eip)); + tcg_constant_i32(svm_flags), + tcg_constant_i32(next_eip - cur_eip)); } + return true; } static inline void gen_movs(DisasContext *s, MemOp ot) @@ -2425,11 +2427,6 @@ static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg) } } -static inline int svm_is_rep(int prefixes) -{ - return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); -} - static void gen_svm_check_intercept(DisasContext *s, uint32_t type) { /* no SVM activated; fast case */ @@ -6477,8 +6474,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x6d: ot = mo_b_d32(b, dflag); tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]); - gen_check_io(s, ot, pc_start - s->cs_base, - SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4); + if (!gen_check_io(s, ot, SVM_IOIO_TYPE_MASK | SVM_IOIO_STR_MASK)) { + break; + } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } @@ -6496,8 +6494,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x6f: ot = mo_b_d32(b, dflag); tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]); - gen_check_io(s, ot, pc_start - s->cs_base, - svm_is_rep(prefixes) | 4); + if (!gen_check_io(s, ot, SVM_IOIO_STR_MASK)) { + break; + } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } @@ -6520,8 +6519,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) ot = mo_b_d32(b, dflag); val = x86_ldub_code(env, s); tcg_gen_movi_tl(s->T0, val); - gen_check_io(s, ot, pc_start - s->cs_base, - SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); + if (!gen_check_io(s, ot, SVM_IOIO_TYPE_MASK)) { + break; + } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } @@ -6538,8 +6538,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) ot = mo_b_d32(b, dflag); val = x86_ldub_code(env, s); tcg_gen_movi_tl(s->T0, val); - gen_check_io(s, ot, pc_start - s->cs_base, - svm_is_rep(prefixes)); + if (!gen_check_io(s, ot, 0)) { + break; + } gen_op_mov_v_reg(s, ot, s->T1, R_EAX); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { @@ -6557,8 +6558,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xed: ot = mo_b_d32(b, dflag); tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]); - gen_check_io(s, ot, pc_start - s->cs_base, - SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); + if (!gen_check_io(s, ot, SVM_IOIO_TYPE_MASK)) { + break; + } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } @@ -6574,8 +6576,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xef: ot = mo_b_d32(b, dflag); tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]); - gen_check_io(s, ot, pc_start - s->cs_base, - svm_is_rep(prefixes)); + if (!gen_check_io(s, ot, 0)) { + break; + } gen_op_mov_v_reg(s, ot, s->T1, R_EAX); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { From patchwork Sun Feb 28 23:23:18 2021 Content-Type: text/plain; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id b10sm14164049pgm.76.2021.02.28.15.24.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:24:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 47/50] target/i386: Pass in port to gen_check_io Date: Sun, 28 Feb 2021 15:23:18 -0800 Message-Id: <20210228232321.322053-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Pass in a pre-truncated TCGv_i32 value. We were doing the truncation of EDX in multiple places, now only once per insn. While all callers use s->tmp2_i32, for cleanliness of the subroutine, use a parameter anyway. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 55 +++++++++++++++++++------------------ 1 file changed, 29 insertions(+), 26 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 83bcf5cccc..0937c136ff 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -674,19 +674,23 @@ static void gen_helper_out_func(MemOp ot, TCGv_i32 v, TCGv_i32 n) } } -static bool gen_check_io(DisasContext *s, MemOp ot, uint32_t svm_flags) +/* + * Validate that access to [port, port + 1<tmp2_i32, s->T0); if (PE(s) && (CPL(s) > IOPL(s) || VM86(s))) { switch (ot) { case MO_8: - gen_helper_check_iob(cpu_env, s->tmp2_i32); + gen_helper_check_iob(cpu_env, port); break; case MO_16: - gen_helper_check_iow(cpu_env, s->tmp2_i32); + gen_helper_check_iow(cpu_env, port); break; case MO_32: - gen_helper_check_iol(cpu_env, s->tmp2_i32); + gen_helper_check_iol(cpu_env, port); break; default: tcg_abort(); @@ -702,7 +706,7 @@ static bool gen_check_io(DisasContext *s, MemOp ot, uint32_t svm_flags) svm_flags |= SVM_IOIO_REP_MASK; } svm_flags |= 1 << (SVM_IOIO_SIZE_SHIFT + ot); - gen_helper_svm_check_io(cpu_env, s->tmp2_i32, + gen_helper_svm_check_io(cpu_env, port, tcg_constant_i32(svm_flags), tcg_constant_i32(next_eip - cur_eip)); } @@ -6473,8 +6477,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x6c: /* insS */ case 0x6d: ot = mo_b_d32(b, dflag); - tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]); - if (!gen_check_io(s, ot, SVM_IOIO_TYPE_MASK | SVM_IOIO_STR_MASK)) { + tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]); + tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32); + if (!gen_check_io(s, ot, s->tmp2_i32, + SVM_IOIO_TYPE_MASK | SVM_IOIO_STR_MASK)) { break; } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { @@ -6493,8 +6499,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x6e: /* outsS */ case 0x6f: ot = mo_b_d32(b, dflag); - tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]); - if (!gen_check_io(s, ot, SVM_IOIO_STR_MASK)) { + tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]); + tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32); + if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_STR_MASK)) { break; } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { @@ -6518,14 +6525,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xe5: ot = mo_b_d32(b, dflag); val = x86_ldub_code(env, s); - tcg_gen_movi_tl(s->T0, val); - if (!gen_check_io(s, ot, SVM_IOIO_TYPE_MASK)) { + tcg_gen_movi_i32(s->tmp2_i32, val); + if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_TYPE_MASK)) { break; } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - tcg_gen_movi_i32(s->tmp2_i32, val); gen_helper_in_func(ot, s->T1, s->tmp2_i32); gen_op_mov_reg_v(s, ot, R_EAX, s->T1); gen_bpt_io(s, s->tmp2_i32, ot); @@ -6537,16 +6543,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xe7: ot = mo_b_d32(b, dflag); val = x86_ldub_code(env, s); - tcg_gen_movi_tl(s->T0, val); - if (!gen_check_io(s, ot, 0)) { + tcg_gen_movi_i32(s->tmp2_i32, val); + if (!gen_check_io(s, ot, s->tmp2_i32, 0)) { break; } - gen_op_mov_v_reg(s, ot, s->T1, R_EAX); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - tcg_gen_movi_i32(s->tmp2_i32, val); + gen_op_mov_v_reg(s, ot, s->T1, R_EAX); tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32); gen_bpt_io(s, s->tmp2_i32, ot); @@ -6557,14 +6561,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xec: case 0xed: ot = mo_b_d32(b, dflag); - tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]); - if (!gen_check_io(s, ot, SVM_IOIO_TYPE_MASK)) { + tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]); + tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32); + if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_TYPE_MASK)) { break; } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_in_func(ot, s->T1, s->tmp2_i32); gen_op_mov_reg_v(s, ot, R_EAX, s->T1); gen_bpt_io(s, s->tmp2_i32, ot); @@ -6575,16 +6579,15 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xee: case 0xef: ot = mo_b_d32(b, dflag); - tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]); - if (!gen_check_io(s, ot, 0)) { + tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]); + tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32); + if (!gen_check_io(s, ot, s->tmp2_i32, 0)) { break; } - gen_op_mov_v_reg(s, ot, s->T1, R_EAX); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); + gen_op_mov_v_reg(s, ot, s->T1, R_EAX); tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32); gen_bpt_io(s, s->tmp2_i32, ot); From patchwork Sun Feb 28 23:23:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445378 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id b10sm14164049pgm.76.2021.02.28.15.24.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:24:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 48/50] target/i386: Create helper_check_io Date: Sun, 28 Feb 2021 15:23:19 -0800 Message-Id: <20210228232321.322053-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Drop helper_check_io[bwl] and expose their common subroutine to tcg directly. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/i386/helper.h | 4 +--- target/i386/tcg/seg_helper.c | 21 +++------------------ target/i386/tcg/translate.c | 14 +------------- 3 files changed, 5 insertions(+), 34 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index 1d85f033df..47d0d67699 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -86,9 +86,7 @@ DEF_HELPER_1(rdtsc, void, env) DEF_HELPER_1(rdtscp, void, env) DEF_HELPER_FLAGS_1(rdpmc, TCG_CALL_NO_WG, noreturn, env) -DEF_HELPER_2(check_iob, void, env, i32) -DEF_HELPER_2(check_iow, void, env, i32) -DEF_HELPER_2(check_iol, void, env, i32) +DEF_HELPER_FLAGS_3(check_io, TCG_CALL_NO_WG, void, env, i32, i32) DEF_HELPER_3(outb, void, env, i32, i32) DEF_HELPER_2(inb, tl, env, i32) DEF_HELPER_3(outw, void, env, i32, i32) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index cf3f051524..69d6e8f602 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -2418,10 +2418,10 @@ void helper_verw(CPUX86State *env, target_ulong selector1) } /* check if Port I/O is allowed in TSS */ -static inline void check_io(CPUX86State *env, int addr, int size, - uintptr_t retaddr) +void helper_check_io(CPUX86State *env, uint32_t addr, uint32_t size) { - int io_offset, val, mask; + uintptr_t retaddr = GETPC(); + uint32_t io_offset, val, mask; /* TSS must be a valid 32 bit one */ if (!(env->tr.flags & DESC_P_MASK) || @@ -2444,18 +2444,3 @@ static inline void check_io(CPUX86State *env, int addr, int size, raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr); } } - -void helper_check_iob(CPUX86State *env, uint32_t t0) -{ - check_io(env, t0, 1, GETPC()); -} - -void helper_check_iow(CPUX86State *env, uint32_t t0) -{ - check_io(env, t0, 2, GETPC()); -} - -void helper_check_iol(CPUX86State *env, uint32_t t0) -{ - check_io(env, t0, 4, GETPC()); -} diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 0937c136ff..d395ae090e 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -682,19 +682,7 @@ static bool gen_check_io(DisasContext *s, MemOp ot, TCGv_i32 port, uint32_t svm_flags) { if (PE(s) && (CPL(s) > IOPL(s) || VM86(s))) { - switch (ot) { - case MO_8: - gen_helper_check_iob(cpu_env, port); - break; - case MO_16: - gen_helper_check_iow(cpu_env, port); - break; - case MO_32: - gen_helper_check_iol(cpu_env, port); - break; - default: - tcg_abort(); - } + gen_helper_check_io(cpu_env, port, tcg_constant_i32(1 << ot)); } if (GUEST(s)) { target_ulong cur_eip = s->base.pc_next - s->cs_base; From patchwork Sun Feb 28 23:23:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445394 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=memxSsDP; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DpgnF6602z9sR4 for ; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id b10sm14164049pgm.76.2021.02.28.15.24.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:24:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 49/50] target/i386: Move helper_check_io to sysemu Date: Sun, 28 Feb 2021 15:23:20 -0800 Message-Id: <20210228232321.322053-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The we never allow i/o from user-only, and the tss check that helper_check_io does will always fail. Use an ifdef within gen_check_io and return false, indicating that an exception is known to be raised. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/i386/helper.h | 2 +- target/i386/tcg/seg_helper.c | 28 ---------------------------- target/i386/tcg/sysemu/seg_helper.c | 29 +++++++++++++++++++++++++++++ target/i386/tcg/translate.c | 11 +++++++++++ 4 files changed, 41 insertions(+), 29 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index 47d0d67699..3fd0253298 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -86,7 +86,6 @@ DEF_HELPER_1(rdtsc, void, env) DEF_HELPER_1(rdtscp, void, env) DEF_HELPER_FLAGS_1(rdpmc, TCG_CALL_NO_WG, noreturn, env) -DEF_HELPER_FLAGS_3(check_io, TCG_CALL_NO_WG, void, env, i32, i32) DEF_HELPER_3(outb, void, env, i32, i32) DEF_HELPER_2(inb, tl, env, i32) DEF_HELPER_3(outw, void, env, i32, i32) @@ -95,6 +94,7 @@ DEF_HELPER_3(outl, void, env, i32, i32) DEF_HELPER_2(inl, tl, env, i32) #ifndef CONFIG_USER_ONLY +DEF_HELPER_FLAGS_3(check_io, TCG_CALL_NO_WG, void, env, i32, i32) DEF_HELPER_FLAGS_4(bpt_io, TCG_CALL_NO_WG, void, env, i32, i32, tl) DEF_HELPER_2(svm_check_intercept, void, env, i32) DEF_HELPER_4(svm_check_io, void, env, i32, i32, i32) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 69d6e8f602..2f6cdc8239 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -2416,31 +2416,3 @@ void helper_verw(CPUX86State *env, target_ulong selector1) } CC_SRC = eflags | CC_Z; } - -/* check if Port I/O is allowed in TSS */ -void helper_check_io(CPUX86State *env, uint32_t addr, uint32_t size) -{ - uintptr_t retaddr = GETPC(); - uint32_t io_offset, val, mask; - - /* TSS must be a valid 32 bit one */ - if (!(env->tr.flags & DESC_P_MASK) || - ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 || - env->tr.limit < 103) { - goto fail; - } - io_offset = cpu_lduw_kernel_ra(env, env->tr.base + 0x66, retaddr); - io_offset += (addr >> 3); - /* Note: the check needs two bytes */ - if ((io_offset + 1) > env->tr.limit) { - goto fail; - } - val = cpu_lduw_kernel_ra(env, env->tr.base + io_offset, retaddr); - val >>= (addr & 7); - mask = (1 << size) - 1; - /* all bits must be zero to allow the I/O */ - if ((val & mask) != 0) { - fail: - raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr); - } -} diff --git a/target/i386/tcg/sysemu/seg_helper.c b/target/i386/tcg/sysemu/seg_helper.c index 10076d1341..b2e3ba8195 100644 --- a/target/i386/tcg/sysemu/seg_helper.c +++ b/target/i386/tcg/sysemu/seg_helper.c @@ -23,6 +23,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "tcg/helper-tcg.h" +#include "../seg_helper.h" #ifdef TARGET_X86_64 void helper_syscall(CPUX86State *env, int next_eip_addend) @@ -123,3 +124,31 @@ void x86_cpu_do_interrupt(CPUState *cs) env->old_exception = -1; } } + +/* check if Port I/O is allowed in TSS */ +void helper_check_io(CPUX86State *env, uint32_t addr, uint32_t size) +{ + uintptr_t retaddr = GETPC(); + uint32_t io_offset, val, mask; + + /* TSS must be a valid 32 bit one */ + if (!(env->tr.flags & DESC_P_MASK) || + ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 || + env->tr.limit < 103) { + goto fail; + } + io_offset = cpu_lduw_kernel_ra(env, env->tr.base + 0x66, retaddr); + io_offset += (addr >> 3); + /* Note: the check needs two bytes */ + if ((io_offset + 1) > env->tr.limit) { + goto fail; + } + val = cpu_lduw_kernel_ra(env, env->tr.base + io_offset, retaddr); + val >>= (addr & 7); + mask = (1 << size) - 1; + /* all bits must be zero to allow the I/O */ + if ((val & mask) != 0) { + fail: + raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr); + } +} diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index d395ae090e..2276e75d92 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -193,6 +193,7 @@ typedef struct DisasContext { { qemu_build_not_reached(); } #ifdef CONFIG_USER_ONLY +STUB_HELPER(check_io, TCGv_env env, TCGv_i32 port, TCGv_i32 size) STUB_HELPER(clgi, TCGv_env env) STUB_HELPER(flush_page, TCGv_env env, TCGv addr) STUB_HELPER(hlt, TCGv_env env, TCGv_i32 pc_ofs) @@ -217,6 +218,7 @@ static void gen_jr(DisasContext *s, TCGv dest); static void gen_jmp(DisasContext *s, target_ulong eip); static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num); static void gen_op(DisasContext *s1, int op, MemOp ot, int d); +static void gen_exception_gpf(DisasContext *s); /* i386 arith/logic operations */ enum { @@ -681,6 +683,14 @@ static void gen_helper_out_func(MemOp ot, TCGv_i32 v, TCGv_i32 n) static bool gen_check_io(DisasContext *s, MemOp ot, TCGv_i32 port, uint32_t svm_flags) { +#ifdef CONFIG_USER_ONLY + /* + * We do not implement the iopriv(2) syscall, so the TSS check + * will always fail. + */ + gen_exception_gpf(s); + return false; +#else if (PE(s) && (CPL(s) > IOPL(s) || VM86(s))) { gen_helper_check_io(cpu_env, port, tcg_constant_i32(1 << ot)); } @@ -699,6 +709,7 @@ static bool gen_check_io(DisasContext *s, MemOp ot, TCGv_i32 port, tcg_constant_i32(next_eip - cur_eip)); } return true; +#endif } static inline void gen_movs(DisasContext *s, MemOp ot) From patchwork Sun Feb 28 23:23:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1445384 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=J6AplQNS; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DpgJB6sNTz9sRR for ; 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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id b10sm14164049pgm.76.2021.02.28.15.24.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:24:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 50/50] target/i386: Remove user-only i/o stubs Date: Sun, 28 Feb 2021 15:23:21 -0800 Message-Id: <20210228232321.322053-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" With the previous patch for check_io, we now have enough for the compiler to dead-code eliminate all of the i/o helpers. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/i386/helper.h | 3 +- target/i386/tcg/translate.c | 6 ++++ target/i386/tcg/user/misc_stubs.c | 55 ------------------------------- target/i386/tcg/user/meson.build | 1 - 4 files changed, 7 insertions(+), 58 deletions(-) delete mode 100644 target/i386/tcg/user/misc_stubs.c diff --git a/target/i386/helper.h b/target/i386/helper.h index 3fd0253298..f3d8c3f949 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -86,14 +86,13 @@ DEF_HELPER_1(rdtsc, void, env) DEF_HELPER_1(rdtscp, void, env) DEF_HELPER_FLAGS_1(rdpmc, TCG_CALL_NO_WG, noreturn, env) +#ifndef CONFIG_USER_ONLY DEF_HELPER_3(outb, void, env, i32, i32) DEF_HELPER_2(inb, tl, env, i32) DEF_HELPER_3(outw, void, env, i32, i32) DEF_HELPER_2(inw, tl, env, i32) DEF_HELPER_3(outl, void, env, i32, i32) DEF_HELPER_2(inl, tl, env, i32) - -#ifndef CONFIG_USER_ONLY DEF_HELPER_FLAGS_3(check_io, TCG_CALL_NO_WG, void, env, i32, i32) DEF_HELPER_FLAGS_4(bpt_io, TCG_CALL_NO_WG, void, env, i32, i32, tl) DEF_HELPER_2(svm_check_intercept, void, env, i32) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 2276e75d92..1d08e10f38 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -197,8 +197,14 @@ STUB_HELPER(check_io, TCGv_env env, TCGv_i32 port, TCGv_i32 size) STUB_HELPER(clgi, TCGv_env env) STUB_HELPER(flush_page, TCGv_env env, TCGv addr) STUB_HELPER(hlt, TCGv_env env, TCGv_i32 pc_ofs) +STUB_HELPER(inb, TCGv ret, TCGv_env env, TCGv_i32 port) +STUB_HELPER(inw, TCGv ret, TCGv_env env, TCGv_i32 port) +STUB_HELPER(inl, TCGv ret, TCGv_env env, TCGv_i32 port) STUB_HELPER(monitor, TCGv_env env, TCGv addr) STUB_HELPER(mwait, TCGv_env env, TCGv_i32 pc_ofs) +STUB_HELPER(outb, TCGv_env env, TCGv_i32 port, TCGv_i32 val) +STUB_HELPER(outw, TCGv_env env, TCGv_i32 port, TCGv_i32 val) +STUB_HELPER(outl, TCGv_env env, TCGv_i32 port, TCGv_i32 val) STUB_HELPER(rdmsr, TCGv_env env) STUB_HELPER(read_crN, TCGv ret, TCGv_env env, TCGv_i32 reg) STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) diff --git a/target/i386/tcg/user/misc_stubs.c b/target/i386/tcg/user/misc_stubs.c deleted file mode 100644 index df38b44d6e..0000000000 --- a/target/i386/tcg/user/misc_stubs.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * x86 misc helpers - * - * Copyright (c) 2003 Fabrice Bellard - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "exec/helper-proto.h" - -void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) -{ - g_assert_not_reached(); -} - -target_ulong helper_inb(CPUX86State *env, uint32_t port) -{ - g_assert_not_reached(); - return 0; -} - -void helper_outw(CPUX86State *env, uint32_t port, uint32_t data) -{ - g_assert_not_reached(); -} - -target_ulong helper_inw(CPUX86State *env, uint32_t port) -{ - g_assert_not_reached(); - return 0; -} - -void helper_outl(CPUX86State *env, uint32_t port, uint32_t data) -{ - g_assert_not_reached(); -} - -target_ulong helper_inl(CPUX86State *env, uint32_t port) -{ - g_assert_not_reached(); - return 0; -} diff --git a/target/i386/tcg/user/meson.build b/target/i386/tcg/user/meson.build index 16a0be1ae6..2b059d0baf 100644 --- a/target/i386/tcg/user/meson.build +++ b/target/i386/tcg/user/meson.build @@ -1,6 +1,5 @@ i386_user_ss.add(when: ['CONFIG_TCG', 'CONFIG_USER_ONLY'], if_true: files( 'excp_helper.c', - 'misc_stubs.c', 'fpu_helper.c', 'seg_helper.c', ))