From patchwork Tue Feb 23 10:35:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1443457 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=b7oDdDCB; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlFpK5RpKz9sW2 for ; Tue, 23 Feb 2021 21:36:19 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CD845829EA; Tue, 23 Feb 2021 11:36:04 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="b7oDdDCB"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8D431829F0; Tue, 23 Feb 2021 11:36:01 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qt1-x82b.google.com (mail-qt1-x82b.google.com [IPv6:2607:f8b0:4864:20::82b]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B62AF829E6 for ; Tue, 23 Feb 2021 11:35:57 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-qt1-x82b.google.com with SMTP id w6so4028774qti.6 for ; Tue, 23 Feb 2021 02:35:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=od1n5nB1ZybiDqSfKRHBH02QJ/6UCxpVnXF6wE7z6WM=; b=b7oDdDCB0Pqdi1crceYAAD+pGghzyDHAFim2D8uyjfoLsrr4dAo0q/SSUAFDo2T5RH 4g/xjqzrTHLeSD0kIvEX0d0TInNc65u6k4tmFADSD2jlBLNIvec/NH6SuE7HQfOVJ0YX 8bYLjFBGp6yMZv+Knw3EtkwO9LHo+9fUZvOF8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=od1n5nB1ZybiDqSfKRHBH02QJ/6UCxpVnXF6wE7z6WM=; b=fWqVhH2Ko0G5mBSMn0/Zoh/9M5dVRyoVs2dnfA9XdAL0u+40sDuY1ohOd/T8UkGpFT jEb6w4N+ZxcQH7rzcAWxX3kUYr/18rtlBqEQCI+S2SIQ01U15wABx1GSszsPTOLcfnmK xdockBxV3hwH7NiJI4meykfswTcqNdb1sdv5/zKH+7rhCE8I1O6/SoAgoQAAiPEQpxki Gk7Pi97J+1GYIVtnFKB+im62PxllD+ViWEhD8jCdi8MJ/E6ZuG1hkmue1dpKRexwl8Z0 QVlLiqc2JrNZVC7Y5NAh1la+eWSSulxZCIJab1ImSP2q2xEjxHMY4CR3/Ln8ho5YMJkt qD2w== X-Gm-Message-State: AOAM533xpBoDiL4OYeLe4+277zD9YmfTyVYhvW0xFBdVUDxGbVEFK2aN jumDPQy2HlEAC7DAatkaGwzJEU3pXd4BSv8+ X-Google-Smtp-Source: ABdhPJyBr0j9uxxCLgPA7fqBVbIZKc+L0Eqz99McYleG7zYqIfPAVpR+IKNhgkGaide3KwbDUvoXYw== X-Received: by 2002:aed:2ae6:: with SMTP id t93mr9204349qtd.360.1614076556204; Tue, 23 Feb 2021 02:35:56 -0800 (PST) Received: from sjg1.roam.corp.google.com ([70.127.249.40]) by smtp.gmail.com with ESMTPSA id f26sm14264099qkh.80.2021.02.23.02.35.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Feb 2021 02:35:55 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Bin Meng , Andy Shevchenko , Heinrich Schuchardt , Simon Glass , Wolfgang Wallner Subject: [PATCH 1/3] x86: Fix member check in intel_gnvs Date: Tue, 23 Feb 2021 05:35:40 -0500 Message-Id: <20210223103542.1386572-1-sjg@chromium.org> X-Mailer: git-send-email 2.30.0.617.g56c4b15f3c-goog MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean When CONFIG_CHROMEOS is not enabled this currently does not build. Fix it. Reported-by: Heinrich Schuchardt Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/include/asm/intel_gnvs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/include/asm/intel_gnvs.h b/arch/x86/include/asm/intel_gnvs.h index 69a20812e5e..fc743dc9285 100644 --- a/arch/x86/include/asm/intel_gnvs.h +++ b/arch/x86/include/asm/intel_gnvs.h @@ -107,6 +107,10 @@ struct __packed acpi_global_nvs { u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */ #endif }; +#ifdef CONFIG_CHROMEOS check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +#else +check_member(acpi_global_nvs, unused2, GNVS_CHROMEOS_ACPI_OFFSET); +#endif #endif /* _INTEL_GNVS_H_ */ From patchwork Tue Feb 23 10:35:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1443458 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 23 Feb 2021 02:35:57 -0800 (PST) Received: from sjg1.roam.corp.google.com ([70.127.249.40]) by smtp.gmail.com with ESMTPSA id f26sm14264099qkh.80.2021.02.23.02.35.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Feb 2021 02:35:56 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Bin Meng , Andy Shevchenko , Heinrich Schuchardt , Simon Glass Subject: [PATCH 2/3] x86: Move INTEL_ACPIGEN to arch/x86 Date: Tue, 23 Feb 2021 05:35:41 -0500 Message-Id: <20210223103542.1386572-2-sjg@chromium.org> X-Mailer: git-send-email 2.30.0.617.g56c4b15f3c-goog In-Reply-To: <20210223103542.1386572-1-sjg@chromium.org> References: <20210223103542.1386572-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This option is better placed in the x86 code since it is not generic enough to be in the core code. Move it. Reported-by: Heinrich Schuchardt Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/Kconfig | 9 +++++++++ drivers/core/Kconfig | 9 --------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index eddf2a774ef..c8ce2fcb88d 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1001,6 +1001,15 @@ config PCIEX_LENGTH_128MB config PCIEX_LENGTH_64MB bool +config INTEL_ACPIGEN + bool "Support ACPI table generation for Intel SoCs" + depends on ACPIGEN + help + This option adds some functions used for programatic generation of + ACPI tables on Intel SoCs. This provides features for writing CPU + information such as P states and T stages. Also included is a way + to create a GNVS table and set it up. + config INTEL_GMA_ACPI bool "Generate ACPI table for Intel GMA graphics" help diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 00554af4995..1eccac28c62 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -329,15 +329,6 @@ config ACPIGEN things like generating device-specific tables and returning the ACPI name of a device. -config INTEL_ACPIGEN - bool "Support ACPI table generation for Intel SoCs" - depends on ACPIGEN - help - This option adds some functions used for programatic generation of - ACPI tables on Intel SoCs. This provides features for writing CPU - information such as P states and T stages. Also included is a way - to create a GNVS table and set it up. - config BOUNCE_BUFFER bool "Include bounce buffer API" help From patchwork Tue Feb 23 10:35:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1443459 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=K/S0M9Z7; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlFpW0BMYz9s1l for ; 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Tue, 23 Feb 2021 02:35:58 -0800 (PST) Received: from sjg1.roam.corp.google.com ([70.127.249.40]) by smtp.gmail.com with ESMTPSA id f26sm14264099qkh.80.2021.02.23.02.35.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Feb 2021 02:35:57 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Bin Meng , Andy Shevchenko , Heinrich Schuchardt , Simon Glass , Wolfgang Wallner Subject: [PATCH 3/3] x86: Select advanced Intel code only if allowed Date: Tue, 23 Feb 2021 05:35:42 -0500 Message-Id: <20210223103542.1386572-3-sjg@chromium.org> X-Mailer: git-send-email 2.30.0.617.g56c4b15f3c-goog In-Reply-To: <20210223103542.1386572-1-sjg@chromium.org> References: <20210223103542.1386572-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean At present most of the Intel-specific code is built on all devices, even those which don't have software support for the features provided there. This means that any board can enable CONFIG_INTEL_ACPIGEN even if it does not have the required features. Add a new INTEL_SOC option to control this access. This must be selected by SoCs that can support the required features. Reported-by: Heinrich Schuchardt Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/Kconfig | 15 +++++++++++++++ arch/x86/cpu/apollolake/Kconfig | 1 + 2 files changed, 16 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c8ce2fcb88d..b4a86f8fa05 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1001,6 +1001,19 @@ config PCIEX_LENGTH_128MB config PCIEX_LENGTH_64MB bool +config INTEL_SOC + bool + help + This is enabled on Intel SoCs that can support various advanced + features such as power management (requiring asm/arch/pm.h), system + agent (asm/arch/systemagent.h) and an I/O map for ACPI + (asm/arch/iomap.h). + + This cannot be seleted in a defconfig file. It must be enabled by a + 'select' in the SoC's Kconfig. + +if INTEL_SOC + config INTEL_ACPIGEN bool "Support ACPI table generation for Intel SoCs" depends on ACPIGEN @@ -1032,4 +1045,6 @@ config INTEL_GMA_SWSMISCI Select this option for Atom-based platforms which use the SWSMISCI register (0xe0) rather than the SWSCI register (0xe8). +endif # INTEL_SOC + endmenu diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig index f5dbd6cbd34..590fe31dc4b 100644 --- a/arch/x86/cpu/apollolake/Kconfig +++ b/arch/x86/cpu/apollolake/Kconfig @@ -9,6 +9,7 @@ config INTEL_APOLLOLAKE select HAVE_FSP select ARCH_MISC_INIT select USE_CAR + select INTEL_SOC select INTEL_PMC select TPL_X86_TSC_TIMER_NATIVE select SPL_PCH_SUPPORT