From patchwork Fri Jan 12 15:30:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philippe CORNU X-Patchwork-Id: 860005 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zJ6Dl3PGHz9t3p for ; Sat, 13 Jan 2018 02:32:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933992AbeALPcF (ORCPT ); Fri, 12 Jan 2018 10:32:05 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:7554 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933947AbeALPcE (ORCPT ); Fri, 12 Jan 2018 10:32:04 -0500 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w0CFTbaG009259; Fri, 12 Jan 2018 16:31:10 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2febc4x17t-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 12 Jan 2018 16:31:10 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4C2A13A; Fri, 12 Jan 2018 15:31:09 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 068FA2807; Fri, 12 Jan 2018 15:31:09 +0000 (GMT) Received: from SAFEX1HUBCAS24.st.com (10.75.90.95) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.352.0; Fri, 12 Jan 2018 16:31:08 +0100 Received: from localhost (10.201.23.32) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.352.0; Fri, 12 Jan 2018 16:31:08 +0100 From: Philippe Cornu To: Rob Herring , Arnd Bergmann , "Russell King" , Mark Rutland , "Archit Taneja" , Andrzej Hajda , "Laurent Pinchart" , David Airlie , Philippe Cornu , Philipp Zabel , Benjamin Gaignard , Bhumika Goyal , , , , CC: Yannick Fertre , Vincent Abriou , Alexandre Torgue , "Maxime Coquelin" , Gabriel Fernandez , Ludovic Barre , "Fabien Dessenne" , Mickael Reulier Subject: [PATCH v2] dt-bindings: display: stm32: add pixel clock mandatory property Date: Fri, 12 Jan 2018 16:30:34 +0100 Message-ID: <20180112153034.20353-1-philippe.cornu@st.com> X-Mailer: git-send-email 2.15.1 MIME-Version: 1.0 X-Originating-IP: [10.201.23.32] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-12_08:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the DPI/RGB input pixel clock in mandatory properties because it really offers a better preciseness for timing computations. Note: Fix also the DSI panel example where "ref" & "pclk" clocks were swapped. Signed-off-by: Philippe Cornu --- Changes in v2: put new clock in last position (Rob Herring) Documentation/devicetree/bindings/display/st,stm32-ltdc.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt index 029252253ad4..942b7237ae87 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt @@ -29,6 +29,7 @@ Mandatory properties specific to STM32 DSI: - compatible: "st,stm32-dsi". - clock-names: - phy pll reference clock string name, must be "ref". + - DPI/RGB input pixel clock string name, must be "px_clk". - resets: see [5]. - reset-names: see [5]. @@ -97,8 +98,9 @@ Example 2: DSI panel #size-cells = <0>; compatible = "st,stm32-dsi"; reg = <0x40016c00 0x800>; - clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; - clock-names = "ref", "pclk"; + clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>, + <&rcc 1 CLK_LCD>; + clock-names = "pclk", "ref", "px_clk"; resets = <&rcc STM32F4_APB2_RESET(DSI)>; reset-names = "apb";