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Fri, 12 Feb 2021 20:50:13 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 207F2BE056; Fri, 12 Feb 2021 20:50:13 +0000 (GMT) Received: from [9.160.72.247] (unknown [9.160.72.247]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP; Fri, 12 Feb 2021 20:50:12 +0000 (GMT) To: Segher Boessenkool Subject: rs6000: Fix invalid splits when using Altivec style addresses [PR98959] Message-ID: <8f29db7d-e282-4e25-ffed-98ba91b4db7b@linux.ibm.com> Date: Fri, 12 Feb 2021 14:50:12 -0600 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 MIME-Version: 1.0 Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.737 definitions=2021-02-12_09:2021-02-12, 2021-02-12 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 impostorscore=0 clxscore=1015 phishscore=0 adultscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2102120152 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Peter Bergner via Gcc-patches From: Peter Bergner Reply-To: Peter Bergner Cc: Bill Schmidt , GCC Patches Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" The rs6000_emit_le_vsx_* functions assume they are not passed an Altivec style "& ~16" address. However, some of our expanders and splitters do not verify we do not have an Altivec style address before calling those functions, leading to an ICE. The solution here is to guard the expanders and splitters to ensure we do not call them if we're given an Altivec style address. This fixes the ICE. Ok for mainline if my powerpc64le-linux regtesting comes back clean? We'll want backports once this has time to bake on mainline for a while. Ok there too assuming my regtests there are clean? Peter 2021-02-12 Peter Bergner gcc/ PR target/98959 * config/rs6000/rs6000.c (rs6000_emit_le_vsx_permute): Add an assert to ensure we do not have an Altivec style address. * config/rs6000/vsx.md (*vsx_le_perm_load_): Disable if passed an Altivec style address. (*vsx_le_perm_store_): Likewise. (splitters after *vsx_le_perm_store_): Likewise. (vsx_load_): Disable special expander if passed an Altivec style address. (vsx_store_): Likewise. gcc/testsuite/ PR target/98959 * gcc.target/powerpc/pr98959.c: New test. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index ec068c58aa5..e147cbdb52f 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -10059,6 +10059,11 @@ rs6000_const_vec (machine_mode mode) void rs6000_emit_le_vsx_permute (rtx dest, rtx source, machine_mode mode) { + if (MEM_P (dest)) + gcc_assert (!altivec_indexed_or_indirect_operand (dest, mode)); + if (MEM_P (source)) + gcc_assert (!altivec_indexed_or_indirect_operand (source, mode)); + /* Scalar permutations are easier to express in integer modes rather than floating-point modes, so cast them here. We use V1TImode instead of TImode to ensure that the values don't go through GPRs. */ diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 3e0518631df..f6fe88d3600 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -987,11 +987,13 @@ (define_insn_and_split "*vsx_le_undo_permute_" (define_insn_and_split "*vsx_le_perm_load_" [(set (match_operand:VSX_LE_128 0 "vsx_register_operand" "=wa,r") (match_operand:VSX_LE_128 1 "memory_operand" "Z,Q"))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR + && !altivec_indexed_or_indirect_operand (operands[1], mode)" "@ # #" - "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR + && !altivec_indexed_or_indirect_operand (operands[1], mode)" [(const_int 0)] { rtx tmp = (can_create_pseudo_p () @@ -1008,7 +1010,8 @@ (define_insn_and_split "*vsx_le_perm_load_" (define_insn "*vsx_le_perm_store_" [(set (match_operand:VSX_LE_128 0 "memory_operand" "=Z,Q") (match_operand:VSX_LE_128 1 "vsx_register_operand" "+wa,r"))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR + & !altivec_indexed_or_indirect_operand (operands[0], mode)" "@ # #" @@ -1019,7 +1022,8 @@ (define_insn "*vsx_le_perm_store_" (define_split [(set (match_operand:VSX_LE_128 0 "memory_operand") (match_operand:VSX_LE_128 1 "vsx_register_operand"))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed && !TARGET_P9_VECTOR" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed && !TARGET_P9_VECTOR + && !altivec_indexed_or_indirect_operand (operands[0], mode)" [(const_int 0)] { rtx tmp = (can_create_pseudo_p () @@ -1075,7 +1079,8 @@ (define_peephole2 (define_split [(set (match_operand:VSX_LE_128 0 "memory_operand") (match_operand:VSX_LE_128 1 "vsx_register_operand"))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed && !TARGET_P9_VECTOR" + "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed && !TARGET_P9_VECTOR + && !altivec_indexed_or_indirect_operand (operands[0], mode)" [(const_int 0)] { rs6000_emit_le_vsx_permute (operands[1], operands[1], mode); @@ -1241,7 +1246,8 @@ (define_expand "vsx_load_" "VECTOR_MEM_VSX_P (mode)" { /* Expand to swaps if needed, prior to swap optimization. */ - if (!BYTES_BIG_ENDIAN && !TARGET_P9_VECTOR) + if (!BYTES_BIG_ENDIAN && !TARGET_P9_VECTOR + && !altivec_indexed_or_indirect_operand(operands[1], mode)) { rs6000_emit_le_vsx_move (operands[0], operands[1], mode); DONE; @@ -1254,7 +1260,8 @@ (define_expand "vsx_store_" "VECTOR_MEM_VSX_P (mode)" { /* Expand to swaps if needed, prior to swap optimization. */ - if (!BYTES_BIG_ENDIAN && !TARGET_P9_VECTOR) + if (!BYTES_BIG_ENDIAN && !TARGET_P9_VECTOR + && !altivec_indexed_or_indirect_operand(operands[0], mode)) { rs6000_emit_le_vsx_move (operands[0], operands[1], mode); DONE; diff --git a/gcc/testsuite/gcc.target/powerpc/pr98959.c b/gcc/testsuite/gcc.target/powerpc/pr98959.c new file mode 100644 index 00000000000..9e8523db7b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr98959.c @@ -0,0 +1,17 @@ +/* PR target/98959 */ +/* { dg-options "-fno-schedule-insns -O2 -mcmodel=small" } */ + +/* Verify we do not ICE on the following. */ + +typedef __attribute__ ((altivec (vector__))) unsigned __int128 v1ti_t; + +v1ti_t foo (v1ti_t v); + +void +bug () +{ + v1ti_t dv = { ((31415926539) << 6) }; + dv = foo (dv); + if (dv[0] != 0) + __builtin_abort (); +}