From patchwork Wed Feb 3 07:01:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 1435145 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=dGRtKb0i; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DVt4P6R7bz9tlN for ; Wed, 3 Feb 2021 18:05:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231843AbhBCHF0 (ORCPT ); Wed, 3 Feb 2021 02:05:26 -0500 Received: from mail.kernel.org ([198.145.29.99]:35530 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232020AbhBCHD1 (ORCPT ); Wed, 3 Feb 2021 02:03:27 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 9144864F74; Wed, 3 Feb 2021 07:02:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612335721; bh=nJFVkFVcxLt04mnBQIBfm4IXRi2ERW4Q1DqINzouepk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dGRtKb0i4HMj94TBtnNezfk1bY7Db4Y2IOYOT1gq0o8AmV9/BTWPtOJQq0wr+ijGk NR+UKz9zNtGRNQznPZ/3atj0aYsTZPUw6DqQ5Hd9+adHZUNvrEX4CLFAk3zbEeorOy IDjMlorc8V8mE07/D3zCiEjxx/pjRUOnAVHqrkWVjIlKwAYykJOdV35Ko+pkg7e9/0 oJAWf6Yyci4LNgOmdTInEQEc6pADOmAiFAnQjZ70bDGKumNmruzHgAEqZCUa0OT8Jr VGP/5g6kOVfQCE/7FKSUgMjLyp7+gyb5Xgp9nHZX1LztmYx2M8QX44wrVO45kOPi8M 3KwOje6tgrxTA== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l7CAn-001CAQ-WF; Wed, 03 Feb 2021 08:01:58 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Fabio Estevam , Gustavo Pimentel , Jaehoon Chung , Jerome Brunet , Jesper Nilsson , Jingoo Han , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kunihiko Hayashi , Lucas Stach , Marek Szyprowski , Martin Blumenstingl , NXP Linux Team , Neil Armstrong , Pengutronix Kernel Team , Richard Zhu , Rob Herring , Sascha Hauer , Shawn Guo , Thierry Reding , Thomas Petazzoni , Zhou Wang , devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 01/11] doc: bindings: PCI: designware-pcie.txt: convert it to YAML Date: Wed, 3 Feb 2021 08:01:45 +0100 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the file into a DT schema. Signed-off-by: Mauro Carvalho Chehab --- .../bindings/pci/amlogic,meson-pcie.txt | 4 +- .../bindings/pci/axis,artpec6-pcie.txt | 2 +- .../bindings/pci/designware-pcie.txt | 77 ---------- .../bindings/pci/fsl,imx6q-pcie.txt | 2 +- .../bindings/pci/hisilicon-histb-pcie.txt | 2 +- .../bindings/pci/hisilicon-pcie.txt | 2 +- .../devicetree/bindings/pci/kirin-pcie.txt | 2 +- .../bindings/pci/layerscape-pci.txt | 2 +- .../bindings/pci/nvidia,tegra194-pcie.txt | 4 +- .../devicetree/bindings/pci/pci-armada8k.txt | 2 +- .../devicetree/bindings/pci/pci-keystone.txt | 10 +- .../devicetree/bindings/pci/pcie-al.txt | 2 +- .../devicetree/bindings/pci/qcom,pcie.txt | 14 +- .../bindings/pci/samsung,exynos-pcie.yaml | 2 +- .../devicetree/bindings/pci/snps,pcie.yaml | 139 ++++++++++++++++++ .../pci/socionext,uniphier-pcie-ep.yaml | 2 +- .../devicetree/bindings/pci/ti-pci.txt | 4 +- .../devicetree/bindings/pci/uniphier-pcie.txt | 2 +- MAINTAINERS | 2 +- 19 files changed, 169 insertions(+), 107 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/designware-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/snps,pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt index b6acbe694ffb..da9253d43550 100644 --- a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt @@ -3,7 +3,7 @@ Amlogic Meson AXG DWC PCIE SoC controller Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Additional properties are described here: @@ -33,7 +33,7 @@ Required properties: - phy-names: must contain "pcie" - device_type: - should be "pci". As specified in designware-pcie.txt + should be "pci". As specified in snps,pcie.yaml Example configuration: diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt index 979dc7b6cfe8..84b53ae2c376 100644 --- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt +++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt @@ -1,7 +1,7 @@ * Axis ARTPEC-6 PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. Required properties: - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt deleted file mode 100644 index 78494c4050f7..000000000000 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ /dev/null @@ -1,77 +0,0 @@ -* Synopsys DesignWare PCIe interface - -Required properties: -- compatible: - "snps,dw-pcie" for RC mode; - "snps,dw-pcie-ep" for EP mode; -- reg: For designware cores version < 4.80 contains the configuration - address space. For designware core version >= 4.80, contains - the configuration and ATU address space -- reg-names: Must be "config" for the PCIe configuration space and "atu" for - the ATU address space. - (The old way of getting the configuration address space from "ranges" - is deprecated and should be avoided.) -RC mode: -- #address-cells: set to <3> -- #size-cells: set to <2> -- device_type: set to "pci" -- ranges: ranges for the PCI memory and I/O regions -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map: standard PCI - properties to define the mapping of the PCIe interface to interrupt - numbers. -EP mode: -- num-ib-windows: number of inbound address translation windows -- num-ob-windows: number of outbound address translation windows - -Optional properties: -- num-lanes: number of lanes to use (this property should be specified unless - the link is brought already up in BIOS) -- reset-gpio: GPIO pin number of power good signal -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - "pcie" - - "pcie_bus" -- snps,enable-cdm-check: This is a boolean property and if present enables - automatic checking of CDM (Configuration Dependent Module) registers - for data corruption. CDM registers include standard PCIe configuration - space registers, Port Logic registers, DMA and iATU (internal Address - Translation Unit) registers. -RC mode: -- num-viewport: number of view ports configured in hardware. If a platform - does not specify it, the driver assumes 2. -- bus-range: PCI bus numbers covered (it is recommended for new devicetrees - to specify this property, to keep backwards compatibility a range of - 0x00-0xff is assumed if not present) - -EP mode: -- max-functions: maximum number of functions that can be configured - -Example configuration: - - pcie: pcie@dfc00000 { - compatible = "snps,dw-pcie"; - reg = <0xdfc00000 0x0001000>, /* IP registers */ - <0xd0000000 0x0002000>; /* Configuration space */ - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000 - 0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; - interrupts = <25>, <24>; - #interrupt-cells = <1>; - num-lanes = <1>; - }; -or - pcie: pcie@dfc00000 { - compatible = "snps,dw-pcie-ep"; - reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ - <0xdfc01000 0x0001000>, /* IP registers 2 */ - <0xd0000000 0x2000000>; /* Configuration space */ - reg-names = "dbi", "dbi2", "addr_space"; - num-ib-windows = <6>; - num-ob-windows = <2>; - num-lanes = <1>; - }; diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index de4b2baf91e8..9470b279e3e4 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -1,7 +1,7 @@ * Freescale i.MX6 PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. Required properties: - compatible: diff --git a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt index 760b4d740616..2f62119d97b9 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt @@ -3,7 +3,7 @@ HiSilicon STB PCIe host bridge DT description The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core. It shares common functions with the DesignWare PCIe core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Additional properties are described here: diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt index d6796ef54ea1..4d243bfb9709 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt @@ -3,7 +3,7 @@ HiSilicon Hip05 and Hip06 PCIe host bridge DT description HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Additional properties are described here: diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt index 6bbe43818ad5..a38f8e38a67b 100644 --- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt @@ -3,7 +3,7 @@ HiSilicon Kirin SoCs PCIe host DT description Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Additional properties are described here: diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index daa99f7d4c3f..8070adfc1746 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -1,7 +1,7 @@ Freescale Layerscape PCIe controller This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. This controller derives its clocks from the Reset Configuration Word (RCW) which is used to describe the PLL settings at the time of chip-reset. diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt index bd43f3c3ece4..4644d79e0e0c 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt @@ -1,7 +1,7 @@ NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based) This PCIe controller is based on the Synopsis Designware PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. Some of the controller instances are dual mode where in they can work either in root port mode or endpoint mode but one at a time. @@ -22,7 +22,7 @@ Required properties: property. - reg-names: Must include the following entries: "appl": Controller's application logic registers - "config": As per the definition in designware-pcie.txt + "config": As per the definition in snps,pcie.yaml "atu_dma": iATU and DMA registers. This is where the iATU (internal Address Translation Unit) registers of the PCIe core are made available for SW access. diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt index 7a813d0e6d63..4531b895e9ea 100644 --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt @@ -1,7 +1,7 @@ * Marvell Armada 7K/8K PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. Required properties: - compatible: "marvell,armada8k-pcie" diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 47202a2938f2..ac271a0ca078 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -3,9 +3,9 @@ TI Keystone PCIe interface Keystone PCI host Controller is based on the Synopsys DesignWare PCI hardware version 3.65. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt +Documentation/devicetree/bindings/pci/snps,pcie.yaml -Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt +Please refer to Documentation/devicetree/bindings/pci/snps,pcie.yaml for the details of DesignWare DT bindings. Additional properties are described here as well as properties that are not applicable. @@ -82,11 +82,11 @@ reg-names: "dbics" for the DesignWare PCIe registers, "app" for the Address Translation Unit configuration registers and "addr_space" used to map remote RC address space num-ib-windows: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt + Documentation/devicetree/bindings/pci/snps,pcie.yaml num-ob-windows: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt + Documentation/devicetree/bindings/pci/snps,pcie.yaml num-lanes: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt + Documentation/devicetree/bindings/pci/snps,pcie.yaml power-domains: As documented by the generic PM domain bindings in Documentation/devicetree/bindings/power/power_domain.txt. ti,syscon-pcie-mode: phandle to the device control module required to configure diff --git a/Documentation/devicetree/bindings/pci/pcie-al.txt b/Documentation/devicetree/bindings/pci/pcie-al.txt index 557a5089229d..6e1e20e15ae9 100644 --- a/Documentation/devicetree/bindings/pci/pcie-al.txt +++ b/Documentation/devicetree/bindings/pci/pcie-al.txt @@ -2,7 +2,7 @@ Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare PCI core. It inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Properties of the host controller node that differ from it are: diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 3b55310390a0..43c3086cf6ea 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -33,22 +33,22 @@ - device_type: Usage: required Value type: - Definition: Should be "pci". As specified in designware-pcie.txt + Definition: Should be "pci". As specified in snps,pcie.yaml - #address-cells: Usage: required Value type: - Definition: Should be 3. As specified in designware-pcie.txt + Definition: Should be 3. As specified in snps,pcie.yaml - #size-cells: Usage: required Value type: - Definition: Should be 2. As specified in designware-pcie.txt + Definition: Should be 2. As specified in snps,pcie.yaml - ranges: Usage: required Value type: - Definition: As specified in designware-pcie.txt + Definition: As specified in snps,pcie.yaml - interrupts: Usage: required @@ -63,17 +63,17 @@ - #interrupt-cells: Usage: required Value type: - Definition: Should be 1. As specified in designware-pcie.txt + Definition: Should be 1. As specified in snps,pcie.yaml - interrupt-map-mask: Usage: required Value type: - Definition: As specified in designware-pcie.txt + Definition: As specified in snps,pcie.yaml - interrupt-map: Usage: required Value type: - Definition: As specified in designware-pcie.txt + Definition: As specified in snps,pcie.yaml - clocks: Usage: required diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml index 1810bf722350..8a4fe2d021ed 100644 --- a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml @@ -13,7 +13,7 @@ maintainers: description: |+ Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in - designware-pcie.txt. + snps,pcie.yaml. allOf: - $ref: /schemas/pci/pci-bus.yaml# diff --git a/Documentation/devicetree/bindings/pci/snps,pcie.yaml b/Documentation/devicetree/bindings/pci/snps,pcie.yaml new file mode 100644 index 000000000000..eeb5dad6937d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/snps,pcie.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/snps,pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare PCIe interface + +maintainers: + - Jingoo Han + - Gustavo Pimentel + +description: | + Synopsys DesignWare PCIe host controller + +anyOf: + - {} + - items: + contains: + enum: + - snps,dw-pcie + - snps,dw-pcie-ep + +properties: + compatible: + description: | + The compatible can be either: + - snps,dw-pcie # for RC mode + - snps,dw-pcie-ep # For EP mode + or some other value, when there's a host-specific driver + + reg: + description: | + Contains DBI and the configuration address space for all + Designware versions. + For Designware core version >= 4.80, should also contain the + ATU address space. + minItems: 2 + maxItems: 4 + + reset-gpio: + description: GPIO pin number for the PERST# signal + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 8 + + clock-names: + items: + contains: + enum: [ pcie, pcie_bus ] + minItems: 2 + maxItems: 8 + + "snps,enable-cdm-check": + $ref: /schemas/types.yaml#definitions/flag + description: | + This is a boolean property and if present enables + automatic checking of CDM (Configuration Dependent Module) registers + for data corruption. CDM registers include standard PCIe configuration + space registers, Port Logic registers, DMA and iATU (internal Address + Translation Unit) registers. + + # The following are optional properties for RC mode + + num-viewport: + description: | + number of view ports configured in hardware. If a platform + does not specify it, the driver assumes 2. + deprecated: true + + # The following are mandatory properties for EP Mode + + num-ib-windows: + description: number of inbound address translation windows + maxItems: 1 + deprecated: true + + num-ob-windows: + description: number of outbound address translation windows + maxItems: 1 + deprecated: true + + # The following are optional properties for EP mode + + max-functions: + description: maximum number of functions that can be configured + +required: + - reg + - reg-names + +allOf: + - if: + properties: + compatible: + contains: + const: snps,dw-pcie + then: + allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - if: + properties: + compatible: + contains: + const: snps,dw-pcie-ep + then: + required: + - compatible + +additionalProperties: false + +examples: + - | + pcie: pcie@dfc00000 { + compatible = "snps,dw-pcie"; + reg = <0xdfc00000 0x0001000>, /* IP registers */ + <0xd0000000 0x0002000>; /* Configuration space */ + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, + <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; + interrupts = <25>, <24>; + #interrupt-cells = <1>; + num-lanes = <1>; + }; + pcie_ep: pcie_ep@dfd00000 { + compatible = "snps,dw-pcie-ep"; + reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ + <0xdfc01000 0x0001000>, /* IP registers 2 */ + <0xd0000000 0x2000000>; /* Configuration space */ + reg-names = "dbi", "dbi2", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <2>; + num-lanes = <1>; + }; diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml index d6cf8a560ef0..9c8733d21de4 100644 --- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml @@ -10,7 +10,7 @@ description: | UniPhier PCIe endpoint controller is based on the Synopsys DesignWare PCI core. It shares common features with the PCIe DesignWare core and inherits common properties defined in - Documentation/devicetree/bindings/pci/designware-pcie.txt. + Documentation/devicetree/bindings/pci/snps,pcie.yaml. maintainers: - Kunihiko Hayashi diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index d5cbfe6b0d89..dfebfdb9b819 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -12,7 +12,7 @@ PCIe DesignWare Controller number of PHYs as specified in *phys* property. - ti,hwmods : Name of the hwmod associated to the pcie, "pcie", where is the instance number of the pcie from the HW spec. - - num-lanes as specified in ../designware-pcie.txt + - num-lanes as specified in ../snps,pcie.yaml - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control module and the register offset to specify lane selection. @@ -32,7 +32,7 @@ HOST MODE device_type, ranges, interrupt-map-mask, - interrupt-map : as specified in ../designware-pcie.txt + interrupt-map : as specified in ../snps,pcie.yaml - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument should contain the register offset within syscon and the 2nd argument should contain the bit field diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt index c4b7381733a0..17cfe504d800 100644 --- a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt +++ b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt @@ -6,7 +6,7 @@ on Socionext UniPhier SoCs. UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Required properties: - compatible: Should be "socionext,uniphier-pcie". diff --git a/MAINTAINERS b/MAINTAINERS index 2dd0a662d931..0bcba0d4994c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13673,7 +13673,7 @@ M: Jingoo Han M: Gustavo Pimentel L: linux-pci@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pci/designware-pcie.txt +F: Documentation/devicetree/bindings/pci/snps,pcie.yaml F: drivers/pci/controller/dwc/*designware* PCI DRIVER FOR TI DRA7XX/J721E From patchwork Wed Feb 3 07:01:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 1435134 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=iuhKsqo+; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DVt1l3zP4z9tkp for ; Wed, 3 Feb 2021 18:03:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231465AbhBCHDG (ORCPT ); Wed, 3 Feb 2021 02:03:06 -0500 Received: from mail.kernel.org ([198.145.29.99]:34052 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231542AbhBCHCl (ORCPT ); Wed, 3 Feb 2021 02:02:41 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 5CAF164F5D; Wed, 3 Feb 2021 07:02:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612335720; bh=E7yUqQo8Xn6JFXZwfNI1IGv93ZrxMNRZcf6mv6VtGWY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iuhKsqo+otYUgU/fiLZBZYudsjQYEMq+U1nY2q51juNEp1wLW8Nt2NNSWCE5K7E58 knbIl41FPMlMspDz6AEZ0ogi4GVxkrBZx+GpXNRnpQMKLL0ckZ2pd6096GFMgR6uUM 6ZsOMihsfokZhiTxoGhROsr8Vzzx4+rdDjx9bWR276VCwS9VH8S91w6N8TRis6dJpX Yhquj7aZZn4SZ2oTv0UFdNLtQpcnGZl2p56HLbb6wvPGe9cAPOawpkhEvsspMqg5QV ej+h7+ABq2QHAQI3Z+7pQcbBQnq6xEgXuEodWc1Xs1la+Mfgd4sxdMJgtGJyJXGRA4 tJlVSkAmDrz4Q== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l7CAo-001CAS-1k; Wed, 03 Feb 2021 08:01:58 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 02/11] doc: bindings: kirin-pcie.txt: convert it to YAML Date: Wed, 3 Feb 2021 08:01:46 +0100 Message-Id: <8617cb4f27b1f4146b956686f0410e5fc3827379.1612335031.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the file into a DT schema. Signed-off-by: Mauro Carvalho Chehab --- .../bindings/pci/hisilicon,kirin-pcie.yaml | 90 +++++++++++++++++++ .../devicetree/bindings/pci/kirin-pcie.txt | 50 ----------- MAINTAINERS | 2 +- 3 files changed, 91 insertions(+), 51 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file mode 100644 index 000000000000..46f9f3f25dbc --- /dev/null +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin SoCs PCIe host DT description + +maintainers: + - Xiaowei Song + - Binghui Wang + +description: | + Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. + It shares common functions with the PCIe DesignWare core driver. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# +# - $ref: snps,pcie.yaml# + +properties: + compatible: + const: hisilicon,kirin960-pcie + + reg: + description: | + Should contain rc_dbi, apb, phy, config registers location and length. + + reg-names: + items: + - const: dbi # controller configuration registers + - const: apb # apb Ctrl register defined by Kirin + - const: phy # apb PHY register defined by Kirin + - const: config # PCIe configuration space registers + + reset-gpios: + description: The GPIO to generate PCIe PERST# assert and deassert signal. + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - reset-gpios + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie: pcie@f4000000 { + compatible = "hisilicon,kirin960-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, + <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, + <0x0 0xF4000000 0 0x2000>; + reg-names = "dbi","apb","phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy", + "pcie_apb_sys", "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt deleted file mode 100644 index a38f8e38a67b..000000000000 --- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt +++ /dev/null @@ -1,50 +0,0 @@ -HiSilicon Kirin SoCs PCIe host DT description - -Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. -It shares common functions with the PCIe DesignWare core driver and -inherits common properties defined in -Documentation/devicetree/bindings/pci/snps,pcie.yaml. - -Additional properties are described here: - -Required properties -- compatible: - "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC -- reg: Should contain rc_dbi, apb, phy, config registers location and length. -- reg-names: Must include the following entries: - "dbi": controller configuration registers; - "apb": apb Ctrl register defined by Kirin; - "phy": apb PHY register defined by Kirin; - "config": PCIe configuration space registers. -- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. - -Optional properties: - -Example based on kirin960: - - pcie@f4000000 { - compatible = "hisilicon,kirin-pcie"; - reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, - <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; - reg-names = "dbi","apb","phy", "config"; - bus-range = <0x0 0x1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; - num-lanes = <1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, - <0x0 0 0 2 &gic 0 0 0 283 4>, - <0x0 0 0 3 &gic 0 0 0 284 4>, - <0x0 0 0 4 &gic 0 0 0 285 4>; - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_phy_ref", "pcie_aux", - "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; - reset-gpios = <&gpio11 1 0 >; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 0bcba0d4994c..701d7115af74 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13817,7 +13817,7 @@ M: Xiaowei Song M: Binghui Wang L: linux-pci@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pci/kirin-pcie.txt +F: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml F: drivers/pci/controller/dwc/pcie-kirin.c PCIE DRIVER FOR HISILICON STB From patchwork Wed Feb 3 07:01:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 1435135 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=j8QqLCXY; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DVt1m0gLPz9tlM for ; Wed, 3 Feb 2021 18:03:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231784AbhBCHDH (ORCPT ); Wed, 3 Feb 2021 02:03:07 -0500 Received: from mail.kernel.org ([198.145.29.99]:34064 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231636AbhBCHCl (ORCPT ); Wed, 3 Feb 2021 02:02:41 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 5F67964F60; Wed, 3 Feb 2021 07:02:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612335720; bh=718ZInNYsVDn+vu4wb8Pkopea6oBPczm2EkAavwDlgE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j8QqLCXYFRX630qd5yiwa8ak0iKhF5TfZyIlXp3727KMX/ATrS7whGPP5dycQK9iw 5Z1zL/PKmerGv2/lebhs0aeBJGaVK9eX5yltULC3Rx+TQUEVUGt+n0C3rc7ifO5F5+ PwqI1YbPZSN/toAkKRn0f4PlfAu9ghTjfwq+AkNsb5AFqj89F1huYu5OJNRW7xjeqJ z8A4kEV2u9o9v+34iqyV6zVoHHeBbcbsVcG5qy+PMtnhZcCxpyDSfk/8t+Tovlk+5p OlJzARTDjywDCwhEQ1ONWe0QA6K/qn+S/HFO0VYvTps0vH8UKqbmEoU8Sbu90u4J3a I9fL/vhtdZxuA== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l7CAo-001CAU-3B; Wed, 03 Feb 2021 08:01:58 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 03/11] doc: bindings: add new parameters used by Kirin 970 Date: Wed, 3 Feb 2021 08:01:47 +0100 Message-Id: <4d081ef108091aefd46cd7a520a63b94d2911f90.1612335031.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There are a few extra optional bindings that are needed for Kirin 970 based PCIe designs to work. Add them. Signed-off-by: Mauro Carvalho Chehab --- .../bindings/pci/hisilicon,kirin-pcie.yaml | 60 ++++++++++++++++++- 1 file changed, 57 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml index 46f9f3f25dbc..7a58883e07ec 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml @@ -34,8 +34,18 @@ properties: - const: config # PCIe configuration space registers reset-gpios: - description: The GPIO to generate PCIe PERST# assert and deassert signal. - maxItems: 1 + description: The GPIOs to generate PCIe PERST# assert and deassert signal. + minItems: 1 + maxItems: 4 + + clkreq-gpios: + description: CLKREQ signal GPIO pins to be enabled during PCI power on + minItems: 1 + maxItems: 3 + + eye_param: + description: items to adjust the eye parameters + maxItems: 5 required: - compatible @@ -52,12 +62,13 @@ examples: - | #include #include + #include soc { #address-cells = <2>; #size-cells = <2>; - pcie: pcie@f4000000 { + pcie1: pcie@f4000000 { compatible = "hisilicon,kirin960-pcie"; reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, @@ -87,4 +98,47 @@ examples: "pcie_apb_sys", "pcie_aclk"; reset-gpios = <&gpio11 1 0 >; }; + + pcie2: pcie@f5000000 { + compatible = "hisilicon,kirin970-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xfc000000 0x0 0x80000>, + <0x0 0xf5000000 0x0 0x2000>; + pci-supply = <&ldo33>; + reg-names = "dbi", "apb", "phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 0xf6000000 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; + + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, <&gpio17 0 0 >; + + /* vboost iboost pre post main */ + eye_param = <0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>; + msi-parent = <&its_pcie>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreq_pmx_func &pcie_clkreq_cfg_func>; + }; };