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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(39840400004)(346002)(136003)(396003)(376002)(46966006)(956004)(7696005)(81166007)(44144004)(8676002)(2616005)(66616009)(8936002)(44832011)(5660300002)(235185007)(33964004)(82310400003)(83380400001)(186003)(356005)(336012)(36756003)(16526019)(2906002)(26005)(478600001)(6666004)(70206006)(4326008)(70586007)(55016002)(316002)(6916009)(47076005)(8886007)(4743002)(86362001)(4216001)(2700100001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Feb 2021 12:39:03.0022 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c37b9c9-97f1-4b63-8a07-08d8c6ae5b3a X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT006.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB5460 X-Spam-Status: No, score=-14.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_LOTSOFHASH, MSGID_FROM_MTA_HEADER, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tamar Christina via Gcc-patches From: Tamar Christina Reply-To: Tamar Christina Cc: Richard.Earnshaw@arm.com, nd@arm.com, richard.sandiford@arm.com, Marcus.Shawcroft@arm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi All, g:87301e3956d44ad45e384a8eb16c79029d20213a and g:ee4c4fe289e768d3c6b6651c8bfa3fdf458934f4 changed the intrinsics to be proper RTL but accidentally ended up creating a regression because of the ordering in the RTL pattern. The existing RTL that combine should try to match to remove the vec_dup is aarch64_vec_mlal_lane and aarch64_vec_mult_lane which expects the select register to be the second operand of mult. The pattern introduced has it as the first operand so combine was unable to remove the vec_dup. This flips the order such that the patterns optimize correctly. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_mlal_n, aarch64_mlsl, aarch64_mlsl_n): Flip mult operands. gcc/testsuite/ChangeLog: * gcc.target/aarch64/advsimd-intrinsics/smlal-smlsl-mull-optimized.c: New test. --- inline copy of patch -- diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index bca2d8a3437fdcee77c7c357663c78c418b32a88..d1858663a4e78c0861d902b37e93c0b00d75e661 100644 diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index bca2d8a3437fdcee77c7c357663c78c418b32a88..d1858663a4e78c0861d902b37e93c0b00d75e661 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1950,10 +1950,10 @@ (define_insn "aarch64_mlal_n" (plus: (mult: (ANY_EXTEND: - (vec_duplicate:VD_HSI - (match_operand: 3 "register_operand" ""))) + (match_operand:VD_HSI 2 "register_operand" "w")) (ANY_EXTEND: - (match_operand:VD_HSI 2 "register_operand" "w"))) + (vec_duplicate:VD_HSI + (match_operand: 3 "register_operand" "")))) (match_operand: 1 "register_operand" "0")))] "TARGET_SIMD" "mlal\t%0., %2., %3.[0]" @@ -1980,10 +1980,10 @@ (define_insn "aarch64_mlsl_n" (match_operand: 1 "register_operand" "0") (mult: (ANY_EXTEND: - (vec_duplicate:VD_HSI - (match_operand: 3 "register_operand" ""))) + (match_operand:VD_HSI 2 "register_operand" "w")) (ANY_EXTEND: - (match_operand:VD_HSI 2 "register_operand" "w")))))] + (vec_duplicate:VD_HSI + (match_operand: 3 "register_operand" ""))))))] "TARGET_SIMD" "mlsl\t%0., %2., %3.[0]" [(set_attr "type" "neon_mla__long")] @@ -2078,10 +2078,10 @@ (define_insn "aarch64_mull_n" [(set (match_operand: 0 "register_operand" "=w") (mult: (ANY_EXTEND: - (vec_duplicate: - (match_operand: 2 "register_operand" ""))) + (match_operand:VD_HSI 1 "register_operand" "w")) (ANY_EXTEND: - (match_operand:VD_HSI 1 "register_operand" "w"))))] + (vec_duplicate: + (match_operand: 2 "register_operand" "")))))] "TARGET_SIMD" "mull\t%0., %1., %2.[0]" [(set_attr "type" "neon_mul__scalar_long")] diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/smlal-smlsl-mull-optimized.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/smlal-smlsl-mull-optimized.c new file mode 100644 index 0000000000000000000000000000000000000000..1e963e5002e666e32e12b2eef965b206c7344015 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/smlal-smlsl-mull-optimized.c @@ -0,0 +1,45 @@ +/* { dg-do compile { target aarch64-*-* } } */ + +#include + +/* +**add: +** smlal v0.4s, v1.4h, v2.h[3] +** ret +*/ + +int32x4_t add(int32x4_t acc, int16x4_t b, int16x4_t c) { + return vmlal_n_s16(acc, b, c[3]); +} + +/* +**sub: +** smlsl v0.4s, v1.4h, v2.h[3] +** ret +*/ + +int32x4_t sub(int32x4_t acc, int16x4_t b, int16x4_t c) { + return vmlsl_n_s16(acc, b, c[3]); +} + +/* +**smull: +** smull v0.4s, v1.4h, v2.h[3] +** ret +*/ + +int32x4_t smull(int16x4_t b, int16x4_t c) { + return vmull_n_s16(b, c[3]); +} + +/* +**umull: +** umull v0.4s, v1.4h, v2.h[3] +** ret +*/ + +uint32x4_t umull(uint16x4_t b, uint16x4_t c) { + return vmull_n_u16(b, c[3]); +} + +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" {-O[^0]} } } */