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[188.29.165.168]) by smtp.gmail.com with ESMTPSA id z81sm658098wmc.32.2018.01.11.05.08.47 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Jan 2018 05:08:48 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: [committed][AArch64] Avoid GET_MODE_NUNITS in v8.4 support Date: Thu, 11 Jan 2018 13:08:45 +0000 Message-ID: <87efmwlezm.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.3 (gnu/linux) MIME-Version: 1.0 This patch replaces GET_MODE_NUNITS in some of the v8.4 support with equivalent values, in preparation for the switch to NUM_POLY_INT_COEFFS==2. Tested on aarch64-linux-gnu and committed as an obvious extension of the previous patches. Richard 2018-01-11 Richard Sandiford gcc/ * config/aarch64/aarch64-simd.md (aarch64_fmll_low): Avoid GET_MODE_NUNITS. (aarch64_fmll_high): Likewise. (aarch64_fmll_lane_lowv2sf): Likewise. (aarch64_fmll_lane_highv2sf): Likewise. (aarch64_fmllq_laneq_lowv4sf): Likewise. (aarch64_fmllq_laneq_highv4sf): Likewise. (aarch64_fmll_laneq_lowv2sf): Likewise. (aarch64_fmll_laneq_highv2sf): Likewise. (aarch64_fmllq_lane_lowv4sf): Likewise. (aarch64_fmllq_lane_highv4sf): Likewise. Index: gcc/config/aarch64/aarch64-simd.md =================================================================== --- gcc/config/aarch64/aarch64-simd.md 2018-01-11 13:06:19.731271255 +0000 +++ gcc/config/aarch64/aarch64-simd.md 2018-01-11 13:06:36.797355218 +0000 @@ -6060,9 +6060,10 @@ (define_expand "aarch64_fmllmode); - rtx p1 = aarch64_simd_vect_par_cnst_half (mode, nunits, false); - rtx p2 = aarch64_simd_vect_par_cnst_half (mode, nunits, false); + rtx p1 = aarch64_simd_vect_par_cnst_half (mode, + * 2, false); + rtx p2 = aarch64_simd_vect_par_cnst_half (mode, + * 2, false); emit_insn (gen_aarch64_simd_fmll_low (operands[0], operands[1], @@ -6082,9 +6083,8 @@ (define_expand "aarch64_fmllmode); - rtx p1 = aarch64_simd_vect_par_cnst_half (mode, nunits, true); - rtx p2 = aarch64_simd_vect_par_cnst_half (mode, nunits, true); + rtx p1 = aarch64_simd_vect_par_cnst_half (mode, * 2, true); + rtx p2 = aarch64_simd_vect_par_cnst_half (mode, * 2, true); emit_insn (gen_aarch64_simd_fmll_high (operands[0], operands[1], @@ -6173,9 +6173,7 @@ (define_expand "aarch64_fmll_la VFMLA16_LOW))] "TARGET_F16FML" { - rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, - GET_MODE_NUNITS (V4HFmode), - false); + rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, 4, false); rtx lane = aarch64_endian_lane_rtx (V4HFmode, INTVAL (operands[4])); emit_insn (gen_aarch64_simd_fmll_lane_lowv2sf (operands[0], @@ -6196,9 +6194,7 @@ (define_expand "aarch64_fmll_la VFMLA16_HIGH))] "TARGET_F16FML" { - rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, - GET_MODE_NUNITS (V4HFmode), - true); + rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, 4, true); rtx lane = aarch64_endian_lane_rtx (V4HFmode, INTVAL (operands[4])); emit_insn (gen_aarch64_simd_fmll_lane_highv2sf (operands[0], @@ -6292,9 +6288,7 @@ (define_expand "aarch64_fmllq_l VFMLA16_LOW))] "TARGET_F16FML" { - rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, - GET_MODE_NUNITS (V8HFmode), - false); + rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, false); rtx lane = aarch64_endian_lane_rtx (V8HFmode, INTVAL (operands[4])); emit_insn (gen_aarch64_simd_fmllq_laneq_lowv4sf (operands[0], @@ -6314,10 +6308,7 @@ (define_expand "aarch64_fmllq_l VFMLA16_HIGH))] "TARGET_F16FML" { - rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, - GET_MODE_NUNITS (V8HFmode), - true); - + rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, true); rtx lane = aarch64_endian_lane_rtx (V8HFmode, INTVAL (operands[4])); emit_insn (gen_aarch64_simd_fmllq_laneq_highv4sf (operands[0], @@ -6411,9 +6402,7 @@ (define_expand "aarch64_fmll_la VFMLA16_LOW))] "TARGET_F16FML" { - rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, - GET_MODE_NUNITS (V4HFmode), - false); + rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, 4, false); rtx lane = aarch64_endian_lane_rtx (V8HFmode, INTVAL (operands[4])); emit_insn (gen_aarch64_simd_fmll_laneq_lowv2sf (operands[0], @@ -6434,9 +6423,7 @@ (define_expand "aarch64_fmll_la VFMLA16_HIGH))] "TARGET_F16FML" { - rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, - GET_MODE_NUNITS(V4HFmode), - true); + rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, 4, true); rtx lane = aarch64_endian_lane_rtx (V8HFmode, INTVAL (operands[4])); emit_insn (gen_aarch64_simd_fmll_laneq_highv2sf (operands[0], @@ -6531,10 +6518,7 @@ (define_expand "aarch64_fmllq_l VFMLA16_LOW))] "TARGET_F16FML" { - rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, - GET_MODE_NUNITS (V8HFmode), - false); - + rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, false); rtx lane = aarch64_endian_lane_rtx (V4HFmode, INTVAL (operands[4])); emit_insn (gen_aarch64_simd_fmllq_lane_lowv4sf (operands[0], @@ -6554,9 +6538,7 @@ (define_expand "aarch64_fmllq_l VFMLA16_HIGH))] "TARGET_F16FML" { - rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, - GET_MODE_NUNITS (V8HFmode), - true); + rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, true); rtx lane = aarch64_endian_lane_rtx (V4HFmode, INTVAL (operands[4])); emit_insn (gen_aarch64_simd_fmllq_lane_highv4sf (operands[0],