From patchwork Fri Jan 29 09:22:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1433162 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DRsLQ5jyVz9sWC for ; Fri, 29 Jan 2021 20:22:22 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=YeR+aPpy; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4DRsLQ3zJ6zDqLR for ; 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Fri, 29 Jan 2021 09:22:10 +0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 10T9M8WK48693616 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 29 Jan 2021 09:22:08 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F12D442047; Fri, 29 Jan 2021 09:22:07 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B75FB42041; Fri, 29 Jan 2021 09:22:07 +0000 (GMT) Received: from localhost.localdomain.com (unknown [9.145.29.111]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 29 Jan 2021 09:22:07 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org Date: Fri, 29 Jan 2021 10:22:07 +0100 Message-Id: <20210129092207.667519-1-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2021-01-29_03:2021-01-28, 2021-01-29 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 lowpriorityscore=0 bulkscore=0 phishscore=0 adultscore=0 spamscore=0 mlxlogscore=600 suspectscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2101290046 Subject: [Skiboot-stable] [PATCH] phb4: Disable TCE cache line buffer X-BeenThere: skiboot-stable@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "Patches, review, and discussion for stable releases of skiboot" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mikey@neuling.org, skiboot-stable@lists.ozlabs.org Errors-To: skiboot-stable-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot-stable" This patch implements a circumvention for HW557787. It disables the TCE cache line buffer as, under heavy loads, there's a possibility of an entry being re-allocated incorrectly. Signed-off-by: Frederic Barrat --- hw/phb4.c | 1 + include/phb4-regs.h | 1 + 2 files changed, 2 insertions(+) diff --git a/hw/phb4.c b/hw/phb4.c index e7758d34..6788abd2 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -5303,6 +5303,7 @@ static void phb4_init_hw(struct phb4 *p) /* Init_17 - PHB Control */ val = PHB_CTRLR_IRQ_PGSZ_64K; + val |= PHB_CTRLR_TCE_CLB_DISABLE; // HW557787 circumvention val |= SETFIELD(PHB_CTRLR_TVT_ADDR_SEL, 0ull, TVT_2_PER_PE); if (PHB4_CAN_STORE_EOI(p)) val |= PHB_CTRLR_IRQ_STORE_EOI; diff --git a/include/phb4-regs.h b/include/phb4-regs.h index d3b0aac4..b6e77874 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -110,6 +110,7 @@ #define TVT_4_PER_PE 1 #define TVT_8_PER_PE 2 #define TVT_16_PER_PE 3 +#define PHB_CTRLR_TCE_CLB_DISABLE PPC_BIT(21) #define PHB_CTRLR_DMA_RD_SPACING PPC_BITMASK(28,31) #define PHB_AIB_FENCE_CTRL 0x860 #define PHB_TCE_TAG_ENABLE 0x868