From patchwork Thu Jan 11 10:11:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858976 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="t0ZzlK5g"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHM9p39Fyz9t41 for ; Thu, 11 Jan 2018 21:11:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933125AbeAKKL5 (ORCPT ); Thu, 11 Jan 2018 05:11:57 -0500 Received: from mail-pg0-f66.google.com ([74.125.83.66]:33544 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932684AbeAKKL4 (ORCPT ); Thu, 11 Jan 2018 05:11:56 -0500 Received: by mail-pg0-f66.google.com with SMTP id i196so1881717pgd.0; Thu, 11 Jan 2018 02:11:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=n4c7l27jvzaoXynRVIkWgiE5lvsyY4NT8995rTxFRBU=; b=t0ZzlK5gEzikylI2XW/26Rm70z9nLHKb3iHl40GghrjMiM+5Lc0f7ntMKrPGPsYaac YyleMqRGECgE6zRqwKFrokN3nH0T3AJVaQbkG+5lE6GoyqcjLISm2YpJ0ima1PKrUEVN 2Cr4n/vcaGoqtSZ84msdi2jnEdK7rzqvynunvM2Ql8+QdZAQ/0DMKvZ5BUwZsb48bjrG cMsBZHdRKRQapx1c1SgsjApc12tbqwejxz5r/3OtPmWF1ZVwFxUOsOoRuEMJZ+XJyEib hnPUHH6ug/oCRNtlCGoRAiGV8APa3DtZZYlV+DG9P1dViDpcyc5W3eKPT1y3c7WXPA8S NWpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=n4c7l27jvzaoXynRVIkWgiE5lvsyY4NT8995rTxFRBU=; b=FA/j2BWgxDhjp/bYzgleDvaDlIiBxtbcpoxYyKSZNHZr+CCWV1XXuV2ZDQHEP09xGy cQeCChA6inAZvLr0gQvKrXVXHu45DsKAErqQZkInN4MM/rwQXt2u62Ais1EDGEgePwCY 98kK4m5XV2itA0WzUre3oRLsLvcANM/OnFP47u5i/oXpmkYs3dX8Ef/qABmhdofCb/cz TS9E61dOq//+ds+M26ylOjierXukXht53KHyse8tzBEDV3ku4Xoc9fQsH7ZdCbEwCj/d xCVN8oMoSQtrzws1kJTUOqR7ffCHvIQKONAsGKFiStPxeupDYMuo/gfWTJlomjn+PktE 93MQ== X-Gm-Message-State: AKwxyteQAcWqOnuBujc+Z+EBngEEWgIM/ChJOalaUrkdEyebupjoGUyW n6WAr37vVOB/LXBg8C3TYqE= X-Google-Smtp-Source: ACJfBou8fvyILadGx3sLsV0eC7t3SaKw3yPIjWkXSlcdncpWkFd6AXGvXu30YvALMV9QyV1R4i+zXQ== X-Received: by 10.101.97.10 with SMTP id z10mr2753000pgu.24.1515665515007; Thu, 11 Jan 2018 02:11:55 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.11.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:11:54 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 01/26] KVM: PPC: Book3S PR: Move kvmppc_save_tm/kvmppc_restore_tm to separate file Date: Thu, 11 Jan 2018 18:11:14 +0800 Message-Id: <1515665499-31710-2-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo It is a simple patch just for moving kvmppc_save_tm/kvmppc_restore_tm() functionalities to tm.S. There is no logic change. The reconstruct of those APIs will be done in later patches to improve readability. It is for preparation of reusing those APIs on both HV/PR PPC KVM. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/kvm/Makefile | 3 + arch/powerpc/kvm/book3s_hv_rmhandlers.S | 239 ---------------------------- arch/powerpc/kvm/tm.S | 267 ++++++++++++++++++++++++++++++++ 3 files changed, 270 insertions(+), 239 deletions(-) create mode 100644 arch/powerpc/kvm/tm.S diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile index 85ba80d..3886f1b 100644 --- a/arch/powerpc/kvm/Makefile +++ b/arch/powerpc/kvm/Makefile @@ -63,6 +63,9 @@ kvm-pr-y := \ book3s_64_mmu.o \ book3s_32_mmu.o +kvm-book3s_64-builtin-objs-$(CONFIG_KVM_BOOK3S_64_HANDLER) += \ + tm.o + ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE kvm-book3s_64-builtin-objs-$(CONFIG_KVM_BOOK3S_64_HANDLER) += \ book3s_rmhandlers.o diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S index 2659844..a5c8ecd 100644 --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S @@ -39,8 +39,6 @@ BEGIN_FTR_SECTION; \ extsw reg, reg; \ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) -#define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM) - /* Values in HSTATE_NAPPING(r13) */ #define NAPPING_CEDE 1 #define NAPPING_NOVCPU 2 @@ -2951,243 +2949,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) mr r4,r31 blr -#ifdef CONFIG_PPC_TRANSACTIONAL_MEM -/* - * Save transactional state and TM-related registers. - * Called with r9 pointing to the vcpu struct. - * This can modify all checkpointed registers, but - * restores r1, r2 and r9 (vcpu pointer) before exit. - */ -kvmppc_save_tm: - mflr r0 - std r0, PPC_LR_STKOFF(r1) - - /* Turn on TM. */ - mfmsr r8 - li r0, 1 - rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG - mtmsrd r8 - - ld r5, VCPU_MSR(r9) - rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 - beq 1f /* TM not active in guest. */ - - std r1, HSTATE_HOST_R1(r13) - li r3, TM_CAUSE_KVM_RESCHED - - /* Clear the MSR RI since r1, r13 are all going to be foobar. */ - li r5, 0 - mtmsrd r5, 1 - - /* All GPRs are volatile at this point. */ - TRECLAIM(R3) - - /* Temporarily store r13 and r9 so we have some regs to play with */ - SET_SCRATCH0(r13) - GET_PACA(r13) - std r9, PACATMSCRATCH(r13) - ld r9, HSTATE_KVM_VCPU(r13) - - /* Get a few more GPRs free. */ - std r29, VCPU_GPRS_TM(29)(r9) - std r30, VCPU_GPRS_TM(30)(r9) - std r31, VCPU_GPRS_TM(31)(r9) - - /* Save away PPR and DSCR soon so don't run with user values. */ - mfspr r31, SPRN_PPR - HMT_MEDIUM - mfspr r30, SPRN_DSCR - ld r29, HSTATE_DSCR(r13) - mtspr SPRN_DSCR, r29 - - /* Save all but r9, r13 & r29-r31 */ - reg = 0 - .rept 29 - .if (reg != 9) && (reg != 13) - std reg, VCPU_GPRS_TM(reg)(r9) - .endif - reg = reg + 1 - .endr - /* ... now save r13 */ - GET_SCRATCH0(r4) - std r4, VCPU_GPRS_TM(13)(r9) - /* ... and save r9 */ - ld r4, PACATMSCRATCH(r13) - std r4, VCPU_GPRS_TM(9)(r9) - - /* Reload stack pointer and TOC. */ - ld r1, HSTATE_HOST_R1(r13) - ld r2, PACATOC(r13) - - /* Set MSR RI now we have r1 and r13 back. */ - li r5, MSR_RI - mtmsrd r5, 1 - - /* Save away checkpinted SPRs. */ - std r31, VCPU_PPR_TM(r9) - std r30, VCPU_DSCR_TM(r9) - mflr r5 - mfcr r6 - mfctr r7 - mfspr r8, SPRN_AMR - mfspr r10, SPRN_TAR - mfxer r11 - std r5, VCPU_LR_TM(r9) - stw r6, VCPU_CR_TM(r9) - std r7, VCPU_CTR_TM(r9) - std r8, VCPU_AMR_TM(r9) - std r10, VCPU_TAR_TM(r9) - std r11, VCPU_XER_TM(r9) - - /* Restore r12 as trap number. */ - lwz r12, VCPU_TRAP(r9) - - /* Save FP/VSX. */ - addi r3, r9, VCPU_FPRS_TM - bl store_fp_state - addi r3, r9, VCPU_VRS_TM - bl store_vr_state - mfspr r6, SPRN_VRSAVE - stw r6, VCPU_VRSAVE_TM(r9) -1: - /* - * We need to save these SPRs after the treclaim so that the software - * error code is recorded correctly in the TEXASR. Also the user may - * change these outside of a transaction, so they must always be - * context switched. - */ - mfspr r5, SPRN_TFHAR - mfspr r6, SPRN_TFIAR - mfspr r7, SPRN_TEXASR - std r5, VCPU_TFHAR(r9) - std r6, VCPU_TFIAR(r9) - std r7, VCPU_TEXASR(r9) - - ld r0, PPC_LR_STKOFF(r1) - mtlr r0 - blr - -/* - * Restore transactional state and TM-related registers. - * Called with r4 pointing to the vcpu struct. - * This potentially modifies all checkpointed registers. - * It restores r1, r2, r4 from the PACA. - */ -kvmppc_restore_tm: - mflr r0 - std r0, PPC_LR_STKOFF(r1) - - /* Turn on TM/FP/VSX/VMX so we can restore them. */ - mfmsr r5 - li r6, MSR_TM >> 32 - sldi r6, r6, 32 - or r5, r5, r6 - ori r5, r5, MSR_FP - oris r5, r5, (MSR_VEC | MSR_VSX)@h - mtmsrd r5 - - /* - * The user may change these outside of a transaction, so they must - * always be context switched. - */ - ld r5, VCPU_TFHAR(r4) - ld r6, VCPU_TFIAR(r4) - ld r7, VCPU_TEXASR(r4) - mtspr SPRN_TFHAR, r5 - mtspr SPRN_TFIAR, r6 - mtspr SPRN_TEXASR, r7 - - ld r5, VCPU_MSR(r4) - rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 - beqlr /* TM not active in guest */ - std r1, HSTATE_HOST_R1(r13) - - /* Make sure the failure summary is set, otherwise we'll program check - * when we trechkpt. It's possible that this might have been not set - * on a kvmppc_set_one_reg() call but we shouldn't let this crash the - * host. - */ - oris r7, r7, (TEXASR_FS)@h - mtspr SPRN_TEXASR, r7 - - /* - * We need to load up the checkpointed state for the guest. - * We need to do this early as it will blow away any GPRs, VSRs and - * some SPRs. - */ - - mr r31, r4 - addi r3, r31, VCPU_FPRS_TM - bl load_fp_state - addi r3, r31, VCPU_VRS_TM - bl load_vr_state - mr r4, r31 - lwz r7, VCPU_VRSAVE_TM(r4) - mtspr SPRN_VRSAVE, r7 - - ld r5, VCPU_LR_TM(r4) - lwz r6, VCPU_CR_TM(r4) - ld r7, VCPU_CTR_TM(r4) - ld r8, VCPU_AMR_TM(r4) - ld r9, VCPU_TAR_TM(r4) - ld r10, VCPU_XER_TM(r4) - mtlr r5 - mtcr r6 - mtctr r7 - mtspr SPRN_AMR, r8 - mtspr SPRN_TAR, r9 - mtxer r10 - - /* - * Load up PPR and DSCR values but don't put them in the actual SPRs - * till the last moment to avoid running with userspace PPR and DSCR for - * too long. - */ - ld r29, VCPU_DSCR_TM(r4) - ld r30, VCPU_PPR_TM(r4) - - std r2, PACATMSCRATCH(r13) /* Save TOC */ - - /* Clear the MSR RI since r1, r13 are all going to be foobar. */ - li r5, 0 - mtmsrd r5, 1 - - /* Load GPRs r0-r28 */ - reg = 0 - .rept 29 - ld reg, VCPU_GPRS_TM(reg)(r31) - reg = reg + 1 - .endr - - mtspr SPRN_DSCR, r29 - mtspr SPRN_PPR, r30 - - /* Load final GPRs */ - ld 29, VCPU_GPRS_TM(29)(r31) - ld 30, VCPU_GPRS_TM(30)(r31) - ld 31, VCPU_GPRS_TM(31)(r31) - - /* TM checkpointed state is now setup. All GPRs are now volatile. */ - TRECHKPT - - /* Now let's get back the state we need. */ - HMT_MEDIUM - GET_PACA(r13) - ld r29, HSTATE_DSCR(r13) - mtspr SPRN_DSCR, r29 - ld r4, HSTATE_KVM_VCPU(r13) - ld r1, HSTATE_HOST_R1(r13) - ld r2, PACATMSCRATCH(r13) - - /* Set the MSR RI since we have our registers back. */ - li r5, MSR_RI - mtmsrd r5, 1 - - ld r0, PPC_LR_STKOFF(r1) - mtlr r0 - blr -#endif - /* * We come here if we get any exception or interrupt while we are * executing host real mode code while in guest MMU context. diff --git a/arch/powerpc/kvm/tm.S b/arch/powerpc/kvm/tm.S new file mode 100644 index 0000000..072d35e --- /dev/null +++ b/arch/powerpc/kvm/tm.S @@ -0,0 +1,267 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Derived from book3s_hv_rmhandlers.S, which are: + * + * Copyright 2011 Paul Mackerras, IBM Corp. + * + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM +#define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM) +#endif + +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM +/* + * Save transactional state and TM-related registers. + * Called with r9 pointing to the vcpu struct. + * This can modify all checkpointed registers, but + * restores r1, r2 and r9 (vcpu pointer) before exit. + */ +_GLOBAL(kvmppc_save_tm) + mflr r0 + std r0, PPC_LR_STKOFF(r1) + + /* Turn on TM. */ + mfmsr r8 + li r0, 1 + rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG + mtmsrd r8 + + ld r5, VCPU_MSR(r9) + rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 + beq 1f /* TM not active in guest. */ + + std r1, HSTATE_HOST_R1(r13) + li r3, TM_CAUSE_KVM_RESCHED + + /* Clear the MSR RI since r1, r13 are all going to be foobar. */ + li r5, 0 + mtmsrd r5, 1 + + /* All GPRs are volatile at this point. */ + TRECLAIM(R3) + + /* Temporarily store r13 and r9 so we have some regs to play with */ + SET_SCRATCH0(r13) + GET_PACA(r13) + std r9, PACATMSCRATCH(r13) + ld r9, HSTATE_KVM_VCPU(r13) + + /* Get a few more GPRs free. */ + std r29, VCPU_GPRS_TM(29)(r9) + std r30, VCPU_GPRS_TM(30)(r9) + std r31, VCPU_GPRS_TM(31)(r9) + + /* Save away PPR and DSCR soon so don't run with user values. */ + mfspr r31, SPRN_PPR + HMT_MEDIUM + mfspr r30, SPRN_DSCR +#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE + ld r29, HSTATE_DSCR(r13) + mtspr SPRN_DSCR, r29 +#endif + + /* Save all but r9, r13 & r29-r31 */ + reg = 0 + .rept 29 + .if (reg != 9) && (reg != 13) + std reg, VCPU_GPRS_TM(reg)(r9) + .endif + reg = reg + 1 + .endr + /* ... now save r13 */ + GET_SCRATCH0(r4) + std r4, VCPU_GPRS_TM(13)(r9) + /* ... and save r9 */ + ld r4, PACATMSCRATCH(r13) + std r4, VCPU_GPRS_TM(9)(r9) + + /* Reload stack pointer and TOC. */ + ld r1, HSTATE_HOST_R1(r13) + ld r2, PACATOC(r13) + + /* Set MSR RI now we have r1 and r13 back. */ + li r5, MSR_RI + mtmsrd r5, 1 + + /* Save away checkpinted SPRs. */ + std r31, VCPU_PPR_TM(r9) + std r30, VCPU_DSCR_TM(r9) + mflr r5 + mfcr r6 + mfctr r7 + mfspr r8, SPRN_AMR + mfspr r10, SPRN_TAR + mfxer r11 + std r5, VCPU_LR_TM(r9) + stw r6, VCPU_CR_TM(r9) + std r7, VCPU_CTR_TM(r9) + std r8, VCPU_AMR_TM(r9) + std r10, VCPU_TAR_TM(r9) + std r11, VCPU_XER_TM(r9) + + /* Restore r12 as trap number. */ + lwz r12, VCPU_TRAP(r9) + + /* Save FP/VSX. */ + addi r3, r9, VCPU_FPRS_TM + bl store_fp_state + addi r3, r9, VCPU_VRS_TM + bl store_vr_state + mfspr r6, SPRN_VRSAVE + stw r6, VCPU_VRSAVE_TM(r9) +1: + /* + * We need to save these SPRs after the treclaim so that the software + * error code is recorded correctly in the TEXASR. Also the user may + * change these outside of a transaction, so they must always be + * context switched. + */ + mfspr r5, SPRN_TFHAR + mfspr r6, SPRN_TFIAR + mfspr r7, SPRN_TEXASR + std r5, VCPU_TFHAR(r9) + std r6, VCPU_TFIAR(r9) + std r7, VCPU_TEXASR(r9) + + ld r0, PPC_LR_STKOFF(r1) + mtlr r0 + blr + +/* + * Restore transactional state and TM-related registers. + * Called with r4 pointing to the vcpu struct. + * This potentially modifies all checkpointed registers. + * It restores r1, r2, r4 from the PACA. + */ +_GLOBAL(kvmppc_restore_tm) + mflr r0 + std r0, PPC_LR_STKOFF(r1) + + /* Turn on TM/FP/VSX/VMX so we can restore them. */ + mfmsr r5 + li r6, MSR_TM >> 32 + sldi r6, r6, 32 + or r5, r5, r6 + ori r5, r5, MSR_FP + oris r5, r5, (MSR_VEC | MSR_VSX)@h + mtmsrd r5 + + /* + * The user may change these outside of a transaction, so they must + * always be context switched. + */ + ld r5, VCPU_TFHAR(r4) + ld r6, VCPU_TFIAR(r4) + ld r7, VCPU_TEXASR(r4) + mtspr SPRN_TFHAR, r5 + mtspr SPRN_TFIAR, r6 + mtspr SPRN_TEXASR, r7 + + ld r5, VCPU_MSR(r4) + rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 + beqlr /* TM not active in guest */ + std r1, HSTATE_HOST_R1(r13) + + /* Make sure the failure summary is set, otherwise we'll program check + * when we trechkpt. It's possible that this might have been not set + * on a kvmppc_set_one_reg() call but we shouldn't let this crash the + * host. + */ + oris r7, r7, (TEXASR_FS)@h + mtspr SPRN_TEXASR, r7 + + /* + * We need to load up the checkpointed state for the guest. + * We need to do this early as it will blow away any GPRs, VSRs and + * some SPRs. + */ + + mr r31, r4 + addi r3, r31, VCPU_FPRS_TM + bl load_fp_state + addi r3, r31, VCPU_VRS_TM + bl load_vr_state + mr r4, r31 + lwz r7, VCPU_VRSAVE_TM(r4) + mtspr SPRN_VRSAVE, r7 + + ld r5, VCPU_LR_TM(r4) + lwz r6, VCPU_CR_TM(r4) + ld r7, VCPU_CTR_TM(r4) + ld r8, VCPU_AMR_TM(r4) + ld r9, VCPU_TAR_TM(r4) + ld r10, VCPU_XER_TM(r4) + mtlr r5 + mtcr r6 + mtctr r7 + mtspr SPRN_AMR, r8 + mtspr SPRN_TAR, r9 + mtxer r10 + + /* + * Load up PPR and DSCR values but don't put them in the actual SPRs + * till the last moment to avoid running with userspace PPR and DSCR for + * too long. + */ + ld r29, VCPU_DSCR_TM(r4) + ld r30, VCPU_PPR_TM(r4) + + std r2, PACATMSCRATCH(r13) /* Save TOC */ + + /* Clear the MSR RI since r1, r13 are all going to be foobar. */ + li r5, 0 + mtmsrd r5, 1 + + /* Load GPRs r0-r28 */ + reg = 0 + .rept 29 + ld reg, VCPU_GPRS_TM(reg)(r31) + reg = reg + 1 + .endr + + mtspr SPRN_DSCR, r29 + mtspr SPRN_PPR, r30 + + /* Load final GPRs */ + ld 29, VCPU_GPRS_TM(29)(r31) + ld 30, VCPU_GPRS_TM(30)(r31) + ld 31, VCPU_GPRS_TM(31)(r31) + + /* TM checkpointed state is now setup. All GPRs are now volatile. */ + TRECHKPT + + /* Now let's get back the state we need. */ + HMT_MEDIUM + GET_PACA(r13) +#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE + ld r29, HSTATE_DSCR(r13) + mtspr SPRN_DSCR, r29 +#endif + ld r4, HSTATE_KVM_VCPU(r13) + ld r1, HSTATE_HOST_R1(r13) + ld r2, PACATMSCRATCH(r13) + + /* Set the MSR RI since we have our registers back. */ + li r5, MSR_RI + mtmsrd r5, 1 + + ld r0, PPC_LR_STKOFF(r1) + mtlr r0 + blr +#endif From patchwork Thu Jan 11 10:11:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858977 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="no/qCh2V"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHM9v48Czz9t50 for ; Thu, 11 Jan 2018 21:12:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933156AbeAKKMA (ORCPT ); Thu, 11 Jan 2018 05:12:00 -0500 Received: from mail-pf0-f196.google.com ([209.85.192.196]:35938 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932684AbeAKKL7 (ORCPT ); Thu, 11 Jan 2018 05:11:59 -0500 Received: by mail-pf0-f196.google.com with SMTP id 23so1305266pfp.3; Thu, 11 Jan 2018 02:11:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GlpCsZP5mLTIhQeq3V1Iw10c5lP5lcULTfWfV83Q+NE=; b=no/qCh2VUsxErm+IHsmNpAUMYvoosE6CkcnzpC0/33N1s5tgk3ZNVujEk6OCVskKr4 GAcc+eqH1vZaFREIN5kyUprU+yngIXEYNV7oa9QlfqPmKKguPTLbUx5mGzVBOECMKKSk LUrP+ccuxDTDKZ+gB9BrFKHvzAof+DIbKisiw5BDvD+mpmspxXVjQuThAWbjQk1VIH6f L1H1vTQnJ9/rXmHhNBbKBFXhOJ7INshGEhJzkRpXoA7ZCBHT5ar7CGHhMJUIBlIfpoHO E0G7if2JEFQMMUuYEapKlSvHAoGsuLcWWpqAXtUINbkgm4tfPQsKGDkhByGaE0LW2C1h i+iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GlpCsZP5mLTIhQeq3V1Iw10c5lP5lcULTfWfV83Q+NE=; b=nkbkQBEDTD+LDD9uzNMHquIXX4Cp/WDScMzFpikVVqdnWotZofTrOLIxp8CEZHMi5F o8es83wl8dqWsHGbUI47dz7bCs2LUkP8k5YyC0hamM8UaQpohz0QjtmlMpBiE9fNVTrF VpBILB8mDd71kzyjxe1txT4tuGMY2G9BX9qOZwcjSTJzIsG1int8w88iWMJrBoOP9PHH Hvtn9ld33cE4aV2+Mmpe4A5L6z9b0xUh1ecFP8klR+IZnMO+bQFb08AXHB9Efu1M55dw 9tgfcfZrCO2k1l3TMWB8/FhIC/czs/6LjHkcshVuGDiI7CZFmX2KLXkHu6aFhgYLr89t 0flg== X-Gm-Message-State: AKGB3mJV4GQYvwjm+R6Mnq7h3TeViZcgbk4vm7jfdaaVLBybdo1N7trm IxE1gorcwrUZKLwHnsFZKHTh6A== X-Google-Smtp-Source: ACJfBosF4MJ6xIBkrRYcPHqxgKiM+9cnndzPgg3PVgItfZOb4ZLUXsNssN/QxM0liszmWfOHW2Sx6g== X-Received: by 10.98.159.25 with SMTP id g25mr19331093pfe.39.1515665518635; Thu, 11 Jan 2018 02:11:58 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.11.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:11:57 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 02/26] KVM: PPC: Book3S PR: add new parameter (guest MSR) for kvmppc_save_tm()/kvmppc_restore_tm() Date: Thu, 11 Jan 2018 18:11:15 +0800 Message-Id: <1515665499-31710-3-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo HV KVM and PR KVM need different MSR source to indicate whether treclaim. or trecheckpoint. is necessary. This patch add new parameter (guest MSR) for these kvmppc_save_tm/ kvmppc_restore_tm() APIs: - For HV KVM, it is VCPU_MSR - For PR KVM, it is current host MSR or VCPU_SHADOW_SRR1 This enhancement enables these 2 APIs to be reused by PR KVM later. And the patch keeps HV KVM logic unchanged. This patch also reworks kvmppc_save_tm()/kvmppc_restore_tm() to have a clean ABI: r3 for vcpu and r4 for guest_msr. Signed-off-by: Simon Guo --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 12 ++++++- arch/powerpc/kvm/tm.S | 61 ++++++++++++++++++--------------- 2 files changed, 45 insertions(+), 28 deletions(-) diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S index a5c8ecd..613fd27 100644 --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S @@ -808,7 +808,10 @@ BEGIN_FTR_SECTION /* * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR */ + mr r3, r4 + ld r4, VCPU_MSR(r3) bl kvmppc_restore_tm + ld r4, HSTATE_KVM_VCPU(r13) END_FTR_SECTION_IFSET(CPU_FTR_TM) #endif @@ -1680,7 +1683,10 @@ BEGIN_FTR_SECTION /* * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR */ + mr r3, r9 + ld r4, VCPU_MSR(r3) bl kvmppc_save_tm + ld r9, HSTATE_KVM_VCPU(r13) END_FTR_SECTION_IFSET(CPU_FTR_TM) #endif @@ -2543,7 +2549,8 @@ BEGIN_FTR_SECTION /* * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR */ - ld r9, HSTATE_KVM_VCPU(r13) + ld r3, HSTATE_KVM_VCPU(r13) + ld r4, VCPU_MSR(r3) bl kvmppc_save_tm END_FTR_SECTION_IFSET(CPU_FTR_TM) #endif @@ -2656,7 +2663,10 @@ BEGIN_FTR_SECTION /* * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR */ + mr r3, r4 + ld r4, VCPU_MSR(r3) bl kvmppc_restore_tm + ld r4, HSTATE_KVM_VCPU(r13) END_FTR_SECTION_IFSET(CPU_FTR_TM) #endif diff --git a/arch/powerpc/kvm/tm.S b/arch/powerpc/kvm/tm.S index 072d35e..e779b15 100644 --- a/arch/powerpc/kvm/tm.S +++ b/arch/powerpc/kvm/tm.S @@ -28,9 +28,12 @@ #ifdef CONFIG_PPC_TRANSACTIONAL_MEM /* * Save transactional state and TM-related registers. - * Called with r9 pointing to the vcpu struct. + * Called with: + * - r3 pointing to the vcpu struct + * - r4 points to the MSR with current TS bits: + * (For HV KVM, it is VCPU_MSR ; For PR KVM, it is host MSR). * This can modify all checkpointed registers, but - * restores r1, r2 and r9 (vcpu pointer) before exit. + * restores r1, r2 before exit. */ _GLOBAL(kvmppc_save_tm) mflr r0 @@ -42,11 +45,11 @@ _GLOBAL(kvmppc_save_tm) rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG mtmsrd r8 - ld r5, VCPU_MSR(r9) - rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 + rldicl. r4, r4, 64 - MSR_TS_S_LG, 62 beq 1f /* TM not active in guest. */ - std r1, HSTATE_HOST_R1(r13) + std r1, HSTATE_SCRATCH2(r13) + std r3, HSTATE_SCRATCH1(r13) li r3, TM_CAUSE_KVM_RESCHED /* Clear the MSR RI since r1, r13 are all going to be foobar. */ @@ -60,7 +63,7 @@ _GLOBAL(kvmppc_save_tm) SET_SCRATCH0(r13) GET_PACA(r13) std r9, PACATMSCRATCH(r13) - ld r9, HSTATE_KVM_VCPU(r13) + ld r9, HSTATE_SCRATCH1(r13) /* Get a few more GPRs free. */ std r29, VCPU_GPRS_TM(29)(r9) @@ -92,7 +95,7 @@ _GLOBAL(kvmppc_save_tm) std r4, VCPU_GPRS_TM(9)(r9) /* Reload stack pointer and TOC. */ - ld r1, HSTATE_HOST_R1(r13) + ld r1, HSTATE_SCRATCH2(r13) ld r2, PACATOC(r13) /* Set MSR RI now we have r1 and r13 back. */ @@ -145,9 +148,13 @@ _GLOBAL(kvmppc_save_tm) /* * Restore transactional state and TM-related registers. - * Called with r4 pointing to the vcpu struct. + * Called with: + * - r3 pointing to the vcpu struct. + * - r4 is the guest MSR with desired TS bits: + * For HV KVM, it is VCPU_MSR + * For PR KVM, it is provided by caller * This potentially modifies all checkpointed registers. - * It restores r1, r2, r4 from the PACA. + * It restores r1, r2 from the PACA. */ _GLOBAL(kvmppc_restore_tm) mflr r0 @@ -166,17 +173,17 @@ _GLOBAL(kvmppc_restore_tm) * The user may change these outside of a transaction, so they must * always be context switched. */ - ld r5, VCPU_TFHAR(r4) - ld r6, VCPU_TFIAR(r4) - ld r7, VCPU_TEXASR(r4) + ld r5, VCPU_TFHAR(r3) + ld r6, VCPU_TFIAR(r3) + ld r7, VCPU_TEXASR(r3) mtspr SPRN_TFHAR, r5 mtspr SPRN_TFIAR, r6 mtspr SPRN_TEXASR, r7 - ld r5, VCPU_MSR(r4) + mr r5, r4 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 beqlr /* TM not active in guest */ - std r1, HSTATE_HOST_R1(r13) + std r1, HSTATE_SCRATCH2(r13) /* Make sure the failure summary is set, otherwise we'll program check * when we trechkpt. It's possible that this might have been not set @@ -192,21 +199,21 @@ _GLOBAL(kvmppc_restore_tm) * some SPRs. */ - mr r31, r4 + mr r31, r3 addi r3, r31, VCPU_FPRS_TM bl load_fp_state addi r3, r31, VCPU_VRS_TM bl load_vr_state - mr r4, r31 - lwz r7, VCPU_VRSAVE_TM(r4) + mr r3, r31 + lwz r7, VCPU_VRSAVE_TM(r3) mtspr SPRN_VRSAVE, r7 - ld r5, VCPU_LR_TM(r4) - lwz r6, VCPU_CR_TM(r4) - ld r7, VCPU_CTR_TM(r4) - ld r8, VCPU_AMR_TM(r4) - ld r9, VCPU_TAR_TM(r4) - ld r10, VCPU_XER_TM(r4) + ld r5, VCPU_LR_TM(r3) + lwz r6, VCPU_CR_TM(r3) + ld r7, VCPU_CTR_TM(r3) + ld r8, VCPU_AMR_TM(r3) + ld r9, VCPU_TAR_TM(r3) + ld r10, VCPU_XER_TM(r3) mtlr r5 mtcr r6 mtctr r7 @@ -219,8 +226,8 @@ _GLOBAL(kvmppc_restore_tm) * till the last moment to avoid running with userspace PPR and DSCR for * too long. */ - ld r29, VCPU_DSCR_TM(r4) - ld r30, VCPU_PPR_TM(r4) + ld r29, VCPU_DSCR_TM(r3) + ld r30, VCPU_PPR_TM(r3) std r2, PACATMSCRATCH(r13) /* Save TOC */ @@ -253,8 +260,7 @@ _GLOBAL(kvmppc_restore_tm) ld r29, HSTATE_DSCR(r13) mtspr SPRN_DSCR, r29 #endif - ld r4, HSTATE_KVM_VCPU(r13) - ld r1, HSTATE_HOST_R1(r13) + ld r1, HSTATE_SCRATCH2(r13) ld r2, PACATMSCRATCH(r13) /* Set the MSR RI since we have our registers back. */ @@ -264,4 +270,5 @@ _GLOBAL(kvmppc_restore_tm) ld r0, PPC_LR_STKOFF(r1) mtlr r0 blr + #endif From patchwork Thu Jan 11 10:11:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858978 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Ru4EhQ76"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHM9x0mTZz9t5n for ; Thu, 11 Jan 2018 21:12:05 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933177AbeAKKME (ORCPT ); Thu, 11 Jan 2018 05:12:04 -0500 Received: from mail-pf0-f193.google.com ([209.85.192.193]:40838 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933149AbeAKKMC (ORCPT ); Thu, 11 Jan 2018 05:12:02 -0500 Received: by mail-pf0-f193.google.com with SMTP id i66so1304535pfd.7; Thu, 11 Jan 2018 02:12:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iqLrOER+eC+3uHBd4xUOXubvHwiqGbRcZ+0On3c9pQc=; b=Ru4EhQ767/hawIA43DRHHRx8BnAoEzkg20/e85bbozn1ITIyo86eCe9vTh06C8dufv OkKSxrxHIAcJ8OKyHu2uGljdx0PA9Ot/LQck47QRdeYe5Xx4ZEWlTJmu1ndGd25OQlJU j+fTqmqmjBQ29QMrrS49udMDdMXGBF/wvgsg57VErkxZJJ0oDuKM4y0JYjxM8PhK9S85 9hl5Z+LHdL7vJsVPPkrdYT1kjr5fp1JVsJCKJG8VHkykXXvBB2pkB5ljra7zTUrLlXej xsYeaSvUM6XlfuQ20Im5r1pawAWrv+Hj+GpNbKr0mjN+GIzotW6I0KQVmAlPZNgImYZD 8AUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iqLrOER+eC+3uHBd4xUOXubvHwiqGbRcZ+0On3c9pQc=; b=k/F26cDPjjmRF8OI3vURjrPl3ise+vHnfd7vDytWhU+1wdPxPQX/Ns5n8pn3oP8ZN4 JZCJYonO53AjB90ep6c85gCYz0/Z+gyXgqzfPwrVvN1Y/6nhFY+lJiFlohwoLMnOcvqA vl5njvx3hr7RuPgNkGEit05LFRk9cAlk2vZJN2n9VNx3z8KGFa3RdFKLNZy9/4KQtxs/ nbO/w4qAzT2WYTbLcBJLjusKs4hOoSwxipF3WfoYP7L6XCVqhXBTwEyYq0JO0+6aeJM8 LQk89KcbfYRLqZ4WuvPupErp9SiXlNGAk0BWinoSkWCMyagNa7zYdVM6/mfGur59wWgx Ovgw== X-Gm-Message-State: AKwxytcr7PsIniQ5LM+RR9HQvaYz7xiHqIXkTuXgEyH+LZ9usLkG2x5x bU+C5imlsSzsSqmanM3OsT7DZA== X-Google-Smtp-Source: ACJfBot3Bvsbp4TFWZq1IUB763WC4n2IIQaVCuulUNy1dO4O/Quiwe0+Aek5yLqxg0FTi6OYG0aTzg== X-Received: by 10.84.248.135 with SMTP id q7mr1356679pll.86.1515665522155; Thu, 11 Jan 2018 02:12:02 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.11.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:01 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 03/26] KVM: PPC: Book3S PR: turn on FP/VSX/VMX MSR bits in kvmppc_save_tm() Date: Thu, 11 Jan 2018 18:11:16 +0800 Message-Id: <1515665499-31710-4-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo kvmppc_save_tm() invokes store_fp_state/store_vr_state(). So it is mandatory to turn on FP/VSX/VMX MSR bits for its execution, just like what kvmppc_restore_tm() did. Previsouly HV KVM has turned the bits on outside of function kvmppc_save_tm(). Now we include this bit change in kvmppc_save_tm() so that the logic is more clean. And PR KVM can reuse it later. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/kvm/tm.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/kvm/tm.S b/arch/powerpc/kvm/tm.S index e779b15..2d6fe5b 100644 --- a/arch/powerpc/kvm/tm.S +++ b/arch/powerpc/kvm/tm.S @@ -43,6 +43,8 @@ _GLOBAL(kvmppc_save_tm) mfmsr r8 li r0, 1 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG + ori r8, r8, MSR_FP + oris r8, r8, (MSR_VEC | MSR_VSX)@h mtmsrd r8 rldicl. r4, r4, 64 - MSR_TS_S_LG, 62 From patchwork Thu Jan 11 10:11:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858979 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QlIkGvYM"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHMB00t45z9t3w for ; Thu, 11 Jan 2018 21:12:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933149AbeAKKMH (ORCPT ); Thu, 11 Jan 2018 05:12:07 -0500 Received: from mail-pg0-f67.google.com ([74.125.83.67]:33957 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933119AbeAKKMG (ORCPT ); Thu, 11 Jan 2018 05:12:06 -0500 Received: by mail-pg0-f67.google.com with SMTP id j4so1883336pgp.1; Thu, 11 Jan 2018 02:12:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ujk2s772VVdSlzpiCSQFbwpyFwXPLK5rnFJFaf2nmIg=; b=QlIkGvYMdIVaniC3C+UkYI4WGKjrAc32Ug027YuIWUhbK78PVzsHtTddnKRBhZka2o 28rIyQjxVU1DmIo1Gn+3ehFUq15hExuhO6UDOzlH3ifFPjyalXbEIWTKUyEHH/XHA2S7 Zn7QQ3vmwWZ44ThsXZu4Xi7cVT+pALgnTg3YjLceqaBfGJdnLuIlmb59p3cyVN8NZVty BSXqa4nKxacSD2xR8ETSp5pBefzDQKu7Bd1gdJ3F/liYfidVhSeWPI5x1Es1DzHxQrK3 7Eshv/sBoZkI4LqRL2W7onnhlRgOApEqRHFi8zQLLy4VGlBQSi3VoJGRv6Yrjl2WG2Ma vjEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ujk2s772VVdSlzpiCSQFbwpyFwXPLK5rnFJFaf2nmIg=; b=bfTXSTtVmN67P150X3W9aS+bHK7lC+vV3NI7Wc3+XB9fM4fvC/vpjL9KyZ/S4xlYQb SExX3ZLY9YV9vOclyea0yrHInpt9EW8aBNzHIjLgWbwr87fJ+qgtD7NxJ2kOXs4xYP5r KuTQvXzjJtTUa9lij5mViBSAupHmaBTRPa5A0GCvyn1SIQT/0hR5WR3nT2Cnt6tQlYMF e7yMScMU3pr68pTHZw9mDN3/nL+SCla95zTH+xdXW2beafx55bOcOR3j6M25Mvm4EjEU /ty4OINg6YgdNH4zKGfYMPfMXM/gza5WFRHSw2Y66VsXOWN35etqZY2EE+wFQtcOdKsD DhBg== X-Gm-Message-State: AKwxytdubUMG6COeWlG1W/1bCOUTd4nrn7hH+AaszKdutprdGIJLCSev HuC/80TPFB6gH+ozI4eglAw= X-Google-Smtp-Source: ACJfBouetpzDlMaPQtj5CqK4H7n9PeIcm0qvHp2+v4TBqw018doSXqp8KSUjvvD54/EcnqL+wJ1Pag== X-Received: by 10.159.229.3 with SMTP id s3mr1994949plq.161.1515665525582; Thu, 11 Jan 2018 02:12:05 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:05 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 04/26] KVM: PPC: Book3S PR: add C function wrapper for _kvmppc_save/restore_tm() Date: Thu, 11 Jan 2018 18:11:17 +0800 Message-Id: <1515665499-31710-5-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo Currently _kvmppc_save/restore_tm() APIs can only be invoked from assembly function. This patch adds C function wrappers for them so that they can be safely called from C function. Signed-off-by: Simon Guo --- arch/powerpc/include/asm/asm-prototypes.h | 7 ++ arch/powerpc/kvm/book3s_hv_rmhandlers.S | 8 +-- arch/powerpc/kvm/tm.S | 107 +++++++++++++++++++++++++++++- 3 files changed, 116 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/asm-prototypes.h b/arch/powerpc/include/asm/asm-prototypes.h index 7330150..9c3b290 100644 --- a/arch/powerpc/include/asm/asm-prototypes.h +++ b/arch/powerpc/include/asm/asm-prototypes.h @@ -126,4 +126,11 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4, void _mcount(void); unsigned long prepare_ftrace_return(unsigned long parent, unsigned long ip); +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM +/* Transaction memory related */ +struct kvm_vcpu; +void _kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu, u64 guest_msr); +void _kvmppc_save_tm_pr(struct kvm_vcpu *vcpu, u64 guest_msr); +#endif + #endif /* _ASM_POWERPC_ASM_PROTOTYPES_H */ diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S index 613fd27..4c8d5b1 100644 --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S @@ -810,7 +810,7 @@ BEGIN_FTR_SECTION */ mr r3, r4 ld r4, VCPU_MSR(r3) - bl kvmppc_restore_tm + bl __kvmppc_restore_tm ld r4, HSTATE_KVM_VCPU(r13) END_FTR_SECTION_IFSET(CPU_FTR_TM) #endif @@ -1685,7 +1685,7 @@ BEGIN_FTR_SECTION */ mr r3, r9 ld r4, VCPU_MSR(r3) - bl kvmppc_save_tm + bl __kvmppc_save_tm ld r9, HSTATE_KVM_VCPU(r13) END_FTR_SECTION_IFSET(CPU_FTR_TM) #endif @@ -2551,7 +2551,7 @@ BEGIN_FTR_SECTION */ ld r3, HSTATE_KVM_VCPU(r13) ld r4, VCPU_MSR(r3) - bl kvmppc_save_tm + bl __kvmppc_save_tm END_FTR_SECTION_IFSET(CPU_FTR_TM) #endif @@ -2665,7 +2665,7 @@ BEGIN_FTR_SECTION */ mr r3, r4 ld r4, VCPU_MSR(r3) - bl kvmppc_restore_tm + bl __kvmppc_restore_tm ld r4, HSTATE_KVM_VCPU(r13) END_FTR_SECTION_IFSET(CPU_FTR_TM) #endif diff --git a/arch/powerpc/kvm/tm.S b/arch/powerpc/kvm/tm.S index 2d6fe5b..5752bae 100644 --- a/arch/powerpc/kvm/tm.S +++ b/arch/powerpc/kvm/tm.S @@ -35,7 +35,7 @@ * This can modify all checkpointed registers, but * restores r1, r2 before exit. */ -_GLOBAL(kvmppc_save_tm) +_GLOBAL(__kvmppc_save_tm) mflr r0 std r0, PPC_LR_STKOFF(r1) @@ -149,6 +149,58 @@ _GLOBAL(kvmppc_save_tm) blr /* + * _kvmppc_save_tm() is a wrapper around __kvmppc_save_tm(), so that it can + * be invoked from C function by PR KVM only. + */ +_GLOBAL(_kvmppc_save_tm_pr) + mflr r5 + std r5, PPC_LR_STKOFF(r1) + stdu r1, -SWITCH_FRAME_SIZE(r1) + SAVE_NVGPRS(r1) + + /* save MSR since TM/math bits might be impacted + * by __kvmppc_save_tm(). + */ + mfmsr r5 + SAVE_GPR(5, r1) + + /* also save DSCR/CR so that it can be recovered later */ + mfspr r6, SPRN_DSCR + SAVE_GPR(6, r1) + + mfcr r7 + stw r7, _CCR(r1) + + /* allocate stack frame for __kvmppc_save_tm since + * it will save LR into its stackframe and we don't + * want to corrupt _kvmppc_save_tm_pr's. + */ + stdu r1, -PPC_MIN_STKFRM(r1) + bl __kvmppc_save_tm + addi r1, r1, PPC_MIN_STKFRM + + ld r7, _CCR(r1) + mtcr r7 + + REST_GPR(6, r1) + mtspr SPRN_DSCR, r6 + + /* need preserve current MSR's MSR_TS bits */ + REST_GPR(5, r1) + mfmsr r6 + rldicl r6, r6, 64 - MSR_TS_S_LG, 62 + rldimi r5, r6, MSR_TS_S_LG, 63 - MSR_TS_T_LG + mtmsrd r5 + + REST_NVGPRS(r1) + addi r1, r1, SWITCH_FRAME_SIZE + ld r5, PPC_LR_STKOFF(r1) + mtlr r5 + blr + +EXPORT_SYMBOL_GPL(_kvmppc_save_tm_pr); + +/* * Restore transactional state and TM-related registers. * Called with: * - r3 pointing to the vcpu struct. @@ -158,7 +210,7 @@ _GLOBAL(kvmppc_save_tm) * This potentially modifies all checkpointed registers. * It restores r1, r2 from the PACA. */ -_GLOBAL(kvmppc_restore_tm) +_GLOBAL(__kvmppc_restore_tm) mflr r0 std r0, PPC_LR_STKOFF(r1) @@ -186,6 +238,7 @@ _GLOBAL(kvmppc_restore_tm) rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 beqlr /* TM not active in guest */ std r1, HSTATE_SCRATCH2(r13) + std r3, HSTATE_SCRATCH1(r13) /* Make sure the failure summary is set, otherwise we'll program check * when we trechkpt. It's possible that this might have been not set @@ -262,6 +315,7 @@ _GLOBAL(kvmppc_restore_tm) ld r29, HSTATE_DSCR(r13) mtspr SPRN_DSCR, r29 #endif + ld r3, HSTATE_SCRATCH1(r13) ld r1, HSTATE_SCRATCH2(r13) ld r2, PACATMSCRATCH(r13) @@ -273,4 +327,53 @@ _GLOBAL(kvmppc_restore_tm) mtlr r0 blr +/* + * _kvmppc_restore_tm() is a wrapper around __kvmppc_restore_tm(), so that it + * can be invoked from C function by PR KVM only. + */ +_GLOBAL(_kvmppc_restore_tm_pr) + mflr r5 + std r5, PPC_LR_STKOFF(r1) + stdu r1, -SWITCH_FRAME_SIZE(r1) + SAVE_NVGPRS(r1) + + /* save MSR to avoid TM/math bits change */ + mfmsr r5 + SAVE_GPR(5, r1) + + /* also save DSCR/CR so that it can be recovered later */ + mfspr r6, SPRN_DSCR + SAVE_GPR(6, r1) + + mfcr r7 + stw r7, _CCR(r1) + + /* allocate stack frame for __kvmppc_restore_tm since + * it will save LR into its own stackframe. + */ + stdu r1, -PPC_MIN_STKFRM(r1) + + bl __kvmppc_restore_tm + addi r1, r1, PPC_MIN_STKFRM + + ld r7, _CCR(r1) + mtcr r7 + + REST_GPR(6, r1) + mtspr SPRN_DSCR, r6 + + /* need preserve current MSR's MSR_TS bits */ + REST_GPR(5, r1) + mfmsr r6 + rldicl r6, r6, 64 - MSR_TS_S_LG, 62 + rldimi r5, r6, MSR_TS_S_LG, 63 - MSR_TS_T_LG + mtmsrd r5 + + REST_NVGPRS(r1) + addi r1, r1, SWITCH_FRAME_SIZE + ld r5, PPC_LR_STKOFF(r1) + mtlr r5 + blr + +EXPORT_SYMBOL_GPL(_kvmppc_restore_tm_pr); #endif From patchwork Thu Jan 11 10:11:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858980 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="rlAiGuCk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHMB45lRWz9t4t for ; Thu, 11 Jan 2018 21:12:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933119AbeAKKML (ORCPT ); Thu, 11 Jan 2018 05:12:11 -0500 Received: from mail-pf0-f194.google.com ([209.85.192.194]:43176 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932684AbeAKKMK (ORCPT ); Thu, 11 Jan 2018 05:12:10 -0500 Received: by mail-pf0-f194.google.com with SMTP id e3so1306156pfi.10; Thu, 11 Jan 2018 02:12:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RtWOQENhvsiUnDxkcXPhmW4BvfvsgOyddlcayjaGgyY=; b=rlAiGuCkKdP5A7Apqsvanp/n5CtqFJEsdScNohIoKmd7+cl5pyzX0hgg30rAWEe/Uh nGPJKCE8cQe/n1w+GAzpmlX2RwkJbCN/hznal8X0P/LF/PLBo0KBgqPFnmdNI2Uv+brw 79o8rht1IfsnVH48mXkGsU5ZptfctJtRflyQpMxVHZ887ah9mOlY/eqbqPLQ890/bksT isPNWzXmNnRqjtt4isG0/y7rs9aVg2feIYSt1ONFUa4BSykeQrvDsrnNgYLKOz+YBtSX oUNojoLSj+H5tJJDBIDMQADvE6nD4RxoBxbR/OLOEaovNHsHucOrG02k/QxywPH8xthk bfOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RtWOQENhvsiUnDxkcXPhmW4BvfvsgOyddlcayjaGgyY=; b=qS++NUdJCLlsXrFNiD8kh7AM71f/4v3+ly+a9+EGeqmSietAM3PrwXoqU/dT5jgjCh I8vavrrxG+KDmUK0iagR7gE/FYo/blzAOaxhBiGBxhkAsZdrkabtYr6PzHKs4cOzQ34B dOj43JzRl/qdplxzcFR2yf3lkHOQTdiDdMgz6BWMUJn0cOCQBEsmV6JdgQskYvVkDia7 ikkOG/gZV4orx5nEwEVXac91e82pAQWnG6hopw4Fc0g5fHoOpmwS2jN2J6AjMCACqBZB +hZW5vOO11f046eXmd+oUeUa7Ds+0fIiqos7cdrZq2CVr7rmLKmg986yVaiqT5nU0ZwC zILg== X-Gm-Message-State: AKGB3mJ4hjymTmoZsMuYmjRnoSV2E7l89G4Fs8Kkpnn/8qQfd3Tcb34t R/zSnxaP61np0MNDEnGnTrlcug== X-Google-Smtp-Source: ACJfBosj236ZGPXDqxi1H1Y2i3vk22pBCz3gx4Z5lWJl96rt+ZFiXG9aSozNc77Z0dcEJey0r+2k2Q== X-Received: by 10.99.99.129 with SMTP id x123mr15111493pgb.437.1515665529761; Thu, 11 Jan 2018 02:12:09 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:09 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 05/26] KVM: PPC: Book3S PR: In PR KVM suspends Transactional state when inject an interrupt. Date: Thu, 11 Jan 2018 18:11:18 +0800 Message-Id: <1515665499-31710-6-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo This patch simulates interrupt behavior per Power ISA while injecting interrupt in PR KVM: - When interrupt happens, transactional state should be suspended. kvmppc_mmu_book3s_64_reset_msr() will be invoked when injecting an interrupt. This patch performs this ISA logic in kvmppc_mmu_book3s_64_reset_msr(). Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/kvm/book3s_64_mmu.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kvm/book3s_64_mmu.c b/arch/powerpc/kvm/book3s_64_mmu.c index 29ebe2f..6048dbd 100644 --- a/arch/powerpc/kvm/book3s_64_mmu.c +++ b/arch/powerpc/kvm/book3s_64_mmu.c @@ -38,7 +38,16 @@ static void kvmppc_mmu_book3s_64_reset_msr(struct kvm_vcpu *vcpu) { - kvmppc_set_msr(vcpu, vcpu->arch.intr_msr); + unsigned long msr = vcpu->arch.intr_msr; + unsigned long cur_msr = kvmppc_get_msr(vcpu); + + /* If transactional, change to suspend mode on IRQ delivery */ + if (MSR_TM_TRANSACTIONAL(cur_msr)) + msr |= MSR_TS_S; + else + msr |= cur_msr & MSR_TS_MASK; + + kvmppc_set_msr(vcpu, msr); } static struct kvmppc_slb *kvmppc_mmu_book3s_64_find_slbe( From patchwork Thu Jan 11 10:11:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858981 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LeiIuXdE"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHMB7016vz9t41 for ; Thu, 11 Jan 2018 21:12:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932985AbeAKKMO (ORCPT ); Thu, 11 Jan 2018 05:12:14 -0500 Received: from mail-pf0-f193.google.com ([209.85.192.193]:34706 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932684AbeAKKMM (ORCPT ); Thu, 11 Jan 2018 05:12:12 -0500 Received: by mail-pf0-f193.google.com with SMTP id e76so1307294pfk.1; Thu, 11 Jan 2018 02:12:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=biEL1BN4lVeQIKN91OlBgmTC7bljBxVFN2NsviMchfU=; b=LeiIuXdEdjMlP6So+Ne76QDlNo0YAzbpdWpLQi+u4nzVK1pQN2kUgIF1B1w1UOKBcB uuzNfOUvJ4/fYkQBesaE/U7jVGz50N585ms80+ZX13p4rC68WXnSWcLAiMNLFU/8GXkI YCG9nBVIMpjI9EiA5Zh24h2pDO4uUmxUhHmHbNPoRfon6n7mD+R7KSWTtXgjTrZTzVzM gZFisPbdT0/4Dy7lI7J4V9a6+gDTMX7ePf/EG+/lEVRj7Mf/qPQ5s7nXUMREBkI9yDe+ TRRO+gSS7ddZMqnL0dVAulx03KIwaEfkRo7Mi+5VZOpxkqwFGGs/MizwDmLUV537Hi/J r05g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=biEL1BN4lVeQIKN91OlBgmTC7bljBxVFN2NsviMchfU=; b=g+tEHiTVjIwR2Ubs0CXrHs8IqB4FDN8j4luI3uVoMEijyuN0KGQF0Ndnznb7iLfTgc iJ4lI0YJw5ZJ6Gk9LrWX8Y5AzZIldYSm9lzBqI02UtESCVMx11yAjl4Jl95uEqw+U0hZ iDx8pQqUkhyUxpe8cCIKRNchmYGasCZlEgRNfCY0iDxmyN+mMg2AUY1OMQtJiEiDjnOw 98arbJ88USffUwrHEBo50J9jFFEnC+4Xd/tbxLp1pLmVAZmDppbVTGxp5zOvowhArluO ktc4GVKqE8NkDKWLDEoFdxnKnxw3oCjUsxl71nro8lbl4A1zAzJLvv0lHpb2uZrfjsDP /eWg== X-Gm-Message-State: AKGB3mI4g0qRrG7q0oRHOLLxh7Y6M/A3HH7kaSWgsh7mCXVaOx5G1S87 hRJ+ZIeJtucv1bjdxyG1gO8= X-Google-Smtp-Source: ACJfBouVsUshLBOy0Z/anaOYip2qXgSO4Z0gSvnXPG8BunZa4J62FL3glfQN+4w4sVOtz64IgfJXuA== X-Received: by 10.98.16.132 with SMTP id 4mr12418752pfq.42.1515665532430; Thu, 11 Jan 2018 02:12:12 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:11 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 06/26] KVM: PPC: Book3S PR: PR KVM pass through MSR TM/TS bits to shadow_msr. Date: Thu, 11 Jan 2018 18:11:19 +0800 Message-Id: <1515665499-31710-7-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo PowerPC TM functionality needs MSR TM/TS bits support in hardware level. Guest TM functionality can not be emulated with "fake" MSR (msr in magic page) TS bits. This patch syncs TM/TS bits in shadow_msr with the MSR value in magic page, so that the MSR TS value which guest sees is consistent with actual MSR bits running in guest. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/kvm/book3s_pr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index d0dc862..4e9acdd 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -322,7 +322,12 @@ static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu) ulong smsr = guest_msr; /* Guest MSR values */ +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE | + MSR_TM | MSR_TS_MASK; +#else smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE; +#endif /* Process MSR values */ smsr |= MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_PR | MSR_EE; /* External providers the guest reserved */ From patchwork Thu Jan 11 10:11:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858982 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="trZI2Lib"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHMBD2s6wz9t3n for ; Thu, 11 Jan 2018 21:12:20 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933240AbeAKKMR (ORCPT ); Thu, 11 Jan 2018 05:12:17 -0500 Received: from mail-pg0-f65.google.com ([74.125.83.65]:40886 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933227AbeAKKMP (ORCPT ); Thu, 11 Jan 2018 05:12:15 -0500 Received: by mail-pg0-f65.google.com with SMTP id q12so1863985pgt.7; Thu, 11 Jan 2018 02:12:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pNkUP1d4Pto6aqXZ6++37EGX0AOPSHUUOSr1SA1EmTU=; b=trZI2Lib5RmH4K+39OENBBu9vSHM/nB3frfu+lG1J72uUc1uFm1aHgAl4PMWEwCZwZ mZJ9PMaImZs3xtg0YhlYw8pWyANQvVLWkMv6LECNqtkRjpIsGt8GdrozHCBCutYgJbWv s2ve7qI62/nG//bHjXHlNU0PSfHD3J+RukHH4VoJPyUXzYx6iUQdNTD6PvOAd/ecOWwn C3rRWKP3m8NaTPh+m90s7v4o67MgL0OFLgbnu3mZaT2TSxVfASqF5zFk9sjRAp9BtyD4 hN/nD+M01xh/1YCPjGWRQ9wHqpXdHdJvyY42VnXMlGZ6wSvS/hLOzczfQVFsy8L+J92W +KdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pNkUP1d4Pto6aqXZ6++37EGX0AOPSHUUOSr1SA1EmTU=; b=YiL0QGjFBskNNRDXZDBprKh1mjTEtEnRTUuBf+keus3FeZvnTR57QiaoNk6nyWZ2GM 9lrutfEZCOFo45oTCd8mFJIzTfwh6rFSVC5OsUT5jitJbNiZfCg+vrKdKi3dG8cqpn3u lPpTzG+BRO9LWhKRyMsMckM3Kcd5fcLaiK+YVSty2Teb32+XOoJYEDnsTjs8nbSsaz4G WfwEjxPlefBhjFHfJAI3ZjAVpgl4wwregDAgBmFX+9leWW96BDkyoCkQ29WU/58msGU9 IKCNy+DvcnGcqAL/js7dCY2PbP03v5zE/fHOTqvPTfzu9H5c8f7MYl/g8GRGkdN7DAnZ ONnw== X-Gm-Message-State: AKGB3mJH+D2BeXNL3fNZfISb5aPJUKPQrmGsH0oG5sTD+x1o36XvXOzX 6ZYEHr5xIQG4FLoA2PMOrFQ= X-Google-Smtp-Source: ACJfBovAlz091BcNpUM/k1vAzZKWVYXEPkalb+GZhFT/oAzpoJyytKyYyDHQHYt+CkhJNhKtQNsVMQ== X-Received: by 10.98.6.130 with SMTP id 124mr19480713pfg.8.1515665535405; Thu, 11 Jan 2018 02:12:15 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:14 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 07/26] KVM: PPC: Book3S PR: add TEXASR related macros Date: Thu, 11 Jan 2018 18:11:20 +0800 Message-Id: <1515665499-31710-8-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo This patches add some macros for CR0/TEXASR bits so that PR KVM TM logic(tbegin./treclaim./tabort.) can make use of them later. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/include/asm/reg.h | 21 ++++++++++++++++++++- arch/powerpc/platforms/powernv/copy-paste.h | 3 +-- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index b779f3c..6c293bc 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -146,6 +146,12 @@ #define MSR_64BIT 0 #endif +/* Condition Register related */ +#define CR0_SHIFT 28 +#define CR0_MASK 0xF +#define CR0_TBEGIN_FAILURE (0x2 << 28) /* 0b0010 */ + + /* Power Management - Processor Stop Status and Control Register Fields */ #define PSSCR_RL_MASK 0x0000000F /* Requested Level */ #define PSSCR_MTL_MASK 0x000000F0 /* Maximum Transition Level */ @@ -237,8 +243,21 @@ #define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */ #define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */ #define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */ -#define TEXASR_FS __MASK(63-36) /* TEXASR Failure Summary */ +#define TEXASR_FC_LG (63 - 7) /* Failure Code */ +#define TEXASR_HV_LG (63 - 34) /* Hypervisor state*/ +#define TEXASR_PR_LG (63 - 35) /* Privilege level */ +#define TEXASR_FS_LG (63 - 36) /* failure summary */ +#define TEXASR_EX_LG (63 - 37) /* TFIAR exact bit */ +#define TEXASR_ROT_LG (63 - 38) /* ROT bit */ +#define TEXASR_FC (ASM_CONST(0xFF) << TEXASR_FC_LG) +#define TEXASR_HV __MASK(TEXASR_HV_LG) +#define TEXASR_PR __MASK(TEXASR_PR_LG) +#define TEXASR_FS __MASK(TEXASR_FS_LG) +#define TEXASR_EX __MASK(TEXASR_EX_LG) +#define TEXASR_ROT __MASK(TEXASR_ROT_LG) + #define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */ + #define SPRN_TIDR 144 /* Thread ID register */ #define SPRN_CTRLF 0x088 #define SPRN_CTRLT 0x098 diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h index c9a5036..3fa62de 100644 --- a/arch/powerpc/platforms/powernv/copy-paste.h +++ b/arch/powerpc/platforms/powernv/copy-paste.h @@ -7,9 +7,8 @@ * 2 of the License, or (at your option) any later version. */ #include +#include -#define CR0_SHIFT 28 -#define CR0_MASK 0xF /* * Copy/paste instructions: * From patchwork Thu Jan 11 10:11:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858983 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LO1Wu0rs"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHMBG48bVz9t6B for ; Thu, 11 Jan 2018 21:12:22 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933221AbeAKKMV (ORCPT ); Thu, 11 Jan 2018 05:12:21 -0500 Received: from mail-pf0-f194.google.com ([209.85.192.194]:35605 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933227AbeAKKMS (ORCPT ); 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Thu, 11 Jan 2018 02:12:18 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:17 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 08/26] KVM: PPC: Book3S PR: Sync TM bits to shadow msr for problem state guest Date: Thu, 11 Jan 2018 18:11:21 +0800 Message-Id: <1515665499-31710-9-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo MSR TS bits can be modified with non-privileged instruction like tbegin./tend. That means guest can change MSR value "silently" without notifying host. It is necessary to sync the TM bits to host so that host can calculate shadow msr correctly. note privilege guest will always fail transactions so we only take care of problem state guest. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/kvm/book3s_pr.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index 4e9acdd..7ec866a 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -977,6 +977,9 @@ int kvmppc_handle_exit_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, { int r = RESUME_HOST; int s; +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + ulong old_msr = kvmppc_get_msr(vcpu); +#endif vcpu->stat.sum_exits++; @@ -988,6 +991,28 @@ int kvmppc_handle_exit_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, trace_kvm_exit(exit_nr, vcpu); guest_exit(); +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + /* + * Unlike other MSR bits, MSR[TS]bits can be changed at guest without + * notifying host: + * modified by unprivileged instructions like "tbegin"/"tend"/ + * "tresume"/"tsuspend" in PR KVM guest. + * + * It is necessary to sync here to calculate a correct shadow_msr. + * + * privileged guest's tbegin will be failed at present. So we + * only take care of problem state guest. + */ + if (unlikely((old_msr & MSR_PR) && + (vcpu->arch.shadow_srr1 & (MSR_TS_MASK)) != + (old_msr & (MSR_TS_MASK)))) { + old_msr &= ~(MSR_TS_MASK); + old_msr |= (vcpu->arch.shadow_srr1 & (MSR_TS_MASK)); + kvmppc_set_msr_fast(vcpu, old_msr); + kvmppc_recalc_shadow_msr(vcpu); + } +#endif + switch (exit_nr) { case BOOK3S_INTERRUPT_INST_STORAGE: { From patchwork Thu Jan 11 10:11:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858984 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="J2wur7XC"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHMBJ5wn6z9t5Q for ; Thu, 11 Jan 2018 21:12:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932684AbeAKKMY (ORCPT ); Thu, 11 Jan 2018 05:12:24 -0500 Received: from mail-pf0-f195.google.com ([209.85.192.195]:47015 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932982AbeAKKMX (ORCPT ); Thu, 11 Jan 2018 05:12:23 -0500 Received: by mail-pf0-f195.google.com with SMTP id y5so1309490pff.13; Thu, 11 Jan 2018 02:12:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Fd7zRPuC8QHUggE7nig11elvhE6bWqgSLOfzfP6sqbc=; b=J2wur7XCgvB4A7neeBgIP/V/4jNqG52LmwoIa/kn6/2ycLsW+23e8qS3djSnS8jMY7 7i22rH55FXBk9YEYNEWfoK78B5VOUBdBKnJfalqiEV/aufJUOx53Ow9o70ZKA9w7fMiu P2g9naXeft8aS00zsL5S2Dmp9AIzxN2F+OonbvAhbB2FmU5dRsjPQhDONqrDw6XqDN/h CjTD8v0SaO+1a1Tvc5sBxVunw7JyjX36iDIRlAiDqfx8/x2IO/x2tcgdeRR325awrP+X ZCcy6r9UK4e/iY/XdIko2SfN2p6YHu0NkGnE+0vcxKnHQX9zFfH02cMS3ELI54wF2eVV cayg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Fd7zRPuC8QHUggE7nig11elvhE6bWqgSLOfzfP6sqbc=; b=kzUDHLrA7wgZxL4MhVthBVpSRe5d8bYG/+dNcz0wzHgedI+v0K8D0/x4SfDia1Xl2X mwUORF2Tm1251LEJ0//+DNRNQmpHArER1bDfhZRaK26vLvMf6+Uf8pFT2nb8/NI0GD1o rvlAI3n/n4hY1yALDkFEETsZ6tsxODVX/MNx3cb5pnSJHXmBiZ1ozjEJJ7XeZOiv07Bd WEkods1LhWJ3OO2Mc/EgQTXKedclWmeQa4qb7f1AnAUzXQJbqKASnBmOeFgbuNjrO1re wgcaEra2uUw51E8LvfJUSfZR+mk1+P+UFfoxXqplzsWSKBD3QTFBt3DwtDTEdIRsLdjz /gnw== X-Gm-Message-State: AKGB3mJFChro4X/yM4VxWxGGLYRt4rLX8ZNHapD1wRgw+Eiasa7gLrGv 7W6aXXsxnDCFGsYadwAZZu8= X-Google-Smtp-Source: ACJfBottUy0wNO/wJHR8X2nmES2VGMPORX3Sv104aI8d6iVIs0PI6WEP0r2fXgU3SXKXwWAb4VPuQQ== X-Received: by 10.99.163.96 with SMTP id v32mr10918936pgn.432.1515665542682; Thu, 11 Jan 2018 02:12:22 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:22 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 09/26] KVM: PPC: Book3S PR: implement RFID TM behavior to suppress change from S0 to N0 Date: Thu, 11 Jan 2018 18:11:22 +0800 Message-Id: <1515665499-31710-10-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo Accordingly to ISA specification for RFID, in MSR TM disabled and TS suspended state(S0), if the target MSR is TM disabled and TS state is inactive(N0), rfid should suppress this update. This patch make RFID emulation of PR KVM to be consistent with this. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/kvm/book3s_emulate.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c index 68d6898..2eb457b 100644 --- a/arch/powerpc/kvm/book3s_emulate.c +++ b/arch/powerpc/kvm/book3s_emulate.c @@ -117,11 +117,28 @@ int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, case 19: switch (get_xop(inst)) { case OP_19_XOP_RFID: - case OP_19_XOP_RFI: + case OP_19_XOP_RFI: { + unsigned long srr1 = kvmppc_get_srr1(vcpu); +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + unsigned long cur_msr = kvmppc_get_msr(vcpu); + + /* + * add rules to fit in ISA specification regarding TM + * state transistion in TM disable/Suspended state, + * and target TM state is TM inactive(00) state. (the + * change should be suppressed). + */ + if (((cur_msr & MSR_TM) == 0) && + ((srr1 & MSR_TM) == 0) && + MSR_TM_SUSPENDED(cur_msr) && + !MSR_TM_ACTIVE(srr1)) + srr1 |= MSR_TS_S; +#endif kvmppc_set_pc(vcpu, kvmppc_get_srr0(vcpu)); - kvmppc_set_msr(vcpu, kvmppc_get_srr1(vcpu)); + kvmppc_set_msr(vcpu, srr1); *advance = 0; break; + } default: emulated = EMULATE_FAIL; From patchwork Thu Jan 11 10:11:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858985 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="e2VADSz5"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHMBN6pB9z9t44 for ; Thu, 11 Jan 2018 21:12:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933261AbeAKKM1 (ORCPT ); Thu, 11 Jan 2018 05:12:27 -0500 Received: from mail-pf0-f193.google.com ([209.85.192.193]:34740 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932982AbeAKKM0 (ORCPT ); Thu, 11 Jan 2018 05:12:26 -0500 Received: by mail-pf0-f193.google.com with SMTP id e76so1307700pfk.1; Thu, 11 Jan 2018 02:12:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eT4BDlNIqleU/m87GmIEjCEDyR7qHDW+W3PCFt7PDyY=; b=e2VADSz5knX6hTdBfhwjiCjStcIS2K8B++BKvaPfiqPcTDBSskzgKIuYq3VRYF2iyB YZI6Ma3uzR3YWVS6Ry8S6ar5IC488ju6+xxzoANSGBOn8TkZYh8LMPtmtz1GOl9ey5HB R7EJvzOVwWqUgYAjmAfuDCdwTxdNiyq3oAecGSSP40EBvKodh7Ph6xqv+ZirTw3fTaKE bMd3lklXgoW8b42I3hOmoafxCgXX7Fn6D0ynfCcZpeaYSyZG5XfrdnMt01tcXCYPOoxA dUVcoeGbdX03WJB+XAMn2G6AwpHDH31u0z4WdGFi100zsawamF56VvJLxpB5gEX+SVl6 gc6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eT4BDlNIqleU/m87GmIEjCEDyR7qHDW+W3PCFt7PDyY=; b=oRqGJyAlNgZN1foE310x4reYRFReku8sECedHe76T+P2i3c9snBmhWkjhAn9rxlITb nXlln+I8/Lf9EQAEPMCJCb1grw6aEP4Onb6aa587qci2XYUq3lhGOa2BWcl3X++ByhMg UT3TKGmPQcqsZuFQ1SqwQ38mCXXN9XoS9JFKTQIFgzVTK5kxcayaSEcXEdoq5RwRwrOv 24j3RGhL5O2hx4WHWzVhdtmKrP8mWjeHTE3zF9fyfWe9zIbRXERqq2myEGWvXiZ3gECZ ryJ2FmHYLWAXSNX7Iunm9iWoZ3tDl2bI9eLFt4EYh5ZvFC6nBDBDTqHYZTulcegh50fW eA9g== X-Gm-Message-State: AKwxytfsx2n3aFdo2/It2S7BSRutke2XYclyFAu2Cj5gF3D9hMZrMVPX XSMKaDZ8Ll950HiyPEXiCWEYUA== X-Google-Smtp-Source: ACJfBotYfngC38zUZaR1mIcDP1DEHwR/OFgp7SPLKGe3E8EPU2o+O3qVpbPbfF+SDdYRy10rAs36zw== X-Received: by 10.84.247.145 with SMTP id o17mr1629971pll.269.1515665546070; Thu, 11 Jan 2018 02:12:26 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:25 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 10/26] KVM: PPC: Book3S PR: set MSR HV bit accordingly for PPC970 and others. Date: Thu, 11 Jan 2018 18:11:23 +0800 Message-Id: <1515665499-31710-11-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo Apple G5 machines(PPC970/FX/GX/MP) have supervisor mode disabled and MSR HV bit is forced into 1. We should follow this in PR KVM guest. This patch set MSR HV=1 for G5 machines and HV=0 for others on PR KVM guest. Signed-off-by: Simon Guo Suggested-by: Paul Mackerras Reviewed-by: Paul Mackerras --- arch/powerpc/kvm/book3s_pr.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index 7ec866a..b2f7566 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -320,6 +320,7 @@ static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu) { ulong guest_msr = kvmppc_get_msr(vcpu); ulong smsr = guest_msr; + u32 guest_pvr = vcpu->arch.pvr; /* Guest MSR values */ #ifdef CONFIG_PPC_TRANSACTIONAL_MEM @@ -334,7 +335,16 @@ static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu) smsr |= (guest_msr & vcpu->arch.guest_owned_ext); /* 64-bit Process MSR values */ #ifdef CONFIG_PPC_BOOK3S_64 - smsr |= MSR_ISF | MSR_HV; + smsr |= MSR_ISF; + + /* for PPC970 chip, its HV bit is hard-wired to 1. For others, + * we should clear HV bit. + */ + if ((PVR_VER(guest_pvr) == PVR_970) || + (PVR_VER(guest_pvr) == PVR_970FX) || + (PVR_VER(guest_pvr) == PVR_970MP) || + (PVR_VER(guest_pvr) == PVR_970GX)) + smsr |= MSR_HV; #endif vcpu->arch.shadow_msr = smsr; } From patchwork Thu Jan 11 10:11:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858986 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="mjkgzvyb"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHMBR46Qqz9t50 for ; Thu, 11 Jan 2018 21:12:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933227AbeAKKMb (ORCPT ); Thu, 11 Jan 2018 05:12:31 -0500 Received: from mail-pf0-f195.google.com ([209.85.192.195]:42281 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932982AbeAKKMa (ORCPT ); Thu, 11 Jan 2018 05:12:30 -0500 Received: by mail-pf0-f195.google.com with SMTP id d23so1311175pfe.9; Thu, 11 Jan 2018 02:12:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VII/ozmMKZUIeV+gwPQyvE/UN00EyCVC3v9unNc3jXc=; b=mjkgzvybCZG79f3Nmz/hRvTpZGDJLMQtyKv+MOlpktymT+yOSJL34EI5awERMdEXZW DOkKIUf2tdSiX5vy0tubdJOI8CO4kEbUOjG6CV+bRUBqnV9gNsYs214YQdoHvRyI8wxm n7kmqTomFvSU/y27m/QsmtRe5opLHD4F1HTeF0ZAlCeLurubUA+hweLKQqa80XNIl32a WTHSurU6cTHsobnR1dFXDh0qrZ1UMnuFYX7QU5UxfwPUHh/6bHNjHq/O1+ioyTT9XDJX JktuTtvZWQa30VcsQnDFsAfSomMs8tZBcqf7MZWc0GkrQYH3KdWhWGgeUp4sgCyx8Dd/ d5/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VII/ozmMKZUIeV+gwPQyvE/UN00EyCVC3v9unNc3jXc=; b=s+Z3876WOOAbODR9+eo0xVTDgCG4FvS6JwIh8ymY4AI3AV7+f2n8m97/SvR39XAPNm D2bqY+aYF4D3EowaCG7AVBn/7G1db8xbXIKXLc6/ZKu9WJ+5njiT16O13w0grSWPCTrr o2amdumMCH6hAwhpCBkzjkkqavdYFwpzerB5zoflKZlJsHYV7VkDf0focvbulIroGDF/ lIMOj8bAZp87P8sORUI9gGBCev+EznsHA6d6dOJQKC9YAz7s13fd9eB460DRzzIuJCK3 13QoRHx/EN+E/Nzb3RhcwoMJVacN33Lbe0m3OHlupMkD8UcvWq3kEPpi4SC/5G1SWK2F cerw== X-Gm-Message-State: AKwxytebf2q5fMx5cZcuFgG+Nb0N2j3wAuEcvScW4LqYA8aBb3AoY6cK x4z1Khci6ugBvROBbaztqWc/Ew== X-Google-Smtp-Source: ACJfBotdx4XOv3XocSpuc4vWCJYQoYy4ateiIISwC5arBUay856nuD4+/aZtlH5NBiLK4xv5Tan+Yg== X-Received: by 10.84.143.131 with SMTP id 3mr2015006plz.385.1515665549608; Thu, 11 Jan 2018 02:12:29 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:29 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 11/26] KVM: PPC: Book3S PR: prevent TS bits change in kvmppc_interrupt_pr() Date: Thu, 11 Jan 2018 18:11:24 +0800 Message-Id: <1515665499-31710-12-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo PR KVM host usually equipped with enabled TM in its host MSR value, and with non-transactional TS value. When a guest with TM active traps into PR KVM host, the rfid at the tail of kvmppc_interrupt_pr() will try to switch TS bits from S0 (Suspended & TM disabled) to N1 (Non-transactional & TM enabled). That will leads to TM Bad Thing interrupt. This patch manually sets target TS bits unchanged to avoid this exception. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/kvm/book3s_segment.S | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/powerpc/kvm/book3s_segment.S b/arch/powerpc/kvm/book3s_segment.S index 2a2b96d..675e9a2 100644 --- a/arch/powerpc/kvm/book3s_segment.S +++ b/arch/powerpc/kvm/book3s_segment.S @@ -383,6 +383,19 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) */ PPC_LL r6, HSTATE_HOST_MSR(r13) +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + /* + * We don't want to change MSR[TS] bits via rfi here. + * The actual TM handling logic will be in host with + * recovered DR/IR bits after HSTATE_VMHANDLER. + * And MSR_TM can be enabled in HOST_MSR so rfid may + * not suppress this change and can lead to exception. + * Manually set MSR to prevent TS state change here. + */ + mfmsr r7 + rldicl r7, r7, 64 - MSR_TS_S_LG, 62 + rldimi r6, r7, MSR_TS_S_LG, 63 - MSR_TS_T_LG +#endif PPC_LL r8, HSTATE_VMHANDLER(r13) #ifdef CONFIG_PPC64 From patchwork Thu Jan 11 10:11:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858987 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="BAHEnZn3"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHMBW6D24z9t50 for ; Thu, 11 Jan 2018 21:12:35 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933271AbeAKKMe (ORCPT ); Thu, 11 Jan 2018 05:12:34 -0500 Received: from mail-pf0-f194.google.com ([209.85.192.194]:38265 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932982AbeAKKMd (ORCPT ); Thu, 11 Jan 2018 05:12:33 -0500 Received: by mail-pf0-f194.google.com with SMTP id k19so1309493pfj.5; Thu, 11 Jan 2018 02:12:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2wC9NkHUFhYZ9e4o08Amebiq6CGfaKHA+mYyWXCbS4I=; b=BAHEnZn34xwxYFf1p/p+3OTYxe16cG/0PHcLRJm1LIbywySEAx+ubgp9Pw3t7iG9X0 2FK3EZWa0TKWRsYGM25J8M5saybGoQi6QtWb53z2Ly7utGth7+NjYazJMNvEyVtJtTcC LI3wj0HgMlFeE648yNcfh+My5SyZtv2omh7y/5eQkG5N8o3dJVIs1AF4avMe2OZp6Que 1pTa/EaSiWJj2R5SaaG2JEr6f+MNbOVwc15lyfEMcdORtnp8KFKh3DK78jkTSddmHo48 PWapom0mJHBFylDXswtjlZHy4luFk2m9verJHpf7UCEXo2KcY/ClaPenbKpXCfxjqem2 eAcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2wC9NkHUFhYZ9e4o08Amebiq6CGfaKHA+mYyWXCbS4I=; b=PV4ihvf3gCecLKJIEb91nqsC6VZ8+rpo7yiKcgxiTdGtW9Lpsxi6nFt+4/cPX5D0KJ IHlnyv7nhuiXdFdKWAoGLcsI9LUsJCW32E65XYQSTe3YrsI5Q7LecYC5Sh5eBlf/WF9h WK7Z4ANYw7poRWJm2GEoQhsWape/9ulrxl6+PlBrucgTxqD+O3UocmiaKrNuss9dQlCA DnMBFr1aaXQwtM6JtlPgkFszq1P4dmmzF0nYbz6fxUgjHhEoXCCByMby1a1HwI7z/xHq CckVXONgzW3jjgZwz8hUD7MEwqtCrgfzlH9R2KsoDsU+B9qNcDNwcBVORSjt0k2UKHEi 7fCw== X-Gm-Message-State: AKGB3mIXgeoJxuDNb+9FJ4S0BqfRjZFFNLUGw63XKw2U6tG2agJfsdF8 +02I/Zt3hBRVXws2V8YHL+g= X-Google-Smtp-Source: ACJfBovES9naZUIjrqXx3eR1yltXTIy0D3Zbop6YeeBiK/cN//KP7igIiiLGuOh/f7oKBf9w9SrfKQ== X-Received: by 10.84.244.202 with SMTP id f10mr17841013plt.386.1515665553293; Thu, 11 Jan 2018 02:12:33 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:32 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 12/26] powerpc: export symbol msr_check_and_set(). Date: Thu, 11 Jan 2018 18:11:25 +0800 Message-Id: <1515665499-31710-13-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo PR KVM will need to reuse msr_check_and_set(). This patch exports this API for reuse. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/kernel/process.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 72be0c3..8f430e6 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -152,6 +152,7 @@ unsigned long msr_check_and_set(unsigned long bits) return newmsr; } +EXPORT_SYMBOL_GPL(msr_check_and_set); void __msr_check_and_clear(unsigned long bits) { From patchwork Thu Jan 11 10:11:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858988 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Qwyr940p"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHMBb5zK9z9t5x for ; Thu, 11 Jan 2018 21:12:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933156AbeAKKMi (ORCPT ); Thu, 11 Jan 2018 05:12:38 -0500 Received: from mail-pf0-f193.google.com ([209.85.192.193]:39744 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933269AbeAKKMh (ORCPT ); Thu, 11 Jan 2018 05:12:37 -0500 Received: by mail-pf0-f193.google.com with SMTP id e11so1305980pff.6; Thu, 11 Jan 2018 02:12:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FpLWgFTmNyWVVKOS1nRTEKwWwq+QkxXeTu/YbSGvglA=; b=Qwyr940pgAA5GjcAVsYcXxmOmYjOPIWt2ZsKYag0K3yB7be+Kvz2R9208qawOdHg22 fdO6b/5L71q851WUNMXBTUfzM3wOpvm9kMiIxFqOJ9Zb6xf9T0XiXab5stnq4H/0XCbb Caqf+yeP/WaTM6YTtAb2Fi1+RPcso/2j6BSg2zycSdsEgbGk7Koxzx1B2W+8X21pYr79 LNKKPw/bdDcknOCFVLgi1NUwAEDImDEvXiTzh/7mKhxDAcSF/97HmVunQrY8cMlhlMYl hlCIEPGgSF4FdCKE1IsbULF1Y5hMunZuFB+seuIVoLvN8sznN5VX0ALJ7WGqIKkATdK9 WOWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FpLWgFTmNyWVVKOS1nRTEKwWwq+QkxXeTu/YbSGvglA=; b=IeC5jVBH6+MuDEzc4+SD+N4CnaSRMTL0VShjrC85VisH3+9CGkIRJzT9TcQubl45jV INrBndHhxbah56qgIaj5JbxIw/LQoLgrTDsg8DEBYtMAUMfRXEhO+/Q4gyxwdNXzJNnD B7ApBzu/cyCMjTVSreb1DXOkyAt8Ge7IrHXdA6gRtclXR9tFRbOst72VzwXS9l+gE/Pp fPCvzFs3nUlxL560pzLJ02R+Yx7XCUHAb4lGxB7b7eTL71JnHmGc7zlVOt78a+78UeJl xh/aBMv2qhXamO+edv+k3jwuajBEOaNBx1q2kSSem+eeWxqKa78/ajVJ6KmfcSlwAET6 mKXQ== X-Gm-Message-State: AKwxyteuR8OS3Dp5rfGRTyEMm2bqXOZlXytOZy5l7+IgD4rLUnVVZGb3 h+noU+ew7cenOErslOHiQEo= X-Google-Smtp-Source: ACJfBovoXrdkJ0udmgnuWOApZWekXfhlELxVJgA2ivm+Ek0ZpQpWVEJEWWJDbpq7X93vKJWdKMWY8w== X-Received: by 10.159.251.136 with SMTP id m8mr1325083pls.432.1515665557057; Thu, 11 Jan 2018 02:12:37 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:36 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 13/26] KVM: PPC: Book3S PR: adds new kvmppc_copyto_vcpu_tm/kvmppc_copyfrom_vcpu_tm API for PR KVM. Date: Thu, 11 Jan 2018 18:11:26 +0800 Message-Id: <1515665499-31710-14-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo This patch adds 2 new APIs: kvmppc_copyto_vcpu_tm() and kvmppc_copyfrom_vcpu_tm(). These 2 APIs will be used to copy from/to TM data between VCPU_TM/VCPU area. PR KVM will use these APIs for treclaim. or trchkpt. emulation. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/kvm/book3s_emulate.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c index 2eb457b..e096d01 100644 --- a/arch/powerpc/kvm/book3s_emulate.c +++ b/arch/powerpc/kvm/book3s_emulate.c @@ -87,6 +87,45 @@ static bool spr_allowed(struct kvm_vcpu *vcpu, enum priv_level level) return true; } +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM +void kvmppc_copyto_vcpu_tm(struct kvm_vcpu *vcpu) +{ + memcpy(&vcpu->arch.gpr_tm[0], &vcpu->arch.gpr[0], + sizeof(vcpu->arch.gpr_tm)); + memcpy(&vcpu->arch.fp_tm, &vcpu->arch.fp, + sizeof(struct thread_fp_state)); + memcpy(&vcpu->arch.vr_tm, &vcpu->arch.vr, + sizeof(struct thread_vr_state)); + vcpu->arch.ppr_tm = vcpu->arch.ppr; + vcpu->arch.dscr_tm = vcpu->arch.dscr; + vcpu->arch.amr_tm = vcpu->arch.amr; + vcpu->arch.ctr_tm = vcpu->arch.ctr; + vcpu->arch.tar_tm = vcpu->arch.tar; + vcpu->arch.lr_tm = vcpu->arch.lr; + vcpu->arch.cr_tm = vcpu->arch.cr; + vcpu->arch.vrsave_tm = vcpu->arch.vrsave; +} + +void kvmppc_copyfrom_vcpu_tm(struct kvm_vcpu *vcpu) +{ + memcpy(&vcpu->arch.gpr[0], &vcpu->arch.gpr_tm[0], + sizeof(vcpu->arch.gpr)); + memcpy(&vcpu->arch.fp, &vcpu->arch.fp_tm, + sizeof(struct thread_fp_state)); + memcpy(&vcpu->arch.vr, &vcpu->arch.vr_tm, + sizeof(struct thread_vr_state)); + vcpu->arch.ppr = vcpu->arch.ppr_tm; + vcpu->arch.dscr = vcpu->arch.dscr_tm; + vcpu->arch.amr = vcpu->arch.amr_tm; + vcpu->arch.ctr = vcpu->arch.ctr_tm; + vcpu->arch.tar = vcpu->arch.tar_tm; + vcpu->arch.lr = vcpu->arch.lr_tm; + vcpu->arch.cr = vcpu->arch.cr_tm; + vcpu->arch.vrsave = vcpu->arch.vrsave_tm; +} + +#endif + int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, unsigned int inst, int *advance) { From patchwork Thu Jan 11 10:11:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858989 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Thu, 11 Jan 2018 02:12:40 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:40 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 14/26] KVM: PPC: Book3S PR: export tm_enable()/tm_disable/tm_abort() APIs Date: Thu, 11 Jan 2018 18:11:27 +0800 Message-Id: <1515665499-31710-15-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo This patch exports tm_enable()/tm_disable/tm_abort() APIs, which will be used for PR KVM transaction memory logic. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/include/asm/asm-prototypes.h | 3 +++ arch/powerpc/include/asm/tm.h | 2 -- arch/powerpc/kernel/tm.S | 12 ++++++++++++ arch/powerpc/mm/hash_utils_64.c | 1 + 4 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/asm-prototypes.h b/arch/powerpc/include/asm/asm-prototypes.h index 9c3b290..2a0f54e 100644 --- a/arch/powerpc/include/asm/asm-prototypes.h +++ b/arch/powerpc/include/asm/asm-prototypes.h @@ -133,4 +133,7 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4, void _kvmppc_save_tm_pr(struct kvm_vcpu *vcpu, u64 guest_msr); #endif +void tm_enable(void); +void tm_disable(void); +void tm_abort(uint8_t cause); #endif /* _ASM_POWERPC_ASM_PROTOTYPES_H */ diff --git a/arch/powerpc/include/asm/tm.h b/arch/powerpc/include/asm/tm.h index b1658c9..e94f6db 100644 --- a/arch/powerpc/include/asm/tm.h +++ b/arch/powerpc/include/asm/tm.h @@ -10,12 +10,10 @@ #ifndef __ASSEMBLY__ -extern void tm_enable(void); extern void tm_reclaim(struct thread_struct *thread, uint8_t cause); extern void tm_reclaim_current(uint8_t cause); extern void tm_recheckpoint(struct thread_struct *thread); -extern void tm_abort(uint8_t cause); extern void tm_save_sprs(struct thread_struct *thread); extern void tm_restore_sprs(struct thread_struct *thread); diff --git a/arch/powerpc/kernel/tm.S b/arch/powerpc/kernel/tm.S index b92ac8e..ff12f47 100644 --- a/arch/powerpc/kernel/tm.S +++ b/arch/powerpc/kernel/tm.S @@ -12,6 +12,7 @@ #include #include #include +#include #ifdef CONFIG_VSX /* See fpu.S, this is borrowed from there */ @@ -55,6 +56,16 @@ _GLOBAL(tm_enable) or r4, r4, r3 mtmsrd r4 1: blr +EXPORT_SYMBOL_GPL(tm_enable); + +_GLOBAL(tm_disable) + mfmsr r4 + li r3, MSR_TM >> 32 + sldi r3, r3, 32 + andc r4, r4, r3 + mtmsrd r4 + blr +EXPORT_SYMBOL_GPL(tm_disable); _GLOBAL(tm_save_sprs) mfspr r0, SPRN_TFHAR @@ -78,6 +89,7 @@ _GLOBAL(tm_restore_sprs) _GLOBAL(tm_abort) TABORT(R3) blr +EXPORT_SYMBOL_GPL(tm_abort); /* void tm_reclaim(struct thread_struct *thread, * uint8_t cause) diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index 655a5a9..d354de6 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -63,6 +63,7 @@ #include #include #include +#include #ifdef DEBUG #define DBG(fmt...) udbg_printf(fmt) From patchwork Thu Jan 11 10:11:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858990 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="VsFj9vE6"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHMBl1yTrz9t6B for ; Thu, 11 Jan 2018 21:12:47 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933294AbeAKKMq (ORCPT ); Thu, 11 Jan 2018 05:12:46 -0500 Received: from mail-pg0-f68.google.com ([74.125.83.68]:44527 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933269AbeAKKMo (ORCPT ); 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Thu, 11 Jan 2018 02:12:44 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:43 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 15/26] KVM: PPC: Book3S PR: add kvmppc_save/restore_tm_sprs() APIs Date: Thu, 11 Jan 2018 18:11:28 +0800 Message-Id: <1515665499-31710-16-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo This patch adds 2 new APIs kvmppc_save_tm_sprs()/kvmppc_restore_tm_sprs() for the purpose of TEXASR/TFIAR/TFHAR save/restore. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/kvm/book3s_pr.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index b2f7566..5224b3c 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -42,6 +42,7 @@ #include #include #include +#include #include "book3s.h" @@ -235,6 +236,27 @@ void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu, preempt_enable(); } +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM +static inline void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu) +{ + tm_enable(); + vcpu->arch.tfhar = mfspr(SPRN_TFHAR); + vcpu->arch.texasr = mfspr(SPRN_TEXASR); + vcpu->arch.tfiar = mfspr(SPRN_TFIAR); + tm_disable(); +} + +static inline void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) +{ + tm_enable(); + mtspr(SPRN_TFHAR, vcpu->arch.tfhar); + mtspr(SPRN_TEXASR, vcpu->arch.texasr); + mtspr(SPRN_TFIAR, vcpu->arch.tfiar); + tm_disable(); +} + +#endif + static int kvmppc_core_check_requests_pr(struct kvm_vcpu *vcpu) { int r = 1; /* Indicate we want to get back into the guest */ From patchwork Thu Jan 11 10:11:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858991 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pmv/ggrl"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHMBq4nrCz9t44 for ; Thu, 11 Jan 2018 21:12:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933305AbeAKKMu (ORCPT ); Thu, 11 Jan 2018 05:12:50 -0500 Received: from mail-pf0-f195.google.com ([209.85.192.195]:36043 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933292AbeAKKMs (ORCPT ); Thu, 11 Jan 2018 05:12:48 -0500 Received: by mail-pf0-f195.google.com with SMTP id 23so1306569pfp.3; Thu, 11 Jan 2018 02:12:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pgUO0iRtkt4u2qDl1qlnrQzPK9BkADmj0SWOtFPFGxw=; b=pmv/ggrl9k+CnnofF6aRqj6tLphF//QywKXcApES7TMPt0yQo+O/FtnR50mfyKxBhP gVIX24G+RZz4ozNj+pyKiq8aV9r7ggj01KbzL/dgrvvL6t0IEPvDx+4FEvaBcL4UciLw nORtGi0c4Fs6SrVTc9vYehuJMkqc786E8GchV6U1v3bDbzFQmirbP2nZX9BUZ48W6OeB 2F3NMle4QpnSCrQM49m8cHc4AvFZLaKSGNHEf2dgE3sKxE3DD1VxkBdDjTMeMvmAS/Dz qSO9DBopVo6RBCrQAAjeiLXjL5SagXxWcwtXA3kuYV7+qmtjsgrzFs3d2SfdXT4zJRwF c/1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pgUO0iRtkt4u2qDl1qlnrQzPK9BkADmj0SWOtFPFGxw=; b=TUdH4AsEiRvK/mvWqUV2lDovil7QhmbqcgQPLexw85nGq5WeVj0TVPa5OHvVs/tWVC gXFYP8IPEy1sMA09G23GiB0gm7Wl8bGvF34Px4kWPKSLG1FOpp4cIDAR1rz1gcTSrqhv DE9iX5svuTm9xwsTIhVwmAVFkJNN0lW6Dllmx8ffq04C8xUSKJImjrtDzBDDRRHCAJwD GDGEK0gFIzJThn9GXYTl9BBWHWvAWRD2kHPX1nbtvk7GAx3B50e72oQscQjeMau8xr1s JgNkSnX8h7IG03NRPuQngzM7xt/t8I0MeFVh0JdDuf6Kkh5dDwes5XZN62MtvyQrcwE3 H2Vw== X-Gm-Message-State: AKwxytcK1oHe+1jacAA/iFfLHk765NWpCkzZV0MYBmxNza4yYrMqDBo6 z5S4iBay5I6e93Nj9/8YvtI= X-Google-Smtp-Source: ACJfBosbu9rv3+GuOLaPD0x8Tc0H6z1YS0ZTCh4kFsRKhFhMxb8XMu2IhsFDLF/YHBWnKwVbZ5of/g== X-Received: by 10.159.229.12 with SMTP id s12mr1543784plq.333.1515665567588; Thu, 11 Jan 2018 02:12:47 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:47 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 16/26] KVM: PPC: Book3S PR: add transaction memory save/restore skeleton for PR KVM Date: Thu, 11 Jan 2018 18:11:29 +0800 Message-Id: <1515665499-31710-17-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo The transaction memory checkpoint area save/restore behavior is triggered when VCPU qemu process is switching out/into CPU. ie. at kvmppc_core_vcpu_put_pr() and kvmppc_core_vcpu_load_pr(). MSR TM active state is determined by TS bits: active: 10(transactional) or 01 (suspended) inactive: 00 (non-transactional) We don't "fake" TM functionality for guest. We "sync" guest virtual MSR TM active state(10 or 01) with shadow MSR. That is to say, we don't emulate a transactional guest with a TM inactive MSR. TM SPR support(TFIAR/TFAR/TEXASR) has already been supported by commit 9916d57e64a4 ("KVM: PPC: Book3S PR: Expose TM registers"). Math register support (FPR/VMX/VSX) will be done at subsequent patch. - TM save: When kvmppc_save_tm_pr() is invoked, whether TM context need to be saved can be determined by current host MSR state: * TM active - save TM context * TM inactive - no need to do so and only save TM SPRs. - TM restore: However when kvmppc_restore_tm_pr() is invoked, there is an issue to determine whether TM restore should be performed. The TM active host MSR val saved in kernel stack is not loaded yet. We don't know whether there is a transaction to be restored from current host MSR TM status at kvmppc_restore_tm_pr(). To solve this issue, we save current MSR into vcpu->arch.save_msr_tm at kvmppc_save_tm_pr(), and kvmppc_restore_tm_pr() check TS bits of vcpu->arch.save_msr_tm to decide whether to do TM restore. Signed-off-by: Simon Guo Suggested-by: Paul Mackerras --- arch/powerpc/include/asm/kvm_book3s.h | 6 +++++ arch/powerpc/include/asm/kvm_host.h | 1 + arch/powerpc/kvm/book3s_pr.c | 41 +++++++++++++++++++++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h index 9a66700..d8dbfa5 100644 --- a/arch/powerpc/include/asm/kvm_book3s.h +++ b/arch/powerpc/include/asm/kvm_book3s.h @@ -253,6 +253,12 @@ extern void kvmppc_copy_to_svcpu(struct kvmppc_book3s_shadow_vcpu *svcpu, struct kvm_vcpu *vcpu); extern void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu, struct kvmppc_book3s_shadow_vcpu *svcpu); + +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM +void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu); +void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu); +#endif + extern int kvm_irq_bypass; static inline struct kvmppc_vcpu_book3s *to_book3s(struct kvm_vcpu *vcpu) diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h index 3aa5b57..eb3b821 100644 --- a/arch/powerpc/include/asm/kvm_host.h +++ b/arch/powerpc/include/asm/kvm_host.h @@ -627,6 +627,7 @@ struct kvm_vcpu_arch { struct thread_vr_state vr_tm; u32 vrsave_tm; /* also USPRG0 */ + u64 save_msr_tm; /* TS bits: whether TM restore is required */ #endif #ifdef CONFIG_KVM_EXIT_TIMING diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index 5224b3c..eef0928 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -43,6 +43,7 @@ #include #include #include +#include #include "book3s.h" @@ -114,6 +115,9 @@ static void kvmppc_core_vcpu_load_pr(struct kvm_vcpu *vcpu, int cpu) if (kvmppc_is_split_real(vcpu)) kvmppc_fixup_split_real(vcpu); +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + kvmppc_restore_tm_pr(vcpu); +#endif } static void kvmppc_core_vcpu_put_pr(struct kvm_vcpu *vcpu) @@ -131,6 +135,10 @@ static void kvmppc_core_vcpu_put_pr(struct kvm_vcpu *vcpu) if (kvmppc_is_split_real(vcpu)) kvmppc_unfixup_split_real(vcpu); +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + kvmppc_save_tm_pr(vcpu); +#endif + kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX); kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); @@ -255,6 +263,39 @@ static inline void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) tm_disable(); } +void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu) +{ + /* + * When kvmppc_save_tm_pr() is invoked, whether TM context need to + * be saved can be determined by current MSR TS active state. + * + * We save current MSR's TM TS bits into vcpu->arch.save_msr_tm. + * So that kvmppc_restore_tm_pr() can decide to do TM restore or + * not based on that. + */ + vcpu->arch.save_msr_tm = mfmsr(); + + if (!(MSR_TM_ACTIVE(vcpu->arch.save_msr_tm))) { + kvmppc_save_tm_sprs(vcpu); + return; + } + + preempt_disable(); + _kvmppc_save_tm_pr(vcpu, mfmsr()); + preempt_enable(); +} + +void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu) +{ + if (!MSR_TM_ACTIVE(vcpu->arch.save_msr_tm)) { + kvmppc_restore_tm_sprs(vcpu); + return; + } + + preempt_disable(); + _kvmppc_restore_tm_pr(vcpu, vcpu->arch.save_msr_tm); + preempt_enable(); +} #endif static int kvmppc_core_check_requests_pr(struct kvm_vcpu *vcpu) From patchwork Thu Jan 11 10:11:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858992 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ivuKtYDn"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHMBt0mR7z9t6m for ; Thu, 11 Jan 2018 21:12:54 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933149AbeAKKMx (ORCPT ); Thu, 11 Jan 2018 05:12:53 -0500 Received: from mail-pg0-f66.google.com ([74.125.83.66]:44540 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933292AbeAKKMw (ORCPT ); Thu, 11 Jan 2018 05:12:52 -0500 Received: by mail-pg0-f66.google.com with SMTP id m20so1842432pgc.11; Thu, 11 Jan 2018 02:12:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Thu, 11 Jan 2018 02:12:51 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:50 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 17/26] KVM: PPC: Book3S PR: add math support for PR KVM HTM Date: Thu, 11 Jan 2018 18:11:30 +0800 Message-Id: <1515665499-31710-18-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo The math registers will be saved into vcpu->arch.fp/vr and corresponding vcpu->arch.fp_tm/vr_tm area. We flush or giveup the math regs into vcpu->arch.fp/vr before saving transaction. After transaction is restored, the math regs will be loaded back into regs. If there is a FP/VEC/VSX unavailable exception during transaction active state, the math checkpoint content might be incorrect and we need to do treclaim./load the correct checkpoint val/trechkpt. sequence to retry the transaction. If transaction is active, and the qemu process is switching out of CPU, we need to keep the "guest_owned_ext" bits unchanged after qemu process is switched back. The reason is that if we allow guest_owned_ext change freely during a transaction, there will lack information to handle FP/VEC/VSX unavailable exception during transaction active state. Detail is as follows: Assume we allow math bits to be given up freely during transaction: - If it is the first FP unavailable exception after tbegin., vcpu->arch.fp/ vr need to be loaded for trechkpt. - If it is the 2nd or subsequent FP unavailable exception after tbegin., vcpu->arch.fp_tm/vr_tm need to be loaded for trechkpt. It will bring much additional complexity to cover both cases. That is why we always save guest_owned_ext into vcpu->arch.save_msr_tm at kvmppc_save_tm_pr(), then check those bits in vcpu->arch.save_msr_tm at kvmppc_restore_tm_pr() to determine what math contents will be loaded. With this, we will always load vcpu->arch.fp/vr in math unavailable exception during active transaction. Signed-off-by: Simon Guo --- arch/powerpc/include/asm/kvm_host.h | 4 +- arch/powerpc/kvm/book3s_pr.c | 114 +++++++++++++++++++++++++++++------- 2 files changed, 95 insertions(+), 23 deletions(-) diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h index eb3b821..1124c62 100644 --- a/arch/powerpc/include/asm/kvm_host.h +++ b/arch/powerpc/include/asm/kvm_host.h @@ -627,7 +627,9 @@ struct kvm_vcpu_arch { struct thread_vr_state vr_tm; u32 vrsave_tm; /* also USPRG0 */ - u64 save_msr_tm; /* TS bits: whether TM restore is required */ + u64 save_msr_tm; /* TS bits: whether TM restore is required + * FP/VEC/VSX bits: saved guest_owned_ext + */ #endif #ifdef CONFIG_KVM_EXIT_TIMING diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index eef0928..c35bd02 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -55,6 +55,7 @@ static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, ulong msr); +static int kvmppc_load_ext(struct kvm_vcpu *vcpu, ulong msr); static void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac); /* Some compatibility defines */ @@ -280,6 +281,33 @@ void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu) return; } + /* when we are in transaction active state and switch out of CPU, + * we need to be careful to not "change" guest_owned_ext bits after + * kvmppc_save_tm_pr()/kvmppc_restore_tm_pr() pair. The reason is + * that we need to distinguish following 2 FP/VEC/VSX unavailable + * exception cases in TM active state: + * 1) tbegin. is executed with guest_owned_ext FP/VEC/VSX off. Then + * there comes a FP/VEC/VSX unavailable exception during transaction. + * In this case, the vcpu->arch.fp/vr contents need to be loaded as + * checkpoint contents. + * 2) tbegin. is executed with guest_owned_ext FP/VEC/VSX on. Then + * there is task switch during suspended state. If we giveup ext and + * update guest_owned_ext as no FP/VEC/VSX bits during context switch, + * we need to load vcpu->arch.fp_tm/vr_tm contents as checkpoint + * content. + * + * As a result, we don't change guest_owned_ext bits during + * kvmppc_save/restore_tm_pr() pair. So that we can only use + * vcpu->arch.fp/vr contents as checkpoint contents. + * And we need to "save" the guest_owned_ext bits here who indicates + * which math bits need to be "restored" in kvmppc_restore_tm_pr(). + */ + vcpu->arch.save_msr_tm &= ~(MSR_FP | MSR_VEC | MSR_VSX); + vcpu->arch.save_msr_tm |= (vcpu->arch.guest_owned_ext & + (MSR_FP | MSR_VEC | MSR_VSX)); + + kvmppc_giveup_ext(vcpu, MSR_VSX); + preempt_disable(); _kvmppc_save_tm_pr(vcpu, mfmsr()); preempt_enable(); @@ -295,6 +323,16 @@ void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu) preempt_disable(); _kvmppc_restore_tm_pr(vcpu, vcpu->arch.save_msr_tm); preempt_enable(); + + if (vcpu->arch.save_msr_tm & MSR_VSX) + kvmppc_load_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX); + else { + if (vcpu->arch.save_msr_tm & MSR_VEC) + kvmppc_load_ext(vcpu, MSR_VEC); + + if (vcpu->arch.save_msr_tm & MSR_FP) + kvmppc_load_ext(vcpu, MSR_FP); + } } #endif @@ -788,12 +826,41 @@ static void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac) #endif } +static int kvmppc_load_ext(struct kvm_vcpu *vcpu, ulong msr) +{ + struct thread_struct *t = ¤t->thread; + + if (msr & MSR_FP) { + preempt_disable(); + enable_kernel_fp(); + load_fp_state(&vcpu->arch.fp); + disable_kernel_fp(); + t->fp_save_area = &vcpu->arch.fp; + preempt_enable(); + } + + if (msr & MSR_VEC) { +#ifdef CONFIG_ALTIVEC + preempt_disable(); + enable_kernel_altivec(); + load_vr_state(&vcpu->arch.vr); + disable_kernel_altivec(); + t->vr_save_area = &vcpu->arch.vr; + preempt_enable(); +#endif + } + + t->regs->msr |= msr; + vcpu->arch.guest_owned_ext |= msr; + kvmppc_recalc_shadow_msr(vcpu); + + return RESUME_GUEST; +} + /* Handle external providers (FPU, Altivec, VSX) */ static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, ulong msr) { - struct thread_struct *t = ¤t->thread; - /* When we have paired singles, we emulate in software */ if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) return RESUME_GUEST; @@ -829,31 +896,34 @@ static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, printk(KERN_INFO "Loading up ext 0x%lx\n", msr); #endif - if (msr & MSR_FP) { +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + /* if TM is active, the checkpointed math content + * might be invalid. We need to reclaim current + * transaction, load the correct math, and perform + * rechkpoint. + */ + if (MSR_TM_ACTIVE(mfmsr())) { preempt_disable(); - enable_kernel_fp(); - load_fp_state(&vcpu->arch.fp); - disable_kernel_fp(); - t->fp_save_area = &vcpu->arch.fp; - preempt_enable(); - } + kvmppc_save_tm_pr(vcpu); + /* need update the chkpt math reg saving content, + * so that we can checkpoint with desired fp value. + */ + if (msr & MSR_FP) + memcpy(&vcpu->arch.fp_tm, &vcpu->arch.fp, + sizeof(struct thread_fp_state)); + + if (msr & MSR_VEC) { + memcpy(&vcpu->arch.vr_tm, &vcpu->arch.vr, + sizeof(struct thread_vr_state)); + vcpu->arch.vrsave_tm = vcpu->arch.vrsave; + } - if (msr & MSR_VEC) { -#ifdef CONFIG_ALTIVEC - preempt_disable(); - enable_kernel_altivec(); - load_vr_state(&vcpu->arch.vr); - disable_kernel_altivec(); - t->vr_save_area = &vcpu->arch.vr; + kvmppc_restore_tm_pr(vcpu); preempt_enable(); -#endif } +#endif - t->regs->msr |= msr; - vcpu->arch.guest_owned_ext |= msr; - kvmppc_recalc_shadow_msr(vcpu); - - return RESUME_GUEST; + return kvmppc_load_ext(vcpu, msr); } /* From patchwork Thu Jan 11 10:11:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858993 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="R5EwasCP"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHMBx3Knyz9t6n for ; Thu, 11 Jan 2018 21:12:57 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933311AbeAKKM4 (ORCPT ); Thu, 11 Jan 2018 05:12:56 -0500 Received: from mail-pf0-f196.google.com ([209.85.192.196]:41272 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933292AbeAKKMz (ORCPT ); Thu, 11 Jan 2018 05:12:55 -0500 Received: by mail-pf0-f196.google.com with SMTP id j3so1309249pfh.8; Thu, 11 Jan 2018 02:12:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BITbLBFD5VROJyl12kxYOktmZxB+SZlayHMzOF+/nss=; b=R5EwasCPZxFk8Vm4BEfFE29hHw6x5DFeRhPyZzwxJ4V1UOkTPKgDD1wlKHHBCsObNa RnUkLaYLuKK3kJZEN/r3iOcxZZIdrU19oCoejVgwQpND6BXyitmGVfRVChqYoKNMTU1h VgQ8kE6rjOCM1J30Ik1MRHD98kmtQaw3HgoxeBt2uGwHeWIdGEJD6Ijh7nw0IEPc7aDJ BStlseSrnnJCglRUNnTl/WvWNCIp9GeUmf756EnqiraczAGfBja8H2RQ386ju/LTmGPs y9pKP/uS55h984EoKVDQL+O/zNIFKaaJVAtdttcbU2WCpGB9dGofAzYDkfJYMJyZRgyP Wf9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BITbLBFD5VROJyl12kxYOktmZxB+SZlayHMzOF+/nss=; b=UcVS0TxnxcYA3qjtQQzOwpMoAU6WeXFY/l/Pl3LuuhrjWuNDgT+/GEzuueM5WhTjOO 3D1W9nvwqtbfJYZibAa2q/tqtgVawoDJHfrB0Y4RECEM0cOfKTX3CH1NnwLULpvDyHnp IcZdmXfVwPnf8AzLZmF0Q8PlWR06HtSSLw8Odn66DtdJRklWvIsgY9kDNKAU4JuahzpP PcRGCLmlQ03/VJxvyIzBzDEv/pss5BE650EUHxbLq2tblv/u06EkUezejADI2Qa///fJ Zncckh/HjAW7Ep9+YK9lx3HXryWUwyAdVC4D2O00Mx84taJCs2fXoblGf1o7YFxIEU0n GBZQ== X-Gm-Message-State: AKGB3mKfaH6oLRi5cVYJ3FCiPb9dGEf24wLHNhgY9j6TOpav2gCnknA4 mIwTBaPPONz/ERrW8zGEIKsvjQ== X-Google-Smtp-Source: ACJfBovkUgn+a5pdWhn4GA6ve8oXJEJhk0D4MS3+gEg4HezZ0VRUdN1/7kONUnxB6bW0pzS42mdKzw== X-Received: by 10.124.25.1 with SMTP id c1mr14203983plz.372.1515665575347; Thu, 11 Jan 2018 02:12:55 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:54 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 18/26] KVM: PPC: Book3S PR: make mtspr/mfspr emulation behavior based on active TM SPRs Date: Thu, 11 Jan 2018 18:11:31 +0800 Message-Id: <1515665499-31710-19-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo The mfspr/mtspr on TM SPRs(TEXASR/TFIAR/TFHAR) are non-privileged instructions and can be executed at PR KVM guest without trapping into host in problem state. We only emulate mtspr/mfspr texasr/tfiar/tfhar at guest PR=0 state. When we are emulating mtspr tm sprs at guest PR=0 state, the emulation result need to be visible to guest PR=1 state. That is, the actual TM SPR val should be loaded into actual registers. We already flush TM SPRs into vcpu when switching out of CPU, and load TM SPRs when switching back. This patch corrects mfspr()/mtspr() emulation for TM SPRs to make the actual source/dest based on actual TM SPRs. Signed-off-by: Simon Guo --- arch/powerpc/kvm/book3s_emulate.c | 35 +++++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c index e096d01..c2836330 100644 --- a/arch/powerpc/kvm/book3s_emulate.c +++ b/arch/powerpc/kvm/book3s_emulate.c @@ -521,13 +521,26 @@ int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val) break; #ifdef CONFIG_PPC_TRANSACTIONAL_MEM case SPRN_TFHAR: - vcpu->arch.tfhar = spr_val; - break; case SPRN_TEXASR: - vcpu->arch.texasr = spr_val; - break; case SPRN_TFIAR: - vcpu->arch.tfiar = spr_val; + if (MSR_TM_ACTIVE(kvmppc_get_msr(vcpu))) { + /* it is illegal to mtspr() TM regs in + * other than non-transactional state. + */ + kvmppc_core_queue_program(vcpu, SRR1_PROGTM); + emulated = EMULATE_AGAIN; + break; + } + + tm_enable(); + if (sprn == SPRN_TFHAR) + mtspr(SPRN_TFHAR, spr_val); + else if (sprn == SPRN_TEXASR) + mtspr(SPRN_TEXASR, spr_val); + else + mtspr(SPRN_TFIAR, spr_val); + tm_disable(); + break; #endif #endif @@ -674,13 +687,19 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val break; #ifdef CONFIG_PPC_TRANSACTIONAL_MEM case SPRN_TFHAR: - *spr_val = vcpu->arch.tfhar; + tm_enable(); + *spr_val = mfspr(SPRN_TFHAR); + tm_disable(); break; case SPRN_TEXASR: - *spr_val = vcpu->arch.texasr; + tm_enable(); + *spr_val = mfspr(SPRN_TEXASR); + tm_disable(); break; case SPRN_TFIAR: - *spr_val = vcpu->arch.tfiar; + tm_enable(); + *spr_val = mfspr(SPRN_TFIAR); + tm_disable(); break; #endif #endif From patchwork Thu Jan 11 10:11:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858994 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; 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Thu, 11 Jan 2018 02:12:58 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:57 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 19/26] KVM: PPC: Book3S PR: always fail transaction in guest privilege state Date: Thu, 11 Jan 2018 18:11:32 +0800 Message-Id: <1515665499-31710-20-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo Currently kernel doesn't use transaction memory. And there is an issue for privilege guest that: tbegin/tsuspend/tresume/tabort TM instructions can impact MSR TM bits without trap into PR host. So following code will lead to a false mfmsr result: tbegin <- MSR bits update to Transaction active. beq <- failover handler branch mfmsr <- still read MSR bits from magic page with transaction inactive. It is not an issue for non-privilege guest since its mfmsr is not patched with magic page and will always trap into PR host. This patch will always fail tbegin attempt for privilege guest, so that the above issue is prevented. It is benign since currently (guest) kernel doesn't initiate a transaction. Test case: https://github.com/justdoitqd/publicFiles/blob/master/test_tbegin_pr.c Signed-off-by: Simon Guo --- arch/powerpc/include/asm/kvm_book3s.h | 1 + arch/powerpc/kvm/book3s_emulate.c | 34 ++++++++++++++++++++++++++++++++++ arch/powerpc/kvm/book3s_pr.c | 11 ++++++++++- 3 files changed, 45 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h index d8dbfa5..524cd82 100644 --- a/arch/powerpc/include/asm/kvm_book3s.h +++ b/arch/powerpc/include/asm/kvm_book3s.h @@ -257,6 +257,7 @@ extern void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu, #ifdef CONFIG_PPC_TRANSACTIONAL_MEM void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu); void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu); +void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu); #endif extern int kvm_irq_bypass; diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c index c2836330..1eb1900 100644 --- a/arch/powerpc/kvm/book3s_emulate.c +++ b/arch/powerpc/kvm/book3s_emulate.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "book3s.h" #define OP_19_XOP_RFID 18 @@ -47,6 +48,8 @@ #define OP_31_XOP_EIOIO 854 #define OP_31_XOP_SLBMFEE 915 +#define OP_31_XOP_TBEGIN 654 + /* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */ #define OP_31_XOP_DCBZ 1010 @@ -360,6 +363,37 @@ int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, break; } +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + case OP_31_XOP_TBEGIN: + { + if (!(kvmppc_get_msr(vcpu) & MSR_PR)) { + preempt_disable(); + vcpu->arch.cr = (CR0_TBEGIN_FAILURE | + (vcpu->arch.cr & ~(CR0_MASK << CR0_SHIFT))); + + vcpu->arch.texasr = (TEXASR_FS | TEXASR_EX | + (((u64)(TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) + << TEXASR_FC_LG)); + + if ((inst >> 21) & 0x1) + vcpu->arch.texasr |= TEXASR_ROT; + + if (kvmppc_get_msr(vcpu) & MSR_PR) + vcpu->arch.texasr |= TEXASR_PR; + + if (kvmppc_get_msr(vcpu) & MSR_HV) + vcpu->arch.texasr |= TEXASR_HV; + + vcpu->arch.tfhar = kvmppc_get_pc(vcpu) + 4; + vcpu->arch.tfiar = kvmppc_get_pc(vcpu); + + kvmppc_restore_tm_sprs(vcpu); + preempt_enable(); + } else + emulated = EMULATE_FAIL; + break; + } +#endif default: emulated = EMULATE_FAIL; } diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index c35bd02..a26f4db 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -255,7 +255,7 @@ static inline void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu) tm_disable(); } -static inline void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) +inline void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) { tm_enable(); mtspr(SPRN_TFHAR, vcpu->arch.tfhar); @@ -447,6 +447,15 @@ static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu) (PVR_VER(guest_pvr) == PVR_970GX)) smsr |= MSR_HV; #endif +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + /* + * in guest privileged state, we want to fail all TM transactions. + * So disable MSR TM bit so that all tbegin. will be able to be + * trapped into host. + */ + if (!(guest_msr & MSR_PR)) + smsr &= ~MSR_TM; +#endif vcpu->arch.shadow_msr = smsr; } From patchwork Thu Jan 11 10:11:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858995 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; 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Thu, 11 Jan 2018 02:13:02 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:13:01 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 20/26] KVM: PPC: Book3S PR: enable NV reg restore for reading TM SPR at guest privilege state Date: Thu, 11 Jan 2018 18:11:33 +0800 Message-Id: <1515665499-31710-21-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo Currently kvmppc_handle_fac() will not update NV GPRs and thus it can return with GUEST_RESUME. However PR KVM guest always disables MSR_TM bit at privilege state. If PR privilege guest are trying to read TM SPRs, it will trigger TM facility unavailable exception and fall into kvmppc_handle_fac(). Then the emulation will be done by kvmppc_core_emulate_mfspr_pr(). The mfspr instruction can include a RT with NV reg. So it is necessary to restore NV GPRs at this case, to reflect the update to NV RT. This patch make kvmppc_handle_fac() return GUEST_RESUME_NV at TM fac exception and with guest privilege state. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/kvm/book3s_pr.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index a26f4db..1d105fa 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -1030,6 +1030,18 @@ static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac) break; } +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + /* Since we disabled MSR_TM at privilege state, the mfspr instruction + * for TM spr can trigger TM fac unavailable. In this case, the + * emulation is handled by kvmppc_emulate_fac(), which invokes + * kvmppc_emulate_mfspr() finally. But note the mfspr can include + * RT for NV registers. So it need to restore those NV reg to reflect + * the update. + */ + if ((fac == FSCR_TM_LG) && !(kvmppc_get_msr(vcpu) & MSR_PR)) + return RESUME_GUEST_NV; +#endif + return RESUME_GUEST; } @@ -1416,8 +1428,7 @@ int kvmppc_handle_exit_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, } #ifdef CONFIG_PPC_BOOK3S_64 case BOOK3S_INTERRUPT_FAC_UNAVAIL: - kvmppc_handle_fac(vcpu, vcpu->arch.shadow_fscr >> 56); - r = RESUME_GUEST; + r = kvmppc_handle_fac(vcpu, vcpu->arch.shadow_fscr >> 56); break; #endif case BOOK3S_INTERRUPT_MACHINE_CHECK: From patchwork Thu Jan 11 10:11:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858996 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kJTjD3DV"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHMC76MkCz9ryk for ; Thu, 11 Jan 2018 21:13:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933331AbeAKKNH (ORCPT ); Thu, 11 Jan 2018 05:13:07 -0500 Received: from mail-pg0-f65.google.com ([74.125.83.65]:42814 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933080AbeAKKNG (ORCPT ); Thu, 11 Jan 2018 05:13:06 -0500 Received: by mail-pg0-f65.google.com with SMTP id q67so1857432pga.9; Thu, 11 Jan 2018 02:13:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+Y3FEr48wNnEeVtzmAwpc6fK2n/nBT3fhb/fDvWioNc=; b=kJTjD3DV7nEyGh9j9b5Exr8khhqYvyQbegk5CyxLYLQMQKfGutDc/QapZHt1L4Atih 7/RQOkh/dSUENaqUkmKDnmFW3PexYMnF4JiXmLUCcZn8+ZsYwPIyl3Fkx5QyTyndEPBh rGrKH1frW94IQ66pIPntq22D947meHVZtRFrG0SSQLtrRQOCzOS2tVQd2Em0hc2t9xN0 tXCJP2utBjkQmFDmvSspCuooGUYLx/AvRO184zER7wLpV9veavc877o1V+KdEfYwdldP gN2XCmcet1QcAvYKphTp+7SsJab7j1Ji3P0NeyBU2XtUF4zsPv4O0SSmJOvIhjNRC5w+ aFtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+Y3FEr48wNnEeVtzmAwpc6fK2n/nBT3fhb/fDvWioNc=; b=nIG1PSSSuMyH4Cno+EMJcluUf4LdKViXurOT5bqZW/xdz7alD8/PhxWiSDgZqZ+gXV xuLwziw/NDTBwox1BnUOcQvkziQ+3WXtdaU7/MfsyRrzuV4ZIiskp7Ood4kxf1n/87OI u/g1TULmNE+8omcuUKz0YCMoYkP6iezn70/wpi2i9Jv7IfHH3UnWyrhXZohzuRfZGux1 CYQPJx1lyIhkO284mDvG/lXXboHgrD9+4NlfQEHMRntz+3Ht5NP18KpDKNgz3OOufbpA E2boVRl/zGrelqBrJJcDE3TZhQSKPC0Wkj10ZGqUeerwGjS6QMBwJZMV6CDFuXeeqBkS J4bQ== X-Gm-Message-State: AKGB3mLd7pJi+3ZUrY9+cgHei6Sc0ROtz44DXYkUtYc4zu58HDahhiHN WBVpnAcepQgrxiTPIWWKEm8= X-Google-Smtp-Source: ACJfBoupJdNw+CMa8N/tosp2NNYwhnCa4Hje4YLDyCCKwhN9SO7Vi8KOadlCSXyJ25u9kyM262tZew== X-Received: by 10.101.93.79 with SMTP id e15mr9505010pgt.129.1515665585664; Thu, 11 Jan 2018 02:13:05 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.13.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:13:05 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 21/26] KVM: PPC: Book3S PR: adds emulation for treclaim. Date: Thu, 11 Jan 2018 18:11:34 +0800 Message-Id: <1515665499-31710-22-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo This patch adds support for "treclaim." emulation when PR KVM guest executes treclaim. and traps to host. We will firstly doing treclaim. and save TM checkpoint and doing treclaim. Then it is necessary to update vcpu current reg content with checkpointed vals. When rfid into guest again, those vcpu current reg content(now the checkpoint vals) will be loaded into regs. Signed-off-by: Simon Guo --- arch/powerpc/include/asm/reg.h | 4 +++ arch/powerpc/kvm/book3s_emulate.c | 66 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 69 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 6c293bc..b3bcf6b 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -244,12 +244,16 @@ #define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */ #define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */ #define TEXASR_FC_LG (63 - 7) /* Failure Code */ +#define TEXASR_AB_LG (63 - 31) /* Abort */ +#define TEXASR_SU_LG (63 - 32) /* Suspend */ #define TEXASR_HV_LG (63 - 34) /* Hypervisor state*/ #define TEXASR_PR_LG (63 - 35) /* Privilege level */ #define TEXASR_FS_LG (63 - 36) /* failure summary */ #define TEXASR_EX_LG (63 - 37) /* TFIAR exact bit */ #define TEXASR_ROT_LG (63 - 38) /* ROT bit */ #define TEXASR_FC (ASM_CONST(0xFF) << TEXASR_FC_LG) +#define TEXASR_AB __MASK(TEXASR_AB_LG) +#define TEXASR_SU __MASK(TEXASR_SU_LG) #define TEXASR_HV __MASK(TEXASR_HV_LG) #define TEXASR_PR __MASK(TEXASR_PR_LG) #define TEXASR_FS __MASK(TEXASR_FS_LG) diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c index 1eb1900..51c0e20 100644 --- a/arch/powerpc/kvm/book3s_emulate.c +++ b/arch/powerpc/kvm/book3s_emulate.c @@ -25,6 +25,7 @@ #include #include #include "book3s.h" +#include #define OP_19_XOP_RFID 18 #define OP_19_XOP_RFI 50 @@ -50,6 +51,8 @@ #define OP_31_XOP_TBEGIN 654 +#define OP_31_XOP_TRECLAIM 942 + /* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */ #define OP_31_XOP_DCBZ 1010 @@ -109,7 +112,7 @@ void kvmppc_copyto_vcpu_tm(struct kvm_vcpu *vcpu) vcpu->arch.vrsave_tm = vcpu->arch.vrsave; } -void kvmppc_copyfrom_vcpu_tm(struct kvm_vcpu *vcpu) +static void kvmppc_copyfrom_vcpu_tm(struct kvm_vcpu *vcpu) { memcpy(&vcpu->arch.gpr[0], &vcpu->arch.gpr_tm[0], sizeof(vcpu->arch.gpr)); @@ -127,6 +130,42 @@ void kvmppc_copyfrom_vcpu_tm(struct kvm_vcpu *vcpu) vcpu->arch.vrsave = vcpu->arch.vrsave_tm; } +static void kvmppc_emulate_treclaim(struct kvm_vcpu *vcpu, int ra_val) +{ + unsigned long guest_msr = kvmppc_get_msr(vcpu); + int fc_val = ra_val ? ra_val : 1; + + kvmppc_save_tm_pr(vcpu); + + preempt_disable(); + kvmppc_copyfrom_vcpu_tm(vcpu); + preempt_enable(); + + /* + * treclaim need quit to non-transactional state. + */ + guest_msr &= ~(MSR_TS_MASK); + kvmppc_set_msr(vcpu, guest_msr); + + preempt_disable(); + tm_enable(); + vcpu->arch.texasr = mfspr(SPRN_TEXASR); + vcpu->arch.texasr &= ~TEXASR_FC; + vcpu->arch.texasr |= ((u64)fc_val << TEXASR_FC_LG); + + vcpu->arch.texasr &= ~(TEXASR_PR | TEXASR_HV); + if (kvmppc_get_msr(vcpu) & MSR_PR) + vcpu->arch.texasr |= TEXASR_PR; + + if (kvmppc_get_msr(vcpu) & MSR_HV) + vcpu->arch.texasr |= TEXASR_HV; + + vcpu->arch.tfiar = kvmppc_get_pc(vcpu); + mtspr(SPRN_TEXASR, vcpu->arch.texasr); + mtspr(SPRN_TFIAR, vcpu->arch.tfiar); + tm_disable(); + preempt_enable(); +} #endif int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, @@ -393,6 +432,31 @@ int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, emulated = EMULATE_FAIL; break; } + case OP_31_XOP_TRECLAIM: + { + ulong guest_msr = kvmppc_get_msr(vcpu); + unsigned long ra_val = 0; + + /* generate interrupt based on priorities */ + if (guest_msr & MSR_PR) { + /* Privileged Instruction type Program Interrupt */ + kvmppc_core_queue_program(vcpu, SRR1_PROGPRIV); + emulated = EMULATE_AGAIN; + break; + } + + if (!MSR_TM_SUSPENDED(guest_msr)) { + /* TM bad thing interrupt */ + kvmppc_core_queue_program(vcpu, SRR1_PROGTM); + emulated = EMULATE_AGAIN; + break; + } + + if (ra) + ra_val = kvmppc_get_gpr(vcpu, ra); + kvmppc_emulate_treclaim(vcpu, ra_val); + break; + } #endif default: emulated = EMULATE_FAIL; From patchwork Thu Jan 11 10:11:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858997 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="lh8sxHBp"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHMCC1zgLz9t75 for ; Thu, 11 Jan 2018 21:13:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933178AbeAKKNK (ORCPT ); Thu, 11 Jan 2018 05:13:10 -0500 Received: from mail-pf0-f195.google.com ([209.85.192.195]:46086 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933340AbeAKKNJ (ORCPT ); Thu, 11 Jan 2018 05:13:09 -0500 Received: by mail-pf0-f195.google.com with SMTP id y5so1310722pff.13; Thu, 11 Jan 2018 02:13:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kSQcuN7doeiv0hEibfof9Vac1TdUIqRXeQQBG+lZ0vQ=; b=lh8sxHBpWzqARNvKxunU1JT3v4YZ9WYH1dbziy28XLQwTgHyFsPJwMEXkRprKe6Mu/ SzzfyFA8haEcAkQcoTWV+KCwwwbeuVT17lsi3GTQ92QfWDQysVqf26rI5Bazw1QEJgMC fNiGpasfWTRmvBXyT4EX8haaL86p7VBTd4MyaNnKkWqaiACUzPzZjraoeSVb7ia1i/Ft yIJWaAPtXX6j6EHT+Z/zfcwPUdMsZxCU8zuPejZhAfK1P62kvjDLEeBMwwGDDQTkBqbe 5SoAQ6dGYt6VyEQuynvEc31oNCoLbrSEyU1HsNcU9sEUMqqsHvDkN0Y+bB3CH2Se3HHV kEeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kSQcuN7doeiv0hEibfof9Vac1TdUIqRXeQQBG+lZ0vQ=; b=BSanrgNc021A+Qcn0FP2SwweRuoqf93+flVvPhUlG2rrj4ud4xAX2z60RYHU2e51Md k9vmp/sNSjtHvc2O+dgtKKpuaAESvf8mfINaj7oooN0WFa4ILyELMkbiAOFqX5uqPJ91 93ICmx0PcWcikok+ZercAnIztVAwR1CtfH6bDYU56s1YQYB0fBAOuETU1hBbtMw3Q0Zw nYmw0wOJNqHmKvA7vvEEDZYcRFYfG7p0kG29aj477sBB+sF3l9xx4xYtn7fHFUhQlXUB VBWFUKhcM8oW0AO9qJXo7P9jKoxciBaH2H38umhIBnQge8DVIuZnSn3nzlY71/195tpA KFCw== X-Gm-Message-State: AKwxytcNhNkFh1+8NdtQZaxiIB/MguBORGKKgWi+Yq3yhyNYIYeL4+P4 Ypjj30OcaMIwGBjZ2lxLG4606g== X-Google-Smtp-Source: ACJfBosNuUCYo31qBe9TsnWWcWVgilo+LQARQzn777ci2XYHdt+wY1GBg147ui0DUNp2gCTwWy/XhA== X-Received: by 10.98.78.148 with SMTP id c142mr7111111pfb.153.1515665588939; Thu, 11 Jan 2018 02:13:08 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.13.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:13:08 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 22/26] KVM: PPC: Book3S PR: add emulation for trechkpt in PR KVM. Date: Thu, 11 Jan 2018 18:11:35 +0800 Message-Id: <1515665499-31710-23-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo This patch adds host emulation when guest PR KVM executes "trechkpt.", which is a privileged instruction and will trap into host. We firstly copy vcpu ongoing content into vcpu tm checkpoint content, then perform kvmppc_restore_tm_pr() to do trechkpt. with updated vcpu tm checkpoint vals. Signed-off-by: Simon Guo --- arch/powerpc/kvm/book3s_emulate.c | 57 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c index 51c0e20..52a2e46 100644 --- a/arch/powerpc/kvm/book3s_emulate.c +++ b/arch/powerpc/kvm/book3s_emulate.c @@ -52,6 +52,7 @@ #define OP_31_XOP_TBEGIN 654 #define OP_31_XOP_TRECLAIM 942 +#define OP_31_XOP_TRCHKPT 1006 /* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */ #define OP_31_XOP_DCBZ 1010 @@ -94,7 +95,7 @@ static bool spr_allowed(struct kvm_vcpu *vcpu, enum priv_level level) } #ifdef CONFIG_PPC_TRANSACTIONAL_MEM -void kvmppc_copyto_vcpu_tm(struct kvm_vcpu *vcpu) +static void kvmppc_copyto_vcpu_tm(struct kvm_vcpu *vcpu) { memcpy(&vcpu->arch.gpr_tm[0], &vcpu->arch.gpr[0], sizeof(vcpu->arch.gpr_tm)); @@ -166,6 +167,32 @@ static void kvmppc_emulate_treclaim(struct kvm_vcpu *vcpu, int ra_val) tm_disable(); preempt_enable(); } + +static void kvmppc_emulate_trchkpt(struct kvm_vcpu *vcpu) +{ + unsigned long guest_msr = kvmppc_get_msr(vcpu); + + preempt_disable(); + vcpu->arch.save_msr_tm = MSR_TS_S; + vcpu->arch.save_msr_tm &= ~(MSR_FP | MSR_VEC | MSR_VSX); + vcpu->arch.save_msr_tm |= (vcpu->arch.guest_owned_ext & + (MSR_FP | MSR_VEC | MSR_VSX)); + /* + * need flush FP/VEC/VSX to vcpu save area before + * copy. + */ + kvmppc_giveup_ext(vcpu, MSR_VSX); + kvmppc_copyto_vcpu_tm(vcpu); + kvmppc_restore_tm_pr(vcpu); + preempt_enable(); + + /* + * as a result of trecheckpoint. set TS to suspended. + */ + guest_msr &= ~(MSR_TS_MASK); + guest_msr |= MSR_TS_S; + kvmppc_set_msr(vcpu, guest_msr); +} #endif int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, @@ -457,6 +484,34 @@ int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, kvmppc_emulate_treclaim(vcpu, ra_val); break; } + case OP_31_XOP_TRCHKPT: + { + ulong guest_msr = kvmppc_get_msr(vcpu); + unsigned long texasr; + + /* generate interrupt based on priorities */ + if (guest_msr & MSR_PR) { + /* Privileged Instruction type Program Intr */ + kvmppc_core_queue_program(vcpu, SRR1_PROGPRIV); + emulated = EMULATE_AGAIN; + break; + } + + tm_enable(); + texasr = mfspr(SPRN_TEXASR); + tm_disable(); + + if (MSR_TM_ACTIVE(guest_msr) || + !(texasr & (TEXASR_FS))) { + /* TM bad thing interrupt */ + kvmppc_core_queue_program(vcpu, SRR1_PROGTM); + emulated = EMULATE_AGAIN; + break; + } + + kvmppc_emulate_trchkpt(vcpu); + break; + } #endif default: emulated = EMULATE_FAIL; From patchwork Thu Jan 11 10:11:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 858998 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Y6o8q2tB"; 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Thu, 11 Jan 2018 02:13:12 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 23/26] KVM: PPC: Book3S PR: add emulation for tabort. for privilege guest Date: Thu, 11 Jan 2018 18:11:36 +0800 Message-Id: <1515665499-31710-24-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo Currently privilege guest will be run with TM disabled. Although the privilege guest cannot initiate a new transaction, it can use tabort to terminate its problem state's transaction. So it is still necessary to emulate tabort. for privilege guest. This patch adds emulation for tabort. of privilege guest. Tested with: https://github.com/justdoitqd/publicFiles/blob/master/test_tabort.c Signed-off-by: Simon Guo --- arch/powerpc/include/asm/kvm_book3s.h | 1 + arch/powerpc/kvm/book3s_emulate.c | 31 +++++++++++++++++++++++++++++++ arch/powerpc/kvm/book3s_pr.c | 2 +- 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h index 524cd82..8bd454c 100644 --- a/arch/powerpc/include/asm/kvm_book3s.h +++ b/arch/powerpc/include/asm/kvm_book3s.h @@ -258,6 +258,7 @@ extern void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu, void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu); void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu); void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu); +void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu); #endif extern int kvm_irq_bypass; diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c index 52a2e46..65eb236 100644 --- a/arch/powerpc/kvm/book3s_emulate.c +++ b/arch/powerpc/kvm/book3s_emulate.c @@ -50,6 +50,7 @@ #define OP_31_XOP_SLBMFEE 915 #define OP_31_XOP_TBEGIN 654 +#define OP_31_XOP_TABORT 910 #define OP_31_XOP_TRECLAIM 942 #define OP_31_XOP_TRCHKPT 1006 @@ -193,6 +194,19 @@ static void kvmppc_emulate_trchkpt(struct kvm_vcpu *vcpu) guest_msr |= MSR_TS_S; kvmppc_set_msr(vcpu, guest_msr); } + +/* emulate tabort. at guest privilege state */ +static void kvmppc_emulate_tabort(struct kvm_vcpu *vcpu, int ra_val) +{ + /* currently we only emulate tabort. but no emulation of other + * tabort variants since there is no kernel usage of them at + * present. + */ + tm_enable(); + tm_abort(ra_val); + tm_disable(); +} + #endif int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, @@ -459,6 +473,23 @@ int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, emulated = EMULATE_FAIL; break; } + case OP_31_XOP_TABORT: + { + ulong guest_msr = kvmppc_get_msr(vcpu); + unsigned long ra_val = 0; + + /* only emulate for privilege guest, since problem state + * guest can run with TM enabled and we don't expect to + * trap at here for that case. + */ + WARN_ON(guest_msr & MSR_PR); + + if (ra) + ra_val = kvmppc_get_gpr(vcpu, ra); + + kvmppc_emulate_tabort(vcpu, ra_val); + break; + } case OP_31_XOP_TRECLAIM: { ulong guest_msr = kvmppc_get_msr(vcpu); diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index 1d105fa..f65415b 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -246,7 +246,7 @@ void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu, } #ifdef CONFIG_PPC_TRANSACTIONAL_MEM -static inline void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu) +inline void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu) { tm_enable(); vcpu->arch.tfhar = mfspr(SPRN_TFHAR); From patchwork Thu Jan 11 10:11:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 859000 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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Thu, 11 Jan 2018 02:13:16 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 24/26] KVM: PPC: Book3S PR: add guard code to prevent returning to guest with PR=0 and Transactional state Date: Thu, 11 Jan 2018 18:11:37 +0800 Message-Id: <1515665499-31710-25-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo Currently PR KVM doesn't support transaction memory at guest privilege state. This patch adds a check at setting guest msr, so that we can never return to guest with PR=0 and TS=0b10. A tabort will be emulated to indicate this and fail transaction immediately. Signed-off-by: Simon Guo --- arch/powerpc/include/uapi/asm/tm.h | 2 +- arch/powerpc/kvm/book3s.h | 1 + arch/powerpc/kvm/book3s_emulate.c | 2 +- arch/powerpc/kvm/book3s_pr.c | 13 ++++++++++++- 4 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/uapi/asm/tm.h b/arch/powerpc/include/uapi/asm/tm.h index e1bf0e2..e2947c9 100644 --- a/arch/powerpc/include/uapi/asm/tm.h +++ b/arch/powerpc/include/uapi/asm/tm.h @@ -13,7 +13,7 @@ #define TM_CAUSE_TLBI 0xdc #define TM_CAUSE_FAC_UNAV 0xda #define TM_CAUSE_SYSCALL 0xd8 -#define TM_CAUSE_MISC 0xd6 /* future use */ +#define TM_CAUSE_PRIV_T 0xd6 #define TM_CAUSE_SIGNAL 0xd4 #define TM_CAUSE_ALIGNMENT 0xd2 #define TM_CAUSE_EMULATE 0xd0 diff --git a/arch/powerpc/kvm/book3s.h b/arch/powerpc/kvm/book3s.h index d2b3ec0..9beb57b 100644 --- a/arch/powerpc/kvm/book3s.h +++ b/arch/powerpc/kvm/book3s.h @@ -32,4 +32,5 @@ extern int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, extern int kvmppc_book3s_init_pr(void); extern void kvmppc_book3s_exit_pr(void); +extern void kvmppc_emulate_tabort(struct kvm_vcpu *vcpu, int ra_val); #endif diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c index 65eb236..11d76be 100644 --- a/arch/powerpc/kvm/book3s_emulate.c +++ b/arch/powerpc/kvm/book3s_emulate.c @@ -196,7 +196,7 @@ static void kvmppc_emulate_trchkpt(struct kvm_vcpu *vcpu) } /* emulate tabort. at guest privilege state */ -static void kvmppc_emulate_tabort(struct kvm_vcpu *vcpu, int ra_val) +void kvmppc_emulate_tabort(struct kvm_vcpu *vcpu, int ra_val) { /* currently we only emulate tabort. but no emulation of other * tabort variants since there is no kernel usage of them at diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index f65415b..cc568bc 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -461,12 +461,23 @@ static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu) static void kvmppc_set_msr_pr(struct kvm_vcpu *vcpu, u64 msr) { - ulong old_msr = kvmppc_get_msr(vcpu); + ulong old_msr; #ifdef EXIT_DEBUG printk(KERN_INFO "KVM: Set MSR to 0x%llx\n", msr); #endif +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + /* We should never target guest MSR to TS=10 && PR=0, + * since we always fail transaction for guest privilege + * state. + */ + if (!(msr & MSR_PR) && MSR_TM_TRANSACTIONAL(msr)) + kvmppc_emulate_tabort(vcpu, + TM_CAUSE_PRIV_T | TM_CAUSE_PERSISTENT); +#endif + + old_msr = kvmppc_get_msr(vcpu); msr &= to_book3s(vcpu)->msr_mask; kvmppc_set_msr_fast(vcpu, msr); kvmppc_recalc_shadow_msr(vcpu); From patchwork Thu Jan 11 10:11:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 859001 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; 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Thu, 11 Jan 2018 02:13:20 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.13.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:13:19 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 25/26] KVM: PPC: Book3S PR: Support TAR handling for PR KVM HTM. Date: Thu, 11 Jan 2018 18:11:38 +0800 Message-Id: <1515665499-31710-26-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo Currently guest kernel doesn't handle TAR fac unavailable and it always runs with TAR bit on. PR KVM will lazily enable TAR. TAR is not a frequent-use reg and it is not included in SVCPU struct. To make it work for transaction memory at PR KVM: 1). Flush/giveup TAR at kvmppc_save_tm_pr(). 2) If we are receiving a TAR fac unavail exception inside a transaction, the checkpointed TAR might be a TAR value from another process. So we need treclaim the transaction, then load the desired TAR value into reg, and perform trecheckpoint. 3) Load TAR facility at kvmppc_restore_tm_pr() when TM active. The reason we always loads TAR when restoring TM is that: If we don't do this way, when there is a TAR fac unavailable exception during TM active: case 1: it is the 1st TAR fac unavail exception after tbegin. vcpu->arch.tar should be reloaded as checkpoint tar val. case 2: it is the 2nd or later TAR fac unavail exception after tbegin. vcpu->arch.tar_tm should be reloaded as checkpoint tar val. There will be unnecessary difficulty to handle the above 2 cases. at the end of emulating treclaim., the correct TAR val need to be loaded into reg if FSCR_TAR bit is on. at the beginning of emulating trechkpt., TAR needs to be flushed so that the right tar val can be copy into tar_tm. Tested with: tools/testing/selftests/powerpc/tm/tm-tar tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar (remove DSCR/PPR related testing). Signed-off-by: Simon Guo --- arch/powerpc/include/asm/kvm_book3s.h | 1 + arch/powerpc/kvm/book3s_emulate.c | 4 ++++ arch/powerpc/kvm/book3s_pr.c | 31 +++++++++++++++++++++++++++++-- arch/powerpc/kvm/tm.S | 16 ++++++++++++++-- 4 files changed, 48 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h index 8bd454c..6635506 100644 --- a/arch/powerpc/include/asm/kvm_book3s.h +++ b/arch/powerpc/include/asm/kvm_book3s.h @@ -259,6 +259,7 @@ extern void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu, void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu); void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu); void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu); +void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac); #endif extern int kvm_irq_bypass; diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c index 11d76be..52ae307 100644 --- a/arch/powerpc/kvm/book3s_emulate.c +++ b/arch/powerpc/kvm/book3s_emulate.c @@ -167,6 +167,9 @@ static void kvmppc_emulate_treclaim(struct kvm_vcpu *vcpu, int ra_val) mtspr(SPRN_TFIAR, vcpu->arch.tfiar); tm_disable(); preempt_enable(); + + if (vcpu->arch.shadow_fscr & FSCR_TAR) + mtspr(SPRN_TAR, vcpu->arch.tar); } static void kvmppc_emulate_trchkpt(struct kvm_vcpu *vcpu) @@ -183,6 +186,7 @@ static void kvmppc_emulate_trchkpt(struct kvm_vcpu *vcpu) * copy. */ kvmppc_giveup_ext(vcpu, MSR_VSX); + kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); kvmppc_copyto_vcpu_tm(vcpu); kvmppc_restore_tm_pr(vcpu); preempt_enable(); diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index cc568bc..9085524 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -56,7 +56,6 @@ static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, ulong msr); static int kvmppc_load_ext(struct kvm_vcpu *vcpu, ulong msr); -static void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac); /* Some compatibility defines */ #ifdef CONFIG_PPC_BOOK3S_32 @@ -306,6 +305,7 @@ void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu) vcpu->arch.save_msr_tm |= (vcpu->arch.guest_owned_ext & (MSR_FP | MSR_VEC | MSR_VSX)); + kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); kvmppc_giveup_ext(vcpu, MSR_VSX); preempt_disable(); @@ -320,8 +320,20 @@ void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu) return; } + preempt_disable(); _kvmppc_restore_tm_pr(vcpu, vcpu->arch.save_msr_tm); + + if (!(vcpu->arch.shadow_fscr & FSCR_TAR)) { + /* always restore TAR in TM active state, since we don't + * want to be confused at fac unavailable while TM active: + * load vcpu->arch.tar or vcpu->arch.tar_tm as chkpt value? + */ + current->thread.tar = mfspr(SPRN_TAR); + mtspr(SPRN_TAR, vcpu->arch.tar); + vcpu->arch.shadow_fscr |= FSCR_TAR; + } + preempt_enable(); if (vcpu->arch.save_msr_tm & MSR_VSX) @@ -333,6 +345,7 @@ void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu) if (vcpu->arch.save_msr_tm & MSR_FP) kvmppc_load_ext(vcpu, MSR_FP); } + } #endif @@ -828,7 +841,7 @@ void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr) } /* Give up facility (TAR / EBB / DSCR) */ -static void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac) +void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac) { #ifdef CONFIG_PPC_BOOK3S_64 if (!(vcpu->arch.shadow_fscr & (1ULL << fac))) { @@ -1031,6 +1044,20 @@ static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac) switch (fac) { case FSCR_TAR_LG: + if (MSR_TM_ACTIVE(mfmsr())) { + /* When tbegin. was executed, the TAR in checkpoint + * state might be invalid. We need treclaim., then + * load correct TAR value, and perform trechkpt., + * so that valid TAR val can be checkpointed. + */ + preempt_disable(); + kvmppc_save_tm_pr(vcpu); + + vcpu->arch.tar_tm = vcpu->arch.tar; + + kvmppc_restore_tm_pr(vcpu); + preempt_enable(); + } /* TAR switching isn't lazy in Linux yet */ current->thread.tar = mfspr(SPRN_TAR); mtspr(SPRN_TAR, vcpu->arch.tar); diff --git a/arch/powerpc/kvm/tm.S b/arch/powerpc/kvm/tm.S index 5752bae..8b73af4 100644 --- a/arch/powerpc/kvm/tm.S +++ b/arch/powerpc/kvm/tm.S @@ -164,13 +164,16 @@ _GLOBAL(_kvmppc_save_tm_pr) mfmsr r5 SAVE_GPR(5, r1) - /* also save DSCR/CR so that it can be recovered later */ + /* also save DSCR/CR/TAR so that it can be recovered later */ mfspr r6, SPRN_DSCR SAVE_GPR(6, r1) mfcr r7 stw r7, _CCR(r1) + mfspr r8, SPRN_TAR + SAVE_GPR(8, r1) + /* allocate stack frame for __kvmppc_save_tm since * it will save LR into its stackframe and we don't * want to corrupt _kvmppc_save_tm_pr's. @@ -179,6 +182,9 @@ _GLOBAL(_kvmppc_save_tm_pr) bl __kvmppc_save_tm addi r1, r1, PPC_MIN_STKFRM + REST_GPR(8, r1) + mtspr SPRN_TAR, r8 + ld r7, _CCR(r1) mtcr r7 @@ -341,13 +347,16 @@ _GLOBAL(_kvmppc_restore_tm_pr) mfmsr r5 SAVE_GPR(5, r1) - /* also save DSCR/CR so that it can be recovered later */ + /* also save DSCR/CR/TAR so that it can be recovered later */ mfspr r6, SPRN_DSCR SAVE_GPR(6, r1) mfcr r7 stw r7, _CCR(r1) + mfspr r8, SPRN_TAR + SAVE_GPR(8, r1) + /* allocate stack frame for __kvmppc_restore_tm since * it will save LR into its own stackframe. */ @@ -356,6 +365,9 @@ _GLOBAL(_kvmppc_restore_tm_pr) bl __kvmppc_restore_tm addi r1, r1, PPC_MIN_STKFRM + REST_GPR(8, r1) + mtspr SPRN_TAR, r8 + ld r7, _CCR(r1) mtcr r7 From patchwork Thu Jan 11 10:11:39 2018 Content-Type: text/plain; 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Thu, 11 Jan 2018 02:13:24 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.13.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:13:23 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH 26/26] KVM: PPC: Book3S PR: enable HTM for PR KVM for KVM_CHECK_EXTENSION ioctl Date: Thu, 11 Jan 2018 18:11:39 +0800 Message-Id: <1515665499-31710-27-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo With current patch set, PR KVM now supports HTM. So this patch turns it on for PR KVM. Tested with: https://github.com/justdoitqd/publicFiles/blob/master/test_kvm_htm_cap.c Signed-off-by: Simon Guo --- arch/powerpc/kvm/powerpc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c index 1915e86..0b431aa 100644 --- a/arch/powerpc/kvm/powerpc.c +++ b/arch/powerpc/kvm/powerpc.c @@ -643,8 +643,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) break; #endif case KVM_CAP_PPC_HTM: - r = hv_enabled && - (cur_cpu_spec->cpu_user_features2 & PPC_FEATURE2_HTM_COMP); + r = (cur_cpu_spec->cpu_user_features2 & PPC_FEATURE2_HTM_COMP); break; default: r = 0;