From patchwork Wed Jan 27 09:20:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jakub Jelinek X-Patchwork-Id: 1432091 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=TxF3raq5; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DQdPd43C3z9sVS for ; Wed, 27 Jan 2021 20:20:51 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7F5F73945C09; Wed, 27 Jan 2021 09:20:48 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7F5F73945C09 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1611739248; bh=go26zp9nA+AnWE7uOsDSKAhcLokXLnDd1UXchFu1XIU=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=TxF3raq5P1avPM4i/SQR/RWMnIoY818VSJMCDYuKlmV0yFDuErKs90QBmvON8kBMH h4zDZXnQ4KS2tFjyaB6hboyYNEZvuRWM2u/DlxU4m062aTcrutF7kcI3pUXlYFvCHo l5fcu72vnJ4zpvCX7VQMcQtzqFVWFkjfypjz0Axk= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by sourceware.org (Postfix) with ESMTP id 4BA103939C28 for ; Wed, 27 Jan 2021 09:20:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 4BA103939C28 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-221-EYwwVsCaO5updu5yMqXUhQ-1; Wed, 27 Jan 2021 04:20:43 -0500 X-MC-Unique: EYwwVsCaO5updu5yMqXUhQ-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 7CD449CDA2; Wed, 27 Jan 2021 09:20:42 +0000 (UTC) Received: from tucnak.zalov.cz (ovpn-112-64.ams2.redhat.com [10.36.112.64]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 0321E10021AA; Wed, 27 Jan 2021 09:20:41 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.16.1/8.16.1) with ESMTPS id 10R9KdpQ3393516 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Wed, 27 Jan 2021 10:20:39 +0100 Received: (from jakub@localhost) by tucnak.zalov.cz (8.16.1/8.16.1/Submit) id 10R9Kc5B3393515; Wed, 27 Jan 2021 10:20:38 +0100 Date: Wed, 27 Jan 2021 10:20:38 +0100 To: Uros Bizjak Subject: [PATCH] i386: Add peephole2 for __atomic_sub_fetch (x, y, z) == 0 [PR98737] Message-ID: <20210127092038.GN4020736@tucnak> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Disposition: inline X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jakub Jelinek via Gcc-patches From: Jakub Jelinek Reply-To: Jakub Jelinek Cc: gcc-patches@gcc.gnu.org Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi! This patch adds a peephole2 for the optimization requested in the PR, namely that we emit awful code for __atomic_sub_fetch (x, y, z) == 0 or __atomic_sub_fetch (x, y, z) != 0 when y is not constant. This can't be done in the combiner which punts on combining UNSPEC_VOLATILE into other insns. For other ops we'd need different peephole2s, this one is specific with its comparison instruction and negation that need to be matched. Bootstrapped/regtested on x86_64-linux and i686-linux. Is this ok for trunk (as exception), or for GCC 12? 2021-01-27 Jakub Jelinek PR target/98737 * config/i386/sync.md (neg; mov; lock xadd; add peephole2): New define_peephole2. (*atomic_fetch_sub_cmp): New define_insn. * gcc.target/i386/pr98737.c: New test. Jakub --- gcc/config/i386/sync.md.jj 2021-01-04 10:25:45.392159555 +0100 +++ gcc/config/i386/sync.md 2021-01-26 16:03:13.911100510 +0100 @@ -777,6 +777,63 @@ (define_insn "*atomic_fetch_add_cmp}\t{%1, %0|%0, %1}"; }) +;; Similarly, peephole for __sync_sub_fetch (x, b) == 0 into just +;; lock sub followed by testing of flags instead of lock xadd, negation and +;; comparison. +(define_peephole2 + [(parallel [(set (match_operand 0 "register_operand") + (neg (match_dup 0))) + (clobber (reg:CC FLAGS_REG))]) + (set (match_operand:SWI 1 "register_operand") + (match_operand:SWI 2 "register_operand")) + (parallel [(set (match_operand:SWI 3 "register_operand") + (unspec_volatile:SWI + [(match_operand:SWI 4 "memory_operand") + (match_operand:SI 5 "const_int_operand")] + UNSPECV_XCHG)) + (set (match_dup 4) + (plus:SWI (match_dup 4) + (match_dup 3))) + (clobber (reg:CC FLAGS_REG))]) + (parallel [(set (reg:CCZ FLAGS_REG) + (compare:CCZ (neg:SWI + (match_operand:SWI 6 "register_operand")) + (match_dup 3))) + (clobber (match_dup 3))])] + "(GET_MODE (operands[0]) == mode + || GET_MODE (operands[0]) == mode) + && reg_or_subregno (operands[0]) == reg_or_subregno (operands[2]) + && (rtx_equal_p (operands[2], operands[3]) + ? rtx_equal_p (operands[1], operands[6]) + : (rtx_equal_p (operands[2], operands[6]) + && rtx_equal_p (operands[1], operands[3]))) + && peep2_reg_dead_p (4, operands[6]) + && peep2_reg_dead_p (4, operands[3]) + && !reg_overlap_mentioned_p (operands[1], operands[4]) + && !reg_overlap_mentioned_p (operands[2], operands[4])" + [(parallel [(set (reg:CCZ FLAGS_REG) + (compare:CCZ + (unspec_volatile:SWI [(match_dup 4) (match_dup 5)] + UNSPECV_XCHG) + (match_dup 2))) + (set (match_dup 4) + (minus:SWI (match_dup 4) + (match_dup 2)))])]) + +(define_insn "*atomic_fetch_sub_cmp" + [(set (reg:CCZ FLAGS_REG) + (compare:CCZ + (unspec_volatile:SWI + [(match_operand:SWI 0 "memory_operand" "+m") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPECV_XCHG) + (match_operand:SWI 1 "register_operand" "r"))) + (set (match_dup 0) + (minus:SWI (match_dup 0) + (match_dup 1)))] + "" + "lock{%;} %K2sub{}\t{%1, %0|%0, %1}") + ;; Recall that xchg implicitly sets LOCK#, so adding it again wastes space. ;; In addition, it is always a full barrier, so we can ignore the memory model. (define_insn "atomic_exchange" --- gcc/testsuite/gcc.target/i386/pr98737.c.jj 2021-01-26 15:59:24.640620178 +0100 +++ gcc/testsuite/gcc.target/i386/pr98737.c 2021-01-26 16:00:02.898205888 +0100 @@ -0,0 +1,38 @@ +/* PR target/98737 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -masm=att" } */ +/* { dg-additional-options "-march=i686" { target ia32 } } */ +/* { dg-final { scan-assembler "lock\[^\n\r]\*subq\t" { target lp64 } } } */ +/* { dg-final { scan-assembler "lock\[^\n\r]\*subl\t" } } */ +/* { dg-final { scan-assembler "lock\[^\n\r]\*subw\t" } } */ +/* { dg-final { scan-assembler "lock\[^\n\r]\*subb\t" } } */ +/* { dg-final { scan-assembler-not "lock\[^\n\r]\*xadd" } } */ + +long a; +int b; +short c; +char d; + +int +foo (long x) +{ + return __atomic_sub_fetch (&a, x, __ATOMIC_RELEASE) == 0; +} + +int +bar (int x) +{ + return __atomic_sub_fetch (&b, x, __ATOMIC_RELEASE) == 0; +} + +int +baz (short x) +{ + return __atomic_sub_fetch (&c, x, __ATOMIC_RELEASE) == 0; +} + +int +qux (char x) +{ + return __atomic_sub_fetch (&d, x, __ATOMIC_RELEASE) == 0; +}