From patchwork Thu Jan 11 06:08:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 858816 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHFmr2T8qz9t34 for ; Thu, 11 Jan 2018 17:08:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753515AbeAKGIZ (ORCPT ); Thu, 11 Jan 2018 01:08:25 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5249 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751017AbeAKGIY (ORCPT ); Thu, 11 Jan 2018 01:08:24 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 10 Jan 2018 22:08:25 -0800 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 10 Jan 2018 22:09:19 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 10 Jan 2018 22:09:19 -0800 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 11 Jan 2018 06:08:23 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Thu, 11 Jan 2018 06:08:23 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.32]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 10 Jan 2018 22:08:22 -0800 From: Manikanta Maddireddy To: , , , CC: , , , , , , , , , , , Manikanta Maddireddy Subject: [PATCH V6 1/7] of: Export of_pci_range_to_resource() Date: Thu, 11 Jan 2018 11:38:02 +0530 Message-ID: <1515650888-9459-2-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1515650888-9459-1-git-send-email-mmaddireddy@nvidia.com> References: <1515650888-9459-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra PCIe host driver parses of_pci_range from device tree and converts to resource. Export of_pci_range_to_resource() to allow Tegra PCIe host driver to be compiled as loadable kernel module. Signed-off-by: Manikanta Maddireddy Acked-by: Rob Herring --- V2: * commit message update V3: * no change in this patch V4: * no change in this patch V5: * no change in this patch V6: * no change in this patch drivers/of/address.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/of/address.c b/drivers/of/address.c index fa6cabfc3cb9..8d9b93f8701a 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c @@ -361,6 +361,7 @@ int of_pci_range_to_resource(struct of_pci_range *range, res->end = (resource_size_t)OF_BAD_ADDR; return err; } +EXPORT_SYMBOL(of_pci_range_to_resource); #endif /* CONFIG_PCI */ /* From patchwork Thu Jan 11 06:08:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 858817 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHFmv16qrz9s7n for ; Thu, 11 Jan 2018 17:08:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753639AbeAKGI3 (ORCPT ); Thu, 11 Jan 2018 01:08:29 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:13342 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751017AbeAKGI2 (ORCPT ); Thu, 11 Jan 2018 01:08:28 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Wed, 10 Jan 2018 22:08:42 -0800 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 10 Jan 2018 22:08:28 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 10 Jan 2018 22:08:28 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 11 Jan 2018 06:08:28 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Thu, 11 Jan 2018 06:08:28 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.32]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 10 Jan 2018 22:08:27 -0800 From: Manikanta Maddireddy To: , , , CC: , , , , , , , , , , , Manikanta Maddireddy Subject: [PATCH V6 2/7] PCI: tegra: Use bus->sysdata to store and get host private data Date: Thu, 11 Jan 2018 11:38:03 +0530 Message-ID: <1515650888-9459-3-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1515650888-9459-1-git-send-email-mmaddireddy@nvidia.com> References: <1515650888-9459-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra host driver is using pci_find_host_bridge() to get private data, however pci_find_host_bridge() is causing module build failure because it is not exported. pci_find_host_bridge() can be avoided by using bus->sysdata to store and get private data. Signed-off-by: Manikanta Maddireddy Acked-by: Thierry Reding --- V4: * new patch in V4 V5: * Rebase on top of linux-next V6: * no change in this patch drivers/pci/host/pci-tegra.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 4c105fbda777..059aa73d5f76 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -379,8 +379,7 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { - struct pci_host_bridge *host = pci_find_host_bridge(bus); - struct tegra_pcie *pcie = pci_host_bridge_priv(host); + struct tegra_pcie *pcie = bus->sysdata; void __iomem *addr = NULL; if (bus->number == 0) { @@ -573,8 +572,7 @@ static int tegra_pcie_request_resources(struct tegra_pcie *pcie) static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin) { - struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus); - struct tegra_pcie *pcie = pci_host_bridge_priv(host); + struct tegra_pcie *pcie = pdev->bus->sysdata; int irq; tegra_cpuidle_pcie_irqs_in_use(); @@ -2258,6 +2256,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) return -ENOMEM; pcie = pci_host_bridge_priv(host); + host->sysdata = pcie; pcie->soc = of_device_get_match_data(dev); INIT_LIST_HEAD(&pcie->ports); From patchwork Thu Jan 11 06:08:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 858820 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHFn10Z03z9s7n for ; Thu, 11 Jan 2018 17:08:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753712AbeAKGIe (ORCPT ); Thu, 11 Jan 2018 01:08:34 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:13354 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753683AbeAKGId (ORCPT ); Thu, 11 Jan 2018 01:08:33 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Wed, 10 Jan 2018 22:08:47 -0800 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 10 Jan 2018 22:08:33 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 10 Jan 2018 22:08:33 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 11 Jan 2018 06:08:33 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Thu, 11 Jan 2018 06:08:32 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.32]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 10 Jan 2018 22:08:32 -0800 From: Manikanta Maddireddy To: , , , CC: , , , , , , , , , , , Manikanta Maddireddy Subject: [PATCH V6 3/7] PCI: tegra: Remove PCI_REASSIGN_ALL_BUS flag for Tegra PCIe Date: Thu, 11 Jan 2018 11:38:04 +0530 Message-ID: <1515650888-9459-4-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1515650888-9459-1-git-send-email-mmaddireddy@nvidia.com> References: <1515650888-9459-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Primary, secondary and subordinate default bus numbers are 0 in Tegra and it is expecting SW to program these numbers in configration space. pci_scan_bridge_extend() function programs these numbers in configuration space if secondary & subordinate bus numbers are 0 or PCI_REASSIGN_ALL_BUS flag is set. Since secondary & subordinate default bus numbers are 0, PCI_REASSIGN_ALL_BUS flag can be removed for Tegra PCIe. Signed-off-by: Manikanta Maddireddy Acked-by: Thierry Reding --- V3: * new patch in V3 V4: * no change in this patch V5: * no change in this patch V6: * Rebased on lpieralisi/pci/tegra branch drivers/pci/host/pci-tegra.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 059aa73d5f76..e4b47ebc91fe 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -2293,7 +2293,6 @@ static int tegra_pcie_probe(struct platform_device *pdev) tegra_pcie_enable_ports(pcie); - pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS); host->busnr = pcie->busn.start; host->dev.parent = &pdev->dev; host->ops = &tegra_pcie_ops; From patchwork Thu Jan 11 06:08:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 858822 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHFn50MyJz9t34 for ; Thu, 11 Jan 2018 17:08:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753777AbeAKGIj (ORCPT ); Thu, 11 Jan 2018 01:08:39 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5267 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753762AbeAKGIi (ORCPT ); Thu, 11 Jan 2018 01:08:38 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 10 Jan 2018 22:08:39 -0800 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 10 Jan 2018 22:08:38 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 10 Jan 2018 22:08:38 -0800 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 11 Jan 2018 06:08:37 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Thu, 11 Jan 2018 06:08:37 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.32]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 10 Jan 2018 22:08:36 -0800 From: Manikanta Maddireddy To: , , , CC: , , , , , , , , , , , Manikanta Maddireddy Subject: [PATCH V6 4/7] PCI: tegra: Free resources on probe failure Date: Thu, 11 Jan 2018 11:38:05 +0530 Message-ID: <1515650888-9459-5-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1515650888-9459-1-git-send-email-mmaddireddy@nvidia.com> References: <1515650888-9459-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org tegra_pcie_probe() can fail in multiple instances, this patch takes care of freeing the resources which are allocated before probe fail. Signed-off-by: Manikanta Maddireddy Acked-by: Thierry Reding --- V2: * no change in this patch V3: * change 'if check' to 'legacy_phy is true' for tegra_pcie_phys_put_legacy() * commit log correction V4: * no change in this patch V5: * Decoupled from https://patchwork.ozlabs.org/patch/832053/ and rebased on linux-next V6: * no change in this patch drivers/pci/host/pci-tegra.c | 99 +++++++++++++++++++++++++++++++++++--------- 1 file changed, 79 insertions(+), 20 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index e4b47ebc91fe..e68507f658d8 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -562,14 +562,25 @@ static int tegra_pcie_request_resources(struct tegra_pcie *pcie) pci_add_resource(windows, &pcie->busn); err = devm_request_pci_bus_resources(dev, windows); - if (err < 0) + if (err < 0) { + pci_free_resource_list(windows); return err; + } pci_remap_iospace(&pcie->pio, pcie->io.start); return 0; } +static void tegra_pcie_free_resources(struct tegra_pcie *pcie) +{ + struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); + struct list_head *windows = &host->windows; + + pci_unmap_iospace(&pcie->pio); + pci_free_resource_list(windows); +} + static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin) { struct tegra_pcie *pcie = pdev->bus->sysdata; @@ -979,24 +990,35 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) return 0; } -static void tegra_pcie_power_off(struct tegra_pcie *pcie) +static void tegra_pcie_disable_controller(struct tegra_pcie *pcie) { - struct device *dev = pcie->dev; - const struct tegra_pcie_soc *soc = pcie->soc; int err; - /* TODO: disable and unprepare clocks? */ + reset_control_assert(pcie->pcie_xrst); - if (soc->program_uphy) { + if (pcie->soc->program_uphy) { err = tegra_pcie_phy_power_off(pcie); if (err < 0) - dev_err(dev, "failed to power off PHY(s): %d\n", err); + dev_err(pcie->dev, "failed to power off PHY(s): %d\n", + err); } +} + +static void tegra_pcie_power_off(struct tegra_pcie *pcie) +{ + struct device *dev = pcie->dev; + const struct tegra_pcie_soc *soc = pcie->soc; + int err; - reset_control_assert(pcie->pcie_xrst); reset_control_assert(pcie->afi_rst); reset_control_assert(pcie->pex_rst); + clk_disable_unprepare(pcie->pll_e); + if (soc->has_cml_clk) + clk_disable_unprepare(pcie->cml_clk); + clk_disable_unprepare(pcie->afi_clk); + clk_disable_unprepare(pcie->pex_clk); + if (!dev->pm_domain) tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); @@ -1205,6 +1227,30 @@ static int tegra_pcie_phys_get(struct tegra_pcie *pcie) return 0; } +static void tegra_pcie_phys_put(struct tegra_pcie *pcie) +{ + struct tegra_pcie_port *port; + struct device *dev = pcie->dev; + int err, i; + + if (pcie->legacy_phy) { + err = phy_exit(pcie->phy); + if (err < 0) + dev_err(dev, "failed to teardown PHY: %d\n", err); + return; + } + + list_for_each_entry(port, &pcie->ports, list) { + for (i = 0; i < port->lanes; i++) { + err = phy_exit(port->phys[i]); + if (err < 0) + dev_err(dev, "failed to teardown PHY#%u: %d\n", + i, err); + } + } +} + + static int tegra_pcie_get_resources(struct tegra_pcie *pcie) { struct device *dev = pcie->dev; @@ -1236,7 +1282,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) err = tegra_pcie_power_on(pcie); if (err) { dev_err(dev, "failed to power up: %d\n", err); - return err; + goto phys_put; } pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads"); @@ -1288,6 +1334,9 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) return 0; +phys_put: + if (soc->program_uphy) + tegra_pcie_phys_put(pcie); poweroff: tegra_pcie_power_off(pcie); return err; @@ -1295,20 +1344,15 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) static int tegra_pcie_put_resources(struct tegra_pcie *pcie) { - struct device *dev = pcie->dev; const struct tegra_pcie_soc *soc = pcie->soc; - int err; if (pcie->irq > 0) free_irq(pcie->irq, pcie); tegra_pcie_power_off(pcie); - if (soc->program_uphy) { - err = phy_exit(pcie->phy); - if (err < 0) - dev_err(dev, "failed to teardown PHY: %d\n", err); - } + if (soc->program_uphy) + tegra_pcie_phys_put(pcie); return 0; } @@ -2048,6 +2092,16 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) } } +static void tegra_pcie_disable_ports(struct tegra_pcie *pcie) +{ + struct tegra_pcie_port *port, *tmp; + + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { + tegra_pcie_port_disable(port); + tegra_pcie_port_free(port); + } +} + static const struct tegra_pcie_soc tegra20_pcie = { .num_ports = 2, .msi_base_shift = 0, @@ -2278,7 +2332,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) err = tegra_pcie_request_resources(pcie); if (err) - goto put_resources; + goto disable_controller; /* setup the AFI address translations */ tegra_pcie_setup_translations(pcie); @@ -2287,7 +2341,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) err = tegra_pcie_enable_msi(pcie); if (err < 0) { dev_err(dev, "failed to enable MSI support: %d\n", err); - goto put_resources; + goto free_resources; } } @@ -2302,7 +2356,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) err = pci_scan_root_bus_bridge(host); if (err < 0) { dev_err(dev, "failed to register host: %d\n", err); - goto disable_msi; + goto disable_ports; } pci_bus_size_bridges(host->bus); @@ -2321,9 +2375,14 @@ static int tegra_pcie_probe(struct platform_device *pdev) return 0; -disable_msi: +disable_ports: + tegra_pcie_disable_ports(pcie); if (IS_ENABLED(CONFIG_PCI_MSI)) tegra_pcie_disable_msi(pcie); +free_resources: + tegra_pcie_free_resources(pcie); +disable_controller: + tegra_pcie_disable_controller(pcie); put_resources: tegra_pcie_put_resources(pcie); return err; From patchwork Thu Jan 11 06:08:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 858823 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHFn967NBz9t34 for ; Thu, 11 Jan 2018 17:08:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750892AbeAKGIo (ORCPT ); Thu, 11 Jan 2018 01:08:44 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5277 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753771AbeAKGIn (ORCPT ); Thu, 11 Jan 2018 01:08:43 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 10 Jan 2018 22:08:44 -0800 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 10 Jan 2018 22:08:43 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 10 Jan 2018 22:08:43 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 11 Jan 2018 06:08:42 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Thu, 11 Jan 2018 06:08:42 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.32]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 10 Jan 2018 22:08:41 -0800 From: Manikanta Maddireddy To: , , , CC: , , , , , , , , , , , Manikanta Maddireddy Subject: [PATCH V6 5/7] PCI: tegra: Add loadable kernel module support Date: Thu, 11 Jan 2018 11:38:06 +0530 Message-ID: <1515650888-9459-6-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1515650888-9459-1-git-send-email-mmaddireddy@nvidia.com> References: <1515650888-9459-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Implement remove callback function for Tegra PCIe driver to add loadable kernel module support. Change PCI_TEGRA config to tristate to allow pci-tegra driver to be build as a module. Signed-off-by: Manikanta Maddireddy Acked-by: Thierry Reding --- V2: * no change in this patch V3: * use tegra_pcie_debugfs_exit() helper function in tegra_pcie_debugfs_init() V4: * no change in this patch V5: * Decoupled from https://patchwork.ozlabs.org/patch/832053/ and rebased on linux-next V6: * no change in this patch drivers/pci/host/Kconfig | 2 +- drivers/pci/host/pci-tegra.c | 34 +++++++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index 38d12980db0f..6fd2a5937804 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -34,7 +34,7 @@ config PCI_FTPCI100 default ARCH_GEMINI config PCI_TEGRA - bool "NVIDIA Tegra PCIe controller" + tristate "NVIDIA Tegra PCIe controller" depends on ARCH_TEGRA help Say Y here if you want support for the PCIe host controller found diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index e68507f658d8..981f126b14d6 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -2276,6 +2277,12 @@ static const struct file_operations tegra_pcie_ports_ops = { .release = seq_release, }; +static void tegra_pcie_debugfs_exit(struct tegra_pcie *pcie) +{ + debugfs_remove_recursive(pcie->debugfs); + pcie->debugfs = NULL; +} + static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie) { struct dentry *file; @@ -2292,8 +2299,7 @@ static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie) return 0; remove: - debugfs_remove_recursive(pcie->debugfs); - pcie->debugfs = NULL; + tegra_pcie_debugfs_exit(pcie); return -ENOMEM; } @@ -2311,6 +2317,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) pcie = pci_host_bridge_priv(host); host->sysdata = pcie; + platform_set_drvdata(pdev, pcie); pcie->soc = of_device_get_match_data(dev); INIT_LIST_HEAD(&pcie->ports); @@ -2388,6 +2395,25 @@ static int tegra_pcie_probe(struct platform_device *pdev) return err; } +static int tegra_pcie_remove(struct platform_device *pdev) +{ + struct tegra_pcie *pcie = platform_get_drvdata(pdev); + struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); + + if (IS_ENABLED(CONFIG_DEBUG_FS)) + tegra_pcie_debugfs_exit(pcie); + pci_stop_root_bus(host->bus); + pci_remove_root_bus(host->bus); + tegra_pcie_disable_ports(pcie); + if (IS_ENABLED(CONFIG_PCI_MSI)) + tegra_pcie_disable_msi(pcie); + tegra_pcie_free_resources(pcie); + tegra_pcie_disable_controller(pcie); + tegra_pcie_put_resources(pcie); + + return 0; +} + static struct platform_driver tegra_pcie_driver = { .driver = { .name = "tegra-pcie", @@ -2395,5 +2421,7 @@ static struct platform_driver tegra_pcie_driver = { .suppress_bind_attrs = true, }, .probe = tegra_pcie_probe, + .remove = tegra_pcie_remove, }; -builtin_platform_driver(tegra_pcie_driver); +module_platform_driver(tegra_pcie_driver); +MODULE_LICENSE("GPL"); From patchwork Thu Jan 11 06:08:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 858826 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHFnH0MH9z9t34 for ; Thu, 11 Jan 2018 17:08:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753889AbeAKGIt (ORCPT ); Thu, 11 Jan 2018 01:08:49 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:1608 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753876AbeAKGIs (ORCPT ); Thu, 11 Jan 2018 01:08:48 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Wed, 10 Jan 2018 22:08:38 -0800 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 10 Jan 2018 22:09:43 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 10 Jan 2018 22:09:43 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 11 Jan 2018 06:08:47 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Thu, 11 Jan 2018 06:08:47 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.32]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 10 Jan 2018 22:08:46 -0800 From: Manikanta Maddireddy To: , , , CC: , , , , , , , , , , , Manikanta Maddireddy Subject: [PATCH V6 6/7] PCI: tegra: Broadcast PME_Turn_Off message before link goes to L2 Date: Thu, 11 Jan 2018 11:38:07 +0530 Message-ID: <1515650888-9459-7-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1515650888-9459-1-git-send-email-mmaddireddy@nvidia.com> References: <1515650888-9459-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Per PCIe r3.0, sec 5.3.3.2.1, PCIe root port shoould broadcast PME_Turn_Off message before PCIe link goes to L2. PME_Turn_Off broadcast mechanism is implemented in AFI module. Each Tegra PCIe root port has its own PME_Turn_Off and PME_TO_Ack bitmap in AFI_PME register, program this register to broadcast PME_Turn_Off message. Signed-off-by: Manikanta Maddireddy --- V2: * no change in this patch V3: * add PME bitmap in soc data instead of using compatible string * replace while loop with readl_poll_timeout() for polling * commit log correction V4: * no change in this patch V5: * Rebased on linux-next V6: * no change in this patch drivers/pci/host/pci-tegra.c | 45 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 981f126b14d6..cc33fc0fb300 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -153,6 +154,8 @@ #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) +#define AFI_PCIE_PME 0xf0 + #define AFI_PCIE_CONFIG 0x0f8 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe @@ -233,6 +236,8 @@ #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ +#define PME_ACK_TIMEOUT 10000 + struct tegra_msi { struct msi_controller chip; DECLARE_BITMAP(used, INT_PCI_MSI_NR); @@ -251,6 +256,8 @@ struct tegra_pcie_soc { u32 tx_ref_sel; u32 pads_refclk_cfg0; u32 pads_refclk_cfg1; + u8 pme_turnoff_bit[3]; + u8 pme_ack_bit[3]; bool has_pex_clkreq_en; bool has_pex_bias_ctrl; bool has_intr_prsnt_sense; @@ -1358,6 +1365,31 @@ static int tegra_pcie_put_resources(struct tegra_pcie *pcie) return 0; } +static void tegra_pcie_pme_turnoff(struct tegra_pcie_port *port) +{ + struct tegra_pcie *pcie = port->pcie; + const struct tegra_pcie_soc *soc = pcie->soc; + int err; + u32 val; + + val = afi_readl(pcie, AFI_PCIE_PME); + val |= (0x1 << soc->pme_turnoff_bit[port->index]); + afi_writel(pcie, val, AFI_PCIE_PME); + + err = readl_poll_timeout(pcie->afi + AFI_PCIE_PME, val, + val & (0x1 << soc->pme_ack_bit[port->index]), + 1, PME_ACK_TIMEOUT); + if (err) + dev_err(pcie->dev, "PME Ack is not received on port: %d\n", + port->index); + + usleep_range(10000, 11000); + + val = afi_readl(pcie, AFI_PCIE_PME); + val &= ~(0x1 << soc->pme_turnoff_bit[port->index]); + afi_writel(pcie, val, AFI_PCIE_PME); +} + static int tegra_msi_alloc(struct tegra_msi *chip) { int msi; @@ -2109,6 +2141,8 @@ static const struct tegra_pcie_soc tegra20_pcie = { .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, .pads_refclk_cfg0 = 0xfa5cfa5c, + .pme_turnoff_bit = {0, 8}, + .pme_ack_bit = {5, 10}, .has_pex_clkreq_en = false, .has_pex_bias_ctrl = false, .has_intr_prsnt_sense = false, @@ -2125,6 +2159,8 @@ static const struct tegra_pcie_soc tegra30_pcie = { .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, .pads_refclk_cfg0 = 0xfa5cfa5c, .pads_refclk_cfg1 = 0xfa5cfa5c, + .pme_turnoff_bit = {0, 8, 16}, + .pme_ack_bit = {5, 10, 18}, .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_intr_prsnt_sense = true, @@ -2140,6 +2176,8 @@ static const struct tegra_pcie_soc tegra124_pcie = { .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, .pads_refclk_cfg0 = 0x44ac44ac, + .pme_turnoff_bit = {0, 8}, + .pme_ack_bit = {5, 10}, .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_intr_prsnt_sense = true, @@ -2155,6 +2193,8 @@ static const struct tegra_pcie_soc tegra210_pcie = { .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, .pads_refclk_cfg0 = 0x90b890b8, + .pme_turnoff_bit = {0, 8}, + .pme_ack_bit = {5, 10}, .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_intr_prsnt_sense = true, @@ -2171,6 +2211,8 @@ static const struct tegra_pcie_soc tegra186_pcie = { .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, .pads_refclk_cfg0 = 0x80b880b8, .pads_refclk_cfg1 = 0x000480b8, + .pme_turnoff_bit = {0, 8, 12}, + .pme_ack_bit = {5, 10, 14}, .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_intr_prsnt_sense = true, @@ -2399,11 +2441,14 @@ static int tegra_pcie_remove(struct platform_device *pdev) { struct tegra_pcie *pcie = platform_get_drvdata(pdev); struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); + struct tegra_pcie_port *port, *tmp; if (IS_ENABLED(CONFIG_DEBUG_FS)) tegra_pcie_debugfs_exit(pcie); pci_stop_root_bus(host->bus); pci_remove_root_bus(host->bus); + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + tegra_pcie_pme_turnoff(port); tegra_pcie_disable_ports(pcie); if (IS_ENABLED(CONFIG_PCI_MSI)) tegra_pcie_disable_msi(pcie); From patchwork Thu Jan 11 06:08:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 858827 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHFnN0211z9s7n for ; Thu, 11 Jan 2018 17:08:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753660AbeAKGIy (ORCPT ); Thu, 11 Jan 2018 01:08:54 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:1620 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753876AbeAKGIx (ORCPT ); Thu, 11 Jan 2018 01:08:53 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Wed, 10 Jan 2018 22:08:43 -0800 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 10 Jan 2018 22:08:52 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 10 Jan 2018 22:08:52 -0800 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 11 Jan 2018 06:08:52 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Thu, 11 Jan 2018 06:08:52 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.32]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 10 Jan 2018 22:08:51 -0800 From: Manikanta Maddireddy To: , , , CC: , , , , , , , , , , , Manikanta Maddireddy Subject: [PATCH V6 7/7] PCI: tegra: Add power management support Date: Thu, 11 Jan 2018 11:38:08 +0530 Message-ID: <1515650888-9459-8-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1515650888-9459-1-git-send-email-mmaddireddy@nvidia.com> References: <1515650888-9459-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra186 powergate driver is implemented as power domain driver, power partition ungate/gate are registered as power_on/power_off callback functions. There are no direct functions to power gate/ungate host controller in Tegra186. Host controller driver should add "power-domains" property in device tree and implement runtime suspend and resume callback functons. Power gate and ungate is taken care by power domain driver when host controller driver calls pm_runtime_put_sync and pm_runtime_get_sync respectively. Register suspend_noirq & resume_noirq callback functions to allow PCIe to come up after resume from RAM. Both runtime and noirq pm ops share same callback functions. Signed-off-by: Manikanta Maddireddy --- V2: * no change in this patch V3: * no change in this patch V4: * no change in this patch V5: * Decoupled from https://patchwork.ozlabs.org/patch/832053/ and rebased on linux-next V6: * no change in this patch drivers/pci/host/pci-tegra.c | 181 ++++++++++++++++++++++++++----------------- 1 file changed, 110 insertions(+), 71 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index cc33fc0fb300..a106eb7ee695 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -1287,31 +1287,25 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) } } - err = tegra_pcie_power_on(pcie); - if (err) { - dev_err(dev, "failed to power up: %d\n", err); - goto phys_put; - } - pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads"); pcie->pads = devm_ioremap_resource(dev, pads); if (IS_ERR(pcie->pads)) { err = PTR_ERR(pcie->pads); - goto poweroff; + goto phys_put; } afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi"); pcie->afi = devm_ioremap_resource(dev, afi); if (IS_ERR(pcie->afi)) { err = PTR_ERR(pcie->afi); - goto poweroff; + goto phys_put; } /* request configuration space, but remap later, on demand */ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs"); if (!res) { err = -EADDRNOTAVAIL; - goto poweroff; + goto phys_put; } pcie->cs = *res; @@ -1322,14 +1316,14 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) pcie->cfg = devm_ioremap_resource(dev, &pcie->cs); if (IS_ERR(pcie->cfg)) { err = PTR_ERR(pcie->cfg); - goto poweroff; + goto phys_put; } /* request interrupt */ err = platform_get_irq_byname(pdev, "intr"); if (err < 0) { dev_err(dev, "failed to get IRQ: %d\n", err); - goto poweroff; + goto phys_put; } pcie->irq = err; @@ -1337,7 +1331,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie); if (err) { dev_err(dev, "failed to register IRQ: %d\n", err); - goto poweroff; + goto phys_put; } return 0; @@ -1345,8 +1339,6 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) phys_put: if (soc->program_uphy) tegra_pcie_phys_put(pcie); -poweroff: - tegra_pcie_power_off(pcie); return err; } @@ -1357,8 +1349,6 @@ static int tegra_pcie_put_resources(struct tegra_pcie *pcie) if (pcie->irq > 0) free_irq(pcie->irq, pcie); - tegra_pcie_power_off(pcie); - if (soc->program_uphy) tegra_pcie_phys_put(pcie); @@ -1536,37 +1526,41 @@ static int tegra_pcie_enable_msi(struct tegra_pcie *pcie) int err; u32 reg; - mutex_init(&msi->lock); + if (!msi->phys) { + mutex_init(&msi->lock); - msi->chip.dev = dev; - msi->chip.setup_irq = tegra_msi_setup_irq; - msi->chip.teardown_irq = tegra_msi_teardown_irq; + msi->chip.dev = dev; + msi->chip.setup_irq = tegra_msi_setup_irq; + msi->chip.teardown_irq = tegra_msi_teardown_irq; - msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR, - &msi_domain_ops, &msi->chip); - if (!msi->domain) { - dev_err(dev, "failed to create IRQ domain\n"); - return -ENOMEM; - } + msi->domain = irq_domain_add_linear(dev->of_node, + INT_PCI_MSI_NR, + &msi_domain_ops, + &msi->chip); + if (!msi->domain) { + dev_err(dev, "failed to create IRQ domain\n"); + return -ENOMEM; + } - err = platform_get_irq_byname(pdev, "msi"); - if (err < 0) { - dev_err(dev, "failed to get IRQ: %d\n", err); - goto err; - } + err = platform_get_irq_byname(pdev, "msi"); + if (err < 0) { + dev_err(dev, "failed to get IRQ: %d\n", err); + goto err; + } - msi->irq = err; + msi->irq = err; - err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD, - tegra_msi_irq_chip.name, pcie); - if (err < 0) { - dev_err(dev, "failed to request IRQ: %d\n", err); - goto err; - } + err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD, + tegra_msi_irq_chip.name, pcie); + if (err < 0) { + dev_err(dev, "failed to request IRQ: %d\n", err); + goto err; + } - /* setup AFI/FPCI range */ - msi->pages = __get_free_pages(GFP_KERNEL, 0); - msi->phys = virt_to_phys((void *)msi->pages); + /* setup AFI/FPCI range */ + msi->pages = __get_free_pages(GFP_KERNEL, 0); + msi->phys = virt_to_phys((void *)msi->pages); + } afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST); afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST); @@ -2129,10 +2123,8 @@ static void tegra_pcie_disable_ports(struct tegra_pcie *pcie) { struct tegra_pcie_port *port, *tmp; - list_for_each_entry_safe(port, tmp, &pcie->ports, list) { + list_for_each_entry_safe(port, tmp, &pcie->ports, list) tegra_pcie_port_disable(port); - tegra_pcie_port_free(port); - } } static const struct tegra_pcie_soc tegra20_pcie = { @@ -2375,26 +2367,16 @@ static int tegra_pcie_probe(struct platform_device *pdev) return err; } - err = tegra_pcie_enable_controller(pcie); - if (err) + pm_runtime_enable(pcie->dev); + err = pm_runtime_get_sync(pcie->dev); + if (err) { + dev_err(dev, "fail to enable pcie controller: %d\n", err); goto put_resources; + } err = tegra_pcie_request_resources(pcie); if (err) - goto disable_controller; - - /* setup the AFI address translations */ - tegra_pcie_setup_translations(pcie); - - if (IS_ENABLED(CONFIG_PCI_MSI)) { - err = tegra_pcie_enable_msi(pcie); - if (err < 0) { - dev_err(dev, "failed to enable MSI support: %d\n", err); - goto free_resources; - } - } - - tegra_pcie_enable_ports(pcie); + goto pm_runtime_put; host->busnr = pcie->busn.start; host->dev.parent = &pdev->dev; @@ -2405,7 +2387,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) err = pci_scan_root_bus_bridge(host); if (err < 0) { dev_err(dev, "failed to register host: %d\n", err); - goto disable_ports; + goto free_resources; } pci_bus_size_bridges(host->bus); @@ -2424,14 +2406,13 @@ static int tegra_pcie_probe(struct platform_device *pdev) return 0; -disable_ports: - tegra_pcie_disable_ports(pcie); - if (IS_ENABLED(CONFIG_PCI_MSI)) - tegra_pcie_disable_msi(pcie); free_resources: tegra_pcie_free_resources(pcie); -disable_controller: - tegra_pcie_disable_controller(pcie); +pm_runtime_put: + if (IS_ENABLED(CONFIG_PCI_MSI)) + tegra_pcie_disable_msi(pcie); + pm_runtime_put_sync(pcie->dev); + pm_runtime_disable(pcie->dev); put_resources: tegra_pcie_put_resources(pcie); return err; @@ -2447,23 +2428,81 @@ static int tegra_pcie_remove(struct platform_device *pdev) tegra_pcie_debugfs_exit(pcie); pci_stop_root_bus(host->bus); pci_remove_root_bus(host->bus); - list_for_each_entry_safe(port, tmp, &pcie->ports, list) - tegra_pcie_pme_turnoff(port); - tegra_pcie_disable_ports(pcie); if (IS_ENABLED(CONFIG_PCI_MSI)) tegra_pcie_disable_msi(pcie); tegra_pcie_free_resources(pcie); - tegra_pcie_disable_controller(pcie); + pm_runtime_put_sync(pcie->dev); + pm_runtime_disable(pcie->dev); tegra_pcie_put_resources(pcie); + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + tegra_pcie_port_free(port); + + return 0; +} + +static int tegra_pcie_pm_suspend(struct device *dev) +{ + struct tegra_pcie *pcie = dev_get_drvdata(dev); + struct tegra_pcie_port *port, *tmp; + + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + tegra_pcie_pme_turnoff(port); + tegra_pcie_disable_ports(pcie); + tegra_pcie_disable_controller(pcie); + tegra_pcie_power_off(pcie); + + return 0; +} + +static int tegra_pcie_pm_resume(struct device *dev) +{ + struct tegra_pcie *pcie = dev_get_drvdata(dev); + int err; + + err = tegra_pcie_power_on(pcie); + if (err) { + dev_err(dev, "tegra pcie power on fail: %d\n", err); + return err; + } + err = tegra_pcie_enable_controller(pcie); + if (err) { + dev_err(dev, "tegra pcie controller enable fail: %d\n", err); + goto poweroff; + } + tegra_pcie_setup_translations(pcie); + + if (IS_ENABLED(CONFIG_PCI_MSI)) { + err = tegra_pcie_enable_msi(pcie); + if (err < 0) { + dev_err(dev, "failed to enable MSI support: %d\n", err); + goto disable_controller; + } + } + + tegra_pcie_enable_ports(pcie); return 0; + +disable_controller: + tegra_pcie_disable_controller(pcie); +poweroff: + tegra_pcie_power_off(pcie); + + return err; } +static const struct dev_pm_ops tegra_pcie_pm_ops = { + SET_RUNTIME_PM_OPS(tegra_pcie_pm_suspend, tegra_pcie_pm_resume, NULL) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_pcie_pm_suspend, + tegra_pcie_pm_resume) +}; + static struct platform_driver tegra_pcie_driver = { .driver = { .name = "tegra-pcie", .of_match_table = tegra_pcie_of_match, .suppress_bind_attrs = true, + .pm = &tegra_pcie_pm_ops, }, .probe = tegra_pcie_probe, .remove = tegra_pcie_remove,