From patchwork Fri Jan 15 14:03:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1427046 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=PRefXmeN; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DHNJ25C00z9t9b for ; Sat, 16 Jan 2021 01:05:54 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731735AbhAOOFr (ORCPT ); Fri, 15 Jan 2021 09:05:47 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:1768 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731599AbhAOOFq (ORCPT ); Fri, 15 Jan 2021 09:05:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1610719547; x=1642255547; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=K+bmNnrAw2Khp85jJkbS/ratLTdwTztUszUl7HF20jU=; b=PRefXmeN4NLtuwCCrNn3c3SdFwLy2UYGq+djrloe579u0ivyWAtoZA8A LOs3YMDeoLF99fvXMu1vmyOajOg/Oztnn4fbsD6BUJpxHdfb2hcOwd1AJ GoZFp7/0tBqrxN7r7CwOSzmipK1nEAq1HewKOudKfPDpVjSDGbBO20qfX BU5XYfZ2v3lfbEeLWbkH/W0QL+zNOBhf/b1xu8ZQNDBdLOU3+RlsQovWL Wh5qNZjuY2Cnr/v4lqO/IobSXyMoSm/Fw8Osw5390+IZCRGwTMRcZyCOv IhbmUepyYtG9GozUtwhQqh7mvULm/2XlKTzT8klk+oRra5lPekeFH6Wi/ Q==; IronPort-SDR: cafoHsC0EKz4OTw3vtOUYn9lXROkz0krQ3ePgk8YBGRDa3ZutmHK/u1JDPvP4lTYn3W0mJ/4M7 Ul4v5jVhkTsyjLLTeUuPOFsx4Mash/ppH+MkMJYQ0gqUJP/qG1bJJllzZUvZfCz3jny+a02FJ6 C1JuH9xWAgnErbg75YrjVsQ57x1HXhIfyp36JdM4Cx887cpiTF6EOMKS3sD0a7DQOUPGE6cd3C z8O7M+HnDL4U5ZUDFm30W86HKD4eE5rB+D0ahdCPmKozoCp83XI28eMmDlwwSaByzSeqXKk4Pd f9U= X-IronPort-AV: E=Sophos;i="5.79,349,1602518400"; d="scan'208";a="158693632" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 15 Jan 2021 22:04:41 +0800 IronPort-SDR: TLJONqUGnusHRJHcbCwKrhHxbA5rzoy4B/I4dF5Ai6Po+ae6EDPu5IOiJVKKb0xvbr2SkgBjHx z+ta/jJd5l4v4uGybv4rDVUXgCWpAS+W82Gjum1qaeE7xhfWySsWsfwrkNl9Cr/1y2QO7zjaz5 V5AU0uPxAQc2CBPM/0+eecHMA1PuIZjbZocjeDJHAaHF3kJVZk4RuDyUB804HHzyNpO+OlvZ31 /K1cXpxX1TF3IDu3+m+sZ8SJuSw0obNM3Wu34WC3Up/TS30T+nPCk2gxuKJHBa50VMNJEWuyK9 k1YmVvXMrXSM9YS8D9Qedp0l Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2021 05:49:22 -0800 IronPort-SDR: BBA2VcmEWsXlQGi2G4NSddqbZF5tHke3YMHFJ131VaRTqpawQJGx4pyDxMuz9Xtf1hRTijUTgI UmCMbZVYS7TZzeHLQjKJEXMSorfFMb3VlGDuyQUCusCChl4Fn7h+J6KxJUBLPk4GkstJSrJ2G8 JBgyux0UveduYzMCuLHts96kSDS2A2tKo62x2XZ6EX9ZwBTjp6FLz0sw7j42puJgwF6WgVTeA9 asBRj1yxtA7moHzc6MDrGKhkOxR03BpZTBv/lvrUpzJgJUiqyp2PgMv6QurNu5Y8RkxxKr0ioP yNU= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.70.177]) by uls-op-cesaip02.wdc.com with ESMTP; 15 Jan 2021 06:04:40 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Sean Anderson , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v12 03/17] dt-bindings: fix sifive plic compatible string Date: Fri, 15 Jan 2021 23:03:38 +0900 Message-Id: <20210115140352.146941-4-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210115140352.146941-1-damien.lemoal@wdc.com> References: <20210115140352.146941-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allow the compatible string of a Sifive plic node to specify only "sifive,plic-1.0.0" without an additional required string specifying the SoC implementing the IP block. With this change, the plic node of RISC-V SoCs using a generic implementation of the plic without any SoC specific tweak can be correctly defined. Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../interrupt-controller/sifive,plic-1.0.0.yaml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index b9a61c9f7530..167418a0021a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -41,9 +41,13 @@ maintainers: properties: compatible: - items: - - const: sifive,fu540-c000-plic - - const: sifive,plic-1.0.0 + oneOf: + - items: + - const: sifive,fu540-c000-plic + - const: sifive,plic-1.0.0 + + - items: + - const: sifive,plic-1.0.0 reg: maxItems: 1 From patchwork Fri Jan 15 14:03:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1427047 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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15 Jan 2021 06:04:41 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v12 04/17] dt-bindings: add Canaan boards compatible strings Date: Fri, 15 Jan 2021 23:03:39 +0900 Message-Id: <20210115140352.146941-5-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210115140352.146941-1-damien.lemoal@wdc.com> References: <20210115140352.146941-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Introduce the file riscv/canaan.yaml to document compatible strings related to the Canaan Kendryte K210 SoC. The compatible string "canaan,kendryte-k210" used to indicate the use of this SoC to the early SoC init code is added. This new file also defines the compatible strings of all supported boards based on this SoC. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../devicetree/bindings/riscv/canaan.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/canaan.yaml diff --git a/Documentation/devicetree/bindings/riscv/canaan.yaml b/Documentation/devicetree/bindings/riscv/canaan.yaml new file mode 100644 index 000000000000..f8f3f286bd55 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/canaan.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/canaan.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan SoC-based boards + +maintainers: + - Damien Le Moal + +description: + Canaan Kendryte K210 SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: sipeed,maix-bit + - const: sipeed,maix-bitm + - const: canaan,kendryte-k210 + + - items: + - const: sipeed,maix-go + - const: canaan,kendryte-k210 + + - items: + - const: sipeed,maix-dock-m1 + - const: sipeed,maix-dock-m1w + - const: canaan,kendryte-k210 + + - items: + - const: sipeed,maixduino + - const: canaan,kendryte-k210 + + - items: + - const: canaan,kendryte-kd233 + - const: canaan,kendryte-k210 + + - items: + - const: canaan,kendryte-k210 + +additionalProperties: true + +... From patchwork Fri Jan 15 14:03:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1427048 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=Qkv2aunF; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DHNJ50mrFz9tD5 for ; Sat, 16 Jan 2021 01:05:57 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732423AbhAOOFu (ORCPT ); Fri, 15 Jan 2021 09:05:50 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:1776 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731599AbhAOOFt (ORCPT ); Fri, 15 Jan 2021 09:05:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1610719550; x=1642255550; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pxt0C0mCAFqqSrNoTsLwsfHLdzD156W4WrdlqAAuxAw=; b=Qkv2aunFW5c+3jnQUcuQ8T5eocY4SseniAVZGBxpJvhTahsYSaeuLeTc BMeGZEt1B/OQsBxV076ASzD8+UU8koA0bHKCOCILrQqECqK5wfeLNXWRm A6TvckerVh83W04BhkfkjMIIgg5Q+DTwQ2Y7lOJ8U4b3rrc/3yklZSrp8 2fumdxFnPXDZnUhzl5jBOnh+fYOqDRbR+gRQuVWjnre5Qegi++jXDtaaC Gb6RlDVVoURzXxc7YRWkW7cCz7NoLzexkpq2wZeRxMGLDrjQ60u0SyjVp KfN3G6/qqOPBqK5dLFgSOgem5jg6eX5KnWog1wwJD37L3cn99pcFjLCY7 A==; IronPort-SDR: xBljeKVhw8eGy9HKb+iStC3X23Hl70Hmzx+uQ8KZ2p+asTGW+oDm//uZKbRCTSqkKqTbqsHHyo 84epEsxHwS0eMCWWmXM6iPhsoAYEaXMHXINEZTD1ESC37YRYjdOvs61mHMuaXN2FEnidd0rAbw s6N5yjzkPDifCPIDETR/0UyZFEG6luLd/mKXznHptn7r29TKnQzpHPds6ohltYlPJ6qwkr05uw VfTTUqTA1aaOpKzXhYrAbbbX8BgskJO1gjKYBpSuF61fBXfUj0iDlZSIN/1B/9XAsjx1icfNTp XDk= X-IronPort-AV: E=Sophos;i="5.79,349,1602518400"; d="scan'208";a="158693641" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 15 Jan 2021 22:04:44 +0800 IronPort-SDR: M/qMz9rZ1q42jEEqCHJBcMevp/lcnVCpaI59L6gZhdOpnpqK2Ir6M3MHgVr7fZ4mFZ6xkAeX3s SLG8heBOMD3LsXK1DNC1fpsAaYI8teT/Gos4f3hQrwkVDAserv6CekwaciB6FENn/jrWK13+h2 WBB8ufQ/sqJgjNBK2K3D4bft5V6kX4lwtI3k6fSezLtIeMQ3zCZe7mCvuh+P9bXuBh8MLmAv6Q X6JaIkGugBva09bcVFh2J9xFhnrqPAQpfEjxyXTP93N2ltnAx5c9h8eVnzLDEOOlqC7NDK0BpK ALXsG57/wRWlvrFRUumoVstK Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2021 05:49:25 -0800 IronPort-SDR: dHkqvMBXqqxx5Y/UbDfm5GjSMh8nlDWjvnixhN2QS7T94ALvzIie9Rvbdc0tYFYNn3DL8CkMFR QDUVyyBxh+CG/iq77QXRNuXD6nFZfGJ+CuK+5J3c03abzR9juRS6jD78bO39QZIuQVm/McRPrr aiztDOF13jZNzEIxByfVyKXwca8FmwUD+7HpOI/E93uMbcIUaAhAvA+vEFZ6ZO82ADl6qE4njf tpULBK8P3PbCyr9gsIs52WbI5br4dTzLQs+AlppsGN7T82sW6ud2sIe+Ko11kb+8FUeQ6A/8Ju OjI= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.70.177]) by uls-op-cesaip02.wdc.com with ESMTP; 15 Jan 2021 06:04:43 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Sean Anderson , Yash Shah , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v12 05/17] dt-bindings: fix sifive gpio properties Date: Fri, 15 Jan 2021 23:03:40 +0900 Message-Id: <20210115140352.146941-6-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210115140352.146941-1-damien.lemoal@wdc.com> References: <20210115140352.146941-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The sifive gpio IP block supports up to 32 GPIOs. Reflect that in the interrupts property description and maxItems. Also add the standard ngpios property to describe the number of GPIOs available on the implementation. Also add the "canaan,k210-gpiohs" compatible string for the Canaan K210 SoC which uses the Sifive gpio IP block. For this compatible string, do not define the clocks property as required as the K210 SoC does not have a software controllable clock for the Sifive gpio block. Cc: Yash Shah Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../devicetree/bindings/gpio/sifive,gpio.yaml | 21 ++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml index ab22056f8b44..2cef18ca737c 100644 --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml @@ -16,6 +16,7 @@ properties: - enum: - sifive,fu540-c000-gpio - sifive,fu740-c000-gpio + - canaan,k210-gpiohs - const: sifive,gpio0 reg: @@ -23,9 +24,9 @@ properties: interrupts: description: - interrupt mapping one per GPIO. Maximum 16 GPIOs. + interrupt mapping one per GPIO. Maximum 32 GPIOs. minItems: 1 - maxItems: 16 + maxItems: 32 interrupt-controller: true @@ -38,6 +39,10 @@ properties: "#gpio-cells": const: 2 + ngpios: + minimum: 1 + maximum: 32 + gpio-controller: true required: @@ -46,10 +51,20 @@ required: - interrupts - interrupt-controller - "#interrupt-cells" - - clocks - "#gpio-cells" - gpio-controller +if: + properties: + compatible: + contains: + enum: + - sifive,fu540-c000-gpio + - sifive,fu740-c000-gpio +then: + required: + - clocks + additionalProperties: false examples: From patchwork Fri Jan 15 14:03:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1427051 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=BayrrjiB; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DHNJh2W9lz9t9y for ; Sat, 16 Jan 2021 01:06:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729011AbhAOOG1 (ORCPT ); Fri, 15 Jan 2021 09:06:27 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:1768 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725910AbhAOOG1 (ORCPT ); Fri, 15 Jan 2021 09:06:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1610719588; x=1642255588; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CN0WY+YBp4RNoOYHuHqovxX2R6rFlSK3nLo4F3hEm8c=; b=BayrrjiB04pw9UZhmjku0WQWpCpt7jbMzUVLHmTRQdjYzJAoXzf49C03 rosfscbVFN9wPhPvEiOyYD83HpzDcDIUVmAbnoVgNdLaEohou5xhcCDF0 mvvgGeJ3J9t66iPEGUFPwsSvZCmE6CxQ+1Fil2tkMctRNQB+WiUTvHshI lyPW1mqeyo2yLiFskfhwpFa22v+00pAfp0GlwrDx3s7bhurjfsAdWAAgh 7RE9KvQhG0kwyenltN7MTYZO2Lsn21bKtS927rVfFSo/AMH0A2yon0M8+ WfAoeXf2hGScaLB8LXI2GvH9H5OTnw5mv3y47LRTJil/8XVPNpL8ucno5 Q==; IronPort-SDR: JxUFObFRuLV+ZlWBYf8iZ5UEXQObeQpEeVS5jx1Hm0jHZ/up+WtRYZ/X30Rnl9BawzfZz1kL+y ppOJA31NMuz9xF1K/CDqHgcGfzavn7SJVpPPMABLamRFDFbOvCJWY2FmE7fyti3Xrpb1OyzFBw j/B22SCx5otb12feFXBEEa794Gm9tBEoHPl5xJXI/d7mb3a5EqbJUyOeKDHxfjsbL91wOn3SEG gkj3fmccNhLxfMN1+8H/+7Aa91fCTxhV9f6unKe8fGsEtmZgqka4amNELcn70+AQisf23A3wX3 6tM= X-IronPort-AV: E=Sophos;i="5.79,349,1602518400"; d="scan'208";a="158693648" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 15 Jan 2021 22:04:46 +0800 IronPort-SDR: ieNcKxnTrMmcPaftTy8eFtCSkbsMZY2wKsl8O1jy+VTXaxlYDmscL/mSb+1Sgnq3trXLNEmy4B jkc3yEipQJ3hJYr8BYzt3L44zvd54boyhsQUnICrZjg6WyEU4h2hUbPsg/NCMqawC1b3wQa4/b xjcS0hQA+P2Ap9IQpMdCEZ1zj9t2AAStZTr6s2uCRAattT3L2nNVIPzOyAuUgv0o+yf/HMn/by ndOk1rRphZFNS+BDste1pVg6C1gmUaXX7WDRxZYcCeWqYvCXiAsTHAOShT+KCN2opqQ3gflX1s VP2PR2lMxvZkgbHBe9uc2A/0 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2021 05:49:27 -0800 IronPort-SDR: Fn3rEK6WIfgU9zOzR3ARbUv9VcNsbosccCPrnWgTYWHMmo87uBBAmDczhH1AT9628znV+U34cs WGUzgOiONdK4XKuQOB0rxVLXeN88ktY2CluiC/pTVO6t7JrsGjbor1U/CXNqeDqWjVurQLfeVe epw5TwXvQw9F3FQEjWihOK9ijjARh2FHgYxgJIOzRbORu+JNeljHw0OGQnLEPfDhUqu/bio9xi kFJsajIEIajbIu6pM2/hEgU/1XQ0LIvjLH8JYK1kCZ9r2lVVPo8MYQeu6/xCYpVu8vkMVGWqDg NJc= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.70.177]) by uls-op-cesaip02.wdc.com with ESMTP; 15 Jan 2021 06:04:44 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Sean Anderson , Daniel Lezcano , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v12 06/17] dt-bindings: add resets property to dw-apb-timer Date: Fri, 15 Jan 2021 23:03:41 +0900 Message-Id: <20210115140352.146941-7-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210115140352.146941-1-damien.lemoal@wdc.com> References: <20210115140352.146941-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Synopsis DesignWare APB timer driver (drivers/clocksource/dw_apb_timer_of.c) indirectly uses the resets property of its node as it executes the function of_reset_control_get(). Make sure that this property is documented in timer/snps,dw-apb-timer.yaml to avoid make dtbs_check warnings. Cc: Daniel Lezcano Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml index d65faf289a83..d33c9205a909 100644 --- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml +++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml @@ -24,6 +24,9 @@ properties: interrupts: maxItems: 1 + resets: + maxItems: 1 + clocks: minItems: 1 items: From patchwork Fri Jan 15 14:03:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1427052 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=Hm67ImCN; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DHNJj37YJz9tB1 for ; Sat, 16 Jan 2021 01:06:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729384AbhAOOG2 (ORCPT ); Fri, 15 Jan 2021 09:06:28 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:1772 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725910AbhAOOG2 (ORCPT ); Fri, 15 Jan 2021 09:06:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1610719589; x=1642255589; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0gydr514UdHfaLZyMWZlPzEDnEe7NJxvNWRTRtcTWlQ=; b=Hm67ImCNHvNLpzLlVQCWhB+6zl8rSz9WUsqP3fE38+dcLytA5pDnnZKP crc/j/xVHQ1T312JORhGew1Hnm8LlQqXBHUiQnWPhe/BRhpudUUbS2o6A PasK3VHqRHbf9IAIEP7TnmHcVcGj+TtrWECL00YY90k+Z5TS8e53HFqpN u4AlVSxRvvJB2GmGwg9RWIVq0XpqvFDPC2rZd86Wcn2l1/K6hAJc4sMb6 RNS5sNfmAdmUWIC4CmF0UAJAAbMTDyy8MCdBE/OxXGCF1xcZ5N/Hy4dm9 3DIgzu/f0MgdpuxEGYqPzPxt75fPC60ZJuNWTAMAGi4luCn4ATSrKv+Ro Q==; IronPort-SDR: XJA864xaevv5tsqn1IMK7XyVQqumBSMYJFZy8zhmg4kXjZ8vbq4Pxe0eig5o1003SKwy87jXlh 3CFlh16HRn/IYAzxOi80ZD3aRCRp4jmYsRB7O2VftQRojR6l+xAq65OedzxDy/D5hzXNEdLMPZ e9IDEqtY+yPt+X3WSdSEFaRyCmtVEpcBGS5I03/oUtCNgKq2JxBRM2NupcZhCfltfdvOiEJv17 pdW8rJRlJJO3MuFVzg7NOfBo4M3jW/3YQd75gnw2J/R1H3Gow9hhF45Tw1OHeLbO/bW6tyKASu 9xs= X-IronPort-AV: E=Sophos;i="5.79,349,1602518400"; d="scan'208";a="158693656" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 15 Jan 2021 22:04:47 +0800 IronPort-SDR: tf/fZfKQQ7dDe+diNQVRthjAX2Z6XUfV/KSS+GVIp3NHfnDIKkwqO52kmkdlOT6XX5xX9zULKS SJYbRdf+fY5CDAhmXdLO7Qt9KezVGFb9KIwNGTZO/IR6Tu5/c4TtFaqN9idUkxPmaPDVJA7d9D IM/VntJGV0hsPlTWWF2VlN77dmKqjHusLP/uDWsesO0ocK3GTnlEv43Ofy/8IfGKG9LX26ozEy AY0k2yCmGKxfxeUr0Q11Et98QphNKRhNIdlr8Bbn5dBoPoETRCfe4URJs7AcEjKTvFI/QEt2uV JFnH87LWtjnatbM0EiWr6rIG Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2021 05:49:28 -0800 IronPort-SDR: sfbO9Hl3NbtP06FM9vFhxxWYbPbnhsLD6vbTWtQYPKLZp/V3Eg+5Ck5uQjf3w7e1MwD91XpEy2 m6s8/sYAhKD1j74L94lYXg7z4ljN+zvNsZc3I9BSv+4V4KYFfMMgXoFkfXg7CSfZQFoqxiSQ6F tpIM8S5qeVrMkm/+V0PbJjyBraILXmaexm9e/XKQiuFHVQsA3WpkT0VmXFYlx1EaUAZ10bhWjx LDU5o7Mi/UjyOkk68tFhMf6jDS2Y7E+TxnFOfsX2ef3/HvFTyepd0z6bL4tw3rzvNfC7wivLrl jeY= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.70.177]) by uls-op-cesaip02.wdc.com with ESMTP; 15 Jan 2021 06:04:46 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Sean Anderson , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v12 07/17] dt-bindings: update risc-v cpu properties Date: Fri, 15 Jan 2021 23:03:42 +0900 Message-Id: <20210115140352.146941-8-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210115140352.146941-1-damien.lemoal@wdc.com> References: <20210115140352.146941-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip version using a draft verion of the RISC-V ISA specifications. To avoid any confusion with CPU cores using stable specifications, add the compatible string "canaan,k210" for this SoC CPU cores. Also add the "riscv,none" value to the mmu-type property to allow a DT to indicate that the CPU being described does not have an MMU or that it has an MMU that is not usable (which is the case for the K210 SoC). Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index eb6843f69f7c..e534f6a7cfa1 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -39,6 +39,7 @@ properties: - sifive,u74 - sifive,u5 - sifive,u7 + - canaan,k210 - const: riscv - const: riscv # Simulator only description: @@ -56,6 +57,7 @@ properties: - riscv,sv32 - riscv,sv39 - riscv,sv48 + - riscv,none riscv,isa: description: From patchwork Fri Jan 15 14:03:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1427053 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=Q/7wj1Du; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DHNJm0hDcz9t9b for ; Sat, 16 Jan 2021 01:06:32 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731075AbhAOOGb (ORCPT ); Fri, 15 Jan 2021 09:06:31 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:1776 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725910AbhAOOGb (ORCPT ); Fri, 15 Jan 2021 09:06:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1610719591; x=1642255591; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EtL2qzwmDcnW1fQU2frLeb46tiz62PjL2rf0Kz9/lC8=; b=Q/7wj1Dukp80GDH2jM2fsQ4ldBAj15h/Aamm0BZvnrfWGh/AdpcoO4yl Qe0lsm4LkZ+nYFuwa0wzJV5slp91Ctynf55BwfQNqT2I0yeOdSgz8o1Vp xLtQdziF18Uxv6GxtHwshU/TSKZ/q6N5+3CwP+zmGWlf1yA4e+mmQzrxl P5xxrlpCgqQdMlW9qDGVMvjSarYkphZN1VFtM4H0KfenCFdSDwTm9aUVy c0h227LgHvgz2+WlQRKnhkHlxjySlui2nXI1WIsme02cmWfMt91ELkq8q IgfDzM4vEskSq81frPxrmVVu8vNGeDiQ63s+NL3zlmjwC8pH/VlrwhixR g==; IronPort-SDR: 3jG/0FOz+BwnLbr6PqB7QxnGBACdfBPvORpVnCMZ/ZbLaFPgHTsfcOnOQ4aI9HOFR5U/kCy/N1 k1l3hm5iUsPkT0yymoHzUVZVKLbfoi+3yItCi1J9m/y4q54Ue6mUcpF/5gegZ4nlRV9/QsdYJE 2Zhxx1q2ZB0LakusTRzJFiQ3jCblbce8zloETRN1VKDJX3HuB91olTZaSAZcNfCFFpPU9VpKY6 TpR2ygF7CdT95QB7TroURPVQR6KLT6pTUc4JTQat801QNq9FWAG5BVgGnSNjdxbmW19VbgRj2X TBE= X-IronPort-AV: E=Sophos;i="5.79,349,1602518400"; d="scan'208";a="158693661" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 15 Jan 2021 22:04:49 +0800 IronPort-SDR: DbsO85ryw+4pMeRVm0rbjm81SrJsAFsK/OTydcUzQTbw1DrAGuBByKNKtMrpSAiEr32OZ5Tmu9 722CB6gVNPGlpdecoC8IYFTWXBvfEX4L9raw9fpaeLgHHVq9elEq5nArnE9XAMXbcTNGWmYoo3 pKDQAgsT+F4n8ibUPW3tVyyO8Modb/02xhe6iaMBKBTHaZw5SlrdaV4vQER/u+5/2kT4WXKE0M 6+LfIkWyaOavZ/oVRWkiwc5ml12Uk3Hl2H9ThaKTIXPB17weZfGVpHxuaY+9L8WlxBkNMLzPI+ 9h/Quw+uMLH4YgvH1Odyb+5n Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2021 05:49:30 -0800 IronPort-SDR: JC5ud1Aie5s5GBUGPKB/4k1MQtXjjQf7M952OQjx03uRNLt+E5iO5tqDsoCi7OCT87qba+eyUp Cfug/866HQFAlEFwNvHGaGgU1ZIcile0z9jt/VzR0MujlG1hELIuLPzCZ9C27pjx/CTf/iNcoE EBHQCeWBN3AxnKpi27AP58PzwoOHF0Etb4WzWJ7yhxcPCQMRXhkxaOq7ZYxmRGtgG9iVJplplC DeridHx9Jfbwq3u/liz3g2bBJO416LxNUbpf7605bGf7PJN/FWReeJ3ld3K2c4J+DZzhXJ5C5f PtY= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.70.177]) by uls-op-cesaip02.wdc.com with ESMTP; 15 Jan 2021 06:04:47 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Sean Anderson , Anup Patel , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v12 08/17] dt-bindings: fix sifive clint compatible string Date: Fri, 15 Jan 2021 23:03:43 +0900 Message-Id: <20210115140352.146941-9-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210115140352.146941-1-damien.lemoal@wdc.com> References: <20210115140352.146941-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Fix the Sifive clint compatible string definition to make the value "sifive,fu540-c000-clint" optional, allowing a DT to specify only "sifive,clint0" for its generic implementation without any tweak. With this change, a Sifive clint node can now be defined as explained in the compatible string description. Cc: Anup Patel Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../devicetree/bindings/timer/sifive,clint.yaml | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 2a0e9cd9fbcf..c6b1f37a2949 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -22,12 +22,13 @@ description: properties: compatible: - items: - - const: sifive,fu540-c000-clint - - const: sifive,clint0 + oneOf: + - items: + - enum: + - sifive,fu540-c000-clint + - sifive,clint0 description: - Should be "sifive,-clint" and "sifive,clint". Supported compatible strings are - "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive From patchwork Fri Jan 15 14:03:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1427059 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=SzIWSM0D; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DHNKk4sZ5z9t9y for ; Sat, 16 Jan 2021 01:07:22 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726030AbhAOOHI (ORCPT ); Fri, 15 Jan 2021 09:07:08 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:1768 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732225AbhAOOHI (ORCPT ); Fri, 15 Jan 2021 09:07:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1610719629; x=1642255629; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6Hey1gBLFBlTZ5G4DZApRpa+IynzpXO3Am42+Zc7r64=; b=SzIWSM0D/TNH0LihT3J3XqHWhQaCMCqEuZrCAopoAcEe/rFKcHFY2r6i DeA6EDlyD1v4lQVWeJHgmQ9lJAYTMFwnAmqid4oapHtaEGel1k30DB/US +CUSMOQeYO5lo2ACN8w9yDHllfNaXd2eBlWhVq02J+Tbc12E2A0+m/MbD B73VSbiOX1CMJK3MoNfkgNV7lO/zFuzdxe4HSyUp0REZGdyDDiFhKX+4l JbJFre40C8VIGw9TvcGk8n00cOmzoh4rGagarv5FtVUyTaRZquvXCjaUs 51Xa/ir9ybCCZtoU1hD/avq/omUbtdx1jSo3WxwdHhNyk6i/CW9k5nLyN g==; IronPort-SDR: BbrJtpOB6a7bEwBPabJJay7cXDWHQ7V8JACwq6TokTeZHgEyiuGupVhWqUv9iagHAWh/iRQIiK LSM3cbMH/SiCEM0YrqISudrT/pD4bpSeinGVsglxaxkCsOyRoRa0NH8AWJTHbCg/HNdiS9g0+B b4leP9h3mHewLjZcoVc4/ORfPFxS5WqI5tnx0qfLV6+FlE6+1tzWqcVSJOMmKMptYUnLuLX/2P bd803hXObDbPImJTpwjJznq1+caOk76kduxrgu21dGfr2684MzMezny890oX0jpqez5m34oMxn pDs= X-IronPort-AV: E=Sophos;i="5.79,349,1602518400"; d="scan'208";a="158693667" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 15 Jan 2021 22:04:50 +0800 IronPort-SDR: I+t7c5dbzXa7MqREtk1/hlmv+CLifdyJV4jh2jOrOfr6kiRWM/AFdAi2X/eVFm4ormR/vaZOZ9 gDeK6eyoqzMqiXAkTpeGfEfH8xGx3FwfEAnJXiF5QvJIP/ZYTNvW3nHQCh1BaSmnZjprelNR09 +HAAaefd4PxKbFlxQ22seyarWX323jRnGwUN7OOn6fOGK6OSOyip2F/eb0CFds8u4SbGTL2jdm aUGBcQ6j9eBALrFQy9ekFtQx+/5zsIsyTt7Hix9KI5qUu44VefNAp4KtKbexscYtXQ4ZgivXhR LmTgJpgELDMTk99WuFVoFFII Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2021 05:49:31 -0800 IronPort-SDR: 07YQ9R4XlMpkoOR+DsPyg/KEDFXvGd1xFmU7Mjkeuj4dO5vcGvduSEHy2+O0aHQd/SczwDpv3c 3aXFGn7aKJYerpf3MSL0Rf/B1KYGl+e3hUAOkKdSlms3I1N9aPOpBCeIQ/2Y8sbWVnn0baUbwB gOwwBFvuzUNqjfbfzRGcLlHLHs/ITDZ0CwuUucyO6/izphmv9LVkB7qybAsEWzzsFdR2RByLfG 2YtPnXY4xEoiOoTz8x9+293gMkIIT8Tx25J1LCxdsSYzKBNgzWpzMiE8TqLv7j95vFZhAqwrJB irI= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.70.177]) by uls-op-cesaip02.wdc.com with ESMTP; 15 Jan 2021 06:04:49 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Sean Anderson , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v12 09/17] dt-bindings: update sifive serial Date: Fri, 15 Jan 2021 23:03:44 +0900 Message-Id: <20210115140352.146941-10-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210115140352.146941-1-damien.lemoal@wdc.com> References: <20210115140352.146941-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the compatible string "canaan,k210-uarths" to the sifive uart bindings as the Canaan Kendryte K210 includes a Sifive uart IP block for the main serial console. Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- Documentation/devicetree/bindings/serial/sifive-serial.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml index 3ac5c7ff2758..5fa94dacbba9 100644 --- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml +++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml @@ -20,6 +20,7 @@ properties: - enum: - sifive,fu540-c000-uart - sifive,fu740-c000-uart + - canaan,k210-uarths - const: sifive,uart0 description: From patchwork Fri Jan 15 14:03:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1427060 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=Y00fbgb4; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DHNKl3Hhrz9t9b for ; Sat, 16 Jan 2021 01:07:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732225AbhAOOHL (ORCPT ); Fri, 15 Jan 2021 09:07:11 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:1772 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731589AbhAOOHK (ORCPT ); Fri, 15 Jan 2021 09:07:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1610719630; x=1642255630; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZlqJghz1HsCbQWhgiEkRnPRW1SlzItAYGGlI8A8kibU=; b=Y00fbgb4OI63TnHuH4PcYxzlM6TCsb1UEQ+cFJ5yyu0U2sJfivwrXY9s pt5B89GHA2m+4/ACMWgaU2GQ4/XGwIhASlFoc5IHVYzoeZGPO+hMSK8D0 Czq+k/OoSQVkJNckrzoWXiddmyU40WgpPM0KB6ywH/oqCmF3Dx6w3p0DV 7lruOWwY5QI+kkmg9zyoZuL92QcO4qFnZWRB+GtKzlFyE6s+EUwxaDaQJ ODtLA57cUyHUaIq0Fx4xAztLwGeu47AYxaH7FAwUZmt5d/BQOvp95EmU3 wgySOKCRQzxyfwMgZBZ3jQaB4Z2UezX6+gsvzwnleKXe+2YG69lOqD8tN A==; IronPort-SDR: hR23sX543c9TOrea6YEnoiuzJU0CUSmfuX56JoFbr2CcaeKQ86GHu5k8w2Z10FExysQ+CaGFAZ uy7fDneTb93j9jy13R4B5AmRk1diOWPtcBuJZlSEBf1UJnYbaPlagl7QXp+ahSKdI/x+B/a59J 2gir0Y2BFQubUK1jbGPiK4GE7ZIA0pDSOG59Sg9VlGBZ+KwZcqa7bX0X4Rsp2WjaZ9ZELj2EEs K8BPFeY9VDvwx7Vgj/DtZuN4V6zdoKBubBpOFtrFTh5g0fm+dJPqVXIY65KlgDrsjAVyQMDSqu aU0= X-IronPort-AV: E=Sophos;i="5.79,349,1602518400"; d="scan'208";a="158693672" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 15 Jan 2021 22:04:52 +0800 IronPort-SDR: chi6xB5CQ7DJIWvI7Y9XQ1ygzOZYJY/sCJff/xm9ZTnQG5ZQ009nE7Ldt5w51VuFj5+VyfRvh+ aBj+9dES8c+resvXxzZKrZTeRLl6U+mT53VTmoQHMtVkIOjwu6X+ujt/lJ9iRqUdACzDoYumBI BgbO5wri9PsXKueDRQ2QdZkS3S+yCk7VZ9o7g82J6CQC05XeBJ2C/NjjEbMgdlVUe0/tkDfFT8 +94o/4x1z2iJhJ26QfRIIiomz5VFbwJL/G0HVMjBtgwYouzV9zUN3jwZ6DNTsC89A+10ybNkuk 8bMdFEZorQu56k23X8SFfYxO Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2021 05:49:32 -0800 IronPort-SDR: UvoflRK6I1YiUTA4oRVwDGP1l4kvVHliC12ikMXRZAH+Vuf33H71sHhc4vj6C91n8R7ClpSpEL u2D9k8SG4He53Tew669oN62p+RD+IYWmpHC04m6/Ec4eTmyXI5tmwAegG8xLv/UDCiZjaQR2Ta 4PF2DXPB84c6SExr9MfYYziGxo2oW9ib9GwrKewZ2iLFRbLoz3vrMPR9/pJubd5B8M1StPjzYR q63n54rvqbzWbvX45DNqsjT82n8HMUud6v4hwylR4DU81boT/F8xIOwxLU99okxe0k99VKPHQf JIY= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.70.177]) by uls-op-cesaip02.wdc.com with ESMTP; 15 Jan 2021 06:04:50 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v12 10/17] riscv: Update Canaan Kendryte K210 device tree Date: Fri, 15 Jan 2021 23:03:45 +0900 Message-Id: <20210115140352.146941-11-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210115140352.146941-1-damien.lemoal@wdc.com> References: <20210115140352.146941-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update the Canaan Kendryte K210 base device tree k210.dtsi to define all peripherals of the SoC, their clocks and reset lines. The device tree file k210.dts is renamed to k210_generic.dts and becomes the default value selection of the SOC_CANAAN_K210_DTB_BUILTIN_SOURCE configuration option. No device beside the serial console is defined by this device tree. This makes this generic device tree suitable for use with a builtin initramfs with all known K210 based boards. These changes result in the K210_CLK_ACLK clock ID to be unused and removed from the dt-bindings k210-clk.h header file. Most updates to the k210.dtsi file come from Sean Anderson's work on U-Boot support for the K210. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- arch/riscv/Kconfig.socs | 2 +- arch/riscv/boot/dts/canaan/k210.dts | 23 - arch/riscv/boot/dts/canaan/k210.dtsi | 535 +++++++++++++++++++- arch/riscv/boot/dts/canaan/k210_generic.dts | 46 ++ include/dt-bindings/clock/k210-clk.h | 1 - 5 files changed, 554 insertions(+), 53 deletions(-) delete mode 100644 arch/riscv/boot/dts/canaan/k210.dts create mode 100644 arch/riscv/boot/dts/canaan/k210_generic.dts diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 6402746c68f3..7efcece8896c 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -51,7 +51,7 @@ config SOC_CANAAN_K210_DTB_SOURCE string "Source file for the Canaan Kendryte K210 builtin DTB" depends on SOC_CANAAN depends on SOC_CANAAN_K210_DTB_BUILTIN - default "k210" + default "k210_generic" help Base name (without suffix, relative to arch/riscv/boot/dts/canaan) for the DTS file that will be used to produce the DTB linked into the diff --git a/arch/riscv/boot/dts/canaan/k210.dts b/arch/riscv/boot/dts/canaan/k210.dts deleted file mode 100644 index 0d1f28fce6b2..000000000000 --- a/arch/riscv/boot/dts/canaan/k210.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020 Western Digital Corporation or its affiliates. - */ - -/dts-v1/; - -#include "k210.dtsi" - -/ { - model = "Kendryte K210 generic"; - compatible = "kendryte,k210"; - - chosen { - bootargs = "earlycon console=ttySIF0"; - stdout-path = "serial0"; - }; -}; - -&uarths0 { - status = "okay"; -}; - diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 354b263195a3..995c044e7b60 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -1,9 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Sean Anderson + * Copyright (C) 2019-20 Sean Anderson * Copyright (C) 2020 Western Digital Corporation or its affiliates. */ #include +#include +#include / { /* @@ -12,14 +14,33 @@ / { */ #address-cells = <1>; #size-cells = <1>; - compatible = "kendryte,k210"; + compatible = "canaan,kendryte-k210"; aliases { + cpu0 = &cpu0; + cpu1 = &cpu1; + dma0 = &dmac0; + gpio0 = &gpio0; + gpio1 = &gpio1_0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + pinctrl0 = &fpioa; serial0 = &uarths0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; }; /* - * The K210 has an sv39 MMU following the priviledge specification v1.9. + * The K210 has an sv39 MMU following the privileged specification v1.9. * Since this is a non-ratified draft specification, the kernel does not * support it and the K210 support enabled only for the !MMU case. * Be consistent with this by setting the CPUs MMU type to "none". @@ -30,14 +51,14 @@ cpus { timebase-frequency = <7800000>; cpu0: cpu@0 { device_type = "cpu"; + compatible = "canaan,k210", "riscv"; reg = <0>; - compatible = "kendryte,k210", "sifive,rocket0", "riscv"; riscv,isa = "rv64imafdc"; - mmu-type = "none"; - i-cache-size = <0x8000>; + mmu-type = "riscv,none"; i-cache-block-size = <64>; - d-cache-size = <0x8000>; + i-cache-size = <0x8000>; d-cache-block-size = <64>; + d-cache-size = <0x8000>; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; @@ -46,14 +67,14 @@ cpu0_intc: interrupt-controller { }; cpu1: cpu@1 { device_type = "cpu"; + compatible = "canaan,k210", "riscv"; reg = <1>; - compatible = "kendryte,k210", "sifive,rocket0", "riscv"; riscv,isa = "rv64imafdc"; - mmu-type = "none"; - i-cache-size = <0x8000>; + mmu-type = "riscv,none"; i-cache-block-size = <64>; - d-cache-size = <0x8000>; + i-cache-size = <0x8000>; d-cache-block-size = <64>; + d-cache-size = <0x8000>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; @@ -64,10 +85,15 @@ cpu1_intc: interrupt-controller { sram: memory@80000000 { device_type = "memory"; + compatible = "canaan,k210-sram"; reg = <0x80000000 0x400000>, <0x80400000 0x200000>, <0x80600000 0x200000>; reg-names = "sram0", "sram1", "aisram"; + clocks = <&sysclk K210_CLK_SRAM0>, + <&sysclk K210_CLK_SRAM1>, + <&sysclk K210_CLK_AI>; + clock-names = "sram0", "sram1", "aisram"; }; clocks { @@ -81,40 +107,493 @@ in0: oscillator { soc { #address-cells = <1>; #size-cells = <1>; - compatible = "kendryte,k210-soc", "simple-bus"; + compatible = "simple-bus"; ranges; interrupt-parent = <&plic0>; - sysctl: sysctl@50440000 { - compatible = "kendryte,k210-sysctl", "simple-mfd"; - reg = <0x50440000 0x1000>; - #clock-cells = <1>; + debug0: debug@0 { + compatible = "canaan,k210-debug", "riscv,debug"; + reg = <0x0 0x1000>; + status = "disabled"; + }; + + rom0: nvmem@1000 { + reg = <0x1000 0x1000>; + read-only; + status = "disabled"; }; clint0: clint@2000000 { - #interrupt-cells = <1>; - compatible = "riscv,clint0"; + compatible = "sifive,clint0"; reg = <0x2000000 0xC000>; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7>; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7>; }; - plic0: interrupt-controller@c000000 { + plic0: interrupt-controller@C000000 { #interrupt-cells = <1>; - interrupt-controller; - compatible = "kendryte,k210-plic0", "riscv,plic0"; + #address-cells = <0>; + compatible = "sifive,plic-1.0.0"; reg = <0xC000000 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 0xffffffff>, - <&cpu1_intc 11>, <&cpu1_intc 0xffffffff>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>; riscv,ndev = <65>; - riscv,max-priority = <7>; }; uarths0: serial@38000000 { - compatible = "kendryte,k210-uarths", "sifive,uart0"; + compatible = "canaan,k210-uarths", "sifive,uart0"; reg = <0x38000000 0x1000>; interrupts = <33>; - clocks = <&sysctl K210_CLK_CPU>; + clocks = <&sysclk K210_CLK_CPU>; + status = "disabled"; + }; + + gpio0: gpio-controller@38001000 { + #interrupt-cells = <2>; + #gpio-cells = <2>; + compatible = "canaan,k210-gpiohs", "sifive,gpio0"; + reg = <0x38001000 0x1000>; + interrupt-controller; + interrupts = <34 35 36 37 38 39 40 41 + 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 + 58 59 60 61 62 63 64 65>; + gpio-controller; + ngpios = <32>; + status = "disabled"; + }; + + kpu0: kpu@40800000 { + compatible = "canaan,k210-kpu"; + reg = <0x40800000 0xc00000>; + interrupts = <25>; + clocks = <&sysclk K210_CLK_AI>; + status = "disabled"; + }; + + fft0: fft@42000000 { + compatible = "canaan,k210-fft"; + reg = <0x42000000 0x400000>; + interrupts = <26>; + clocks = <&sysclk K210_CLK_FFT>; + resets = <&sysrst K210_RST_FFT>; + status = "disabled"; + }; + + dmac0: dma-controller@50000000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x50000000 0x1000>; + interrupts = <27 28 29 30 31 32>; + clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&sysrst K210_RST_DMA>; + dma-channels = <6>; + snps,dma-masters = <2>; + snps,priority = <0 1 2 3 4 5>; + snps,data-width = <5>; + snps,block-size = <0x200000 0x200000 0x200000 + 0x200000 0x200000 0x200000>; + snps,axi-max-burst-len = <256>; + status = "disabled"; + }; + + apb0: bus@50200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB0>; + + gpio1: gpio@50200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x50200000 0x80>; + clocks = <&sysclk K210_CLK_APB0>, + <&sysclk K210_CLK_GPIO>; + clock-names = "bus", "db"; + resets = <&sysrst K210_RST_GPIO>; + status = "disabled"; + + gpio1_0: gpio-port@0 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + interrupt-controller; + interrupts = <23>; + gpio-controller; + ngpios = <8>; + }; + }; + + uart1: serial@50210000 { + compatible = "snps,dw-apb-uart"; + reg = <0x50210000 0x100>; + interrupts = <11>; + clocks = <&sysclk K210_CLK_UART1>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART1>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + uart2: serial@50220000 { + compatible = "snps,dw-apb-uart"; + reg = <0x50220000 0x100>; + interrupts = <12>; + clocks = <&sysclk K210_CLK_UART2>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART2>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + uart3: serial@50230000 { + compatible = "snps,dw-apb-uart"; + reg = <0x50230000 0x100>; + interrupts = <13>; + clocks = <&sysclk K210_CLK_UART3>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART3>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + spi2: spi@50240000 { + compatible = "canaan,k210-spi"; + spi-slave; + reg = <0x50240000 0x100>; + interrupts = <3>; + clocks = <&sysclk K210_CLK_SPI2>, + <&sysclk K210_CLK_APB0>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI2>; + spi-max-frequency = <25000000>; + status = "disabled"; + }; + + i2s0: i2s@50250000 { + compatible = "snps,designware-i2s"; + reg = <0x50250000 0x200>; + interrupts = <5>; + clocks = <&sysclk K210_CLK_I2S0>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S0>; + status = "disabled"; + }; + + apu0: sound@520250200 { + compatible = "canaan,k210-apu"; + reg = <0x50250200 0x200>; + status = "disabled"; + }; + + i2s1: i2s@50260000 { + compatible = "snps,designware-i2s"; + reg = <0x50260000 0x200>; + interrupts = <6>; + clocks = <&sysclk K210_CLK_I2S1>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S1>; + status = "disabled"; + }; + + i2s2: i2s@50270000 { + compatible = "snps,designware-i2s"; + reg = <0x50270000 0x200>; + interrupts = <7>; + clocks = <&sysclk K210_CLK_I2S2>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S2>; + status = "disabled"; + }; + + i2c0: i2c@50280000 { + compatible = "snps,designware-i2c"; + reg = <0x50280000 0x100>; + interrupts = <8>; + clocks = <&sysclk K210_CLK_I2C0>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C0>; + status = "disabled"; + }; + + i2c1: i2c@50290000 { + compatible = "snps,designware-i2c"; + reg = <0x50290000 0x100>; + interrupts = <9>; + clocks = <&sysclk K210_CLK_I2C1>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@502A0000 { + compatible = "snps,designware-i2c"; + reg = <0x502A0000 0x100>; + interrupts = <10>; + clocks = <&sysclk K210_CLK_I2C2>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C2>; + status = "disabled"; + }; + + fpioa: pinmux@502B0000 { + compatible = "canaan,k210-fpioa"; + reg = <0x502B0000 0x100>; + clocks = <&sysclk K210_CLK_FPIOA>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_FPIOA>; + canaan,k210-sysctl-power = <&sysctl 108>; + status = "disabled"; + }; + + sha256: sha256@502C0000 { + compatible = "canaan,k210-sha256"; + reg = <0x502C0000 0x100>; + clocks = <&sysclk K210_CLK_SHA>; + resets = <&sysrst K210_RST_SHA>; + status = "disabled"; + }; + + timer0: timer@502D0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502D0000 0x100>; + interrupts = <14 15>; + clocks = <&sysclk K210_CLK_TIMER0>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER0>; + status = "disabled"; + }; + + timer1: timer@502E0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502E0000 0x100>; + interrupts = <16 17>; + clocks = <&sysclk K210_CLK_TIMER1>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER1>; + status = "disabled"; + }; + + timer2: timer@502F0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502F0000 0x100>; + interrupts = <18 19>; + clocks = <&sysclk K210_CLK_TIMER2>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER2>; + status = "disabled"; + }; + }; + + apb1: bus@50400000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB1>; + + wdt0: watchdog@50400000 { + compatible = "snps,dw-wdt"; + reg = <0x50400000 0x100>; + interrupts = <21>; + clocks = <&sysclk K210_CLK_WDT0>, + <&sysclk K210_CLK_APB1>; + clock-names = "tclk", "pclk"; + resets = <&sysrst K210_RST_WDT0>; + status = "disabled"; + }; + + wdt1: watchdog@50410000 { + compatible = "snps,dw-wdt"; + reg = <0x50410000 0x100>; + interrupts = <22>; + clocks = <&sysclk K210_CLK_WDT1>, + <&sysclk K210_CLK_APB1>; + clock-names = "tclk", "pclk"; + resets = <&sysrst K210_RST_WDT1>; + status = "disabled"; + }; + + otp0: nvmem@50420000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "canaan,k210-otp"; + reg = <0x50420000 0x100>, + <0x88000000 0x20000>; + reg-names = "reg", "mem"; + clocks = <&sysclk K210_CLK_ROM>; + resets = <&sysrst K210_RST_ROM>; + read-only; + status = "disabled"; + + /* Bootloader */ + firmware@00000 { + reg = <0x00000 0xC200>; + }; + + /* + * config string as described in RISC-V + * privileged spec 1.9 + */ + config-1-9@1c000 { + reg = <0x1C000 0x1000>; + }; + + /* + * Device tree containing only registers, + * interrupts, and cpus + */ + fdt@1d000 { + reg = <0x1D000 0x2000>; + }; + + /* CPU/ROM credits */ + credits@1f000 { + reg = <0x1F000 0x1000>; + }; + }; + + dvp0: camera@50430000 { + compatible = "canaan,k210-dvp"; + reg = <0x50430000 0x100>; + interrupts = <24>; + clocks = <&sysclk K210_CLK_DVP>; + resets = <&sysrst K210_RST_DVP>; + canaan,k210-misc-offset = <&sysctl 84>; + status = "disabled"; + }; + + sysctl: syscon@50440000 { + compatible = "canaan,k210-sysctl", + "syscon", "simple-mfd"; + reg = <0x50440000 0x100>; + clocks = <&sysclk K210_CLK_APB1>; + clock-names = "pclk"; + + sysclk: clock-controller { + #clock-cells = <1>; + compatible = "canaan,k210-clk"; + clocks = <&in0>; + }; + + sysrst: reset-controller { + compatible = "canaan,k210-rst"; + #reset-cells = <1>; + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&sysctl>; + offset = <48>; + mask = <1>; + value = <1>; + }; + }; + + aes0: aes@50450000 { + compatible = "canaan,k210-aes"; + reg = <0x50450000 0x100>; + clocks = <&sysclk K210_CLK_AES>; + resets = <&sysrst K210_RST_AES>; + status = "disabled"; + }; + + rtc: rtc@50460000 { + compatible = "canaan,k210-rtc"; + reg = <0x50460000 0x100>; + clocks = <&in0>; + resets = <&sysrst K210_RST_RTC>; + interrupts = <20>; + status = "disabled"; + }; + }; + + apb2: bus@52000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB2>; + + spi0: spi@52000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "canaan,k210-spi"; + reg = <0x52000000 0x100>; + interrupts = <1>; + clocks = <&sysclk K210_CLK_SPI0>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI0>; + reset-names = "spi"; + spi-max-frequency = <25000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi1: spi@53000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "canaan,k210-spi"; + reg = <0x53000000 0x100>; + interrupts = <2>; + clocks = <&sysclk K210_CLK_SPI1>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI1>; + reset-names = "spi"; + spi-max-frequency = <25000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi3: spi@54000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwc-ssi-1.01a"; + reg = <0x54000000 0x200>; + interrupts = <4>; + clocks = <&sysclk K210_CLK_SPI3>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI3>; + reset-names = "spi"; + /* Could possibly go up to 200 MHz */ + spi-max-frequency = <100000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; }; }; }; diff --git a/arch/riscv/boot/dts/canaan/k210_generic.dts b/arch/riscv/boot/dts/canaan/k210_generic.dts new file mode 100644 index 000000000000..396c8ca4d24d --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k210_generic.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "Kendryte K210 generic"; + compatible = "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; +}; + +&fpioa { + pinctrl-0 = <&jtag_pins>; + pinctrl-names = "default"; + status = "okay"; + + jtag_pins: jtag-pinmux { + pinmux = , + , + , + ; + }; + + uarths_pins: uarths-pinmux { + pinmux = , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/include/dt-bindings/clock/k210-clk.h b/include/dt-bindings/clock/k210-clk.h index a48176ad3c23..b2de702cbf75 100644 --- a/include/dt-bindings/clock/k210-clk.h +++ b/include/dt-bindings/clock/k210-clk.h @@ -9,7 +9,6 @@ /* * Kendryte K210 SoC clock identifiers (arbitrary values). */ -#define K210_CLK_ACLK 0 #define K210_CLK_CPU 0 #define K210_CLK_SRAM0 1 #define K210_CLK_SRAM1 2