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[83.57.173.190]) by smtp.gmail.com with ESMTPSA id w17sm839127ejk.124.2021.01.12.10.35.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:35:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Subject: [RFC PATCH v6 01/11] hw/ssi: imx_spi: Use a macro for number of chip selects supported Date: Tue, 12 Jan 2021 19:35:19 +0100 Message-Id: <20210112183529.2011863-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, Alistair Francis , Peter Chubb Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Avoid using a magic number (4) everywhere for the number of chip selects supported. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210112145526.31095-2-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Juan Quintela --- include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/hw/ssi/imx_spi.h b/include/hw/ssi/imx_spi.h index b82b17f3643..eeaf49bbac3 100644 --- a/include/hw/ssi/imx_spi.h +++ b/include/hw/ssi/imx_spi.h @@ -77,6 +77,9 @@ #define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH) +/* number of chip selects supported */ +#define ECSPI_NUM_CS 4 + #define TYPE_IMX_SPI "imx.spi" OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI) @@ -89,7 +92,7 @@ struct IMXSPIState { qemu_irq irq; - qemu_irq cs_lines[4]; + qemu_irq cs_lines[ECSPI_NUM_CS]; SSIBus *bus; diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index d8885ae454e..e605049a213 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -361,7 +361,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, /* We are in master mode */ - for (i = 0; i < 4; i++) { + for (i = 0; i < ECSPI_NUM_CS; i++) { qemu_set_irq(s->cs_lines[i], i == imx_spi_selected_channel(s) ? 0 : 1); } @@ -424,7 +424,7 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - for (i = 0; i < 4; ++i) { + for (i = 0; i < ECSPI_NUM_CS; ++i) { sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } From patchwork Tue Jan 12 18:35:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1425420 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=dUoqNviw; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DFfRt1R5Mz9sWk for ; Wed, 13 Jan 2021 05:36:41 +1100 (AEDT) Received: from localhost ([::1]:49744 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzOX1-00011H-Ck for incoming@patchwork.ozlabs.org; Tue, 12 Jan 2021 13:36:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55358) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOWH-0000y5-78; Tue, 12 Jan 2021 13:35:53 -0500 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]:44378) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOWE-0007F9-Ew; Tue, 12 Jan 2021 13:35:52 -0500 Received: by mail-ej1-x633.google.com with SMTP id w1so4885077ejf.11; Tue, 12 Jan 2021 10:35:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZanZiJ3tTZSMBujs+F1bLNbZeY/v2F63RmtFKqnRXj4=; b=dUoqNviw/pjbxVL7TjynR6A/+y579dM8g8u+tMtPz5fQKSBztKWEBI65tCRom+hNZg oijQ3NMQuMtbqnWixlyHuKiXVl7ctkHdWR3mkl4limigjVmNPQ1dP+o+vCm4AINfqTFM OwoYnNBXYUKlO+HrMvdwAjHpZz1Elkn8zMkJ6WAWlEGb7xdQFaNSgC7Yj8fbGVxxnnl1 TEc9ZK4FVs8xRxYBHwAfRR1q3CFBWXKrDDJzdfKJ/2lQjsewJ9pha7GJi43E94CnBcyx ZChaVjTEoUy0Ujb/AcUHZlQS/vcw78KtaeViYaaO4Nyi1xYxK+L4wjGlks+Gns47KNo+ nbNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ZanZiJ3tTZSMBujs+F1bLNbZeY/v2F63RmtFKqnRXj4=; b=bme45xCW6FJFlbaYULaw22IOeNMRAkfNXMdYJs30kpnp/KykUCt/5laXMypZTUdKk+ o3VrPTHAo2ZJMxQbVllkO6yUYRVhIWoEzbeqemMK/zbjJXm7rP7RtuGnDIcgF7Y16T0t 4/SzBxgih68HR46yTJ8HPqwop5abH7Ua7fnMbaNN0Te3ncoBhCk17SackLZr6SRuaVwe SIn0PxnJ+zqyMryYcOYPuMsfraKYfvfOJAcb3oM4Hd2wepxvSA0IrMnkSgcV11C/T6Xy voHOrBPPgi8WY1yBxvqWIJWPdj6CEuj9EUHbzsY3B4NVZ/RilPQeGOeGA0jb6vqI4W4a KQig== X-Gm-Message-State: AOAM533uGt67gffzF9DBrLuOy9YJVWTvbvAnq6PVZszM09O0oHrerWT7 54hXzQw6fBwtRWWmZfyh0B4= X-Google-Smtp-Source: ABdhPJysWxc+TAlm+ctgH1Xuw3U+dIcY2JoBnCZcJOfWq19ss3KHzzKDrTCH6LUMvGYcbq/pkumZmw== X-Received: by 2002:a17:906:653:: with SMTP id t19mr138235ejb.44.1610476548916; Tue, 12 Jan 2021 10:35:48 -0800 (PST) Received: from x1w.redhat.com (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id qn4sm1510593ejb.50.2021.01.12.10.35.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:35:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Subject: [RFC PATCH v6 02/11] hw/ssi: imx_spi: Remove pointless variable initialization Date: Tue, 12 Jan 2021 19:35:20 +0100 Message-Id: <20210112183529.2011863-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" 'burst_length' is cleared in imx_spi_reset(), which is called after imx_spi_realize(). Remove the initialization to simplify. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Juan Quintela --- hw/ssi/imx_spi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index e605049a213..40f72c36b61 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -428,8 +428,6 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } - s->burst_length = 0; - fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE); fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE); } From patchwork Tue Jan 12 18:35:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1425422 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=oa8ugs1b; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DFfVS0X82z9sWk for ; Wed, 13 Jan 2021 05:38:56 +1100 (AEDT) Received: from localhost ([::1]:58106 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzOZC-0004WL-21 for incoming@patchwork.ozlabs.org; Tue, 12 Jan 2021 13:38:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55392) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOWQ-0001A4-Sw; Tue, 12 Jan 2021 13:36:03 -0500 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]:38817) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOWP-0007IV-D3; Tue, 12 Jan 2021 13:36:02 -0500 Received: by mail-ed1-x534.google.com with SMTP id w10so2536878edu.5; Tue, 12 Jan 2021 10:36:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cIbTTFaWqBlw1RG7hwtN0wXtBq0CsVDSjfCtHIelito=; b=oa8ugs1bbQImjYGvzrrC9iWH7/IjBH8mPKKCZ8C05gGEOlFpRWPXcWH4bujSXJxR8L vfdcmn6vRw7g3PkYOqWmlzTbHMNuY1Ph7Irgfxri+atvvyZtQN/41RqW7jM5djB97iUw ir2MPcYNIOm8vAX8c5zUSTIwz5ikhwBjsvnKdgbCuC0y4NzD7nqrrEtLK84qtCfZ9Pyy d857Hx/cImqGReyN6V3IacfHN0VmVMQ+ng/9uFA/GNnDlGZU9qHodYNM8iiS86lZhSKa qFSarRoX10B9uNaB6TRZJbBqeVfKG70WV+My3vz1aGTACF3yp615ysOW/t8kmLyR+2WT c7/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cIbTTFaWqBlw1RG7hwtN0wXtBq0CsVDSjfCtHIelito=; b=Tns69vjJxrRWRbAb8MMQ/0keXswoxC6n/Ox0pFXMTthbwVysSp7k4OFHgP1j7S1wWY N1zyaIQvfW2yxWmlb65ORsIevkxcs++Q2no9ulqoHMxdwNMC3wBGKY/XxjessMJncmeQ dageGtA/yMZm74y+fXli5fKDWkbiL5u2O99i2pjUUNH8uoUUU/CjTtmundgJmdVSwXkQ xbYdRJtU3c97gC3byOdslFkG/1vHW5iuVlY4Yh3Pvuw3eY1z2g4LSKn5/ilWtoxbgd0s N4/SjAu6STgD2/NWLGgO31uj214yusy3muioOR5OAwwqcD/qK4UvQNLxotpc0zm9WIeJ lTyg== X-Gm-Message-State: AOAM5305MBO8W3RAUIV9o0yQ6EjOJAKq/IlAS2z38z7QIDBnaY45/px6 lLOefOCISYDpDsDDX4u3i6M= X-Google-Smtp-Source: ABdhPJwXzxR76AAx/y9vRklqRXPWNY6DAT3STKdSWqBWNiTOJe5HoaMnC6gcmQVmIM/ugRNI5omFog== X-Received: by 2002:a50:f745:: with SMTP id j5mr384426edn.92.1610476559715; Tue, 12 Jan 2021 10:35:59 -0800 (PST) Received: from x1w.redhat.com (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id x16sm1526282ejb.38.2021.01.12.10.35.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:35:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Subject: [RFC PATCH v6 03/11] hw/ssi: imx_spi: Convert some debug printf()s to trace events Date: Tue, 12 Jan 2021 19:35:21 +0100 Message-Id: <20210112183529.2011863-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert some DPRINTF() to trace events. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Juan Quintela --- hw/ssi/imx_spi.c | 8 ++++---- hw/ssi/trace-events | 7 +++++++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 40f72c36b61..35ab33c0511 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -14,6 +14,7 @@ #include "migration/vmstate.h" #include "qemu/log.h" #include "qemu/module.h" +#include "trace.h" #ifndef DEBUG_IMX_SPI #define DEBUG_IMX_SPI 0 @@ -232,7 +233,7 @@ static void imx_spi_reset(DeviceState *dev) { IMXSPIState *s = IMX_SPI(dev); - DPRINTF("\n"); + trace_imx_spi_reset(); memset(s->regs, 0, sizeof(s->regs)); @@ -290,7 +291,7 @@ static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) break; } - DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value); + trace_imx_spi_read(index, imx_spi_reg_name(index), value); imx_spi_update_irq(s); @@ -310,8 +311,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, return; } - DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index), - (uint32_t)value); + trace_imx_spi_write(index, imx_spi_reg_name(index), value); change_mask = s->regs[index] ^ value; diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events index 612d3d6087a..20fcaf32df6 100644 --- a/hw/ssi/trace-events +++ b/hw/ssi/trace-events @@ -1,3 +1,5 @@ +# See docs/devel/tracing.txt for syntax documentation. + # aspeed_smc.c aspeed_smc_flash_set_segment(int cs, uint64_t reg, uint64_t start, uint64_t end) "CS%d segreg=0x%"PRIx64" [ 0x%"PRIx64" - 0x%"PRIx64" ]" @@ -10,6 +12,11 @@ aspeed_smc_dma_rw(const char *dir, uint32_t flash_addr, uint32_t dram_addr, uint aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64 aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect" +# imx_spi.c +imx_spi_reset(void) "" +imx_spi_read(uint32_t index, const char *name, uint32_t value) "index:%u (%s) value:0x%08x" +imx_spi_write(uint32_t index, const char *name, uint32_t value) "index:%u (%s) value:0x%08x" + # npcm7xx_fiu.c npcm7xx_fiu_enter_reset(const char *id, int reset_type) "%s reset type: %d" From patchwork Tue Jan 12 18:35:22 2021 Content-Type: text/plain; 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[83.57.173.190]) by smtp.gmail.com with ESMTPSA id bo20sm1862004edb.1.2021.01.12.10.36.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Subject: [RFC PATCH v6 04/11] hw/ssi: imx_spi: Reduce 'change_mask' variable scope Date: Tue, 12 Jan 2021 19:35:22 +0100 Message-Id: <20210112183529.2011863-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 35ab33c0511..bcc535f2893 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -303,7 +303,6 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, { IMXSPIState *s = opaque; uint32_t index = offset >> 2; - uint32_t change_mask; if (index >= ECSPI_MAX) { qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" @@ -313,7 +312,6 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, trace_imx_spi_write(index, imx_spi_reg_name(index), value); - change_mask = s->regs[index] ^ value; switch (index) { case ECSPI_RXDATA: @@ -357,6 +355,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, } if (imx_spi_channel_is_master(s)) { + uint32_t change_mask = s->regs[index] ^ value; int i; /* We are in master mode */ From patchwork Tue Jan 12 18:35:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1425428 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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[83.57.173.190]) by smtp.gmail.com with ESMTPSA id d8sm1823526edm.75.2021.01.12.10.36.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:10 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Subject: [RFC PATCH v6 05/11] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Date: Tue, 12 Jan 2021 19:35:23 +0100 Message-Id: <20210112183529.2011863-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" When the block is disabled, all registers are reset with the exception of the ECSPI_CONREG. It is initialized to zero when the instance is created. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Juan Quintela --- hw/ssi/imx_spi.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index bcc535f2893..96aecc8fa28 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -232,12 +232,23 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) static void imx_spi_reset(DeviceState *dev) { IMXSPIState *s = IMX_SPI(dev); + unsigned i; trace_imx_spi_reset(); - memset(s->regs, 0, sizeof(s->regs)); - - s->regs[ECSPI_STATREG] = 0x00000003; + for (i = 0; i < ARRAY_SIZE(s->regs); i++) { + switch (i) { + case ECSPI_CONREG: + /* CONREG is not updated on reset */ + break; + case ECSPI_STATREG: + s->regs[i] = 0x00000003; + break; + default: + s->regs[i] = 0; + break; + } + } imx_spi_rxfifo_reset(s); imx_spi_txfifo_reset(s); From patchwork Tue Jan 12 18:35:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1425437 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=APEjyaBz; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DFfwl4DDyz9ssD for ; Wed, 13 Jan 2021 05:58:14 +1100 (AEDT) Received: from localhost ([::1]:45200 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzOrs-0006Jq-0e for incoming@patchwork.ozlabs.org; Tue, 12 Jan 2021 13:58:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55474) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOWi-0001kJ-3C; Tue, 12 Jan 2021 13:36:20 -0500 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]:36991) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOWg-0007TJ-EO; Tue, 12 Jan 2021 13:36:19 -0500 Received: by mail-ed1-x52a.google.com with SMTP id cm17so3471897edb.4; Tue, 12 Jan 2021 10:36:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=s5mgKFMjtxL8UOIPFrajTKd7ASiN1mJ6g35FLNPKpAg=; b=APEjyaBzm/Du1d/Ys5l2VuIvlSxTisLqbzBMDlXcYC/JYhgqGXvmketuAr9kV2yaK+ LUCSHVoMmdD8itt2tRm0Ws9w6PUvVszR6gFABsvuhAZ0NV3YJeK0VOKkwRA/YAQpInAn L8EgFn10Q7FP1TJzVIfU+j7OWy7k1IJF97B9sQOCSoCPDBDGQ7UuTHuky7avtHvEnI4J ZfvV/2Xk21tvefzXWJ3fI3Q5LJInvAs/h4z3x8Ii3XIQyuFcWA+05V0PI8HSzbROcTFu z7lo7G+7KNY6aiEM18l3OnvtU8gcX+Jth4Q8olBJvjMfWPsMavzd+t1nm6V2+sl8bq48 JW/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=s5mgKFMjtxL8UOIPFrajTKd7ASiN1mJ6g35FLNPKpAg=; b=TDYbyQZCUVYLtv3LEBv4git8Stw9pQf8KwD11tuz6fPtX/XwGsuzyR4CZD+NdLvYzI O9reD7s4KJEus9gTh5MshlvbTm4AjPAdw9ukWAWqLSjpwIQcx2ZbXG1/wL09oXurPsWr pR8KeI4BhVZGbPjo19KNOvFVl/CHA1qW3UWGFym4VYHlOy6ThzSUYB8tglQUIUTLr9YU OipU5HaB2V6kYSoMpCOXtVt1P0+Rc3sjUTAXPu6LrJnVjRPMj79wphVJ2O1hQDm7t6AT E/FSXIpXJatSGFN/Fs4nWGzt6xhAtZGikN99c1LuGMFC3FsC4aUt9npX2jmhKLU0FzLS tmIg== X-Gm-Message-State: AOAM530ix4UnBaRnVyA/ES4IT11Y04yrKmD1oobCTQGYrpJWx/tE5r4y MZ0PSXLbak5ph0MohT8HNRI= X-Google-Smtp-Source: ABdhPJwkjhG+m1UD4DrA6ECTXBpnxlTrl3X3ceYmb4EKbWvuQJLDMsFTmrgQEqnuto2LXLKicYFZ5w== X-Received: by 2002:a50:d80c:: with SMTP id o12mr364538edj.338.1610476576862; Tue, 12 Jan 2021 10:36:16 -0800 (PST) Received: from x1w.redhat.com (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id j9sm1801373eds.66.2021.01.12.10.36.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:16 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Subject: [RFC PATCH v6 06/11] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Date: Tue, 12 Jan 2021 19:35:24 +0100 Message-Id: <20210112183529.2011863-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" When the block is disabled, it stay it is 'internal reset logic' (internal clocks are gated off). Reading any register returns its reset value. Only update this value if the device is enabled. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Juan Quintela --- hw/ssi/imx_spi.c | 60 +++++++++++++++++++++++------------------------- 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 96aecc8fa28..7ac9da0f1d2 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -270,42 +270,40 @@ static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) return 0; } - switch (index) { - case ECSPI_RXDATA: - if (!imx_spi_is_enabled(s)) { - value = 0; - } else if (fifo32_is_empty(&s->rx_fifo)) { - /* value is undefined */ - value = 0xdeadbeef; - } else { - /* read from the RX FIFO */ - value = fifo32_pop(&s->rx_fifo); + value = s->regs[index]; + + if (imx_spi_is_enabled(s)) { + switch (index) { + case ECSPI_RXDATA: + if (fifo32_is_empty(&s->rx_fifo)) { + /* value is undefined */ + value = 0xdeadbeef; + } else { + /* read from the RX FIFO */ + value = fifo32_pop(&s->rx_fifo); + } + break; + case ECSPI_TXDATA: + qemu_log_mask(LOG_GUEST_ERROR, + "[%s]%s: Trying to read from TX FIFO\n", + TYPE_IMX_SPI, __func__); + + /* Reading from TXDATA gives 0 */ + break; + case ECSPI_MSGDATA: + qemu_log_mask(LOG_GUEST_ERROR, + "[%s]%s: Trying to read from MSG FIFO\n", + TYPE_IMX_SPI, __func__); + /* Reading from MSGDATA gives 0 */ + break; + default: + break; } - break; - case ECSPI_TXDATA: - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n", - TYPE_IMX_SPI, __func__); - - /* Reading from TXDATA gives 0 */ - - break; - case ECSPI_MSGDATA: - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n", - TYPE_IMX_SPI, __func__); - - /* Reading from MSGDATA gives 0 */ - - break; - default: - value = s->regs[index]; - break; + imx_spi_update_irq(s); } - trace_imx_spi_read(index, imx_spi_reg_name(index), value); - imx_spi_update_irq(s); - return (uint64_t)value; } From patchwork Tue Jan 12 18:35:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1425427 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[83.57.173.190]) by smtp.gmail.com with ESMTPSA id r21sm1779423eds.91.2021.01.12.10.36.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:21 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Subject: [RFC PATCH v6 07/11] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled Date: Tue, 12 Jan 2021 19:35:25 +0100 Message-Id: <20210112183529.2011863-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" When the block is disabled, only the ECSPI_CONREG register can be modified. Setting the EN bit enabled the device, clearing it "disables the block and resets the internal logic with the exception of the ECSPI_CONREG" register. Move the imx_spi_is_enabled() check earlier. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 7ac9da0f1d2..801daa5cbfa 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -321,6 +321,20 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, trace_imx_spi_write(index, imx_spi_reg_name(index), value); + if (!imx_spi_is_enabled(s)) { + /* Block is disabled */ + if (index != ECSPI_CONREG) { + /* Ignore access */ + return; + } + s->regs[ECSPI_CONREG] = value; + if (value & ECSPI_CONREG_EN) { + /* Keep disabled */ + return; + } + /* Enable the block */ + imx_spi_reset(DEVICE(s)); + } switch (index) { case ECSPI_RXDATA: @@ -328,10 +342,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, TYPE_IMX_SPI, __func__); break; case ECSPI_TXDATA: - if (!imx_spi_is_enabled(s)) { - /* Ignore writes if device is disabled */ - break; - } else if (fifo32_is_full(&s->tx_fifo)) { + if (fifo32_is_full(&s->tx_fifo)) { /* Ignore writes if queue is full */ break; } @@ -357,12 +368,6 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, case ECSPI_CONREG: s->regs[ECSPI_CONREG] = value; - if (!imx_spi_is_enabled(s)) { - /* device is disabled, so this is a reset */ - imx_spi_reset(DEVICE(s)); - return; - } - if (imx_spi_channel_is_master(s)) { uint32_t change_mask = s->regs[index] ^ value; int i; From patchwork Tue Jan 12 18:35:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1425430 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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[83.57.173.190]) by smtp.gmail.com with ESMTPSA id k15sm1503481ejc.79.2021.01.12.10.36.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:27 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Subject: [RFC PATCH v6 08/11] hw/ssi: imx_spi: Disable chip selects when controller is disabled Date: Tue, 12 Jan 2021 19:35:26 +0100 Message-Id: <20210112183529.2011863-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Xuzhou Cheng , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Xuzhou Cheng When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_reset() is called to reset the controller, but chip select lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210112145526.31095-4-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 801daa5cbfa..2f9e800dd3a 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -255,6 +255,10 @@ static void imx_spi_reset(DeviceState *dev) imx_spi_update_irq(s); + for (i = 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } + s->burst_length = 0; } From patchwork Tue Jan 12 18:35:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1425438 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=l20l7gwW; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DFg2D30cwz9sVk for ; Wed, 13 Jan 2021 06:03:00 +1100 (AEDT) Received: from localhost ([::1]:55158 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzOwU-0002Q7-EB for incoming@patchwork.ozlabs.org; Tue, 12 Jan 2021 14:02:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55588) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOWz-0001ws-J6; Tue, 12 Jan 2021 13:36:37 -0500 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]:38444) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOWy-0007Xb-4C; Tue, 12 Jan 2021 13:36:37 -0500 Received: by mail-ej1-x629.google.com with SMTP id 6so4938540ejz.5; Tue, 12 Jan 2021 10:36:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=URPw2976JZr7XRKyhMiAKOdcNTBQU8VnrnQ2GFeuE/U=; b=l20l7gwWIKPn32PIaaF39Dntbr9gVgUYcerX5b/rTYZA7TyEvIP8nd7HeayFeQK3ut uSpCBts9Krux9jifdRQf1QkakzQnlPS+kaCnIXyJD1M8islpFIJquKX+FaJzEbU13TrO WXb6rNpWZikweRuVb0O9R7GP2Sh5XUn98RmcBMHk8tpygi5E63ytZelumOVZsrCLx4F7 qR471FnxLEEhKy1b8mFjbll+c7yfIay1OmnLuxN8mQ9g5bJbOY7Yee06O1/3qonWxTIU YF053G4+farbNVdkrGKWKpatA1keGPDKMgZAC6GfkocEVaXfIKjdAAhgOtC6K4G2Tww1 2rZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=URPw2976JZr7XRKyhMiAKOdcNTBQU8VnrnQ2GFeuE/U=; b=iCEO1Rj+K3xI5lCDj0NkyP0Mi6Y4uCHG82E+TuZsj+AzPg1xNuuspoymzmJ8qaCVIC QX4LO0RfZO/gkzlXHyNYev8u/ZrhCWgtt4zqph2KOg4oQGjTkmgOGGCHoc1GCFrua8Ux oGDRQH0Zz6waF9bS2n+DAhhBxqcirnq0L5WtZzXxGjttCVYtcGheRZyqyojrioWmAkTt KIgNK3bslykUwx/37JNcG7+MROgKp3BC6rTBL6S/Rm24n1wotola7Kv+pdSiWcRstBt8 k9rN/BYv5PbCnUTp/8KIFH3VfiUcgHvyEayI3tacMnmAbB7w6CCiTtajNEOtwTeTZzW9 pehw== X-Gm-Message-State: AOAM5325PQEbyc0oN7P1fUtpiXEJrkqMhJj8RXaU+16FNoYfGHQ/cDTr FYh49Di+u+mlmXiLnZnnnqSvZLjoss8= X-Google-Smtp-Source: ABdhPJxVs7D+TeVRgmikig04ysNfEvpjXa9GxFu9bq1Fp9EL34h+nql5Lmf/X1Qb7jol/+mc9emwkg== X-Received: by 2002:a17:906:d8a1:: with SMTP id qc1mr125349ejb.294.1610476594097; Tue, 12 Jan 2021 10:36:34 -0800 (PST) Received: from x1w.redhat.com (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id k2sm1516490ejp.6.2021.01.12.10.36.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:33 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Subject: [RFC PATCH v6 09/11] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Date: Tue, 12 Jan 2021 19:35:27 +0100 Message-Id: <20210112183529.2011863-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Current implementation of the imx spi controller expects the burst length to be multiple of 8, which is the most common use case. In case the burst length is not what we expect, log it to give user a chance to notice it, and round it up to be multiple of 8. Signed-off-by: Bin Meng Message-Id: <20210112145526.31095-5-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 2f9e800dd3a..638959daa08 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -129,7 +129,20 @@ static uint8_t imx_spi_selected_channel(IMXSPIState *s) static uint32_t imx_spi_burst_length(IMXSPIState *s) { - return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + uint32_t burst; + + burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + if (burst % 8) { + qemu_log_mask(LOG_UNIMP, + "[%s]%s: burst length (%d) not multiple of 8!\n", + TYPE_IMX_SPI, __func__, burst); + burst = ROUND_UP(burst, 8); + qemu_log_mask(LOG_UNIMP, + "[%s]%s: burst length rounded up to %d; this may not work.\n", + TYPE_IMX_SPI, __func__, burst); + } + + return burst; } static bool imx_spi_is_enabled(IMXSPIState *s) From patchwork Tue Jan 12 18:35:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1425433 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=GGdNkTjd; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DFflH25FQz9t0G for ; Wed, 13 Jan 2021 05:50:03 +1100 (AEDT) Received: from localhost ([::1]:54114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzOjx-0006SP-Au for incoming@patchwork.ozlabs.org; Tue, 12 Jan 2021 13:50:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55636) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOX5-0002Aw-1Z; Tue, 12 Jan 2021 13:36:43 -0500 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]:35528) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOX3-0007Zc-HC; Tue, 12 Jan 2021 13:36:42 -0500 Received: by mail-ed1-x52b.google.com with SMTP id u19so3485492edx.2; Tue, 12 Jan 2021 10:36:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xLLdvkIJe1l73eWOGFy35bKaZgGosmrQIeGMAiRhIRc=; b=GGdNkTjdD2SqUviwqnZEDqQkbcZq129V6FUHz6H1xgq8nZGAWREXGKd6RgQi5DoR3J pUGB0xdlbTctnsCfWeWpFuvl/7NFfHFOeVaHRVd5s322a7WN1zHZfMQmPJJjeJJLTFgA 74aZXkOrwvGpir5QiDW2Or2mLKmEloFYg/0z3KVMqXXhu3bZ/hO8mBlJp7LX/PAqTwLR awm6qogOKyv6w7up9vZ/VnOdX/hfex6EJEAuUMIG5b4IAPspKK3fD2V68VTSC4beSm4C nwBFDCIwtZTsfO0va8uwp76vkS8Ipwwm3V9pjZhwDGIM8K1JV6knoDDX1XJqveMDAXW3 4/Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=xLLdvkIJe1l73eWOGFy35bKaZgGosmrQIeGMAiRhIRc=; b=cLMIfuuXxXWwjNTlzgQCaC1zFESk293U8FdRxBy6ZQcHcDnXdQ7eOkJ9HPx9/UaB2D esqSDzVHbwdugy67Mbm99u0cFW75bWbF+oO2ojnnCLQuO27UuEZ6D0i9aTwb5ekmQVzf sEUBKLCkYMUjvy8NJfQFC7HrGRgjp294wfs6J7AwvA7sVe675hOnKMQdGdwp6wiZq+7J 3p7ndDy9WVF867rvZblpDmr4cHb9EAjXz4tnz/XL7IeFruXVvcmMYkTy8UdFLxclWbZ/ 0q7IeLEUnO2tt1L/xzgalgOuQZS3SbA63rCPMXxVTmsND9z0EDMgDMlanL78aaVnxHlj ljaw== X-Gm-Message-State: AOAM533iAswEn2DhLWfO3zQrcr9Uw88zBZi0n7XZOwcmZeNYq5ggLRNk T6QHR4WAAzhZ4BF8JCDJl5TQfYwoTYQ= X-Google-Smtp-Source: ABdhPJy9RrAi0h8sC/vPap5Yg4VTQNuty1PJc6i07aUmQo+7XHcYfVaZj/YxXT/KfMOdPgGpD0w36Q== X-Received: by 2002:a05:6402:31bb:: with SMTP id dj27mr356816edb.285.1610476599942; Tue, 12 Jan 2021 10:36:39 -0800 (PST) Received: from x1w.redhat.com (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id x20sm1517322ejv.66.2021.01.12.10.36.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Subject: [RFC PATCH v6 10/11] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Date: Tue, 12 Jan 2021 19:35:28 +0100 Message-Id: <20210112183529.2011863-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng For the ECSPIx_CONREG register BURST_LENGTH field, the manual says: 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word. 0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word. Current logic uses either s->burst_length or 32, whichever smaller, to determine how many bits it should read from the tx fifo each time. For example, for a 48 bit burst length, current logic transfers the first 32 bit from the first word in the tx fifo, followed by a 16 bit from the second word in the tx fifo, which is wrong. The correct logic should be: transfer the first 16 bit from the first word in the tx fifo, followed by a 32 bit from the second word in the tx fifo. With this change, SPI flash can be successfully probed by U-Boot on imx6 sabrelite board. => sf probe SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210112145526.31095-6-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 638959daa08..c4e2d2e1c97 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -192,7 +192,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("data tx:0x%08x\n", tx); - tx_burst = MIN(s->burst_length, 32); + tx_burst = (s->burst_length % 32) ? : 32; rx = 0; From patchwork Tue Jan 12 18:35:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1425435 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=mFaV7NYm; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DFfqm6xksz9sVk for ; Wed, 13 Jan 2021 05:53:56 +1100 (AEDT) Received: from localhost ([::1]:60048 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzOni-0000fd-Rb for incoming@patchwork.ozlabs.org; Tue, 12 Jan 2021 13:53:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOXA-0002PW-Ni; Tue, 12 Jan 2021 13:36:48 -0500 Received: from mail-ed1-x52c.google.com ([2a00:1450:4864:20::52c]:36999) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOX9-0007bO-6D; Tue, 12 Jan 2021 13:36:48 -0500 Received: by mail-ed1-x52c.google.com with SMTP id cm17so3473335edb.4; Tue, 12 Jan 2021 10:36:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4l0kq3wxIJBsGcT12cxU3gmDmz9IWzR6E0aRKmJTUjQ=; b=mFaV7NYmXIn6g4HptlIczJ+2QraPAoku178SziHN3Ki75DJqHBhEvxiMUFN9Db/nBx +hpOdBPj375NjffcD1HiIAs4TLsQpAJ3SS+TswKMivRx88KPUJ9KDomUrY4NOxyYm9OP kkT0DnHoxyD3eW1DWDNDV9rr0qpNuOs0BbiHOSJgWV1M5i1nla/YhnCt/7M4qY777ylt vsU4V9oZXrS4cp5QMIaaIVzk6ftBVMGoMDQO+lq/WvOTP6vZkFIK2a4TuYCpUwyNxT+p KueS7vkMS0OWpht6FpjzH2EztTtYqkHyle3ThJksYEMhKjsC0pu3vmRcOhN5IanM1qDq ooog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4l0kq3wxIJBsGcT12cxU3gmDmz9IWzR6E0aRKmJTUjQ=; b=TAIIQKe6L76Dv5S4lgpRqrMW80V99szn2Okt033+pFGjjZNLztLbKC+JMJuhpwlpj0 Tts32xCoJZrh8XyYxWZKnmHrYAM+1g8dVGkCOy+5RlTHpb0667LAaO7Fn6MMTbD1JWMq jktMuijlZDKFFQitkNMIsIwOzEvxtIgskBo+pH+DbLD8AL3dVT7xLu5b3BYGSe05OkPR +kyNLT6nMsEzTofV4tl4vm9nYf84ZXNtCftDKuQh5nT+bEXb4HJzB6Ji4kNyIXZJ8pzQ lXUV06f7KMCfokf6aKkQ66Sc6hmvPNxgvwm0xemri9XR2V9rkb+RMJ7HVuk/tZPijYtX GTeg== X-Gm-Message-State: AOAM5308XKw6FFVqk9SNkyuFXiCt1oXQ5ww420V0BqYOHKXfuMJxJIao 947iIochQLjzwd/pFBKzYAw= X-Google-Smtp-Source: ABdhPJyJun8fhYKMg5tnrCY8tIgZG0kKJ/eXtJ11t71Z3aPw6nE1o0p+5vFfOBCZ9T7InoytwoVgVQ== X-Received: by 2002:a50:fe0e:: with SMTP id f14mr372860edt.159.1610476605633; Tue, 12 Jan 2021 10:36:45 -0800 (PST) Received: from x1w.redhat.com (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id k21sm1830660edq.26.2021.01.12.10.36.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:44 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Subject: [RFC PATCH v6 11/11] hw/ssi: imx_spi: Correct tx and rx fifo endianness Date: Tue, 12 Jan 2021 19:35:29 +0100 Message-Id: <20210112183529.2011863-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng The endianness of data exchange between tx and rx fifo is incorrect. Earlier bytes are supposed to show up on MSB and later bytes on LSB, ie: in big endian. The manual does not explicitly say this, but the U-Boot and Linux driver codes have a swap on the data transferred to tx fifo and from rx fifo. With this change, U-Boot read from / write to SPI flash tests pass. => sf test 1ff000 1000 SPI flash test: 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Test passed 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng Message-Id: <20210112145526.31095-7-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index c4e2d2e1c97..38892698918 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -176,7 +176,6 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) while (!fifo32_is_empty(&s->tx_fifo)) { int tx_burst = 0; - int index = 0; if (s->burst_length <= 0) { s->burst_length = imx_spi_burst_length(s); @@ -197,7 +196,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) rx = 0; while (tx_burst > 0) { - uint8_t byte = tx & 0xff; + uint8_t byte = tx >> (tx_burst - 8); DPRINTF("writing 0x%02x\n", (uint32_t)byte); @@ -206,13 +205,11 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("0x%02x read\n", (uint32_t)byte); - tx = tx >> 8; - rx |= (byte << (index * 8)); + rx = (rx << 8) | byte; /* Remove 8 bits from the actual burst */ tx_burst -= 8; s->burst_length -= 8; - index++; } DPRINTF("data rx:0x%08x\n", rx);