From patchwork Wed Jan 10 05:20:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857944 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="AmhhO4Kb"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zGcnd6KHTz9s7n for ; Wed, 10 Jan 2018 16:21:57 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 86ED0C220FA; Wed, 10 Jan 2018 05:21:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=BAD_ENC_HEADER, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 34C62C2209B; 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DB6PR04MB3221; 6:2JJGr17+sYcUZhyjqQlldl9RwJ0fuVOZJPxGmd6Df6KlxYiZ55aNxu7Rb31l2yM6Ip//XWXe3p96uFn+l5btW32OjFlGbkqHRXRYVlXGs6ySFD/uaFmOH2kStPjXcGoKor4iyumhrrSFZBeDLv0uPzl+QPK21SLThPtlvvl061fjBLByGb1yIDWXNMW8CmMaWFTzGOINZo9ViXRc/1rjuWlaDPwvkML9LQ4qA3FYtY29OPHPcaBpuFTF3Pe8ia16n9mk8r7vSoYjzdMqgsQ868hAsVSqWToTevCSyoP11rL3zFBCrg/4uxum5EmZQygd8D8Fejpw9xMFl+CiMoXGgdPMLZVhc2LsT0D35gL+bpo=; 5:htBEsqG6vs9GRL4zFJqhAHSNeF9bb+ebdimqe49R0t26XoaQhFhLdREZucWviJmuYV9N5wRdoqQyRxZu62+L0Mb7W7FkWChP4x07vbPTO5pXDPCfGa7WYqEWTXFJqZjGT7V9+CgbwI907aMeU1gOh2TL4d+dCwq4ca43ParJhiI=; 24:7LRKx3gvAoLa9AVbQO1m4YrCsmB2cw7n8Fhxzm9HeZUc1OlXtLkcqc94apCsU+HTnKj33hCwS3NRF3H5KJYzdkAZD07FIQUDcP+TJiy1oEM=; 7:sMpVuQetHc9wBN2u5Xws3AhUS+hKFGkvU6NEwjhSvWN235fhP8PTqjMXTy2pM1CHVhTGM+JqPKJF0z3R7uxH+MWNzTwGJkrtUVFolq1+XpvmMOSFe2JLp5ORFuh0E+RSOlBw5gJ1U5kgFCgt3kwEqGo1wVS2bd9Wdj3KPv4kIKneQdqZkDT779IjyGtEkEq8ODUcslExTyfO5jp7QLaBWSy8nRXkVjmOJSkLjboXLyir+U1fV+HelX4hIcdJiZoS SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jan 2018 05:20:47.3249 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6405ecb7-36d0-4154-0e30-08d557e9e98d X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR04MB3221 Cc: u-boot@lists.denx.de, Tom Rini Subject: [U-Boot] [PATCH V5 01/31] arm: imx: Rework i.MX specific commands to be excluded from SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tom Rini The "clocks" and "bootaux" commands are only usable in full U-Boot, not SPL, so do not link them inside of SPL. Rework a little of the bootaux related code to make use of __weak and declare parts of it static as it's local to the file. Cc: Stefano Babic Cc: Fabio Estevam Signed-off-by: Tom Rini --- arch/arm/mach-imx/Makefile | 2 ++ arch/arm/mach-imx/imx_bootaux.c | 13 ++++--------- arch/arm/mach-imx/mx5/clock.c | 4 +++- arch/arm/mach-imx/mx7/clock.c | 2 ++ arch/arm/mach-imx/mx7ulp/clock.c | 2 ++ 5 files changed, 13 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index d7966cfd4a..cf39d08bdd 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -28,7 +28,9 @@ obj-y += cache.o init.o obj-$(CONFIG_SATA) += sata.o obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o obj-$(CONFIG_IMX_RDC) += rdc-sema.o +ifneq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o +endif obj-$(CONFIG_SECURE_BOOT) += hab.o obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o endif diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 69026df763..b62dfbf6bf 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -6,27 +6,22 @@ #include #include +#include /* Allow for arch specific config before we boot */ -static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) +int __weak arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) { /* please define platform specific arch_auxiliary_core_up() */ return CMD_RET_FAILURE; } -int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) - __attribute__((weak, alias("__arch_auxiliary_core_up"))); - /* Allow for arch specific config before we boot */ -static int __arch_auxiliary_core_check_up(u32 core_id) +int __weak arch_auxiliary_core_check_up(u32 core_id) { /* please define platform specific arch_auxiliary_core_check_up() */ return 0; } -int arch_auxiliary_core_check_up(u32 core_id) - __attribute__((weak, alias("__arch_auxiliary_core_check_up"))); - /* * To i.MX6SX and i.MX7D, the image supported by bootaux needs * the reset vector at the head for the image, with SP and PC @@ -40,7 +35,7 @@ int arch_auxiliary_core_check_up(u32 core_id) * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for * accessing the M4 TCMUL. */ -int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong addr; int ret, up; diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c index 610098c175..284f6d4cde 100644 --- a/arch/arm/mach-imx/mx5/clock.c +++ b/arch/arm/mach-imx/mx5/clock.c @@ -911,10 +911,11 @@ void mxc_set_sata_internal_clock(void) } #endif +#ifndef CONFIG_SPL_BUILD /* * Dump some core clockes. */ -int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { u32 freq; @@ -947,3 +948,4 @@ U_BOOT_CMD( "display clocks", "" ); +#endif diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c index 8150faa1a3..c11042d6f5 100644 --- a/arch/arm/mach-imx/mx7/clock.c +++ b/arch/arm/mach-imx/mx7/clock.c @@ -1096,6 +1096,7 @@ void epdc_clock_disable(void) } #endif +#ifndef CONFIG_SPL_BUILD /* * Dump some core clockes. */ @@ -1131,3 +1132,4 @@ U_BOOT_CMD( "display clocks", "" ); +#endif diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index 77b282addd..553d62149d 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -323,6 +323,7 @@ void hab_caam_clock_enable(unsigned char enable) } #endif +#ifndef CONFIG_SPL_BUILD /* * Dump some core clockes. */ @@ -363,3 +364,4 @@ U_BOOT_CMD( "display clocks", "" ); +#endif From patchwork Wed Jan 10 05:20:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857943 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Signed-off-by: Peng Fan Reviewed-by: Fabio Estevam Cc: Stefano Babic Reviewed-by: Stefano Babic --- arch/arm/Kconfig | 14 +++++++++++--- arch/arm/Makefile | 4 ++-- arch/arm/mach-imx/mx8m/Kconfig | 10 ++++++++++ 3 files changed, 23 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-imx/mx8m/Kconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f2c35e32c6..b095bfe2e5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -604,6 +604,12 @@ config ARCH_MESON targeted at media players and tablet computers. We currently support the S905 (GXBaby) 64-bit SoC. +config ARCH_MX8M + bool "NXP i.MX8M platform" + select ARM64 + select DM + select SUPPORT_SPL + config ARCH_MX25 bool "NXP MX25" select CPU_ARM926EJS @@ -1180,13 +1186,15 @@ source "arch/arm/cpu/armv7/ls102xa/Kconfig" source "arch/arm/mach-imx/mx2/Kconfig" -source "arch/arm/mach-imx/mx7ulp/Kconfig" +source "arch/arm/mach-imx/mx5/Kconfig" + +source "arch/arm/mach-imx/mx6/Kconfig" source "arch/arm/mach-imx/mx7/Kconfig" -source "arch/arm/mach-imx/mx6/Kconfig" +source "arch/arm/mach-imx/mx7ulp/Kconfig" -source "arch/arm/mach-imx/mx5/Kconfig" +source "arch/arm/mach-imx/mx8m/Kconfig" source "arch/arm/mach-omap2/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 0e0ae77822..5881fdc8e2 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -95,11 +95,11 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/ ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35)) +ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m)) libs-y += arch/arm/mach-imx/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m vf610)) libs-y += arch/arm/mach-imx/ endif endif diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig new file mode 100644 index 0000000000..3a84c2f2b0 --- /dev/null +++ b/arch/arm/mach-imx/mx8m/Kconfig @@ -0,0 +1,10 @@ +if ARCH_MX8M + +config MX8M + bool + select ROM_UNIFIED_SECTIONS + +config SYS_SOC + default "mx8m" + +endif From patchwork Wed Jan 10 05:20:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857946 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: 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SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jan 2018 05:21:07.0127 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4f23e30-f834-4f87-54db-08d557e9f512 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR04MB3221 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH V5 03/31] imx: mx8m: add register definition header file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add register definition header file for i.MX8M Signed-off-by: Peng Fan Reviewed-by: Fabio Estevam Cc: Stefano Babic Reviewed-by: Stefano Babic --- arch/arm/include/asm/arch-mx8m/imx-regs.h | 468 ++++++++++++++++++++++++++++++ 1 file changed, 468 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx8m/imx-regs.h diff --git a/arch/arm/include/asm/arch-mx8m/imx-regs.h b/arch/arm/include/asm/arch-mx8m/imx-regs.h new file mode 100644 index 0000000000..a10034cc35 --- /dev/null +++ b/arch/arm/include/asm/arch-mx8m/imx-regs.h @@ -0,0 +1,468 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MX8M_REGS_H__ +#define __ASM_ARCH_MX8M_REGS_H__ + +#include + +#define ROM_VERSION_A0 0x800 +#define ROM_VERSION_B0 0x83C + +#define M4_BOOTROM_BASE_ADDR 0x007E0000 + +#define SAI1_BASE_ADDR 0x30010000 +#define SAI6_BASE_ADDR 0x30030000 +#define SAI5_BASE_ADDR 0x30040000 +#define SAI4_BASE_ADDR 0x30050000 +#define SPBA2_BASE_ADDR 0x300F0000 +#define AIPS1_BASE_ADDR 0x301F0000 +#define GPIO1_BASE_ADDR 0X30200000 +#define GPIO2_BASE_ADDR 0x30210000 +#define GPIO3_BASE_ADDR 0x30220000 +#define GPIO4_BASE_ADDR 0x30230000 +#define GPIO5_BASE_ADDR 0x30240000 +#define ANA_TSENSOR_BASE_ADDR 0x30260000 +#define ANA_OSC_BASE_ADDR 0x30270000 +#define WDOG1_BASE_ADDR 0x30280000 +#define WDOG2_BASE_ADDR 0x30290000 +#define WDOG3_BASE_ADDR 0x302A0000 +#define SDMA2_BASE_ADDR 0x302C0000 +#define GPT1_BASE_ADDR 0x302D0000 +#define GPT2_BASE_ADDR 0x302E0000 +#define GPT3_BASE_ADDR 0x302F0000 +#define ROMCP_BASE_ADDR 0x30310000 +#define LCDIF_BASE_ADDR 0x30320000 +#define IOMUXC_BASE_ADDR 0x30330000 +#define IOMUXC_GPR_BASE_ADDR 0x30340000 +#define OCOTP_BASE_ADDR 0x30350000 +#define ANATOP_BASE_ADDR 0x30360000 +#define SNVS_HP_BASE_ADDR 0x30370000 +#define CCM_BASE_ADDR 0x30380000 +#define SRC_BASE_ADDR 0x30390000 +#define GPC_BASE_ADDR 0x303A0000 +#define SEMAPHORE1_BASE_ADDR 0x303B0000 +#define SEMAPHORE2_BASE_ADDR 0x303C0000 +#define RDC_BASE_ADDR 0x303D0000 +#define CSU_BASE_ADDR 0x303E0000 + +#define AIPS2_BASE_ADDR 0x305F0000 +#define PWM1_BASE_ADDR 0x30660000 +#define PWM2_BASE_ADDR 0x30670000 +#define PWM3_BASE_ADDR 0x30680000 +#define PWM4_BASE_ADDR 0x30690000 +#define SYSCNT_RD_BASE_ADDR 0x306A0000 +#define SYSCNT_CMP_BASE_ADDR 0x306B0000 +#define SYSCNT_CTRL_BASE_ADDR 0x306C0000 +#define GPT6_BASE_ADDR 0x306E0000 +#define GPT5_BASE_ADDR 0x306F0000 +#define GPT4_BASE_ADDR 0x30700000 +#define PERFMON1_BASE_ADDR 0x307C0000 +#define PERFMON2_BASE_ADDR 0x307D0000 +#define QOSC_BASE_ADDR 0x307F0000 + +#define SPDIF1_BASE_ADDR 0x30810000 +#define ECSPI1_BASE_ADDR 0x30820000 +#define ECSPI2_BASE_ADDR 0x30830000 +#define ECSPI3_BASE_ADDR 0x30840000 +#define UART1_BASE_ADDR 0x30860000 +#define UART3_BASE_ADDR 0x30880000 +#define UART2_BASE_ADDR 0x30890000 +#define SPDIF2_BASE_ADDR 0x308A0000 +#define SAI2_BASE_ADDR 0x308B0000 +#define SAI3_BASE_ADDR 0x308C0000 +#define SPBA1_BASE_ADDR 0x308F0000 +#define CAAM_BASE_ADDR 0x30900000 +#define AIPS3_BASE_ADDR 0x309F0000 +#define MIPI_PHY_BASE_ADDR 0x30A00000 +#define MIPI_DSI_BASE_ADDR 0x30A10000 +#define I2C1_BASE_ADDR 0x30A20000 +#define I2C2_BASE_ADDR 0x30A30000 +#define I2C3_BASE_ADDR 0x30A40000 +#define I2C4_BASE_ADDR 0x30A50000 +#define UART4_BASE_ADDR 0x30A60000 +#define MIPI_CSI_BASE_ADDR 0x30A70000 +#define MIPI_CSI_PHY1_BASE_ADDR 0x30A80000 +#define CSI1_BASE_ADDR 0x30A90000 +#define MU_A_BASE_ADDR 0x30AA0000 +#define MU_B_BASE_ADDR 0x30AB0000 +#define SEMAPHOR_HS_BASE_ADDR 0x30AC0000 +#define USDHC1_BASE_ADDR 0x30B40000 +#define USDHC2_BASE_ADDR 0x30B50000 +#define MIPI_CS2_BASE_ADDR 0x30B60000 +#define MIPI_CSI_PHY2_BASE_ADDR 0x30B70000 +#define CSI2_BASE_ADDR 0x30B80000 +#define QSPI0_BASE_ADDR 0x30BB0000 +#define QSPI0_AMBA_BASE 0x08000000 +#define SDMA1_BASE_ADDR 0x30BD0000 +#define ENET1_BASE_ADDR 0x30BE0000 + +#define HDMI_CTRL_BASE_ADDR 0x32C00000 +#define AIPS4_BASE_ADDR 0x32DF0000 +#define DC1_BASE_ADDR 0x32E00000 +#define DC2_BASE_ADDR 0x32E10000 +#define DC3_BASE_ADDR 0x32E20000 +#define HDMI_SEC_BASE_ADDR 0x32E40000 +#define TZASC_BASE_ADDR 0x32F80000 +#define MTR_BASE_ADDR 0x32FB0000 +#define PLATFORM_CTRL_BASE_ADDR 0x32FE0000 + +#define MXS_APBH_BASE 0x33000000 +#define MXS_GPMI_BASE 0x33002000 +#define MXS_BCH_BASE 0x33004000 + +#define USB1_BASE_ADDR 0x38100000 +#define USB2_BASE_ADDR 0x38200000 +#define USB1_PHY_BASE_ADDR 0x381F0000 +#define USB2_PHY_BASE_ADDR 0x382F0000 + +#define MXS_LCDIF_BASE LCDIF_BASE_ADDR + +#define SRC_IPS_BASE_ADDR 0x30390000 +#define SRC_DDRC_RCR_ADDR 0x30391000 +#define SRC_DDRC2_RCR_ADDR 0x30391004 + +#define DDRC_DDR_SS_GPR0 0x3d000000 +#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) +#define DDR_CSD1_BASE_ADDR 0x40000000 + +#if !defined(__ASSEMBLY__) +#include +#include +#include + +#define GPR_TZASC_EN BIT(0) +#define GPR_TZASC_EN_LOCK BIT(16) + +#define SRC_SCR_M4_ENABLE_OFFSET 3 +#define SRC_SCR_M4_ENABLE_MASK BIT(3) +#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0 +#define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0) +#define SRC_DDR1_ENABLE_MASK 0x8F000000UL +#define SRC_DDR2_ENABLE_MASK 0x8F000000UL +#define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3) +#define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2) +#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1) +#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0) + +struct iomuxc_gpr_base_regs { + u32 gpr[47]; +}; + +struct ocotp_regs { + u32 ctrl; + u32 ctrl_set; + u32 ctrl_clr; + u32 ctrl_tog; + u32 timing; + u32 rsvd0[3]; + u32 data; + u32 rsvd1[3]; + u32 read_ctrl; + u32 rsvd2[3]; + u32 read_fuse_data; + u32 rsvd3[3]; + u32 sw_sticky; + u32 rsvd4[3]; + u32 scs; + u32 scs_set; + u32 scs_clr; + u32 scs_tog; + u32 crc_addr; + u32 rsvd5[3]; + u32 crc_value; + u32 rsvd6[3]; + u32 version; + u32 rsvd7[0xdb]; + + /* fuse banks */ + struct fuse_bank { + u32 fuse_regs[0x10]; + } bank[0]; +}; + +struct fuse_bank0_regs { + u32 lock; + u32 rsvd0[3]; + u32 uid_low; + u32 rsvd1[3]; + u32 uid_high; + u32 rsvd2[7]; +}; + +struct fuse_bank1_regs { + u32 tester3; + u32 rsvd0[3]; + u32 tester4; + u32 rsvd1[3]; + u32 tester5; + u32 rsvd2[3]; + u32 cfg0; + u32 rsvd3[3]; +}; + +struct anamix_pll { + u32 audio_pll1_cfg0; + u32 audio_pll1_cfg1; + u32 audio_pll2_cfg0; + u32 audio_pll2_cfg1; + u32 video_pll_cfg0; + u32 video_pll_cfg1; + u32 gpu_pll_cfg0; + u32 gpu_pll_cfg1; + u32 vpu_pll_cfg0; + u32 vpu_pll_cfg1; + u32 arm_pll_cfg0; + u32 arm_pll_cfg1; + u32 sys_pll1_cfg0; + u32 sys_pll1_cfg1; + u32 sys_pll1_cfg2; + u32 sys_pll2_cfg0; + u32 sys_pll2_cfg1; + u32 sys_pll2_cfg2; + u32 sys_pll3_cfg0; + u32 sys_pll3_cfg1; + u32 sys_pll3_cfg2; + u32 video_pll2_cfg0; + u32 video_pll2_cfg1; + u32 video_pll2_cfg2; + u32 dram_pll_cfg0; + u32 dram_pll_cfg1; + u32 dram_pll_cfg2; + u32 digprog; + u32 osc_misc_cfg; + u32 pllout_monitor_cfg; + u32 frac_pllout_div_cfg; + u32 sscg_pllout_div_cfg; +}; + +struct fuse_bank9_regs { + u32 mac_addr0; + u32 rsvd0[3]; + u32 mac_addr1; + u32 rsvd1[11]; +}; + +/* System Reset Controller (SRC) */ +struct src { + u32 scr; + u32 a53rcr; + u32 a53rcr1; + u32 m4rcr; + u32 reserved1[4]; + u32 usbophy1_rcr; + u32 usbophy2_rcr; + u32 mipiphy_rcr; + u32 pciephy_rcr; + u32 hdmi_rcr; + u32 disp_rcr; + u32 reserved2[2]; + u32 gpu_rcr; + u32 vpu_rcr; + u32 pcie2_rcr; + u32 mipiphy1_rcr; + u32 mipiphy2_rcr; + u32 reserved3; + u32 sbmr1; + u32 srsr; + u32 reserved4[2]; + u32 sisr; + u32 simr; + u32 sbmr2; + u32 gpr1; + u32 gpr2; + u32 gpr3; + u32 gpr4; + u32 gpr5; + u32 gpr6; + u32 gpr7; + u32 gpr8; + u32 gpr9; + u32 gpr10; + u32 reserved5[985]; + u32 ddr1_rcr; + u32 ddr2_rcr; +}; + +struct gpc_reg { + u32 lpcr_bsc; + u32 lpcr_ad; + u32 lpcr_cpu1; + u32 lpcr_cpu2; + u32 lpcr_cpu3; + u32 slpcr; + u32 mst_cpu_mapping; + u32 mmdc_cpu_mapping; + u32 mlpcr; + u32 pgc_ack_sel; + u32 pgc_ack_sel_m4; + u32 gpc_misc; + u32 imr1_core0; + u32 imr2_core0; + u32 imr3_core0; + u32 imr4_core0; + u32 imr1_core1; + u32 imr2_core1; + u32 imr3_core1; + u32 imr4_core1; + u32 imr1_cpu1; + u32 imr2_cpu1; + u32 imr3_cpu1; + u32 imr4_cpu1; + u32 imr1_cpu3; + u32 imr2_cpu3; + u32 imr3_cpu3; + u32 imr4_cpu3; + u32 isr1_cpu0; + u32 isr2_cpu0; + u32 isr3_cpu0; + u32 isr4_cpu0; + u32 isr1_cpu1; + u32 isr2_cpu1; + u32 isr3_cpu1; + u32 isr4_cpu1; + u32 isr1_cpu2; + u32 isr2_cpu2; + u32 isr3_cpu2; + u32 isr4_cpu2; + u32 isr1_cpu3; + u32 isr2_cpu3; + u32 isr3_cpu3; + u32 isr4_cpu3; + u32 slt0_cfg; + u32 slt1_cfg; + u32 slt2_cfg; + u32 slt3_cfg; + u32 slt4_cfg; + u32 slt5_cfg; + u32 slt6_cfg; + u32 slt7_cfg; + u32 slt8_cfg; + u32 slt9_cfg; + u32 slt10_cfg; + u32 slt11_cfg; + u32 slt12_cfg; + u32 slt13_cfg; + u32 slt14_cfg; + u32 pgc_cpu_0_1_mapping; + u32 cpu_pgc_up_trg; + u32 mix_pgc_up_trg; + u32 pu_pgc_up_trg; + u32 cpu_pgc_dn_trg; + u32 mix_pgc_dn_trg; + u32 pu_pgc_dn_trg; + u32 lpcr_bsc2; + u32 pgc_cpu_2_3_mapping; + u32 lps_cpu0; + u32 lps_cpu1; + u32 lps_cpu2; + u32 lps_cpu3; + u32 gpc_gpr; + u32 gtor; + u32 debug_addr1; + u32 debug_addr2; + u32 cpu_pgc_up_status1; + u32 mix_pgc_up_status0; + u32 mix_pgc_up_status1; + u32 mix_pgc_up_status2; + u32 m4_mix_pgc_up_status0; + u32 m4_mix_pgc_up_status1; + u32 m4_mix_pgc_up_status2; + u32 pu_pgc_up_status0; + u32 pu_pgc_up_status1; + u32 pu_pgc_up_status2; + u32 m4_pu_pgc_up_status0; + u32 m4_pu_pgc_up_status1; + u32 m4_pu_pgc_up_status2; + u32 a53_lp_io_0; + u32 a53_lp_io_1; + u32 a53_lp_io_2; + u32 cpu_pgc_dn_status1; + u32 mix_pgc_dn_status0; + u32 mix_pgc_dn_status1; + u32 mix_pgc_dn_status2; + u32 m4_mix_pgc_dn_status0; + u32 m4_mix_pgc_dn_status1; + u32 m4_mix_pgc_dn_status2; + u32 pu_pgc_dn_status0; + u32 pu_pgc_dn_status1; + u32 pu_pgc_dn_status2; + u32 m4_pu_pgc_dn_status0; + u32 m4_pu_pgc_dn_status1; + u32 m4_pu_pgc_dn_status2; + u32 res[3]; + u32 mix_pdn_flg; + u32 pu_pdn_flg; + u32 m4_mix_pdn_flg; + u32 m4_pu_pdn_flg; + u32 imr1_core2; + u32 imr2_core2; + u32 imr3_core2; + u32 imr4_core2; + u32 imr1_core3; + u32 imr2_core3; + u32 imr3_core3; + u32 imr4_core3; + u32 pgc_ack_sel_pu; + u32 pgc_ack_sel_m4_pu; + u32 slt15_cfg; + u32 slt16_cfg; + u32 slt17_cfg; + u32 slt18_cfg; + u32 slt19_cfg; + u32 gpc_pu_pwrhsk; + u32 slt0_cfg_pu; + u32 slt1_cfg_pu; + u32 slt2_cfg_pu; + u32 slt3_cfg_pu; + u32 slt4_cfg_pu; + u32 slt5_cfg_pu; + u32 slt6_cfg_pu; + u32 slt7_cfg_pu; + u32 slt8_cfg_pu; + u32 slt9_cfg_pu; + u32 slt10_cfg_pu; + u32 slt11_cfg_pu; + u32 slt12_cfg_pu; + u32 slt13_cfg_pu; + u32 slt14_cfg_pu; + u32 slt15_cfg_pu; + u32 slt16_cfg_pu; + u32 slt17_cfg_pu; + u32 slt18_cfg_pu; + u32 slt19_cfg_pu; +}; + +#define WDOG_WDT_MASK BIT(3) +#define WDOG_WDZST_MASK BIT(0) +struct wdog_regs { + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ + u16 wicr; /* Interrupt Control */ + u16 wmcr; /* Miscellaneous Control */ +}; + +struct bootrom_sw_info { + u8 reserved_1; + u8 boot_dev_instance; + u8 boot_dev_type; + u8 reserved_2; + u32 core_freq; + u32 axi_freq; + u32 ddr_freq; + u32 tick_freq; + u32 reserved_3[3]; +}; + +#define ROM_SW_INFO_ADDR_B0 0x00000968 +#define ROM_SW_INFO_ADDR_A0 0x000009e8 + +#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \ + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \ + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0 +#endif +#endif From patchwork Wed Jan 10 05:20:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857948 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="H/LKuj1U"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zGcsy42fGz9s7n for ; Wed, 10 Jan 2018 16:25:42 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 35B6AC2219C; Wed, 10 Jan 2018 05:25:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on 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X-Microsoft-Exchange-Diagnostics: 1; DB6PR04MB3221; 6:f141H0tIsC3jc3jycKfr66JZL3FKf3UlU0ZZm/8IMa3RAbiXhiN+9K6MVrv1lL2Z7g6v/L0JMm1citoI+33vsbRTZHVJw8EoCfydBSn5ol86Dw+7TOBfDi72KyUXC4nK8cDeuA2hWTk5FWbUX9Q+c+Fu7U4DKDo/e0tCqdmrsQ5wzNcu+qOEFAPsXixyjPy7KSWVl/k2TTIXzPhjCbrL0XqVOcX+HscXn5Q6JlrTIBTnZWULKJqQqItC75EA/6sAnPtP5BUuo/M8lN2SQuMRbY1ynMn9sEuPDnTvtKtEola89d0x9Tk/4bEXXmC2HXEM955+CjLGkS73wn7a/dhYxUqSMASWavuv+CZQx1JiH7M=; 5:t1onX68DmMtNYf6mqx3x9DTB85UTcee0PDnsV0X9VmxhraOwdWweDzEnYSJBdGHqJUTNoZEdN8ugOUf8fGCh+uqK8iqvJ1NbYFsJHeGXrMi2NIfDd4K4DO/RzlJsJ8eyNwnGAsGLBWsC3Voi+X0Mg9USMM4RYGH84bR8PlnhfTM=; 24:bbKt8Af4+Jke+73niTK08bVTLA8iH43yKaHwNiirrck66r7Gl7rL53AaekQmRx/a/DvKqq8TH5LOAHIBbKBM1E902d1mxAcfVBS0d4iZ/nY=; 7:EVVmLDiSLv2kEJd8qzqLkalphfOQsglAMeXOFF1AGBAIOCmWHAMvUfMrYHnnkvEG2n4f6EA2tqmwjnDZVo9as6bS7NuqdjA2wExFh42CxwcYskffINZ1zOowsMdTbSN2VDw1hwnC8BJBED4PyHk7oODxqrEvSFky1zv5LjQ1uWtz05LrDoEghQOXvDS6UN5ZdIjGLjfyaZizeNFT3vOZ8ATQEe6HjCHKHviz44qyneL1cwHR44v0hxDd7MUB6CTP SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jan 2018 05:21:10.0752 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2354fb48-1684-46fd-5280-08d557e9f715 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR04MB3221 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH V5 04/31] imx: mx8m: add pin header file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add pin header file for i.MX8M Signed-off-by: Peng Fan Reviewed-by: Fabio Estevam Cc: Stefano Babic Reviewed-by: Stefano Babic --- arch/arm/include/asm/arch-mx8m/mx8mq_pins.h | 623 ++++++++++++++++++++++++++++ 1 file changed, 623 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx8m/mx8mq_pins.h diff --git a/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h b/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h new file mode 100644 index 0000000000..062bea7299 --- /dev/null +++ b/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h @@ -0,0 +1,623 @@ +/* + * Copyright (C) 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MX8MQ_PINS_H__ +#define __ASM_ARCH_MX8MQ_PINS_H__ + +#include + +enum { + IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL = IOMUX_PAD(0x0290, 0x0028, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE = IOMUX_PAD(0x0294, 0x002C, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B = IOMUX_PAD(0x0298, 0x0030, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK = IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE = IOMUX_PAD(0x029C, 0x0034, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V = IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0), + IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO06__ENET_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0), + IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO08__CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO09__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO09__CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO10__USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO11__USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO11__CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0), + + IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO12__USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT0 = IOMUX_PAD(0x02C0, 0x0058, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO13__USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT1 = IOMUX_PAD(0x02C4, 0x005C, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO14__USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO14__CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT2 = IOMUX_PAD(0x02C8, 0x0060, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO15__USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO15__CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0), + IMX8MQ_PAD_GPIO1_IO15__CSU_CSU_INT_DEB = IOMUX_PAD(0x02CC, 0x0064, 7, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0), + IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD2__ENET_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TX_CTL__ENET_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TXC__ENET_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RXC__ENET_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_CLK__GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_CMD__GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA0__GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA1__GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA2__GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA3__GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA4__GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA5__GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA6__GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_DATA7__GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA1__CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA2__CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_DATA3__SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_RESET_B__SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_ALE__GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE1_B__QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE3_B__QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA00__GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DQS__QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_RE_B__QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0), + IMX8MQ_PAD_SAI5_RXFS__SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0), + IMX8MQ_PAD_SAI5_RXC__SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0), + IMX8MQ_PAD_SAI5_RXD0__SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0), + IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0), + IMX8MQ_PAD_SAI5_RXD1__SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0), + IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0), + IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0), + IMX8MQ_PAD_SAI5_RXD2__SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0), + IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0), + IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0), + IMX8MQ_PAD_SAI5_RXD3__SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI5_MCLK__SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0), + IMX8MQ_PAD_SAI5_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0), + IMX8MQ_PAD_SAI5_MCLK__SAI4_MCLK = IOMUX_PAD(0x03C0, 0x0158, 2, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI5_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXFS__SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0), + IMX8MQ_PAD_SAI1_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0), + IMX8MQ_PAD_SAI1_RXFS__ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXFS__GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXC__SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0), + IMX8MQ_PAD_SAI1_RXC__ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXC__GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD0__SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0), + IMX8MQ_PAD_SAI1_RXD0__ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD0__GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD0__SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD1__SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0), + IMX8MQ_PAD_SAI1_RXD1__ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD1__GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD1__SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD2__SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0), + IMX8MQ_PAD_SAI1_RXD2__ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD2__GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD2__SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD3__SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x04E0, 1, 0), + IMX8MQ_PAD_SAI1_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD3__ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD3__GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD3__SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD4__SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD4__SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0), + IMX8MQ_PAD_SAI1_RXD5__ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD5__SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD6__SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD6__SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_RXD7__SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0), + IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_RXD7__SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0), + IMX8MQ_PAD_SAI1_TXFS__SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0), + IMX8MQ_PAD_SAI1_TXFS__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0), + IMX8MQ_PAD_SAI1_TXC__SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0), + IMX8MQ_PAD_SAI1_TXC__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD0__SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD0__ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD0__GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD0__SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD1__SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD1__SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD1__ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD1__GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD1__SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD2__SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD2__SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD2__ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD2__GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD2__SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD3__SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD3__SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD3__ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD3__GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD3__SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD4__SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD4__SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0), + IMX8MQ_PAD_SAI1_TXD4__SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0), + IMX8MQ_PAD_SAI1_TXD4__ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD4__GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD4__SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD5__SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0), + IMX8MQ_PAD_SAI1_TXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD5__ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD5__GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD5__SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD6__SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD6__SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0), + IMX8MQ_PAD_SAI1_TXD6__SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0), + IMX8MQ_PAD_SAI1_TXD6__ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD6__GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD6__SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_TXD7__SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD7__SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0), + IMX8MQ_PAD_SAI1_TXD7__ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD7__GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_TXD7__SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI1_MCLK__SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0), + IMX8MQ_PAD_SAI1_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0), + IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_RXFS__SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_RXFS__SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0), + IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_RXC__SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_RXC__SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0), + IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_RXD0__SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_RXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_TXFS__SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXFS__SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXC__SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_TXD0__SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXD0__SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI2_MCLK__SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI2_MCLK__SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0), + IMX8MQ_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_RXFS__SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXFS__GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0), + IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_RXC__SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXC__GPT1_CAPTURE2 = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0), + IMX8MQ_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_RXD__SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_RXD__SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0), + IMX8MQ_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_TXFS__SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXFS__GPT1_CLK = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXFS__SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0), + IMX8MQ_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_TXC__SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXC__GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXC__SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0), + IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_TXD__SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXD__GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_TXD__SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0), + IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SAI3_MCLK__SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SAI3_MCLK__SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0), + IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SPDIF_TX__SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SPDIF_RX__SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0), + IMX8MQ_PAD_SPDIF_EXT_CLK__GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI1_SCLK__UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0), + IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI1_MOSI__UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0), + IMX8MQ_PAD_ECSPI1_MOSI__GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0), + IMX8MQ_PAD_ECSPI1_MISO__GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0), + IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0), + IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), + IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0), + IMX8MQ_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0), + IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0), + IMX8MQ_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0x10 | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C1_SCL__ENET_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0x10 | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C1_SDA__ENET_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0), + IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0x10 | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C2_SCL__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0x10 | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C2_SDA__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0x10 | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0x10 | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0), + IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0x10 | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C4_SCL__PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0), + IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0x10 | 0, 0x0000, 0, 0), + IMX8MQ_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0), + IMX8MQ_PAD_I2C4_SDA__PCIE2_CLKREQ_B = IOMUX_PAD(0x0498, 0x0230, 2, 0x0528, 0, 0), + IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART1_RXD__UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0), + IMX8MQ_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0), + IMX8MQ_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART1_TXD__UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0), + IMX8MQ_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0), + IMX8MQ_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART2_RXD__UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0), + IMX8MQ_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0), + IMX8MQ_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART2_TXD__UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0), + IMX8MQ_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0), + IMX8MQ_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART3_RXD__UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0), + IMX8MQ_PAD_UART3_RXD__UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0), + IMX8MQ_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART3_TXD__UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0), + IMX8MQ_PAD_UART3_TXD__UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0), + IMX8MQ_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART4_RXD__UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0), + IMX8MQ_PAD_UART4_RXD__UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0), + IMX8MQ_PAD_UART4_RXD__PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0), + IMX8MQ_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0), + + IMX8MQ_PAD_UART4_TXD__UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0), + IMX8MQ_PAD_UART4_TXD__UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0), + IMX8MQ_PAD_UART4_TXD__PCIE2_CLKREQ_B = IOMUX_PAD(0x04B8, 0x0250, 2, 0x0528, 1, 0), + IMX8MQ_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), +}; +#endif From patchwork Wed Jan 10 05:20:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857947 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="jpTFjEVI"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zGcsR3JnYz9s7n for ; Wed, 10 Jan 2018 16:25:15 +1100 (AEDT) Received: by lists.denx.de (Postfix, from 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b=jpTFjEVIyE5kkcjiVhxJerTdNwx5NAZl/FmtxJChspwuQyWq0NrH+B6Of/FaidYgliicELiCIROp/M5D9e18YNDQVObAEgor0sAaLl4eBXDIFdZc9s97fTMuYQHSiZrTfMdgwJE8PgP+4qilbBNaewY5cwcvAhU33CfOkmBALLc= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; Received: from linux-u7w5.ap.freescale.net.net (92.121.68.129) by DB6PR04MB3221.eurprd04.prod.outlook.com (2603:10a6:6:6::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.386.5; Wed, 10 Jan 2018 05:21:13 +0000 From: Peng Fan To: sbabic@denx.de, fabio.estevam@nxp.com Date: Wed, 10 Jan 2018 13:20:22 +0800 Message-Id: <20180110052048.4425-6-peng.fan@nxp.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180110052048.4425-1-peng.fan@nxp.com> References: <20180110052048.4425-1-peng.fan@nxp.com> MIME-Version: 1.0 X-Originating-IP: [92.121.68.129] X-ClientProxiedBy: HK2PR02CA0219.apcprd02.prod.outlook.com (2603:1096:201:20::31) To DB6PR04MB3221.eurprd04.prod.outlook.com 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25:W1Q4mqUzTJ9At2ahsYEguVUMUtYV/EfTVd2acJliVmUULUMItADTp8/hJgaoSH+Z+vOMuCh5hTcjrMEMresjxY7sPHGyEdDtIMKUlO8NoRDxNt1/hSNQjZTeyoWQfl/vDPVukmgJziFBtS92BNE1t3ytn8Sq9f05PeIew/5Uir8rqMcEISzWjgY9k4KwyasBP8PL/cbvZai4xONQ1CKnDJgIRyYMhVNDY8X7YvPnnMzBgJ3WS62Fo+yUd/wbzRv7Lp2WnBGq2Syh/XD3uAOBgoK52U78q7bgeuUHsJKF/LwylD1u2kn9lI+KzIwgz93mhD+i1s8PhJ0bjo7t3qzL/g==; 31:hUz+El6Q3oGD2qSfc0j7Lq1bnzVyOwzUgZwtRjSHRWVbMj4PuUqIQa9Qu86SXJfPyNqwM+e8pmVtqBa7o+aWnzgY8QzuQ0gImMHCxw0HC0ZC9MgDLrGeia6eunpo6jysJdFxh5IbjSnJga+KEBI/eAzPwcE1hNd3AI0E1s1qkWvhoIgFp7Nox1lAjYZHVLrE9FvBMYhbf4D8q/F3oEJzg6BlyRN0Ui9bECwUcKhO+M0= X-MS-TrafficTypeDiagnostic: DB6PR04MB3221: X-Microsoft-Exchange-Diagnostics: 1; DB6PR04MB3221; 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X-Microsoft-Exchange-Diagnostics: 1; DB6PR04MB3221; 6:ggmQTPnePosAVHiyRm9GEgZFWfgIRWunxwRcPIpcwnas2n9UN3vH3GMPu8qimBatwduFvgtc8Oim2XQ7yXibzBuJBcXbcoENiPneRHb1aWxkPWZLdmEil4b+mDu2IdVx4EaAZgTyLgTT8jr1OWVGPGUZH0bGp3mgzeBvDjGuESLGS+PLjOHOO8ZtLgDoitkc8X8yRUxQmsKYr0SMm9BTw89tmfD8T0SoWR6LGG5x247IUCUXU5UHkTa8GwMxo+wO07hFrB8CVzc1gD2c5RrHNvzKH6wWfmYlNUv/Dd2ycijRW3ArAWs7sWi3VDJ+yvym5lTm4LLErvCmbKF3S36u5DHj2w7jufeZY1KwTPUyNLw=; 5:YZEyvIXKbrLXzxsspCUreFACfU7VJcAy6guFXTBiVRW8HmUR+BvH1gRPI0sFMDvxt6j8jTR02C+wV7VvYMaihOzRL8TY4dum+gb53SQ8OomhnrC9zLNGFV7ysXdMVMUeqB3iiYn7VPkKi0Ppsa4PiqQD1EznAJI2MaggAqq+Vh8=; 24:ylhZbFfyzhI+dWj2IbOFj9+kNbhHJ13LY20fC/mZ4tuVIZNcB2tJjasVx9EH8lGCkV9sdUMEBNfapyuxHzs3ILb93BZ7sFJCXzumzokXYtQ=; 7:J1rwsIIUSYg9emDdlq/GrZ28SZ9AB3iFgUNHbRlslJjebtSmYJsvXtz3+vF81yqZSouY4BB2AKqfc9gssJ16kN3wDdRa3VfTz0LeU+ZVXbuIqG9kMT1fCR4EkWbOcuMkGJI6p1pstIXK2LrHl55IzE+CvgWUtlRUKNQYKbScNrKY6V0XAx1B/VR6agAiO4Nfshx0jqKzufqg5MLrYA1xdqQ0K3xpEGIXS06hObhNISpxUfQTfLbiFKRIzRt5/7kw SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jan 2018 05:21:13.6378 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ff73b7f-6fde-4fc0-dae7-08d557e9f902 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR04MB3221 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH V5 05/31] imx: mx8m: add clock driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add clock driver to support i.MX8M. There are two kind PLLs, FRAC pll and SSCG pll. ROM already configured SYS PLL1/2, we only need to configure the output. ocotp/i2c/pll decoding and configuration/usdhc/lcdif/dram pll/ enet clock are configured in the code. Signed-off-by: Peng Fan Cc: Fabio Estevam Cc: Stefano Babic --- arch/arm/include/asm/arch-mx8m/clock.h | 657 +++++++++++++++++++++++++++ arch/arm/mach-imx/mx8m/Makefile | 7 + arch/arm/mach-imx/mx8m/clock.c | 795 +++++++++++++++++++++++++++++++++ arch/arm/mach-imx/mx8m/clock_slice.c | 742 ++++++++++++++++++++++++++++++ 4 files changed, 2201 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx8m/clock.h create mode 100644 arch/arm/mach-imx/mx8m/Makefile create mode 100644 arch/arm/mach-imx/mx8m/clock.c create mode 100644 arch/arm/mach-imx/mx8m/clock_slice.c diff --git a/arch/arm/include/asm/arch-mx8m/clock.h b/arch/arm/include/asm/arch-mx8m/clock.h new file mode 100644 index 0000000000..555512b453 --- /dev/null +++ b/arch/arm/include/asm/arch-mx8m/clock.h @@ -0,0 +1,657 @@ +/* + * Copyright 2017 NXP + * + * Peng Fan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_IMX8M_CLOCK_H +#define _ASM_ARCH_IMX8M_CLOCK_H + +#include + +enum pll_clocks { + ANATOP_ARM_PLL, + ANATOP_GPU_PLL, + ANATOP_SYSTEM_PLL1, + ANATOP_SYSTEM_PLL2, + ANATOP_SYSTEM_PLL3, + ANATOP_AUDIO_PLL1, + ANATOP_AUDIO_PLL2, + ANATOP_VIDEO_PLL1, + ANATOP_VIDEO_PLL2, + ANATOP_DRAM_PLL, +}; + +enum clk_slice_type { + CORE_CLOCK_SLICE, + BUS_CLOCK_SLICE, + IP_CLOCK_SLICE, + AHB_CLOCK_SLICE, + IPG_CLOCK_SLICE, + CORE_SEL_CLOCK_SLICE, + DRAM_SEL_CLOCK_SLICE, +}; + +enum clk_root_index { + MXC_ARM_CLK = 0, + ARM_A53_CLK_ROOT = 0, + ARM_M4_CLK_ROOT = 1, + VPU_A53_CLK_ROOT = 2, + GPU_CORE_CLK_ROOT = 3, + GPU_SHADER_CLK_ROOT = 4, + MAIN_AXI_CLK_ROOT = 16, + ENET_AXI_CLK_ROOT = 17, + NAND_USDHC_BUS_CLK_ROOT = 18, + VPU_BUS_CLK_ROOT = 19, + DISPLAY_AXI_CLK_ROOT = 20, + DISPLAY_APB_CLK_ROOT = 21, + DISPLAY_RTRM_CLK_ROOT = 22, + USB_BUS_CLK_ROOT = 23, + GPU_AXI_CLK_ROOT = 24, + GPU_AHB_CLK_ROOT = 25, + NOC_CLK_ROOT = 26, + NOC_APB_CLK_ROOT = 27, + AHB_CLK_ROOT = 32, + IPG_CLK_ROOT = 33, + MXC_IPG_CLK = 33, + AUDIO_AHB_CLK_ROOT = 34, + MIPI_DSI_ESC_RX_CLK_ROOT = 36, + DRAM_SEL_CFG = 48, + CORE_SEL_CFG = 49, + DRAM_ALT_CLK_ROOT = 64, + DRAM_APB_CLK_ROOT = 65, + VPU_G1_CLK_ROOT = 66, + VPU_G2_CLK_ROOT = 67, + DISPLAY_DTRC_CLK_ROOT = 68, + DISPLAY_DC8000_CLK_ROOT = 69, + PCIE1_CTRL_CLK_ROOT = 70, + PCIE1_PHY_CLK_ROOT = 71, + PCIE1_AUX_CLK_ROOT = 72, + DC_PIXEL_CLK_ROOT = 73, + LCDIF_PIXEL_CLK_ROOT = 74, + SAI1_CLK_ROOT = 75, + SAI2_CLK_ROOT = 76, + SAI3_CLK_ROOT = 77, + SAI4_CLK_ROOT = 78, + SAI5_CLK_ROOT = 79, + SAI6_CLK_ROOT = 80, + SPDIF1_CLK_ROOT = 81, + SPDIF2_CLK_ROOT = 82, + ENET_REF_CLK_ROOT = 83, + ENET_TIMER_CLK_ROOT = 84, + ENET_PHY_REF_CLK_ROOT = 85, + NAND_CLK_ROOT = 86, + QSPI_CLK_ROOT = 87, + MXC_ESDHC_CLK = 88, + USDHC1_CLK_ROOT = 88, + MXC_ESDHC2_CLK = 89, + USDHC2_CLK_ROOT = 89, + I2C1_CLK_ROOT = 90, + MXC_I2C_CLK = 90, + I2C2_CLK_ROOT = 91, + I2C3_CLK_ROOT = 92, + I2C4_CLK_ROOT = 93, + UART1_CLK_ROOT = 94, + UART2_CLK_ROOT = 95, + UART3_CLK_ROOT = 96, + UART4_CLK_ROOT = 97, + USB_CORE_REF_CLK_ROOT = 98, + USB_PHY_REF_CLK_ROOT = 99, + GIC_CLK_ROOT = 100, + ECSPI1_CLK_ROOT = 101, + ECSPI2_CLK_ROOT = 102, + PWM1_CLK_ROOT = 103, + PWM2_CLK_ROOT = 104, + PWM3_CLK_ROOT = 105, + PWM4_CLK_ROOT = 106, + GPT1_CLK_ROOT = 107, + GPT2_CLK_ROOT = 108, + GPT3_CLK_ROOT = 109, + GPT4_CLK_ROOT = 110, + GPT5_CLK_ROOT = 111, + GPT6_CLK_ROOT = 112, + TRACE_CLK_ROOT = 113, + WDOG_CLK_ROOT = 114, + WRCLK_CLK_ROOT = 115, + IPP_DO_CLKO1 = 116, + IPP_DO_CLKO2 = 117, + MIPI_DSI_CORE_CLK_ROOT = 118, + MIPI_DSI_PHY_REF_CLK_ROOT = 119, + MIPI_DSI_DBI_CLK_ROOT = 120, + OLD_MIPI_DSI_ESC_CLK_ROOT = 121, + MIPI_CSI1_CORE_CLK_ROOT = 122, + MIPI_CSI1_PHY_REF_CLK_ROOT = 123, + MIPI_CSI1_ESC_CLK_ROOT = 124, + MIPI_CSI2_CORE_CLK_ROOT = 125, + MIPI_CSI2_PHY_REF_CLK_ROOT = 126, + MIPI_CSI2_ESC_CLK_ROOT = 127, + PCIE2_CTRL_CLK_ROOT = 128, + PCIE2_PHY_CLK_ROOT = 129, + PCIE2_AUX_CLK_ROOT = 130, + ECSPI3_CLK_ROOT = 131, + OLD_MIPI_DSI_ESC_RX_ROOT = 132, + DISPLAY_HDMI_CLK_ROOT = 133, + CLK_ROOT_MAX, +}; + +enum clk_root_src { + OSC_25M_CLK, + ARM_PLL_CLK, + DRAM_PLL1_CLK, + VIDEO_PLL2_CLK, + VPU_PLL_CLK, + GPU_PLL_CLK, + SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_266M_CLK, + SYSTEM_PLL1_200M_CLK, + SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_133M_CLK, + SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL2_500M_CLK, + SYSTEM_PLL2_333M_CLK, + SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_166M_CLK, + SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, + AUDIO_PLL1_CLK, + AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, + OSC_32K_CLK, + EXT_CLK_1, + EXT_CLK_2, + EXT_CLK_3, + EXT_CLK_4, + OSC_27M_CLK, +}; + +/* CCGR index */ +enum clk_ccgr_index { + CCGR_DVFS = 0, + CCGR_ANAMIX = 1, + CCGR_CPU = 2, + CCGR_CSU = 4, + CCGR_DRAM1 = 5, + CCGR_DRAM2_OBSOLETE = 6, + CCGR_ECSPI1 = 7, + CCGR_ECSPI2 = 8, + CCGR_ECSPI3 = 9, + CCGR_ENET1 = 10, + CCGR_GPIO1 = 11, + CCGR_GPIO2 = 12, + CCGR_GPIO3 = 13, + CCGR_GPIO4 = 14, + CCGR_GPIO5 = 15, + CCGR_GPT1 = 16, + CCGR_GPT2 = 17, + CCGR_GPT3 = 18, + CCGR_GPT4 = 19, + CCGR_GPT5 = 20, + CCGR_GPT6 = 21, + CCGR_HS = 22, + CCGR_I2C1 = 23, + CCGR_I2C2 = 24, + CCGR_I2C3 = 25, + CCGR_I2C4 = 26, + CCGR_IOMUX = 27, + CCGR_IOMUX1 = 28, + CCGR_IOMUX2 = 29, + CCGR_IOMUX3 = 30, + CCGR_IOMUX4 = 31, + CCGR_M4 = 32, + CCGR_MU = 33, + CCGR_OCOTP = 34, + CCGR_OCRAM = 35, + CCGR_OCRAM_S = 36, + CCGR_PCIE = 37, + CCGR_PERFMON1 = 38, + CCGR_PERFMON2 = 39, + CCGR_PWM1 = 40, + CCGR_PWM2 = 41, + CCGR_PWM3 = 42, + CCGR_PWM4 = 43, + CCGR_QOS = 44, + CCGR_DISMIX = 45, + CCGR_MEGAMIX = 46, + CCGR_QSPI = 47, + CCGR_RAWNAND = 48, + CCGR_RDC = 49, + CCGR_ROM = 50, + CCGR_SAI1 = 51, + CCGR_SAI2 = 52, + CCGR_SAI3 = 53, + CCGR_SAI4 = 54, + CCGR_SAI5 = 55, + CCGR_SAI6 = 56, + CCGR_SCTR = 57, + CCGR_SDMA1 = 58, + CCGR_SDMA2 = 59, + CCGR_SEC_DEBUG = 60, + CCGR_SEMA1 = 61, + CCGR_SEMA2 = 62, + CCGR_SIM_DISPLAY = 63, + CCGR_SIM_ENET = 64, + CCGR_SIM_M = 65, + CCGR_SIM_MAIN = 66, + CCGR_SIM_S = 67, + CCGR_SIM_WAKEUP = 68, + CCGR_SIM_USB = 69, + CCGR_SIM_VPU = 70, + CCGR_SNVS = 71, + CCGR_TRACE = 72, + CCGR_UART1 = 73, + CCGR_UART2 = 74, + CCGR_UART3 = 75, + CCGR_UART4 = 76, + CCGR_USB_CTRL1 = 77, + CCGR_USB_CTRL2 = 78, + CCGR_USB_PHY1 = 79, + CCGR_USB_PHY2 = 80, + CCGR_USDHC1 = 81, + CCGR_USDHC2 = 82, + CCGR_WDOG1 = 83, + CCGR_WDOG2 = 84, + CCGR_WDOG3 = 85, + CCGR_VA53 = 86, + CCGR_GPU = 87, + CCGR_HEVC = 88, + CCGR_AVC = 89, + CCGR_VP9 = 90, + CCGR_HEVC_INTER = 91, + CCGR_GIC = 92, + CCGR_DISPLAY = 93, + CCGR_HDMI = 94, + CCGR_HDMI_PHY = 95, + CCGR_XTAL = 96, + CCGR_PLL = 97, + CCGR_TSENSOR = 98, + CCGR_VPU_DEC = 99, + CCGR_PCIE2 = 100, + CCGR_MIPI_CSI1 = 101, + CCGR_MIPI_CSI2 = 102, + CCGR_MAX, +}; + +/* src index */ +enum clk_src_index { + CLK_SRC_CKIL_SYNC_REQ = 0, + CLK_SRC_ARM_PLL_EN = 1, + CLK_SRC_GPU_PLL_EN = 2, + CLK_SRC_VPU_PLL_EN = 3, + CLK_SRC_DRAM_PLL_EN = 4, + CLK_SRC_SYSTEM_PLL1_EN = 5, + CLK_SRC_SYSTEM_PLL2_EN = 6, + CLK_SRC_SYSTEM_PLL3_EN = 7, + CLK_SRC_AUDIO_PLL1_EN = 8, + CLK_SRC_AUDIO_PLL2_EN = 9, + CLK_SRC_VIDEO_PLL1_EN = 10, + CLK_SRC_VIDEO_PLL2_EN = 11, + CLK_SRC_ARM_PLL = 12, + CLK_SRC_GPU_PLL = 13, + CLK_SRC_VPU_PLL = 14, + CLK_SRC_DRAM_PLL = 15, + CLK_SRC_SYSTEM_PLL1_800M = 16, + CLK_SRC_SYSTEM_PLL1_400M = 17, + CLK_SRC_SYSTEM_PLL1_266M = 18, + CLK_SRC_SYSTEM_PLL1_200M = 19, + CLK_SRC_SYSTEM_PLL1_160M = 20, + CLK_SRC_SYSTEM_PLL1_133M = 21, + CLK_SRC_SYSTEM_PLL1_100M = 22, + CLK_SRC_SYSTEM_PLL1_80M = 23, + CLK_SRC_SYSTEM_PLL1_40M = 24, + CLK_SRC_SYSTEM_PLL2_1000M = 25, + CLK_SRC_SYSTEM_PLL2_500M = 26, + CLK_SRC_SYSTEM_PLL2_333M = 27, + CLK_SRC_SYSTEM_PLL2_250M = 28, + CLK_SRC_SYSTEM_PLL2_200M = 29, + CLK_SRC_SYSTEM_PLL2_166M = 30, + CLK_SRC_SYSTEM_PLL2_125M = 31, + CLK_SRC_SYSTEM_PLL2_100M = 32, + CLK_SRC_SYSTEM_PLL2_50M = 33, + CLK_SRC_SYSTEM_PLL3 = 34, + CLK_SRC_AUDIO_PLL1 = 35, + CLK_SRC_AUDIO_PLL2 = 36, + CLK_SRC_VIDEO_PLL1 = 37, + CLK_SRC_VIDEO_PLL2 = 38, + CLK_SRC_OSC_25M = 39, + CLK_SRC_OSC_27M = 40, +}; + +enum root_pre_div { + CLK_ROOT_PRE_DIV1 = 0, + CLK_ROOT_PRE_DIV2, + CLK_ROOT_PRE_DIV3, + CLK_ROOT_PRE_DIV4, + CLK_ROOT_PRE_DIV5, + CLK_ROOT_PRE_DIV6, + CLK_ROOT_PRE_DIV7, + CLK_ROOT_PRE_DIV8, +}; + +enum root_post_div { + CLK_ROOT_POST_DIV1 = 0, + CLK_ROOT_POST_DIV2, + CLK_ROOT_POST_DIV3, + CLK_ROOT_POST_DIV4, + CLK_ROOT_POST_DIV5, + CLK_ROOT_POST_DIV6, + CLK_ROOT_POST_DIV7, + CLK_ROOT_POST_DIV8, + CLK_ROOT_POST_DIV9, + CLK_ROOT_POST_DIV10, + CLK_ROOT_POST_DIV11, + CLK_ROOT_POST_DIV12, + CLK_ROOT_POST_DIV13, + CLK_ROOT_POST_DIV14, + CLK_ROOT_POST_DIV15, + CLK_ROOT_POST_DIV16, + CLK_ROOT_POST_DIV17, + CLK_ROOT_POST_DIV18, + CLK_ROOT_POST_DIV19, + CLK_ROOT_POST_DIV20, + CLK_ROOT_POST_DIV21, + CLK_ROOT_POST_DIV22, + CLK_ROOT_POST_DIV23, + CLK_ROOT_POST_DIV24, + CLK_ROOT_POST_DIV25, + CLK_ROOT_POST_DIV26, + CLK_ROOT_POST_DIV27, + CLK_ROOT_POST_DIV28, + CLK_ROOT_POST_DIV29, + CLK_ROOT_POST_DIV30, + CLK_ROOT_POST_DIV31, + CLK_ROOT_POST_DIV32, + CLK_ROOT_POST_DIV33, + CLK_ROOT_POST_DIV34, + CLK_ROOT_POST_DIV35, + CLK_ROOT_POST_DIV36, + CLK_ROOT_POST_DIV37, + CLK_ROOT_POST_DIV38, + CLK_ROOT_POST_DIV39, + CLK_ROOT_POST_DIV40, + CLK_ROOT_POST_DIV41, + CLK_ROOT_POST_DIV42, + CLK_ROOT_POST_DIV43, + CLK_ROOT_POST_DIV44, + CLK_ROOT_POST_DIV45, + CLK_ROOT_POST_DIV46, + CLK_ROOT_POST_DIV47, + CLK_ROOT_POST_DIV48, + CLK_ROOT_POST_DIV49, + CLK_ROOT_POST_DIV50, + CLK_ROOT_POST_DIV51, + CLK_ROOT_POST_DIV52, + CLK_ROOT_POST_DIV53, + CLK_ROOT_POST_DIV54, + CLK_ROOT_POST_DIV55, + CLK_ROOT_POST_DIV56, + CLK_ROOT_POST_DIV57, + CLK_ROOT_POST_DIV58, + CLK_ROOT_POST_DIV59, + CLK_ROOT_POST_DIV60, + CLK_ROOT_POST_DIV61, + CLK_ROOT_POST_DIV62, + CLK_ROOT_POST_DIV63, + CLK_ROOT_POST_DIV64, +}; + +struct clk_root_map { + enum clk_root_index entry; + enum clk_slice_type slice_type; + u32 slice_index; + u8 src_mux[8]; +}; + +struct ccm_ccgr { + u32 ccgr; + u32 ccgr_set; + u32 ccgr_clr; + u32 ccgr_tog; +}; + +struct ccm_root { + u32 target_root; + u32 target_root_set; + u32 target_root_clr; + u32 target_root_tog; + u32 misc; + u32 misc_set; + u32 misc_clr; + u32 misc_tog; + u32 nm_post; + u32 nm_post_root_set; + u32 nm_post_root_clr; + u32 nm_post_root_tog; + u32 nm_pre; + u32 nm_pre_root_set; + u32 nm_pre_root_clr; + u32 nm_pre_root_tog; + u32 db_post; + u32 db_post_root_set; + u32 db_post_root_clr; + u32 db_post_root_tog; + u32 db_pre; + u32 db_pre_root_set; + u32 db_pre_root_clr; + u32 db_pre_root_tog; + u32 reserved[4]; + u32 access_ctrl; + u32 access_ctrl_root_set; + u32 access_ctrl_root_clr; + u32 access_ctrl_root_tog; +}; + +struct ccm_reg { + u32 reserved_0[4096]; + struct ccm_ccgr ccgr_array[192]; + u32 reserved_1[3328]; + struct ccm_root core_root[5]; + u32 reserved_2[352]; + struct ccm_root bus_root[12]; + u32 reserved_3[128]; + struct ccm_root ahb_ipg_root[4]; + u32 reserved_4[384]; + struct ccm_root dram_sel; + struct ccm_root core_sel; + u32 reserved_5[448]; + struct ccm_root ip_root[78]; +}; + +#define CCGR_CLK_ON_MASK 0x03 +#define CLK_SRC_ON_MASK 0x03 + +#define CLK_ROOT_ON BIT(28) +#define CLK_ROOT_OFF (0 << 28) +#define CLK_ROOT_ENABLE_MASK BIT(28) +#define CLK_ROOT_ENABLE_SHIFT 28 +#define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24) + +/* For SEL, only use 1 bit */ +#define CLK_ROOT_SRC_MUX_MASK 0x07000000 +#define CLK_ROOT_SRC_MUX_SHIFT 24 +#define CLK_ROOT_SRC_0 0x00000000 +#define CLK_ROOT_SRC_1 0x01000000 +#define CLK_ROOT_SRC_2 0x02000000 +#define CLK_ROOT_SRC_3 0x03000000 +#define CLK_ROOT_SRC_4 0x04000000 +#define CLK_ROOT_SRC_5 0x05000000 +#define CLK_ROOT_SRC_6 0x06000000 +#define CLK_ROOT_SRC_7 0x07000000 + +#define CLK_ROOT_PRE_DIV_MASK (0x00070000) +#define CLK_ROOT_PRE_DIV_SHIFT 16 +#define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000) + +#define CLK_ROOT_AUDO_SLOW_EN 0x1000 + +#define CLK_ROOT_AUDO_DIV_MASK 0x700 +#define CLK_ROOT_AUDO_DIV_SHIFT 0x8 +#define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700) + +/* For CORE: mask is 0x7; For IPG: mask is 0x3 */ +#define CLK_ROOT_POST_DIV_MASK 0x3f +#define CLK_ROOT_CORE_POST_DIV_MASK 0x7 +#define CLK_ROOT_IPG_POST_DIV_MASK 0x3 +#define CLK_ROOT_POST_DIV_SHIFT 0 +#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f) + +/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/ +#define FRAC_PLL_LOCK_MASK BIT(31) +#define FRAC_PLL_CLKE_MASK BIT(21) +#define FRAC_PLL_PD_MASK BIT(19) +#define FRAC_PLL_REFCLK_SEL_MASK BIT(16) +#define FRAC_PLL_LOCK_SEL_MASK BIT(15) +#define FRAC_PLL_BYPASS_MASK BIT(14) +#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13) +#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12) +#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11) +#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5)) +#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5) +#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5 +#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f +#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f) + +#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16) +#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16) +#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) +#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16) + +#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7) +#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7 +#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f +#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f) + +/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */ +#define SSCG_PLL_LOCK_MASK BIT(31) +#define SSCG_PLL_CLKE_MASK BIT(25) +#define SSCG_PLL_DIV2_CLKE_MASK BIT(23) +#define SSCG_PLL_DIV3_CLKE_MASK BIT(21) +#define SSCG_PLL_DIV4_CLKE_MASK BIT(19) +#define SSCG_PLL_DIV5_CLKE_MASK BIT(17) +#define SSCG_PLL_DIV6_CLKE_MASK BIT(15) +#define SSCG_PLL_DIV8_CLKE_MASK BIT(13) +#define SSCG_PLL_DIV10_CLKE_MASK BIT(11) +#define SSCG_PLL_DIV20_CLKE_MASK BIT(9) +#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9) +#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9) +#define SSCG_PLL_PLL3_CLKE_MASK BIT(9) +#define SSCG_PLL_PD_MASK BIT(7) +#define SSCG_PLL_BYPASS1_MASK BIT(5) +#define SSCG_PLL_BYPASS2_MASK BIT(4) +#define SSCG_PLL_LOCK_SEL_MASK BIT(3) +#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2) +#define SSCG_PLL_REFCLK_SEL_MASK 0x3 +#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16) +#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16) +#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) +#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16) + +#define SSCG_PLL_SSDS_MASK BIT(8) +#define SSCG_PLL_SSMD_MASK (0x7 << 5) +#define SSCG_PLL_SSMF_MASK (0xf << 1) +#define SSCG_PLL_SSE_MASK 0x1 + +#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) +#define SSCG_PLL_REF_DIVR1_SHIFT 25 +#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK) +#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19) +#define SSCG_PLL_REF_DIVR2_SHIFT 19 +#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK) +#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13) +#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13 +#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \ + SSCG_PLL_FEEDBACK_DIV_F1_MASK) +#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7) +#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7 +#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \ + SSCG_PLL_FEEDBACK_DIV_F2_MASK) +#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1) +#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1 +#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \ + SSCG_PLL_OUTPUT_DIV_VAL_MASK) +#define SSCG_PLL_FILTER_RANGE_MASK 0x1 + +#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16) +#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8) +#define HW_DIGPROG_MINOR_MASK 0xff + +#define HW_OSC_27M_CLKE_MASK BIT(4) +#define HW_OSC_25M_CLKE_MASK BIT(2) +#define HW_OSC_32K_SEL_MASK 0x1 +#define HW_OSC_32K_SEL_RTC 0x1 +#define HW_OSC_32K_SEL_25M_DIV800 0x0 + +#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20) +#define HW_FRAC_ARM_PLL_DIV_SHIFT 20 +#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16) +#define HW_FRAC_VPU_PLL_DIV_SHIFT 16 +#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12) +#define HW_FRAC_GPU_PLL_DIV_SHIFT 12 +#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10) +#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10 +#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4) +#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4 +#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7 +#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0 + +#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16) +#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16 +#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14) +#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14 +#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8) +#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8 +#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4) +#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4 +#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7 +#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0 + +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000 +#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000 +#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000 + +enum enet_freq { + ENET_25MHZ = 0, + ENET_50MHZ, + ENET_125MHZ, +}; + +enum frac_pll_out_val { + FRAC_PLL_OUT_1000M, + FRAC_PLL_OUT_1600M, +}; + +u32 imx_get_fecclk(void); +u32 imx_get_uartclk(void); +int clock_init(void); +void init_clk_usdhc(u32 index); +void init_uart_clk(u32 index); +void init_wdog_clk(void); +unsigned int mxc_get_clock(enum clk_root_index clk); +int clock_enable(enum clk_ccgr_index index, bool enable); +int clock_root_enabled(enum clk_root_index clock_id); +int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div, + enum root_post_div post_div, enum clk_root_src clock_src); +int clock_set_target_val(enum clk_root_index clock_id, u32 val); +int clock_get_target_val(enum clk_root_index clock_id, u32 *val); +int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div); +int clock_get_postdiv(enum clk_root_index clock_id, + enum root_post_div *post_div); +int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src); +void mxs_set_lcdclk(u32 base_addr, u32 freq); +int set_clk_qspi(void); +void enable_ocotp_clk(unsigned char enable); +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); +int set_clk_enet(enum enet_freq type); +#endif diff --git a/arch/arm/mach-imx/mx8m/Makefile b/arch/arm/mach-imx/mx8m/Makefile new file mode 100644 index 0000000000..05f38842f0 --- /dev/null +++ b/arch/arm/mach-imx/mx8m/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += clock.o clock_slice.o diff --git a/arch/arm/mach-imx/mx8m/clock.c b/arch/arm/mach-imx/mx8m/clock.c new file mode 100644 index 0000000000..c56ba99d5c --- /dev/null +++ b/arch/arm/mach-imx/mx8m/clock.c @@ -0,0 +1,795 @@ +/* + * Copyright 2017 NXP + * + * Peng Fan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; + +static u32 decode_frac_pll(enum clk_root_src frac_pll) +{ + u32 pll_cfg0, pll_cfg1, pllout; + u32 pll_refclk_sel, pll_refclk; + u32 divr_val, divq_val, divf_val, divff, divfi; + u32 pllout_div_shift, pllout_div_mask, pllout_div; + + switch (frac_pll) { + case ARM_PLL_CLK: + pll_cfg0 = readl(&ana_pll->arm_pll_cfg0); + pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); + pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT; + pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK; + break; + default: + printf("Frac PLL %d not supporte\n", frac_pll); + return 0; + } + + pllout_div = readl(&ana_pll->frac_pllout_div_cfg); + pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift; + + /* Power down */ + if (pll_cfg0 & FRAC_PLL_PD_MASK) + return 0; + + /* output not enabled */ + if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0) + return 0; + + pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK; + + if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M) + pll_refclk = 25000000u; + else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M) + pll_refclk = 27000000u; + else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M) + pll_refclk = 27000000u; + else + pll_refclk = 0; + + if (pll_cfg0 & FRAC_PLL_BYPASS_MASK) + return pll_refclk; + + divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >> + FRAC_PLL_REFCLK_DIV_VAL_SHIFT; + divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK; + + divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >> + FRAC_PLL_FRAC_DIV_CTL_SHIFT; + divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; + + divf_val = 1 + divfi + divff / (1 << 24); + + pllout = pll_refclk / (divr_val + 1) * 8 * divf_val / + ((divq_val + 1) * 2); + + return pllout / (pllout_div + 1); +} + +static u32 decode_sscg_pll(enum clk_root_src sscg_pll) +{ + u32 pll_cfg0, pll_cfg1, pll_cfg2; + u32 pll_refclk_sel, pll_refclk; + u32 divr1, divr2, divf1, divf2, divq, div; + u32 sse; + u32 pll_clke; + u32 pllout_div_shift, pllout_div_mask, pllout_div; + u32 pllout; + + switch (sscg_pll) { + case SYSTEM_PLL1_800M_CLK: + case SYSTEM_PLL1_400M_CLK: + case SYSTEM_PLL1_266M_CLK: + case SYSTEM_PLL1_200M_CLK: + case SYSTEM_PLL1_160M_CLK: + case SYSTEM_PLL1_133M_CLK: + case SYSTEM_PLL1_100M_CLK: + case SYSTEM_PLL1_80M_CLK: + case SYSTEM_PLL1_40M_CLK: + pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0); + pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); + pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2); + pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT; + pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK; + break; + case SYSTEM_PLL2_1000M_CLK: + case SYSTEM_PLL2_500M_CLK: + case SYSTEM_PLL2_333M_CLK: + case SYSTEM_PLL2_250M_CLK: + case SYSTEM_PLL2_200M_CLK: + case SYSTEM_PLL2_166M_CLK: + case SYSTEM_PLL2_125M_CLK: + case SYSTEM_PLL2_100M_CLK: + case SYSTEM_PLL2_50M_CLK: + pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0); + pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); + pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2); + pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT; + pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK; + break; + case SYSTEM_PLL3_CLK: + pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0); + pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); + pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2); + pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT; + pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK; + break; + case DRAM_PLL1_CLK: + pll_cfg0 = readl(&ana_pll->dram_pll_cfg0); + pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); + pll_cfg2 = readl(&ana_pll->dram_pll_cfg2); + pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT; + pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK; + break; + default: + printf("sscg pll %d not supporte\n", sscg_pll); + return 0; + } + + switch (sscg_pll) { + case DRAM_PLL1_CLK: + pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK; + div = 1; + break; + case SYSTEM_PLL3_CLK: + pll_clke = SSCG_PLL_PLL3_CLKE_MASK; + div = 1; + break; + case SYSTEM_PLL2_1000M_CLK: + case SYSTEM_PLL1_800M_CLK: + pll_clke = SSCG_PLL_CLKE_MASK; + div = 1; + break; + case SYSTEM_PLL2_500M_CLK: + case SYSTEM_PLL1_400M_CLK: + pll_clke = SSCG_PLL_DIV2_CLKE_MASK; + div = 2; + break; + case SYSTEM_PLL2_333M_CLK: + case SYSTEM_PLL1_266M_CLK: + pll_clke = SSCG_PLL_DIV3_CLKE_MASK; + div = 3; + break; + case SYSTEM_PLL2_250M_CLK: + case SYSTEM_PLL1_200M_CLK: + pll_clke = SSCG_PLL_DIV4_CLKE_MASK; + div = 4; + break; + case SYSTEM_PLL2_200M_CLK: + case SYSTEM_PLL1_160M_CLK: + pll_clke = SSCG_PLL_DIV5_CLKE_MASK; + div = 5; + break; + case SYSTEM_PLL2_166M_CLK: + case SYSTEM_PLL1_133M_CLK: + pll_clke = SSCG_PLL_DIV6_CLKE_MASK; + div = 6; + break; + case SYSTEM_PLL2_125M_CLK: + case SYSTEM_PLL1_100M_CLK: + pll_clke = SSCG_PLL_DIV8_CLKE_MASK; + div = 8; + break; + case SYSTEM_PLL2_100M_CLK: + case SYSTEM_PLL1_80M_CLK: + pll_clke = SSCG_PLL_DIV10_CLKE_MASK; + div = 10; + break; + case SYSTEM_PLL2_50M_CLK: + case SYSTEM_PLL1_40M_CLK: + pll_clke = SSCG_PLL_DIV20_CLKE_MASK; + div = 20; + break; + default: + printf("sscg pll %d not supporte\n", sscg_pll); + return 0; + } + + /* Power down */ + if (pll_cfg0 & SSCG_PLL_PD_MASK) + return 0; + + /* output not enabled */ + if ((pll_cfg0 & pll_clke) == 0) + return 0; + + pllout_div = readl(&ana_pll->sscg_pllout_div_cfg); + pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift; + + pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK; + + if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M) + pll_refclk = 25000000u; + else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M) + pll_refclk = 27000000u; + else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M) + pll_refclk = 27000000u; + else + pll_refclk = 0; + + /* We assume bypass1/2 are the same value */ + if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) || + (pll_cfg0 & SSCG_PLL_BYPASS2_MASK)) + return pll_refclk; + + divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >> + SSCG_PLL_REF_DIVR1_SHIFT; + divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >> + SSCG_PLL_REF_DIVR2_SHIFT; + divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >> + SSCG_PLL_FEEDBACK_DIV_F1_SHIFT; + divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >> + SSCG_PLL_FEEDBACK_DIV_F2_SHIFT; + divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >> + SSCG_PLL_OUTPUT_DIV_VAL_SHIFT; + sse = pll_cfg1 & SSCG_PLL_SSE_MASK; + + if (sse) + sse = 8; + else + sse = 2; + + pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) / + (divr2 + 1) * (divf2 + 1) / (divq + 1); + + return pllout / (pllout_div + 1) / div; +} + +static u32 get_root_src_clk(enum clk_root_src root_src) +{ + switch (root_src) { + case OSC_25M_CLK: + return 25000000; + case OSC_27M_CLK: + return 25000000; + case OSC_32K_CLK: + return 32000; + case ARM_PLL_CLK: + return decode_frac_pll(root_src); + case SYSTEM_PLL1_800M_CLK: + case SYSTEM_PLL1_400M_CLK: + case SYSTEM_PLL1_266M_CLK: + case SYSTEM_PLL1_200M_CLK: + case SYSTEM_PLL1_160M_CLK: + case SYSTEM_PLL1_133M_CLK: + case SYSTEM_PLL1_100M_CLK: + case SYSTEM_PLL1_80M_CLK: + case SYSTEM_PLL1_40M_CLK: + case SYSTEM_PLL2_1000M_CLK: + case SYSTEM_PLL2_500M_CLK: + case SYSTEM_PLL2_333M_CLK: + case SYSTEM_PLL2_250M_CLK: + case SYSTEM_PLL2_200M_CLK: + case SYSTEM_PLL2_166M_CLK: + case SYSTEM_PLL2_125M_CLK: + case SYSTEM_PLL2_100M_CLK: + case SYSTEM_PLL2_50M_CLK: + case SYSTEM_PLL3_CLK: + return decode_sscg_pll(root_src); + default: + return 0; + } + + return 0; +} + +static u32 get_root_clk(enum clk_root_index clock_id) +{ + enum clk_root_src root_src; + u32 post_podf, pre_podf, root_src_clk; + + if (clock_root_enabled(clock_id) <= 0) + return 0; + + if (clock_get_prediv(clock_id, &pre_podf) < 0) + return 0; + + if (clock_get_postdiv(clock_id, &post_podf) < 0) + return 0; + + if (clock_get_src(clock_id, &root_src) < 0) + return 0; + + root_src_clk = get_root_src_clk(root_src); + + return root_src_clk / (post_podf + 1) / (pre_podf + 1); +} + +#ifdef CONFIG_MXC_OCOTP +void enable_ocotp_clk(unsigned char enable) +{ + clock_enable(CCGR_OCOTP, !!enable); +} +#endif + +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num) +{ + /* 0 - 3 is valid i2c num */ + if (i2c_num > 3) + return -EINVAL; + + clock_enable(CCGR_I2C1 + i2c_num, !!enable); + + return 0; +} + +unsigned int mxc_get_clock(enum clk_root_index clk) +{ + u32 val; + + if (clk >= CLK_ROOT_MAX) + return 0; + + if (clk == MXC_ARM_CLK) + return get_root_clk(ARM_A53_CLK_ROOT); + + if (clk == MXC_IPG_CLK) { + clock_get_target_val(IPG_CLK_ROOT, &val); + val = val & 0x3; + return get_root_clk(AHB_CLK_ROOT) / (val + 1); + } + + return get_root_clk(clk); +} + +u32 imx_get_uartclk(void) +{ + return mxc_get_clock(UART1_CLK_ROOT); +} + +void mxs_set_lcdclk(u32 base_addr, u32 freq) +{ + /* + * LCDIF_PIXEL_CLK: select 800MHz root clock, + * select pre divider 8, output is 100 MHz + */ + clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(4) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8)); +} + +void init_wdog_clk(void) +{ + clock_enable(CCGR_WDOG1, 0); + clock_enable(CCGR_WDOG2, 0); + clock_enable(CCGR_WDOG3, 0); + clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0)); + clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0)); + clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0)); + clock_enable(CCGR_WDOG1, 1); + clock_enable(CCGR_WDOG2, 1); + clock_enable(CCGR_WDOG3, 1); +} + +void init_usb_clk(void) +{ + if (!is_usb_boot()) { + clock_enable(CCGR_USB_CTRL1, 0); + clock_enable(CCGR_USB_CTRL2, 0); + clock_enable(CCGR_USB_PHY1, 0); + clock_enable(CCGR_USB_PHY2, 0); + /* 500MHz */ + clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); + /* 100MHz */ + clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); + /* 100MHz */ + clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); + clock_enable(CCGR_USB_CTRL1, 1); + clock_enable(CCGR_USB_CTRL2, 1); + clock_enable(CCGR_USB_PHY1, 1); + clock_enable(CCGR_USB_PHY2, 1); + } +} + +void init_uart_clk(u32 index) +{ + /* Set uart clock root 25M OSC */ + switch (index) { + case 0: + clock_enable(CCGR_UART1, 0); + clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0)); + clock_enable(CCGR_UART1, 1); + return; + case 1: + clock_enable(CCGR_UART2, 0); + clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0)); + clock_enable(CCGR_UART2, 1); + return; + case 2: + clock_enable(CCGR_UART3, 0); + clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0)); + clock_enable(CCGR_UART3, 1); + return; + case 3: + clock_enable(CCGR_UART4, 0); + clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0)); + clock_enable(CCGR_UART4, 1); + return; + default: + printf("Invalid uart index\n"); + return; + } +} + +void init_clk_usdhc(u32 index) +{ + /* + * set usdhc clock root + * sys pll1 400M + */ + switch (index) { + case 0: + clock_enable(CCGR_USDHC1, 0); + clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); + clock_enable(CCGR_USDHC1, 1); + return; + case 1: + clock_enable(CCGR_USDHC2, 0); + clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); + clock_enable(CCGR_USDHC2, 1); + return; + default: + printf("Invalid usdhc index\n"); + return; + } +} + +int set_clk_qspi(void) +{ + /* + * set qspi root + * sys pll1 100M + */ + clock_enable(CCGR_QSPI, 0); + clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(7)); + clock_enable(CCGR_QSPI, 1); + + return 0; +} + +#ifdef CONFIG_FEC_MXC +int set_clk_enet(enum enet_freq type) +{ + u32 target; + u32 enet1_ref; + + switch (type) { + case ENET_125MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; + break; + case ENET_50MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; + break; + case ENET_25MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; + break; + default: + return -EINVAL; + } + + /* disable the clock first */ + clock_enable(CCGR_ENET1, 0); + clock_enable(CCGR_SIM_ENET, 0); + + /* set enet axi clock 266Mhz */ + target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET_AXI_CLK_ROOT, target); + + target = CLK_ROOT_ON | enet1_ref | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET_REF_CLK_ROOT, target); + + target = CLK_ROOT_ON | + ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); + clock_set_target_val(ENET_TIMER_CLK_ROOT, target); + + /* enable clock */ + clock_enable(CCGR_SIM_ENET, 1); + clock_enable(CCGR_ENET1, 1); + + return 0; +} +#endif + +u32 imx_get_fecclk(void) +{ + return get_root_clk(ENET_AXI_CLK_ROOT); +} + +#ifdef CONFIG_SPL_BUILD +void dram_pll_init(void) +{ + struct src *src = (struct src *)SRC_BASE_ADDR; + void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0; + u32 pwdn_mask = 0, pll_clke = 0, bypass1 = 0, bypass2 = 0; + u32 val; + int ret; + + setbits_le32(GPC_BASE_ADDR + 0xEC, BIT(7)); + setbits_le32(GPC_BASE_ADDR + 0xF8, BIT(5)); + + pwdn_mask = SSCG_PLL_PD_MASK; + pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK; + bypass1 = SSCG_PLL_BYPASS1_MASK; + bypass2 = SSCG_PLL_BYPASS2_MASK; + + /* Enable DDR1 and DDR2 domain */ + writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr); + writel(SRC_DDR1_ENABLE_MASK, &src->ddr2_rcr); + + /* Clear power down bit */ + clrbits_le32(pll_control_reg, pwdn_mask); + /* Eanble ARM_PLL/SYS_PLL */ + setbits_le32(pll_control_reg, pll_clke); + + /* Clear bypass */ + clrbits_le32(pll_control_reg, bypass1); + __udelay(100); + clrbits_le32(pll_control_reg, bypass2); + /* Wait lock */ + ret = readl_poll_timeout(pll_control_reg, val, + val & SSCG_PLL_LOCK_MASK, 1); + if (ret) + printf("%s timeout\n", __func__); +} + +int frac_pll_init(u32 pll, enum frac_pll_out_val val) +{ + void __iomem *pll_cfg0, __iomem *pll_cfg1; + u32 val_cfg0, val_cfg1; + int ret; + + switch (pll) { + case ANATOP_ARM_PLL: + pll_cfg0 = &ana_pll->arm_pll_cfg0; + pll_cfg1 = &ana_pll->arm_pll_cfg1; + + if (val == FRAC_PLL_OUT_1000M) + val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49); + else + val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79); + val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M | + FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK | + FRAC_PLL_REFCLK_DIV_VAL(4) | + FRAC_PLL_OUTPUT_DIV_VAL(0); + break; + default: + return -EINVAL; + } + + /* bypass the clock */ + setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK); + /* Set the value */ + writel(val_cfg1, pll_cfg1); + writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0); + val_cfg0 = readl(pll_cfg0); + /* unbypass the clock */ + clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK); + ret = readl_poll_timeout(pll_cfg0, val_cfg0, + val_cfg0 & FRAC_PLL_LOCK_MASK, 1); + if (ret) + printf("%s timeout\n", __func__); + clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK); + + return 0; +} + +int sscg_pll_init(u32 pll) +{ + void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2; + u32 val_cfg0, val_cfg1, val_cfg2, val; + u32 bypass1_mask = 0x20, bypass2_mask = 0x10; + int ret; + + switch (pll) { + case ANATOP_SYSTEM_PLL1: + pll_cfg0 = &ana_pll->sys_pll1_cfg0; + pll_cfg1 = &ana_pll->sys_pll1_cfg1; + pll_cfg2 = &ana_pll->sys_pll1_cfg2; + /* 800MHz */ + val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) | + SSCG_PLL_FEEDBACK_DIV_F2_VAL(3); + val_cfg1 = 0; + val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | + SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK | + SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK | + SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK | + SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK | + SSCG_PLL_REFCLK_SEL_OSC_25M; + break; + case ANATOP_SYSTEM_PLL2: + pll_cfg0 = &ana_pll->sys_pll2_cfg0; + pll_cfg1 = &ana_pll->sys_pll2_cfg1; + pll_cfg2 = &ana_pll->sys_pll2_cfg2; + /* 1000MHz */ + val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) | + SSCG_PLL_FEEDBACK_DIV_F2_VAL(4); + val_cfg1 = 0; + val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | + SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK | + SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK | + SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK | + SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK | + SSCG_PLL_REFCLK_SEL_OSC_25M; + break; + case ANATOP_SYSTEM_PLL3: + pll_cfg0 = &ana_pll->sys_pll3_cfg0; + pll_cfg1 = &ana_pll->sys_pll3_cfg1; + pll_cfg2 = &ana_pll->sys_pll3_cfg2; + /* 800MHz */ + val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) | + SSCG_PLL_FEEDBACK_DIV_F2_VAL(3); + val_cfg1 = 0; + val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK | + SSCG_PLL_REFCLK_SEL_OSC_25M; + break; + default: + return -EINVAL; + } + + /*bypass*/ + setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask); + /* set value */ + writel(val_cfg2, pll_cfg2); + writel(val_cfg1, pll_cfg1); + /*unbypass1 and wait 70us */ + writel(val_cfg0 | bypass2_mask, pll_cfg1); + + __udelay(70); + + /* unbypass2 and wait lock */ + writel(val_cfg0, pll_cfg1); + ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1); + if (ret) + printf("%s timeout\n", __func__); + + return ret; +} + +int clock_init(void) +{ + u32 grade; + + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0)); + + /* + * 8MQ only supports two grades: consumer and industrial. + * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial + */ + grade = get_cpu_temp_grade(NULL, NULL); + if (!grade) { + frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M); + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1)); + } else { + frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M); + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); + } + /* + * According to ANAMIX SPEC + * sys pll1 fixed at 800MHz + * sys pll2 fixed at 1GHz + * Here we only enable the outputs. + */ + setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK | + SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK | + SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK | + SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK | + SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK); + + setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK | + SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK | + SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK | + SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK | + SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK); + + clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); + + init_wdog_clk(); + clock_enable(CCGR_TSENSOR, 1); + + return 0; +} +#endif + +/* + * Dump some clockes. + */ +#ifndef CONFIG_SPL_BUILD +int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + u32 freq; + + freq = decode_frac_pll(ARM_PLL_CLK); + printf("ARM_PLL %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK); + printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK); + printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK); + printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK); + printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK); + printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK); + printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK); + printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK); + printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK); + printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK); + printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK); + printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK); + printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK); + printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK); + printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK); + printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK); + printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK); + printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK); + printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(SYSTEM_PLL3_CLK); + printf("SYS_PLL3 %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(UART1_CLK_ROOT); + printf("UART1 %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(USDHC1_CLK_ROOT); + printf("USDHC1 %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(QSPI_CLK_ROOT); + printf("QSPI %8d MHz\n", freq / 1000000); + return 0; +} + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_mx8m_showclocks, + "display clocks", + "" +); +#endif diff --git a/arch/arm/mach-imx/mx8m/clock_slice.c b/arch/arm/mach-imx/mx8m/clock_slice.c new file mode 100644 index 0000000000..e734498b94 --- /dev/null +++ b/arch/arm/mach-imx/mx8m/clock_slice.c @@ -0,0 +1,742 @@ +/* + * Copyright 2017 NXP + * + * Peng Fan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR; + +static struct clk_root_map root_array[] = { + {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0, + {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK} + }, + {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1, + {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK} + }, + {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2, + {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK} + }, + {GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3, + {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4, + {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0, + {OSC_25M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK} + }, + {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1, + {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK} + }, + {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2, + {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK} + }, + {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3, + {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK} + }, + {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4, + {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, + EXT_CLK_1, EXT_CLK_4} + }, + {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5, + {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, + EXT_CLK_1, EXT_CLK_3} + }, + {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6, + {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + EXT_CLK_2, EXT_CLK_3} + }, + {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7, + {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8, + {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9, + {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10, + {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11, + {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK} + }, + {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0, + {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK} + }, + {IPG_CLK_ROOT, IPG_CLOCK_SLICE, 0, + {} + }, + {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1, + {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK} + }, + {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL1_CLK }, + }, + {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0, + {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK} + }, + {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1, + {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2, + {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK} + }, + {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3, + {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK} + }, + {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4, + {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK} + }, + {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5, + {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK} + }, + {PCIE1_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6, + {OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK} + }, + {PCIE1_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK, + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, + SYSTEM_PLL1_400M_CLK} + }, + {PCIE1_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8, + {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK} + }, + {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9, + {OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4} + }, + {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10, + {OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4} + }, + {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11, + {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2} + }, + {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12, + {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3} + }, + {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13, + {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4} + }, + {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14, + {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2} + }, + {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15, + {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3} + }, + {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16, + {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4} + }, + {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17, + {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3} + }, + {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18, + {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4} + }, + {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19, + {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4} + }, + {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, + VIDEO_PLL_CLK} + }, + {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21, + {OSC_25M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22, + {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK, + SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK} + }, + {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23, + {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK} + }, + {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24, + {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK} + }, + {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25, + {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK} + }, + {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26, + {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27, + {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28, + {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29, + {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30, + {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31, + {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32, + {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33, + {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34, + {OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35, + {OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36, + {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37, + {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38, + {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1} + }, + {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2} + }, + {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3} + }, + {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1} + }, + {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2} + }, + {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3} + }, + {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49, + {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK, + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3} + }, + {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50, + {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK, + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK} + }, + {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51, + {OSC_25M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK} + }, + {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52, + {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, OSC_27M_CLK, + SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK, + SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK} + }, + {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53, + {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK} + }, + {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54, + {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55, + {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56, + {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {OLD_MIPI_DSI_ESC_CLK_ROOT, IP_CLOCK_SLICE, 57, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58, + {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59, + {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61, + {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62, + {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64, + {OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK} + }, + {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK, + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, + EXT_CLK_4, SYSTEM_PLL1_400M_CLK} + }, + {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66, + {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK} + }, + {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67, + {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {OLD_MIPI_DSI_ESC_RX_ROOT, IP_CLOCK_SLICE, 68, + {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}, + }, + {DISPLAY_HDMI_CLK_ROOT, IP_CLOCK_SLICE, 69, + {OSC_25M_CLK, SYSTEM_PLL1_200M_CLK, SYSTEM_PLL2_200M_CLK, + VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4} + }, + {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0, + {DRAM_PLL1_CLK} + }, + {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0, + {DRAM_PLL1_CLK} + }, +}; + +static int select(enum clk_root_index clock_id) +{ + int i, size; + struct clk_root_map *p = root_array; + + size = ARRAY_SIZE(root_array); + + for (i = 0; i < size; i++, p++) { + if (clock_id == p->entry) + return i; + } + + return -EINVAL; +} + +static void __iomem *get_clk_root_target(enum clk_slice_type slice_type, + u32 slice_index) +{ + void __iomem *clk_root_target; + + switch (slice_type) { + case CORE_CLOCK_SLICE: + clk_root_target = + (void __iomem *)&ccm_reg->core_root[slice_index]; + break; + case BUS_CLOCK_SLICE: + clk_root_target = + (void __iomem *)&ccm_reg->bus_root[slice_index]; + break; + case IP_CLOCK_SLICE: + clk_root_target = + (void __iomem *)&ccm_reg->ip_root[slice_index]; + break; + case AHB_CLOCK_SLICE: + clk_root_target = + (void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2]; + break; + case IPG_CLOCK_SLICE: + clk_root_target = + (void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2 + 1]; + break; + case CORE_SEL_CLOCK_SLICE: + clk_root_target = (void __iomem *)&ccm_reg->core_sel; + break; + case DRAM_SEL_CLOCK_SLICE: + clk_root_target = (void __iomem *)&ccm_reg->dram_sel; + break; + default: + return NULL; + } + + return clk_root_target; +} + +int clock_get_target_val(enum clk_root_index clock_id, u32 *val) +{ + int root_entry; + struct clk_root_map *p; + void __iomem *clk_root_target; + + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + root_entry = select(clock_id); + if (root_entry < 0) + return -EINVAL; + + p = &root_array[root_entry]; + clk_root_target = get_clk_root_target(p->slice_type, p->slice_index); + if (!clk_root_target) + return -EINVAL; + + *val = readl(clk_root_target); + + return 0; +} + +int clock_set_target_val(enum clk_root_index clock_id, u32 val) +{ + int root_entry; + struct clk_root_map *p; + void __iomem *clk_root_target; + + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + root_entry = select(clock_id); + if (root_entry < 0) + return -EINVAL; + + p = &root_array[root_entry]; + clk_root_target = get_clk_root_target(p->slice_type, p->slice_index); + if (!clk_root_target) + return -EINVAL; + + writel(val, clk_root_target); + + return 0; +} + +int clock_root_enabled(enum clk_root_index clock_id) +{ + void __iomem *clk_root_target; + u32 slice_index, slice_type; + u32 val; + int root_entry; + + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + root_entry = select(clock_id); + if (root_entry < 0) + return -EINVAL; + + slice_type = root_array[root_entry].slice_type; + slice_index = root_array[root_entry].slice_index; + + if ((slice_type == IPG_CLOCK_SLICE) || + (slice_type == DRAM_SEL_CLOCK_SLICE) || + (slice_type == CORE_SEL_CLOCK_SLICE)) { + /* + * Not supported, from CCM doc + * TODO + */ + return 0; + } + + clk_root_target = get_clk_root_target(slice_type, slice_index); + if (!clk_root_target) + return -EINVAL; + + val = readl(clk_root_target); + + return (val & CLK_ROOT_ON) ? 1 : 0; +} + +/* CCGR CLK gate operation */ +int clock_enable(enum clk_ccgr_index index, bool enable) +{ + void __iomem *ccgr; + + if (index >= CCGR_MAX) + return -EINVAL; + + if (enable) + ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_set; + else + ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_clr; + + writel(CCGR_CLK_ON_MASK, ccgr); + + return 0; +} + +int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div) +{ + u32 val; + int root_entry; + struct clk_root_map *p; + void __iomem *clk_root_target; + + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + root_entry = select(clock_id); + if (root_entry < 0) + return -EINVAL; + + p = &root_array[root_entry]; + + if ((p->slice_type == CORE_CLOCK_SLICE) || + (p->slice_type == IPG_CLOCK_SLICE) || + (p->slice_type == CORE_SEL_CLOCK_SLICE) || + (p->slice_type == DRAM_SEL_CLOCK_SLICE)) { + *pre_div = 0; + return 0; + } + + clk_root_target = get_clk_root_target(p->slice_type, p->slice_index); + if (!clk_root_target) + return -EINVAL; + + val = readl(clk_root_target); + val &= CLK_ROOT_PRE_DIV_MASK; + val >>= CLK_ROOT_PRE_DIV_SHIFT; + + *pre_div = val; + + return 0; +} + +int clock_get_postdiv(enum clk_root_index clock_id, + enum root_post_div *post_div) +{ + u32 val, mask; + int root_entry; + struct clk_root_map *p; + void __iomem *clk_root_target; + + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + root_entry = select(clock_id); + if (root_entry < 0) + return -EINVAL; + + p = &root_array[root_entry]; + + if ((p->slice_type == CORE_SEL_CLOCK_SLICE) || + (p->slice_type == DRAM_SEL_CLOCK_SLICE)) { + *post_div = 0; + return 0; + } + + clk_root_target = get_clk_root_target(p->slice_type, p->slice_index); + if (!clk_root_target) + return -EINVAL; + + if (p->slice_type == IPG_CLOCK_SLICE) + mask = CLK_ROOT_IPG_POST_DIV_MASK; + else if (p->slice_type == CORE_CLOCK_SLICE) + mask = CLK_ROOT_CORE_POST_DIV_MASK; + else + mask = CLK_ROOT_POST_DIV_MASK; + + val = readl(clk_root_target); + val &= mask; + val >>= CLK_ROOT_POST_DIV_SHIFT; + + *post_div = val; + + return 0; +} + +int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src) +{ + u32 val; + int root_entry; + struct clk_root_map *p; + void __iomem *clk_root_target; + + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + root_entry = select(clock_id); + if (root_entry < 0) + return -EINVAL; + + p = &root_array[root_entry]; + + clk_root_target = get_clk_root_target(p->slice_type, p->slice_index); + if (!clk_root_target) + return -EINVAL; + + val = readl(clk_root_target); + val &= CLK_ROOT_SRC_MUX_MASK; + val >>= CLK_ROOT_SRC_MUX_SHIFT; + + *p_clock_src = p->src_mux[val]; + + return 0; +} From patchwork Wed Jan 10 05:20:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857945 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="GsoltN5b"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zGcqv5c13z9s7n for ; Wed, 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SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jan 2018 05:21:16.9191 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b18d9fb-b6d0-4e2d-2809-08d557e9faf5 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR04MB3221 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH V5 06/31] imx: add sip function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add SiP (Silicon Provider) services function to issue SMC call to Arm Trusted Firmware. More SiP information could be found in https://github.com/ARM-software/arm-trusted-firmware/blob/master/ docs/arm-sip-service.rst Signed-off-by: Peng Fan Reviewed-by: Fabio Estevam Cc: Stefano Babic --- arch/arm/include/asm/mach-imx/sys_proto.h | 3 +++ arch/arm/mach-imx/Makefile | 2 ++ arch/arm/mach-imx/sip.c | 23 +++++++++++++++++++++++ include/imx_sip.h | 14 ++++++++++++++ 4 files changed, 42 insertions(+) create mode 100644 arch/arm/mach-imx/sip.c create mode 100644 include/imx_sip.h diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index d518e03809..c53e5400a1 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -126,4 +126,7 @@ void lcdif_power_down(void); int mxs_reset_block(struct mxs_register_32 *reg); int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); + +unsigned long call_imx_sip(unsigned long id, unsigned long reg0, + unsigned long reg1, unsigned long reg2); #endif diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index cf39d08bdd..63db0e15c4 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -124,6 +124,8 @@ spl/u-boot-nand-spl.imx: SPL FORCE targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-spl.imx) +obj-$(CONFIG_ARM64) += sip.o + obj-$(CONFIG_MX5) += mx5/ obj-$(CONFIG_MX6) += mx6/ obj-$(CONFIG_MX7) += mx7/ diff --git a/arch/arm/mach-imx/sip.c b/arch/arm/mach-imx/sip.c new file mode 100644 index 0000000000..b724330d35 --- /dev/null +++ b/arch/arm/mach-imx/sip.c @@ -0,0 +1,23 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +unsigned long call_imx_sip(unsigned long id, unsigned long reg0, + unsigned long reg1, unsigned long reg2) +{ + struct pt_regs regs; + + regs.regs[0] = id; + regs.regs[1] = reg0; + regs.regs[2] = reg1; + regs.regs[3] = reg2; + + smc_call(®s); + + return regs.regs[0]; +} diff --git a/include/imx_sip.h b/include/imx_sip.h new file mode 100644 index 0000000000..48ab878749 --- /dev/null +++ b/include/imx_sip.h @@ -0,0 +1,14 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IMX_SIP_H__ +#define _IMX_SIP_H_ + +#define IMX_SIP_SRC 0xC2000005 +#define IMX_SIP_SRC_M4_START 0x00 +#define IMX_SIP_SRC_M4_STARTED 0x01 + +#endif From patchwork Wed Jan 10 05:20:24 2018 Content-Type: text/plain; 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Signed-off-by: Peng Fan Reviewed-by: Stefano Babic Reviewed-by: Fabio Estevam --- arch/arm/include/asm/mach-imx/boot_mode.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h b/arch/arm/include/asm/mach-imx/boot_mode.h index a8239f2f7a..e3ed046b25 100644 --- a/arch/arm/include/asm/mach-imx/boot_mode.h +++ b/arch/arm/include/asm/mach-imx/boot_mode.h @@ -26,6 +26,7 @@ enum boot_device { MMC4_BOOT, NAND_BOOT, QSPI_BOOT, + USB_BOOT, UNKNOWN_BOOT, BOOT_DEV_NUM = UNKNOWN_BOOT, }; From patchwork Wed Jan 10 05:20:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857949 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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case 0x00200: return "TEMPSENSE"; +#elif defined(CONFIG_MX8M) + case 0x00100: + return "WDOG2"; + case 0x00200: + return "TEMPSENSE"; #else case 0x00100: return "TEMPSENSE"; @@ -137,6 +142,8 @@ unsigned imx_ddr_size(void) const char *get_imx_type(u32 imxtype) { switch (imxtype) { + case MXC_CPU_MX8MQ: + return "8MQ"; /* Quad-core version of the mx8m */ case MXC_CPU_MX7S: return "7S"; /* Single-core version of the mx7 */ case MXC_CPU_MX7D: @@ -259,7 +266,7 @@ int cpu_mmc_init(bd_t *bis) } #endif -#ifndef CONFIG_MX7 +#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M)) u32 get_ahb_clk(void) { struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -293,6 +300,7 @@ void arch_preboot_os(void) #endif } +#ifndef CONFIG_MX8M void set_chipselect_size(int const cs_size) { unsigned int reg; @@ -323,6 +331,7 @@ void set_chipselect_size(int const cs_size) writel(reg, &iomuxc_regs->gpr[1]); } +#endif #ifdef CONFIG_NXP_BOARD_REVISION int nxp_board_rev(void) From patchwork Wed Jan 10 05:20:26 2018 Content-Type: text/plain; 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Signed-off-by: Peng Fan Reviewed-by: Fabio Estevam Cc: Stefano Babic Reviewed-by: Stefano Babic --- arch/arm/mach-imx/spl.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 723f51fad3..7c4ee82cd1 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -97,8 +97,8 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NONE; } -#elif defined(CONFIG_MX7) -/* Translate iMX7 boot device to the SPL boot device enumeration */ +#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M) +/* Translate iMX7/MX8M boot device to the SPL boot device enumeration */ u32 spl_boot_device(void) { enum boot_device boot_device_spl = get_boot_device(); @@ -112,11 +112,15 @@ u32 spl_boot_device(void) return BOOT_DEVICE_MMC2; case SPI_NOR_BOOT: return BOOT_DEVICE_SPI; + case NAND_BOOT: + return BOOT_DEVICE_NAND; + case USB_BOOT: + return BOOT_DEVICE_USB; default: return BOOT_DEVICE_NONE; } } -#endif /* CONFIG_MX6 || CONFIG_MX7 */ +#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */ #ifdef CONFIG_SPL_USB_GADGET_SUPPORT int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) From patchwork Wed Jan 10 05:20:27 2018 Content-Type: text/plain; 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Signed-off-by: Peng Fan Reviewed-by: Fabio Estevam Cc: Stefano Babic Reviewed-by: Stefano Babic --- arch/arm/include/asm/arch-imx/cpu.h | 6 ++++-- arch/arm/include/asm/mach-imx/sys_proto.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index ec5b419e47..470961c6f7 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -25,12 +25,14 @@ #define MXC_CPU_MX6QP 0x69 #define MXC_CPU_MX7S 0x71 /* dummy ID */ #define MXC_CPU_MX7D 0x72 -#define MXC_CPU_MX7ULP 0x81 /* Temporally hard code */ +#define MXC_CPU_MX8MQ 0x82 +#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 -#define MXC_SOC_MX7ULP 0x80 /* dummy */ +#define MXC_SOC_MX8M 0x80 +#define MXC_SOC_MX7ULP 0xE0 /* dummy */ #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index c53e5400a1..96795e1814 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -27,6 +27,7 @@ #define is_mx6() (is_soc_type(MXC_SOC_MX6)) #define is_mx7() (is_soc_type(MXC_SOC_MX7)) +#define is_mx8m() (is_soc_type(MXC_SOC_MX8M)) #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) From patchwork Wed Jan 10 05:20:28 2018 Content-Type: text/plain; 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Signed-off-by: Peng Fan Reviewed-by: Fabio Estevam Cc: Stefano Babic Reviewed-by: Stefano Babic --- arch/arm/include/asm/mach-imx/iomux-v3.h | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index ed75e9cd9a..800d4cfb50 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -87,7 +87,27 @@ typedef u64 iomux_v3_cfg_t; #define IOMUX_CONFIG_LPSR 0x20 #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ MUX_MODE_SHIFT) -#ifdef CONFIG_MX7 +#ifdef CONFIG_MX8M +#define PAD_CTL_DSE0 (0x0 << 0) +#define PAD_CTL_DSE1 (0x1 << 0) +#define PAD_CTL_DSE2 (0x2 << 0) +#define PAD_CTL_DSE3 (0x3 << 0) +#define PAD_CTL_DSE4 (0x4 << 0) +#define PAD_CTL_DSE5 (0x5 << 0) +#define PAD_CTL_DSE6 (0x6 << 0) +#define PAD_CTL_DSE7 (0x7 << 0) + +#define PAD_CTL_FSEL0 (0x0 << 3) +#define PAD_CTL_FSEL1 (0x1 << 3) +#define PAD_CTL_FSEL2 (0x2 << 3) +#define PAD_CTL_FSEL3 (0x3 << 3) + +#define PAD_CTL_ODE (0x1 << 5) +#define PAD_CTL_PUE (0x1 << 6) +#define PAD_CTL_HYS (0x1 << 7) +#define PAD_CTL_LVTTL (0x1 << 8) + +#elif defined CONFIG_MX7 #define IOMUX_LPSR_SEL_INPUT_OFS 0x70000 From patchwork Wed Jan 10 05:20:29 2018 Content-Type: text/plain; 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DB6PR04MB3221; 6:KKAHanjb3fODOnBqFGKqnLZ5/+7bZ5LXdftiDro/7BkGVrkLA2AqkGd+D5H75z10GluJiLiB4oQptpMLKvstCSMUd+XEkAp3gh/Ej+BObpZ+F2w/0vnXU8HAWPvprL5hnIGdOqaDC4k/qZjS/tEJ3UMckf+3bpyZMWLA8Tj9w60JGV+wtfe/WisH6XtlhjQ7XOQ97x5xzj0Z/a5nwvRnByOxFUr6+gEWmthcy5FeZOGuKH0sPDcTOrLUuXRMmJ06XORnI2xudB688D6MZezid2d6dRcjVFB6uROR+iGkbdDhlbPIC1uHA1vCSBJZrc+BXXggnr4RkdylogaMuwcxsdhfEIWZRNiX/MQ4NyWRh7Q=; 5:b3EIHdiDKvj0vl9oGbhwYs3es1fngzbx5n2swf7QLTzamBtTtlE8qkeimj+dCfbs4/AM/zP3HukhKSTS+vPV5qrmCXcFzDnK2drEAIBWYny6HDL3Gfk2MhoR01qj+p+Kho9jPxnJ7SWsq0tWAJgFFuVsoNQfRDVTAPOpk8AIM14=; 24:DacHE0JeL4F4yXWuXHUXvVbYFPE83LUyHuMa0cn9Asj+vg3IAG47C8+NDjoSU0SNl0V4eqPZfdnOqAZHz1DLrbWFpz6fM4emZ/8QaL6DjYw=; 7:gB6xxsSBEQBUXn6TytOlm+ynb1J2i3GHa0hOYQCWBu4qFEBTa30555nEuYIcvpMQABgrXhgtxrvn795+aaNlrBVzd3i6YF9UG9d/k8/KZ5ZhG1tFcRCEz/Od7EPUFpdTN849zDPC3+iEhEzxts1yGXpg27oQGBlSFZA6iE282pLDPxK0I2RveHRO332pXKKCPnLiW+KYrwRdyjiq3+phQ8HPppNgsEUS4jfpayV7o88TDWVZ4I+HfTQG3Y4rsjWt SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jan 2018 05:21:34.6537 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f760c840-1214-4a20-a05e-08d557ea0589 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR04MB3221 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH V5 12/31] imx: cpu: move speed/temp to common cpu X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The i.MX7 cpu speed/temp code could be reused on i.MX8M, so move them to common cpu code. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam Reviewed-by: Stefano Babic --- arch/arm/mach-imx/cpu.c | 73 +++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/mx7/soc.c | 71 ------------------------------------------- 2 files changed, 73 insertions(+), 71 deletions(-) diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index fae8b0a419..52dbafb50c 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -333,6 +333,79 @@ void set_chipselect_size(int const cs_size) } #endif +#if defined(CONFIG_MX7) +/* + * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440) + * defines a 2-bit SPEED_GRADING + */ +#define OCOTP_TESTER3_SPEED_SHIFT 8 +#define OCOTP_TESTER3_SPEED_800MHZ 0 +#define OCOTP_TESTER3_SPEED_500MHZ 1 +#define OCOTP_TESTER3_SPEED_1GHZ 2 +#define OCOTP_TESTER3_SPEED_1P2GHZ 3 + +u32 get_cpu_speed_grade_hz(void) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[1]; + struct fuse_bank1_regs *fuse = + (struct fuse_bank1_regs *)bank->fuse_regs; + uint32_t val; + + val = readl(&fuse->tester3); + val >>= OCOTP_TESTER3_SPEED_SHIFT; + val &= 0x3; + + switch(val) { + case OCOTP_TESTER3_SPEED_800MHZ: + return 800000000; + case OCOTP_TESTER3_SPEED_500MHZ: + return 500000000; + case OCOTP_TESTER3_SPEED_1GHZ: + return 1000000000; + case OCOTP_TESTER3_SPEED_1P2GHZ: + return 1200000000; + } + return 0; +} + +/* + * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440) + * defines a 2-bit SPEED_GRADING + */ +#define OCOTP_TESTER3_TEMP_SHIFT 6 + +u32 get_cpu_temp_grade(int *minc, int *maxc) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[1]; + struct fuse_bank1_regs *fuse = + (struct fuse_bank1_regs *)bank->fuse_regs; + uint32_t val; + + val = readl(&fuse->tester3); + val >>= OCOTP_TESTER3_TEMP_SHIFT; + val &= 0x3; + + if (minc && maxc) { + if (val == TEMP_AUTOMOTIVE) { + *minc = -40; + *maxc = 125; + } else if (val == TEMP_INDUSTRIAL) { + *minc = -40; + *maxc = 105; + } else if (val == TEMP_EXTCOMMERCIAL) { + *minc = -20; + *maxc = 105; + } else { + *minc = 0; + *maxc = 95; + } + } + return val; +} +#endif + #ifdef CONFIG_NXP_BOARD_REVISION int nxp_board_rev(void) { diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index d160e80146..032dfcf2ce 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -97,77 +97,6 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = { }; #endif -/* - * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440) - * defines a 2-bit SPEED_GRADING - */ -#define OCOTP_TESTER3_SPEED_SHIFT 8 -#define OCOTP_TESTER3_SPEED_800MHZ 0 -#define OCOTP_TESTER3_SPEED_500MHZ 1 -#define OCOTP_TESTER3_SPEED_1GHZ 2 -#define OCOTP_TESTER3_SPEED_1P2GHZ 3 - -u32 get_cpu_speed_grade_hz(void) -{ - struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; - struct fuse_bank *bank = &ocotp->bank[1]; - struct fuse_bank1_regs *fuse = - (struct fuse_bank1_regs *)bank->fuse_regs; - uint32_t val; - - val = readl(&fuse->tester3); - val >>= OCOTP_TESTER3_SPEED_SHIFT; - val &= 0x3; - - switch(val) { - case OCOTP_TESTER3_SPEED_800MHZ: - return 800000000; - case OCOTP_TESTER3_SPEED_500MHZ: - return 500000000; - case OCOTP_TESTER3_SPEED_1GHZ: - return 1000000000; - case OCOTP_TESTER3_SPEED_1P2GHZ: - return 1200000000; - } - return 0; -} - -/* - * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440) - * defines a 2-bit SPEED_GRADING - */ -#define OCOTP_TESTER3_TEMP_SHIFT 6 - -u32 get_cpu_temp_grade(int *minc, int *maxc) -{ - struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; - struct fuse_bank *bank = &ocotp->bank[1]; - struct fuse_bank1_regs *fuse = - (struct fuse_bank1_regs *)bank->fuse_regs; - uint32_t val; - - val = readl(&fuse->tester3); - val >>= OCOTP_TESTER3_TEMP_SHIFT; - val &= 0x3; - - if (minc && maxc) { - if (val == TEMP_AUTOMOTIVE) { - *minc = -40; - *maxc = 125; - } else if (val == TEMP_INDUSTRIAL) { - *minc = -40; - *maxc = 105; - } else if (val == TEMP_EXTCOMMERCIAL) { - *minc = -20; - *maxc = 105; - } else { - *minc = 0; - *maxc = 95; - } - } - return val; -} - static bool is_mx7d(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; From patchwork Wed Jan 10 05:20:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857960 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="PkW1yEXJ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zGd356xC8z9s82 for ; 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bh=JDlKRkjRYuRWZplWdpk7Cj2KYsTo1QpM4zjXQBF9+88=; b=PkW1yEXJ3dktGHw/ZvkSv7LxyKXlGNImoMQfKjgMahjn5d4x/r62RqLW6Tcr1HOth/3X7YPx/xkN7S4+WjMaPfaOVa42I/GJDKUvj/PHCcY8SKgoxeg6heT5ZuCCbREkzbVzgEqLbs4Q/yswe7LWjDpOB1KZJlqnYVulR0G0sl4= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; Received: from linux-u7w5.ap.freescale.net.net (92.121.68.129) by DB6PR04MB3221.eurprd04.prod.outlook.com (2603:10a6:6:6::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.386.5; Wed, 10 Jan 2018 05:21:37 +0000 From: Peng Fan To: sbabic@denx.de, fabio.estevam@nxp.com Date: Wed, 10 Jan 2018 13:20:30 +0800 Message-Id: <20180110052048.4425-14-peng.fan@nxp.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180110052048.4425-1-peng.fan@nxp.com> References: <20180110052048.4425-1-peng.fan@nxp.com> MIME-Version: 1.0 X-Originating-IP: [92.121.68.129] X-ClientProxiedBy: HK2PR02CA0219.apcprd02.prod.outlook.com (2603:1096:201:20::31) To DB6PR04MB3221.eurprd04.prod.outlook.com (2603:10a6:6:6::17) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: f93adf8a-cf1c-4c55-3e56-08d557ea074c X-Microsoft-Antispam: UriScan:; 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Refine get_cpu_speed_grade_hz to support i.MX8M. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam Reviewed-by: Stefano Babic --- arch/arm/mach-imx/cpu.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 52dbafb50c..fd6d08c533 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -333,16 +333,18 @@ void set_chipselect_size(int const cs_size) } #endif -#if defined(CONFIG_MX7) +#if defined(CONFIG_MX7) || defined(CONFIG_MX8M) /* * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440) * defines a 2-bit SPEED_GRADING */ #define OCOTP_TESTER3_SPEED_SHIFT 8 -#define OCOTP_TESTER3_SPEED_800MHZ 0 -#define OCOTP_TESTER3_SPEED_500MHZ 1 -#define OCOTP_TESTER3_SPEED_1GHZ 2 -#define OCOTP_TESTER3_SPEED_1P2GHZ 3 +enum cpu_speed { + OCOTP_TESTER3_SPEED_GRADE0, + OCOTP_TESTER3_SPEED_GRADE1, + OCOTP_TESTER3_SPEED_GRADE2, + OCOTP_TESTER3_SPEED_GRADE3, +}; u32 get_cpu_speed_grade_hz(void) { @@ -357,15 +359,16 @@ u32 get_cpu_speed_grade_hz(void) val &= 0x3; switch(val) { - case OCOTP_TESTER3_SPEED_800MHZ: + case OCOTP_TESTER3_SPEED_GRADE0: return 800000000; - case OCOTP_TESTER3_SPEED_500MHZ: - return 500000000; - case OCOTP_TESTER3_SPEED_1GHZ: - return 1000000000; - case OCOTP_TESTER3_SPEED_1P2GHZ: - return 1200000000; + case OCOTP_TESTER3_SPEED_GRADE1: + return is_mx7() ? 500000000 : 1000000000; + case OCOTP_TESTER3_SPEED_GRADE2: + return is_mx7() ? 1000000000 : 1300000000; + case OCOTP_TESTER3_SPEED_GRADE3: + return is_mx7() ? 1200000000 : 1500000000; } + return 0; } From patchwork Wed Jan 10 05:20:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857952 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Wed, 10 Jan 2018 05:21:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=7Zkt7m85wIJHNu4DkCmRisRIUQ+gupc0wHqN9ozc7fw=; b=kWuEMJL6blVYZ3HIdGU7jcrB/Ky5ufpir7pyNC5RIMd02c0e1WL6gT5PCV0TdsxM/F4ntotSZabkZ+Zh+aUCwh3pJOFQjb862QqJ01BTOO79qpIxzwQI0DURVMtnRlAy+K/HRqEatQ0rBChsPKOIgUqIY0Kwar+Dbp6yM3HXfJk= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; Received: from linux-u7w5.ap.freescale.net.net (92.121.68.129) by DB6PR04MB3221.eurprd04.prod.outlook.com (2603:10a6:6:6::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.386.5; Wed, 10 Jan 2018 05:21:40 +0000 From: Peng Fan To: sbabic@denx.de, fabio.estevam@nxp.com Date: Wed, 10 Jan 2018 13:20:31 +0800 Message-Id: <20180110052048.4425-15-peng.fan@nxp.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180110052048.4425-1-peng.fan@nxp.com> References: <20180110052048.4425-1-peng.fan@nxp.com> MIME-Version: 1.0 X-Originating-IP: [92.121.68.129] X-ClientProxiedBy: HK2PR02CA0219.apcprd02.prod.outlook.com (2603:1096:201:20::31) To DB6PR04MB3221.eurprd04.prod.outlook.com (2603:10a6:6:6::17) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 7acb50cc-140e-4ee0-b289-08d557ea0945 X-Microsoft-Antispam: UriScan:; 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Since fuse regs structure are different for i.MX6/7, use mac address offset in code and define a new local struture imx_mac_fuse. Also sort the config order. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam Reviewed-by: Stefano Babic --- arch/arm/mach-imx/Makefile | 3 ++- arch/arm/mach-imx/mac.c | 61 +++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/mx6/soc.c | 34 ------------------------- arch/arm/mach-imx/mx7/soc.c | 32 ------------------------ 4 files changed, 63 insertions(+), 67 deletions(-) create mode 100644 arch/arm/mach-imx/mac.c diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 63db0e15c4..714b858e73 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -25,12 +25,13 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif ifeq ($(SOC),$(filter $(SOC),mx6 mx7)) obj-y += cache.o init.o -obj-$(CONFIG_SATA) += sata.o +obj-$(CONFIG_FEC_MXC) += mac.o obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o obj-$(CONFIG_IMX_RDC) += rdc-sema.o ifneq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o endif +obj-$(CONFIG_SATA) += sata.o obj-$(CONFIG_SECURE_BOOT) += hab.o obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o endif diff --git a/arch/arm/mach-imx/mac.c b/arch/arm/mach-imx/mac.c new file mode 100644 index 0000000000..dd7fd92d31 --- /dev/null +++ b/arch/arm/mach-imx/mac.c @@ -0,0 +1,61 @@ +/* + * Copyright 2017 NXP + * + * Peng Fan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +struct imx_mac_fuse { + u32 mac_addr0; + u32 rsvd0[3]; + u32 mac_addr1; + u32 rsvd1[3]; + u32 mac_addr2; + u32 rsvd2[7]; +}; + +#define MAC_FUSE_MX6_OFFSET 0x620 +#define MAC_FUSE_MX7_OFFSET 0x640 + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + struct imx_mac_fuse *fuse; + u32 offset; + bool has_second_mac; + + offset = is_mx6() ? MAC_FUSE_MX6_OFFSET : MAC_FUSE_MX7_OFFSET; + fuse = (struct imx_mac_fuse *)(ulong)(OCOTP_BASE_ADDR + offset); + has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull(); + + if (has_second_mac && dev_id == 1) { + u32 value = readl(&fuse->mac_addr2); + + mac[0] = value >> 24; + mac[1] = value >> 16; + mac[2] = value >> 8; + mac[3] = value; + + value = readl(&fuse->mac_addr1); + mac[4] = value >> 24; + mac[5] = value >> 16; + + } else { + u32 value = readl(&fuse->mac_addr1); + + mac[0] = value >> 8; + mac[1] = value; + + value = readl(&fuse->mac_addr0); + mac[2] = value >> 24; + mac[3] = value >> 16; + mac[4] = value >> 8; + mac[5] = value; + } +} diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 43cb58106b..b3bee58f10 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -518,40 +518,6 @@ int board_postclk_init(void) return 0; } -#if defined(CONFIG_FEC_MXC) -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) -{ - struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; - struct fuse_bank *bank = &ocotp->bank[4]; - struct fuse_bank4_regs *fuse = - (struct fuse_bank4_regs *)bank->fuse_regs; - - if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) { - u32 value = readl(&fuse->mac_addr2); - mac[0] = value >> 24 ; - mac[1] = value >> 16 ; - mac[2] = value >> 8 ; - mac[3] = value ; - - value = readl(&fuse->mac_addr1); - mac[4] = value >> 24 ; - mac[5] = value >> 16 ; - - } else { - u32 value = readl(&fuse->mac_addr1); - mac[0] = (value >> 8); - mac[1] = value ; - - value = readl(&fuse->mac_addr0); - mac[2] = value >> 24 ; - mac[3] = value >> 16 ; - mac[4] = value >> 8 ; - mac[5] = value ; - } - -} -#endif - #ifndef CONFIG_SPL_BUILD /* * cfg_val will be used for diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 032dfcf2ce..10dec8bdf4 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -208,38 +208,6 @@ void get_board_serial(struct tag_serialnr *serialnr) } #endif -#if defined(CONFIG_FEC_MXC) -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) -{ - struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; - struct fuse_bank *bank = &ocotp->bank[9]; - struct fuse_bank9_regs *fuse = - (struct fuse_bank9_regs *)bank->fuse_regs; - - if (0 == dev_id) { - u32 value = readl(&fuse->mac_addr1); - mac[0] = (value >> 8); - mac[1] = value; - - value = readl(&fuse->mac_addr0); - mac[2] = value >> 24; - mac[3] = value >> 16; - mac[4] = value >> 8; - mac[5] = value; - } else { - u32 value = readl(&fuse->mac_addr2); - mac[0] = value >> 24; - mac[1] = value >> 16; - mac[2] = value >> 8; - mac[3] = value; - - value = readl(&fuse->mac_addr1); - mac[4] = value >> 24; - mac[5] = value >> 16; - } -} -#endif - #ifdef CONFIG_IMX_BOOTAUX int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) { From patchwork Wed Jan 10 05:20:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857956 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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The i.MX6/7 has different src layout, so define M4 reg offset to ease the cleanup. Redefine the M4 related BIT for share common code. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam --- arch/arm/include/asm/arch-mx6/imx-regs.h | 9 ++++---- arch/arm/include/asm/arch-mx7/imx-regs.h | 10 +++++---- arch/arm/mach-imx/imx_bootaux.c | 36 +++++++++++++++++++++++------- arch/arm/mach-imx/mx6/soc.c | 38 -------------------------------- arch/arm/mach-imx/mx7/soc.c | 36 ------------------------------ 5 files changed, 39 insertions(+), 90 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 48ce0edd06..8513406a8e 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -482,10 +482,11 @@ struct src { #define src_base ((struct src *)SRC_BASE_ADDR) -#define SRC_SCR_M4_ENABLE_OFFSET 22 -#define SRC_SCR_M4_ENABLE_MASK (1 << 22) -#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4 -#define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4) +#define SRC_M4_REG_OFFSET 0 +#define SRC_M4_ENABLE_OFFSET 22 +#define SRC_M4_ENABLE_MASK BIT(22) +#define SRC_M4C_NON_SCLR_RST_OFFSET 4 +#define SRC_M4C_NON_SCLR_RST_MASK BIT(4) /* GPR1 bitfields */ #define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30) diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index f0693f9028..a421b9bc04 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -264,10 +264,12 @@ struct src { u32 ddrc_rcr; }; -#define SRC_M4RCR_M4C_NON_SCLR_RST_OFFSET 0 -#define SRC_M4RCR_M4C_NON_SCLR_RST_MASK (1 << 0) -#define SRC_M4RCR_ENABLE_M4_OFFSET 3 -#define SRC_M4RCR_ENABLE_M4_MASK (1 << 3) +#define SRC_M4_REG_OFFSET 0xC +#define SRC_M4C_NON_SCLR_RST_OFFSET 0 +#define SRC_M4C_NON_SCLR_RST_MASK BIT(0) +#define SRC_M4_ENABLE_OFFSET 3 +#define SRC_M4_ENABLE_MASK BIT(3) + #define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET 1 #define SRC_DDRC_RCR_DDRC_CORE_RST_MASK (1 << 1) diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index b62dfbf6bf..02728514b7 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -5,21 +5,41 @@ */ #include +#include #include #include -/* Allow for arch specific config before we boot */ -int __weak arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) +int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) { - /* please define platform specific arch_auxiliary_core_up() */ - return CMD_RET_FAILURE; + ulong stack, pc; + + if (!boot_private_data) + return -EINVAL; + + stack = *(ulong *)boot_private_data; + pc = *(ulong *)(boot_private_data + 4); + + /* Set the stack and pc to M4 bootROM */ + writel(stack, M4_BOOTROM_BASE_ADDR); + writel(pc, M4_BOOTROM_BASE_ADDR + 4); + + /* Enable M4 */ + clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, + SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK); + + return 0; } -/* Allow for arch specific config before we boot */ -int __weak arch_auxiliary_core_check_up(u32 core_id) +int arch_auxiliary_core_check_up(u32 core_id) { - /* please define platform specific arch_auxiliary_core_check_up() */ - return 0; + unsigned int val; + + val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET); + + if (val & SRC_M4C_NON_SCLR_RST_MASK) + return 0; /* assert in reset */ + + return 1; } /* diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index b3bee58f10..9b3d8f69b2 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -666,41 +666,3 @@ void gpr_init(void) writel(0x007F007F, &iomux->gpr[7]); } } - -#ifdef CONFIG_IMX_BOOTAUX -int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) -{ - struct src *src_reg; - u32 stack, pc; - - if (!boot_private_data) - return -EINVAL; - - stack = *(u32 *)boot_private_data; - pc = *(u32 *)(boot_private_data + 4); - - /* Set the stack and pc to M4 bootROM */ - writel(stack, M4_BOOTROM_BASE_ADDR); - writel(pc, M4_BOOTROM_BASE_ADDR + 4); - - /* Enable M4 */ - src_reg = (struct src *)SRC_BASE_ADDR; - clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK, - SRC_SCR_M4_ENABLE_MASK); - - return 0; -} - -int arch_auxiliary_core_check_up(u32 core_id) -{ - struct src *src_reg = (struct src *)SRC_BASE_ADDR; - unsigned val; - - val = readl(&src_reg->scr); - - if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK) - return 0; /* assert in reset */ - - return 1; -} -#endif diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 10dec8bdf4..72dbd625c9 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -208,42 +208,6 @@ void get_board_serial(struct tag_serialnr *serialnr) } #endif -#ifdef CONFIG_IMX_BOOTAUX -int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) -{ - u32 stack, pc; - struct src *src_reg = (struct src *)SRC_BASE_ADDR; - - if (!boot_private_data) - return 1; - - stack = *(u32 *)boot_private_data; - pc = *(u32 *)(boot_private_data + 4); - - /* Set the stack and pc to M4 bootROM */ - writel(stack, M4_BOOTROM_BASE_ADDR); - writel(pc, M4_BOOTROM_BASE_ADDR + 4); - - /* Enable M4 */ - clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK, - SRC_M4RCR_ENABLE_M4_MASK); - - return 0; -} - -int arch_auxiliary_core_check_up(u32 core_id) -{ - uint32_t val; - struct src *src_reg = (struct src *)SRC_BASE_ADDR; - - val = readl(&src_reg->m4rcr); - if (val & 0x00000001) - return 0; /* assert in reset */ - - return 1; -} -#endif - void set_wdog_reset(struct wdog_regs *wdog) { u32 reg = readw(&wdog->wcr); From patchwork Wed Jan 10 05:20:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857965 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Because i.MX8M use SiP call trap to Arm Trusted Firmware to handle M4, so use #ifdef to avoid build error on i.MX6/7. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx_bootaux.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 02728514b7..6256b3a778 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -6,7 +6,9 @@ #include #include +#include #include +#include #include int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) @@ -24,14 +26,21 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) writel(pc, M4_BOOTROM_BASE_ADDR + 4); /* Enable M4 */ +#ifdef CONFIG_MX8M + call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0); +#else clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK); +#endif return 0; } int arch_auxiliary_core_check_up(u32 core_id) { +#ifdef CONFIG_MX8M + return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0); +#else unsigned int val; val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET); @@ -40,6 +49,7 @@ int arch_auxiliary_core_check_up(u32 core_id) return 0; /* assert in reset */ return 1; +#endif } /* From patchwork Wed Jan 10 05:20:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857971 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="LWx1QE12"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zGdCC3sVgz9s7n for ; Wed, 10 Jan 2018 16:40:39 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2DC89C220C8; Wed, 10 Jan 2018 05:38:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=BAD_ENC_HEADER, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 259D0C2216B; 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Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam Reviewed-by: Stefano Babic --- arch/arm/include/asm/arch-mx7/imx-regs.h | 8 ------- arch/arm/include/asm/mach-imx/boot_mode.h | 9 ++++++++ arch/arm/mach-imx/cpu.c | 38 +++++++++++++++++++++++++++++++ arch/arm/mach-imx/mx7/soc.c | 35 ---------------------------- 4 files changed, 47 insertions(+), 43 deletions(-) diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index a421b9bc04..3726f02af5 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -1210,14 +1210,6 @@ extern void pcie_power_off(void); readl(USBOTG2_IPS_BASE_ADDR + 0x158)) #define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140) -/* Boot device type */ -#define BOOT_TYPE_SD 0x1 -#define BOOT_TYPE_MMC 0x2 -#define BOOT_TYPE_NAND 0x3 -#define BOOT_TYPE_QSPI 0x4 -#define BOOT_TYPE_WEIM 0x5 -#define BOOT_TYPE_SPINOR 0x6 - struct bootrom_sw_info { u8 reserved_1; u8 boot_dev_instance; diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h b/arch/arm/include/asm/mach-imx/boot_mode.h index e3ed046b25..300868a45e 100644 --- a/arch/arm/include/asm/mach-imx/boot_mode.h +++ b/arch/arm/include/asm/mach-imx/boot_mode.h @@ -31,6 +31,15 @@ enum boot_device { BOOT_DEV_NUM = UNKNOWN_BOOT, }; +/* Boot device type */ +#define BOOT_TYPE_SD 0x1 +#define BOOT_TYPE_MMC 0x2 +#define BOOT_TYPE_NAND 0x3 +#define BOOT_TYPE_QSPI 0x4 +#define BOOT_TYPE_WEIM 0x5 +#define BOOT_TYPE_SPINOR 0x6 +#define BOOT_TYPE_USB 0xF + struct boot_mode { const char *name; unsigned cfg_val; diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index fd6d08c533..a7d89f2033 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -409,6 +410,43 @@ u32 get_cpu_temp_grade(int *minc, int *maxc) } #endif +#if defined(CONFIG_MX7) +enum boot_device get_boot_device(void) +{ + struct bootrom_sw_info **p = + (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR; + + enum boot_device boot_dev = SD1_BOOT; + u8 boot_type = (*p)->boot_dev_type; + u8 boot_instance = (*p)->boot_dev_instance; + + switch (boot_type) { + case BOOT_TYPE_SD: + boot_dev = boot_instance + SD1_BOOT; + break; + case BOOT_TYPE_MMC: + boot_dev = boot_instance + MMC1_BOOT; + break; + case BOOT_TYPE_NAND: + boot_dev = NAND_BOOT; + break; + case BOOT_TYPE_QSPI: + boot_dev = QSPI_BOOT; + break; + case BOOT_TYPE_WEIM: + boot_dev = WEIM_NOR_BOOT; + break; + case BOOT_TYPE_SPINOR: + boot_dev = SPI_NOR_BOOT; + break; + default: + break; + } + + return boot_dev; +} +#endif + #ifdef CONFIG_NXP_BOARD_REVISION int nxp_board_rev(void) { diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 72dbd625c9..62bd3a0e5f 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -250,41 +250,6 @@ const struct boot_mode soc_boot_modes[] = { {NULL, 0}, }; -enum boot_device get_boot_device(void) -{ - struct bootrom_sw_info **p = - (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; - - enum boot_device boot_dev = SD1_BOOT; - u8 boot_type = (*p)->boot_dev_type; - u8 boot_instance = (*p)->boot_dev_instance; - - switch (boot_type) { - case BOOT_TYPE_SD: - boot_dev = boot_instance + SD1_BOOT; - break; - case BOOT_TYPE_MMC: - boot_dev = boot_instance + MMC1_BOOT; - break; - case BOOT_TYPE_NAND: - boot_dev = NAND_BOOT; - break; - case BOOT_TYPE_QSPI: - boot_dev = QSPI_BOOT; - break; - case BOOT_TYPE_WEIM: - boot_dev = WEIM_NOR_BOOT; - break; - case BOOT_TYPE_SPINOR: - boot_dev = SPI_NOR_BOOT; - break; - default: - break; - } - - return boot_dev; -} - #ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) { From patchwork Wed Jan 10 05:20:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857973 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam Reviewed-by: Stefano Babic --- arch/arm/mach-imx/cpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index a7d89f2033..4d4d434906 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -410,7 +410,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc) } #endif -#if defined(CONFIG_MX7) +#if defined(CONFIG_MX7) || defined(CONFIG_MX8M) enum boot_device get_boot_device(void) { struct bootrom_sw_info **p = @@ -439,6 +439,11 @@ enum boot_device get_boot_device(void) case BOOT_TYPE_SPINOR: boot_dev = SPI_NOR_BOOT; break; +#ifdef CONFIG_MX8M + case BOOT_TYPE_USB: + boot_dev = USB_BOOT; + break; +#endif default: break; } From patchwork Wed Jan 10 05:20:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857957 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Signed-off-by: Peng Fan --- arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/mmc_env.c | 30 ++++++++++++++++++++++++++++++ arch/arm/mach-imx/mx7/soc.c | 21 --------------------- 3 files changed, 31 insertions(+), 21 deletions(-) create mode 100644 arch/arm/mach-imx/mmc_env.c diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 714b858e73..e38b560d51 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -22,6 +22,7 @@ endif ifeq ($(SOC),$(filter $(SOC),mx7)) obj-y += cpu.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o +obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o endif ifeq ($(SOC),$(filter $(SOC),mx6 mx7)) obj-y += cache.o init.o diff --git a/arch/arm/mach-imx/mmc_env.c b/arch/arm/mach-imx/mmc_env.c new file mode 100644 index 0000000000..ccadd2c1e0 --- /dev/null +++ b/arch/arm/mach-imx/mmc_env.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +__weak int board_mmc_get_env_dev(int devno) +{ + return CONFIG_SYS_MMC_ENV_DEV; +} + +int mmc_get_env_dev(void) +{ + struct bootrom_sw_info **p = + (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR; + int devno = (*p)->boot_dev_instance; + u8 boot_type = (*p)->boot_dev_type; + + /* If not boot from sd/mmc, use default value */ + if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC)) + return CONFIG_SYS_MMC_ENV_DEV; + + return board_mmc_get_env_dev(devno); +} diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 62bd3a0e5f..172be2ccc0 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -250,27 +250,6 @@ const struct boot_mode soc_boot_modes[] = { {NULL, 0}, }; -#ifdef CONFIG_ENV_IS_IN_MMC -__weak int board_mmc_get_env_dev(int devno) -{ - return CONFIG_SYS_MMC_ENV_DEV; -} - -int mmc_get_env_dev(void) -{ - struct bootrom_sw_info **p = - (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; - int devno = (*p)->boot_dev_instance; - u8 boot_type = (*p)->boot_dev_type; - - /* If not boot from sd/mmc, use default value */ - if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC)) - return CONFIG_SYS_MMC_ENV_DEV; - - return board_mmc_get_env_dev(devno); -} -#endif - void s_init(void) { #if !defined CONFIG_SPL_BUILD From patchwork Wed Jan 10 05:20:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857962 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="o2IgqSTX"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zGd5K2qMgz9s7n for ; Wed, 10 Jan 2018 16:35:33 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E4FA7C2210F; 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DB6PR04MB3221; 6:5YTuKrpVNu/7pnXEL7wOq11OifDruHufcpoULJTfjR4rOeWrA+FiFiX65PLg3d6GQ2nJChntzcQ9PvYr6OOY+YeQ0fo/zTULdh8acxaeK6LyciRzkOMuDUmYVBZuVxJInnlJ85oXyPxW1vjWIOwnM6BVUy33+J54JA5JE3h8s2cyelLUQYJ1r8lWbytrlfQPOJtfPhb6Ykc5+UHsnCOS/denW+MNRS1vyomVGRvtNYckLZKrqy+TUAk9lOcQoFzT1RFEHVhLAYiLDUzLEIXtO9h4WgEgItbF63IAyh4+7bQ3SCIzHI3JxEHXJVtjJ0XIlk/lZZfzvdFXHuRo2rY1+0TWw0ipheNvaAHULRBIIp0=; 5:r+dNor75QYmTkhslWcJUA8yECKnSiHFWfMfU4cZNLKldEvDOCFCX4x/LzZ5uL4a1nH+TZYkk4d0lNJjJ5YOU2KUdsIjTpISnrSBYix5Pv1JA2tgglpBELFD3bYsNxmlU9ZrwtHmefPK/hkmMDScf4J4pWYBbkAfPR7oNJU9Bbmg=; 24:PZFrx0SlQWFA70LVO7TUyzyDU+DPJhdnV6uiy+7yOPxj3IE4TOOUx+YfS7pgLk9YS62JNrUIULrurhibN9Zj2WdlywXT/V+K8IVTJNtmNFU=; 7:IxhfjFvUxqI17Ne0HmhPehVOVwf9OeKtHW9iRnWoEhpgp9QGWSRkY4iXRL31+cyuWPnyViQ7lAIfpsAuJ/sxbISzmhMSNjWYJVOYWeWd28oSy7YeUrXSEHbED/7PE4GBw5sU0lo6ZquN1CWPilEAk30MMsNpk+nm0DdxBzQ9ed8iOMATBbbZPSwVtVOsb6FiYe1v7gmC1HORMEHlgRGcRukXU8/9VIhm2XCDdbquEshc8iLxbys3jx4TGw7T7Lqg SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jan 2018 05:22:01.2009 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8dbae6b-8d45-4ef8-06be-08d557ea155a X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR04MB3221 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH V5 20/31] imx: mx8m: add soc related settings and files X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add SoC level initialization code - arch_cpu_init - mmu table - detect cpu revision - reset cpu and wdog settings - timer init - wdog settings - lowlevel init to save/restore registers - a few dummy header file to avoid build failure - ft_system_setup Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam --- arch/arm/include/asm/arch-mx8m/crm_regs.h | 10 ++ arch/arm/include/asm/arch-mx8m/gpio.h | 12 ++ arch/arm/include/asm/arch-mx8m/sys_proto.h | 18 +++ arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/mx8m/Makefile | 3 +- arch/arm/mach-imx/mx8m/lowlevel_init.S | 63 ++++++++ arch/arm/mach-imx/mx8m/soc.c | 227 +++++++++++++++++++++++++++++ 7 files changed, 333 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx8m/crm_regs.h create mode 100644 arch/arm/include/asm/arch-mx8m/gpio.h create mode 100644 arch/arm/include/asm/arch-mx8m/sys_proto.h create mode 100644 arch/arm/mach-imx/mx8m/lowlevel_init.S create mode 100644 arch/arm/mach-imx/mx8m/soc.c diff --git a/arch/arm/include/asm/arch-mx8m/crm_regs.h b/arch/arm/include/asm/arch-mx8m/crm_regs.h new file mode 100644 index 0000000000..6582318983 --- /dev/null +++ b/arch/arm/include/asm/arch-mx8m/crm_regs.h @@ -0,0 +1,10 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_MX8M_CRM_REGS_H +#define _ASM_ARCH_MX8M_CRM_REGS_H +/* Dummy header, some imx-common code needs this file */ +#endif diff --git a/arch/arm/include/asm/arch-mx8m/gpio.h b/arch/arm/include/asm/arch-mx8m/gpio.h new file mode 100644 index 0000000000..b666d37700 --- /dev/null +++ b/arch/arm/include/asm/arch-mx8m/gpio.h @@ -0,0 +1,12 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MX8M_GPIO_H +#define __ASM_ARCH_MX8M_GPIO_H + +#include + +#endif diff --git a/arch/arm/include/asm/arch-mx8m/sys_proto.h b/arch/arm/include/asm/arch-mx8m/sys_proto.h new file mode 100644 index 0000000000..8bf9ac6697 --- /dev/null +++ b/arch/arm/include/asm/arch-mx8m/sys_proto.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_MX8M_SYS_PROTO_H +#define __ARCH_MX8M_SYS_PROTO_H + +#include + +void set_wdog_reset(struct wdog_regs *wdog); +void enable_tzc380(void); +void restore_boot_params(void); +extern unsigned long rom_pointer[]; +enum boot_device get_boot_device(void); +bool is_usb_boot(void); +#endif diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index e38b560d51..4c4e15c6e7 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -132,4 +132,4 @@ obj-$(CONFIG_MX5) += mx5/ obj-$(CONFIG_MX6) += mx6/ obj-$(CONFIG_MX7) += mx7/ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ - +obj-$(CONFIG_MX8M) += mx8m/ diff --git a/arch/arm/mach-imx/mx8m/Makefile b/arch/arm/mach-imx/mx8m/Makefile index 05f38842f0..b1c5d74aab 100644 --- a/arch/arm/mach-imx/mx8m/Makefile +++ b/arch/arm/mach-imx/mx8m/Makefile @@ -4,4 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += clock.o clock_slice.o +obj-y += lowlevel_init.o +obj-y += clock.o clock_slice.o soc.o diff --git a/arch/arm/mach-imx/mx8m/lowlevel_init.S b/arch/arm/mach-imx/mx8m/lowlevel_init.S new file mode 100644 index 0000000000..d388f3ba95 --- /dev/null +++ b/arch/arm/mach-imx/mx8m/lowlevel_init.S @@ -0,0 +1,63 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +.align 8 +.global rom_pointer +rom_pointer: + .space 256 + +/* + * Routine: save_boot_params (called after reset from start.S) + */ + +.global save_boot_params +save_boot_params: + /* The firmware provided ATAG/FDT address can be found in r2/x0 */ + adr x0, rom_pointer + stp x1, x2, [x0], #16 + stp x3, x4, [x0], #16 + stp x5, x6, [x0], #16 + stp x7, x8, [x0], #16 + stp x9, x10, [x0], #16 + stp x11, x12, [x0], #16 + stp x13, x14, [x0], #16 + stp x15, x16, [x0], #16 + stp x17, x18, [x0], #16 + stp x19, x20, [x0], #16 + stp x21, x22, [x0], #16 + stp x23, x24, [x0], #16 + stp x25, x26, [x0], #16 + stp x27, x28, [x0], #16 + stp x29, x30, [x0], #16 + mov x30, sp + str x30, [x0], #8 + + /* Returns */ + b save_boot_params_ret + +.global restore_boot_params +restore_boot_params: + adr x0, rom_pointer + ldp x1, x2, [x0], #16 + ldp x3, x4, [x0], #16 + ldp x5, x6, [x0], #16 + ldp x7, x8, [x0], #16 + ldp x9, x10, [x0], #16 + ldp x11, x12, [x0], #16 + ldp x13, x14, [x0], #16 + ldp x15, x16, [x0], #16 + ldp x17, x18, [x0], #16 + ldp x19, x20, [x0], #16 + ldp x21, x22, [x0], #16 + ldp x23, x24, [x0], #16 + ldp x25, x26, [x0], #16 + ldp x27, x28, [x0], #16 + ldp x29, x30, [x0], #16 + ldr x0, [x0] + mov sp, x0 + ret diff --git a/arch/arm/mach-imx/mx8m/soc.c b/arch/arm/mach-imx/mx8m/soc.c new file mode 100644 index 0000000000..fe6c19c787 --- /dev/null +++ b/arch/arm/mach-imx/mx8m/soc.c @@ -0,0 +1,227 @@ +/* + * Copyright 2017 NXP + * + * Peng Fan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_SECURE_BOOT) +struct imx_sec_config_fuse_t const imx_sec_config_fuse = { + .bank = 1, + .word = 3, +}; +#endif + +int timer_init(void) +{ +#ifdef CONFIG_SPL_BUILD + struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; + unsigned long freq = readl(&sctr->cntfid0); + + /* Update with accurate clock frequency */ + asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory"); + + clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1, + SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG); +#endif + + gd->arch.tbl = 0; + gd->arch.tbu = 0; + + return 0; +} + +void enable_tzc380(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Enable TZASC and lock setting */ + setbits_le32(&gpr->gpr[10], GPR_TZASC_EN); + setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK); +} + +void set_wdog_reset(struct wdog_regs *wdog) +{ + /* + * Output WDOG_B signal to reset external pmic or POR_B decided by + * the board design. Without external reset, the peripherals/DDR/ + * PMIC are not reset, that may cause system working abnormal. + * WDZST bit is write-once only bit. Align this bit in kernel, + * otherwise kernel code will have no chance to set this bit. + */ + setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK); +} + +static struct mm_region imx8m_mem_map[] = { + { + /* ROM */ + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x100000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* OCRAM */ + .virt = 0x900000UL, + .phys = 0x900000UL, + .size = 0x200000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* AIPS */ + .virt = 0xB00000UL, + .phys = 0xB00000UL, + .size = 0x3f500000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* DRAM1 */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0xC0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* DRAM2 */ + .virt = 0x100000000UL, + .phys = 0x100000000UL, + .size = 0x040000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = imx8m_mem_map; + +u32 get_cpu_rev(void) +{ + struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; + u32 reg = readl(&ana_pll->digprog); + u32 type = (reg >> 16) & 0xff; + u32 rom_version; + + reg &= 0xff; + + if (reg == CHIP_REV_1_0) { + /* + * For B0 chip, the DIGPROG is not updated, still TO1.0. + * we have to check ROM version further + */ + rom_version = readl((void __iomem *)ROM_VERSION_A0); + if (rom_version != CHIP_REV_1_0) { + rom_version = readl((void __iomem *)ROM_VERSION_B0); + if (rom_version >= CHIP_REV_2_0) + reg = CHIP_REV_2_0; + } + } + + return (type << 12) | reg; +} + +static void imx_set_wdog_powerdown(bool enable) +{ + struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; + struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; + struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; + + /* Write to the PDE (Power Down Enable) bit */ + writew(enable, &wdog1->wmcr); + writew(enable, &wdog2->wmcr); + writew(enable, &wdog3->wmcr); +} + +int arch_cpu_init(void) +{ + /* + * Init timer at very early state, because sscg pll setting + * will use it + */ + timer_init(); + + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + clock_init(); + imx_set_wdog_powerdown(false); + } + + return 0; +} + +bool is_usb_boot(void) +{ + return get_boot_device() == USB_BOOT; +} + +#ifdef CONFIG_OF_SYSTEM_SETUP +int ft_system_setup(void *blob, bd_t *bd) +{ + int i = 0; + int rc; + int nodeoff; + + /* Disable the CPU idle for A0 chip since the HW does not support it */ + if (is_soc_rev(CHIP_REV_1_0)) { + static const char * const nodes_path[] = { + "/cpus/cpu@0", + "/cpus/cpu@1", + "/cpus/cpu@2", + "/cpus/cpu@3", + }; + + for (i = 0; i < ARRAY_SIZE(nodes_path); i++) { + nodeoff = fdt_path_offset(blob, nodes_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + printf("Found %s node\n", nodes_path[i]); + + rc = fdt_delprop(blob, nodeoff, "cpu-idle-states"); + if (rc) { + printf("Unable to update property %s:%s, err=%s\n", + nodes_path[i], "status", fdt_strerror(rc)); + return rc; + } + + printf("Remove %s:%s\n", nodes_path[i], + "cpu-idle-states"); + } + } + + return 0; +} +#endif + +void reset_cpu(ulong addr) +{ + struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; + + /* Clear WDA to trigger WDOG_B immediately */ + writew((WCR_WDE | WCR_SRS), &wdog->wcr); + + while (1) { + /* + * spin for .5 seconds before reset + */ + } +} From patchwork Wed Jan 10 05:20:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857959 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; 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Signed-off-by: Peng Fan Reviewed-by: Stefano Babic Reviewed-by: Fabio Estevam --- drivers/misc/mxc_ocotp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index 8986bb4ad0..0cf24a4c88 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -35,6 +35,8 @@ #define BM_OUT_STATUS_DED 0x00000400 #define BM_OUT_STATUS_LOCKED 0x00000800 #define BM_OUT_STATUS_PROGFAIL 0x00001000 +#elif defined(CONFIG_MX8M) +#define BM_CTRL_ADDR 0x000000ff #else #define BM_CTRL_ADDR 0x0000007f #endif @@ -79,6 +81,9 @@ #elif defined(CONFIG_MX7ULP) #define FUSE_BANK_SIZE 0x80 #define FUSE_BANKS 31 +#elif defined(CONFIG_MX8M) +#define FUSE_BANK_SIZE 0x40 +#define FUSE_BANKS 64 #else #error "Unsupported architecture\n" #endif @@ -294,6 +299,8 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word, u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0; #ifdef CONFIG_MX7 u32 addr = bank; +#elif defined CONFIG_MX8M + u32 addr = bank << 2 | word; #else u32 addr; /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */ From patchwork Wed Jan 10 05:20:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857966 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="eKmU0bqI"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zGd8D4T3dz9s7n for ; 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bh=8ll7B36PQEuqsFTdzs2bY/R01Pj9zrsofkL2VG3BknA=; b=eKmU0bqIiYOywHRw/DA5YbyvIUbws6AYqt3OtF5otV5OPsQ388IdT0/Vhrull31H7zLimN0AFci4iBBL2HCPpTiwJt1G2Owt+5vPyxNOePNST7Y0cnu8RQ6SeVL1PqjPF/OIN3r+rYUBhlFiSwhs3pu8x8PYRyWMhIehnaxgagA= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; Received: from linux-u7w5.ap.freescale.net.net (92.121.68.129) by DB6PR04MB3221.eurprd04.prod.outlook.com (2603:10a6:6:6::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.386.5; Wed, 10 Jan 2018 05:22:10 +0000 From: Peng Fan To: sbabic@denx.de, fabio.estevam@nxp.com Date: Wed, 10 Jan 2018 13:20:40 +0800 Message-Id: <20180110052048.4425-24-peng.fan@nxp.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180110052048.4425-1-peng.fan@nxp.com> References: <20180110052048.4425-1-peng.fan@nxp.com> MIME-Version: 1.0 X-Originating-IP: [92.121.68.129] X-ClientProxiedBy: HK2PR02CA0219.apcprd02.prod.outlook.com (2603:1096:201:20::31) To DB6PR04MB3221.eurprd04.prod.outlook.com (2603:10a6:6:6::17) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: effbe08a-e75f-4098-2d5e-08d557ea1acf X-Microsoft-Antispam: UriScan:; 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Signed-off-by: Peng Fan Reviewed-by: Stefano Babic Reviewed-by: Fabio Estevam --- drivers/mmc/fsl_esdhc.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 499d622c6d..3a56f7c2bc 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -228,7 +228,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, { int timeout; struct fsl_esdhc *regs = priv->esdhc_regs; -#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) +#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ + defined(CONFIG_MX8M) dma_addr_t addr; #endif uint wml_value; @@ -241,7 +242,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO -#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) +#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ + defined(CONFIG_MX8M) addr = virt_to_phys((void *)(data->dest)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -270,7 +272,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, wml_value << 16); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO -#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) +#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ + defined(CONFIG_MX8M) addr = virt_to_phys((void *)(data->src)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -335,7 +338,8 @@ static void check_and_invalidate_dcache_range unsigned end = 0; unsigned size = roundup(ARCH_DMA_MINALIGN, data->blocks*data->blocksize); -#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) +#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ + defined(CONFIG_MX8M) dma_addr_t addr; addr = virt_to_phys((void *)(data->dest)); From patchwork Wed Jan 10 05:20:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857969 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Also included i.MX7ULP in this patch, since share same with i.MX8M. Signed-off-by: Peng Fan Reviewed-by: Stefano Babic Reviewed-by: Fabio Estevam --- arch/arm/include/asm/mach-imx/regs-lcdif.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h index c6cf03bf5a..38a2c6d4ee 100644 --- a/arch/arm/include/asm/mach-imx/regs-lcdif.h +++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h @@ -19,11 +19,11 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */ mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */ - #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \ defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ - defined(CONFIG_MX7) + defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ + defined(CONFIG_MX8M) mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ #endif mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ @@ -61,7 +61,8 @@ struct mxs_lcdif_regs { #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \ defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ - defined(CONFIG_MX7) + defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ + defined(CONFIG_MX8M) mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ #endif mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ @@ -72,7 +73,8 @@ struct mxs_lcdif_regs { #if defined(CONFIG_MX6SX) || \ defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ - defined(CONFIG_MX7) + defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ + defined(CONFIG_MX8M) mxs_reg_32(hw_lcdif_thres) mxs_reg_32(hw_lcdif_as_ctrl) mxs_reg_32(hw_lcdif_as_buf) From patchwork Wed Jan 10 05:20:42 2018 Content-Type: text/plain; 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There are 4 GPIO banks on i.MX8M. Signed-off-by: Peng Fan Reviewed-by: Fabio Estevam Cc: Stefano Babic Reviewed-by: Stefano Babic --- drivers/gpio/mxc_gpio.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index cfa620bceb..d0e365a54b 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -41,13 +41,13 @@ static unsigned long gpio_ports[] = { [2] = GPIO3_BASE_ADDR, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX7) + defined(CONFIG_MX7) || defined(CONFIG_MX8M) [3] = GPIO4_BASE_ADDR, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX7) + defined(CONFIG_MX7) || defined(CONFIG_MX8M) [4] = GPIO5_BASE_ADDR, -#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M)) [5] = GPIO6_BASE_ADDR, #endif #endif @@ -349,13 +349,17 @@ static const struct mxc_gpio_plat mxc_plat[] = { { 1, (struct gpio_regs *)GPIO2_BASE_ADDR }, { 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ - defined(CONFIG_MX53) || defined(CONFIG_MX6) + defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ + defined(CONFIG_MX8M) { 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, #endif -#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) +#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ + defined(CONFIG_MX8M) { 4, (struct gpio_regs *)GPIO5_BASE_ADDR }, +#ifndef CONFIG_MX8M { 5, (struct gpio_regs *)GPIO6_BASE_ADDR }, #endif +#endif #if defined(CONFIG_MX53) || defined(CONFIG_MX6) { 6, (struct gpio_regs *)GPIO7_BASE_ADDR }, #endif @@ -366,13 +370,17 @@ U_BOOT_DEVICES(mxc_gpios) = { { "gpio_mxc", &mxc_plat[1] }, { "gpio_mxc", &mxc_plat[2] }, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ - defined(CONFIG_MX53) || defined(CONFIG_MX6) + defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ + defined(CONFIG_MX8M) { "gpio_mxc", &mxc_plat[3] }, #endif -#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) +#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ + defined(CONFIG_MX8M) { "gpio_mxc", &mxc_plat[4] }, +#ifndef CONFIG_MX8M { "gpio_mxc", &mxc_plat[5] }, #endif +#endif #if defined(CONFIG_MX53) || defined(CONFIG_MX6) { "gpio_mxc", &mxc_plat[6] }, #endif From patchwork Wed Jan 10 05:20:43 2018 Content-Type: text/plain; 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Accessing these register will cause system hang. Signed-off-by: Peng Fan Acked-by: Joe Hershberger Reviewed-by: Stefano Babic Reviewed-by: Fabio Estevam Reviewed-by: Stefano Babic --- drivers/net/fec_mxc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 433e19f0f8..4cbc8cbbfd 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -562,8 +562,8 @@ static int fec_init(struct eth_device *dev, bd_t *bd) writel(0x00000000, &fec->eth->gaddr1); writel(0x00000000, &fec->eth->gaddr2); - /* Do not access reserved register for i.MX6UL */ - if (!is_mx6ul() && !is_mx6ull()) { + /* Do not access reserved register */ + if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) { /* clear MIB RAM */ for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) writel(0, i); From patchwork Wed Jan 10 05:20:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857961 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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This patch eliminates the warnings by using ulong/long type which is 32bits on 32bits system or 64bits on 64bits system. Signed-off-by: Ye Li Signed-off-by: Peng Fan Acked-by: Joe Hershberger Reviewed-by: Stefano Babic Reviewed-by: Fabio Estevam --- drivers/net/fec_mxc.c | 74 ++++++++++++++++++++++++++++++--------------------- 1 file changed, 43 insertions(+), 31 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 4cbc8cbbfd..ff7ad91116 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -284,7 +284,7 @@ static int fec_tx_task_disable(struct fec_priv *fec) static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) { uint32_t size; - uint8_t *data; + ulong data; int i; /* @@ -293,9 +293,9 @@ static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) */ size = roundup(dsize, ARCH_DMA_MINALIGN); for (i = 0; i < count; i++) { - data = (uint8_t *)fec->rbd_base[i].data_pointer; - memset(data, 0, dsize); - flush_dcache_range((uint32_t)data, (uint32_t)data + size); + data = fec->rbd_base[i].data_pointer; + memset((void *)data, 0, dsize); + flush_dcache_range(data, data + size); fec->rbd_base[i].status = FEC_RBD_EMPTY; fec->rbd_base[i].data_length = 0; @@ -305,8 +305,8 @@ static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; fec->rbd_index = 0; - flush_dcache_range((unsigned)fec->rbd_base, - (unsigned)fec->rbd_base + size); + flush_dcache_range((ulong)fec->rbd_base, + (ulong)fec->rbd_base + size); } /** @@ -323,7 +323,7 @@ static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) */ static void fec_tbd_init(struct fec_priv *fec) { - unsigned addr = (unsigned)fec->tbd_base; + ulong addr = (ulong)fec->tbd_base; unsigned size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); @@ -423,7 +423,7 @@ static int fec_open(struct eth_device *edev) struct fec_priv *fec = (struct fec_priv *)edev->priv; #endif int speed; - uint32_t addr, size; + ulong addr, size; int i; debug("fec_open: fec_open(dev)\n"); @@ -439,7 +439,7 @@ static int fec_open(struct eth_device *edev) /* Flush the descriptors into RAM */ size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); - addr = (uint32_t)fec->rbd_base; + addr = (ulong)fec->rbd_base; flush_dcache_range(addr, addr + size); #ifdef FEC_QUIRK_ENET_MAC @@ -533,8 +533,9 @@ static int fec_init(struct eth_device *dev, bd_t *bd) #else struct fec_priv *fec = (struct fec_priv *)dev->priv; #endif - uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; - int i; + u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop; + u8 *i; + ulong addr; /* Initialize MAC address */ #ifdef CONFIG_DM_ETH @@ -574,8 +575,12 @@ static int fec_init(struct eth_device *dev, bd_t *bd) /* size and address of each buffer */ writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); - writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); - writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); + + addr = (ulong)fec->tbd_base; + writel((uint32_t)addr, &fec->eth->etdsr); + + addr = (ulong)fec->rbd_base; + writel((uint32_t)addr, &fec->eth->erdsr); #ifndef CONFIG_PHYLIB if (fec->xcv_type != SEVENWIRE) @@ -640,8 +645,8 @@ static int fec_send(struct eth_device *dev, void *packet, int length) #endif { unsigned int status; - uint32_t size, end; - uint32_t addr; + u32 size; + ulong addr, end; int timeout = FEC_XFER_TIMEOUT; int ret = 0; @@ -672,13 +677,13 @@ static int fec_send(struct eth_device *dev, void *packet, int length) swap_packet((uint32_t *)packet, length); #endif - addr = (uint32_t)packet; + addr = (ulong)packet; end = roundup(addr + length, ARCH_DMA_MINALIGN); addr &= ~(ARCH_DMA_MINALIGN - 1); flush_dcache_range(addr, end); writew(length, &fec->tbd_base[fec->tbd_index].data_length); - writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer); + writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer); /* * update BD's status now @@ -698,7 +703,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length) * can start DMA. */ size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); - addr = (uint32_t)fec->tbd_base; + addr = (ulong)fec->tbd_base; flush_dcache_range(addr, addr + size); /* @@ -799,7 +804,7 @@ static int fec_recv(struct eth_device *dev) unsigned long ievent; int frame_length, len = 0; uint16_t bd_status; - uint32_t addr, size, end; + ulong addr, size, end; int i; ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); @@ -854,7 +859,7 @@ static int fec_recv(struct eth_device *dev) * the descriptor. The solution is to mark the whole cache line when all * descriptors in the cache line are processed. */ - addr = (uint32_t)rbd; + addr = (ulong)rbd; addr &= ~(ARCH_DMA_MINALIGN - 1); size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); invalidate_dcache_range(addr, addr + size); @@ -882,8 +887,8 @@ static int fec_recv(struct eth_device *dev) len = frame_length; } else { if (bd_status & FEC_RBD_ERR) - debug("error frame: 0x%08x 0x%08x\n", - addr, bd_status); + debug("error frame: 0x%08lx 0x%08x\n", + addr, bd_status); } /* @@ -895,7 +900,7 @@ static int fec_recv(struct eth_device *dev) size = RXDESC_PER_CACHELINE - 1; if ((fec->rbd_index & size) == size) { i = fec->rbd_index - size; - addr = (uint32_t)&fec->rbd_base[i]; + addr = (ulong)&fec->rbd_base[i]; for (; i <= fec->rbd_index ; i++) { fec_rbd_clean(i == (FEC_RBD_NUM - 1), &fec->rbd_base[i]); @@ -922,6 +927,7 @@ static int fec_alloc_descs(struct fec_priv *fec) unsigned int size; int i; uint8_t *data; + ulong addr; /* Allocate TX descriptors. */ size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); @@ -950,11 +956,12 @@ static int fec_alloc_descs(struct fec_priv *fec) memset(data, 0, size); - fec->rbd_base[i].data_pointer = (uint32_t)data; + addr = (ulong)data; + fec->rbd_base[i].data_pointer = (uint32_t)addr; fec->rbd_base[i].status = FEC_RBD_EMPTY; fec->rbd_base[i].data_length = 0; /* Flush the buffer to memory. */ - flush_dcache_range((uint32_t)data, (uint32_t)data + size); + flush_dcache_range(addr, addr + size); } /* Mark the last RBD to close the ring. */ @@ -966,8 +973,10 @@ static int fec_alloc_descs(struct fec_priv *fec) return 0; err_ring: - for (; i >= 0; i--) - free((void *)fec->rbd_base[i].data_pointer); + for (; i >= 0; i--) { + addr = fec->rbd_base[i].data_pointer; + free((void *)addr); + } free(fec->rbd_base); err_rx: free(fec->tbd_base); @@ -978,9 +987,12 @@ err_tx: static void fec_free_descs(struct fec_priv *fec) { int i; + ulong addr; - for (i = 0; i < FEC_RBD_NUM; i++) - free((void *)fec->rbd_base[i].data_pointer); + for (i = 0; i < FEC_RBD_NUM; i++) { + addr = fec->rbd_base[i].data_pointer; + free((void *)addr); + } free(fec->rbd_base); free(fec->tbd_base); } @@ -995,7 +1007,7 @@ struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) struct fec_priv *priv = dev_get_priv(dev); struct ethernet_regs *eth = priv->eth; #else - struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; + struct ethernet_regs *eth = (struct ethernet_regs *)(ulong)base_addr; #endif struct mii_dev *bus; int ret; @@ -1065,7 +1077,7 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, edev->halt = fec_halt; edev->write_hwaddr = fec_set_hwaddr; - fec->eth = (struct ethernet_regs *)base_addr; + fec->eth = (struct ethernet_regs *)(ulong)base_addr; fec->bd = bd; fec->xcv_type = CONFIG_FEC_XCV_TYPE; From patchwork Wed Jan 10 05:20:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857964 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Signed-off-by: Peng Fan Reviewed-by: Fabio Estevam Cc: Stefano Babic --- arch/arm/dts/fsl-imx8-ca53.dtsi | 92 +++++ arch/arm/dts/fsl-imx8mq.dtsi | 429 ++++++++++++++++++++ include/dt-bindings/clock/imx8mq-clock.h | 612 +++++++++++++++++++++++++++++ include/dt-bindings/pinctrl/pins-imx8mq.h | 632 ++++++++++++++++++++++++++++++ 4 files changed, 1765 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8-ca53.dtsi create mode 100644 arch/arm/dts/fsl-imx8mq.dtsi create mode 100644 include/dt-bindings/clock/imx8mq-clock.h create mode 100644 include/dt-bindings/pinctrl/pins-imx8mq.h diff --git a/arch/arm/dts/fsl-imx8-ca53.dtsi b/arch/arm/dts/fsl-imx8-ca53.dtsi new file mode 100644 index 0000000000..6a2292a51e --- /dev/null +++ b/arch/arm/dts/fsl-imx8-ca53.dtsi @@ -0,0 +1,92 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/{ + cpus { + #address-cells = <2>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0000000>; + entry-latency-us = <700>; + exit-latency-us = <250>; + min-residency-us = <1000>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1000000>; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + + /* We have 1 clusters having 4 Cortex-A53 cores */ + A53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0xc4000002>; + cpu_on = <0xc4000003>; + }; +}; diff --git a/arch/arm/dts/fsl-imx8mq.dtsi b/arch/arm/dts/fsl-imx8mq.dtsi new file mode 100644 index 0000000000..814a1b7df4 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq.dtsi @@ -0,0 +1,429 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8-ca53.dtsi" +#include +#include +#include +#include +#include +#include + +/ { + compatible = "fsl,imx8mq"; + interrupt-parent = <&gpc>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x00000000 0x40000000 0 0xc0000000>; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + interrupt-parent = <&gic>; + }; + + power: power-controller { + compatible = "fsl,imx8mq-pm-domain"; + num-domains = <11>; + #power-domain-cells = <1>; + }; + + pwm2: pwm@30670000 { + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x30670000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, + <&clk IMX8MQ_CLK_PWM2_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + gpio1: gpio@30200000 { + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30200000 0x0 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30210000 0x0 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30220000 0x0 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30230000 0x0 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30240000 0x0 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + tmu: tmu@30260000 { + compatible = "fsl,imx8mq-tmu"; + reg = <0x0 0x30260000 0x0 0x10000>; + interrupt = ; + little-endian; + u-boot,dm-pre-reloc; + fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>; + fsl,tmu-calibration = <0x00000000 0x00000020 + 0x00000001 0x00000028 + 0x00000002 0x00000030 + 0x00000003 0x00000038 + 0x00000004 0x00000040 + 0x00000005 0x00000048 + 0x00000006 0x00000050 + 0x00000007 0x00000058 + 0x00000008 0x00000060 + 0x00000009 0x00000068 + 0x0000000a 0x00000070 + 0x0000000b 0x00000077 + + 0x00010000 0x00000057 + 0x00010001 0x0000005b + 0x00010002 0x0000005f + 0x00010003 0x00000063 + 0x00010004 0x00000067 + 0x00010005 0x0000006b + 0x00010006 0x0000006f + 0x00010007 0x00000073 + 0x00010008 0x00000077 + 0x00010009 0x0000007b + 0x0001000a 0x0000007f + + 0x00020000 0x00000002 + 0x00020001 0x0000000e + 0x00020002 0x0000001a + 0x00020003 0x00000026 + 0x00020004 0x00000032 + 0x00020005 0x0000003e + 0x00020006 0x0000004a + 0x00020007 0x00000056 + 0x00020008 0x00000062 + + 0x00030000 0x00000000 + 0x00030001 0x00000008 + 0x00030002 0x00000010 + 0x00030003 0x00000018 + 0x00030004 0x00000020 + 0x00030005 0x00000028 + 0x00030006 0x00000030 + 0x00030007 0x00000038>; + #thermal-sensor-cells = <0>; + }; + + thermal-zones { + /* cpu thermal */ + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + lcdif: lcdif@30320000 { + compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; + reg = <0x0 0x30320000 0x0 0x10000>; + clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; + assigned-clock-rate = <594000000>; + interrupts = ; + status = "disabled"; + }; + + iomuxc: iomuxc@30330000 { + compatible = "fsl,imx8mq-iomuxc"; + reg = <0x0 0x30330000 0x0 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon"; + reg = <0x0 0x30340000 0x0 0x10000>; + }; + + ocotp: ocotp-ctrl@30350000 { + compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon"; + reg = <0x0 0x30350000 0x0 0x10000>; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx8mq-anatop", "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x0 0x30360000 0x0 0x10000>; + interrupts = ; + }; + + clk: ccm@30380000 { + compatible = "fsl,imx8mq-ccm"; + reg = <0x0 0x30380000 0x0 0x10000>; + interrupts = , + ; + #clock-cells = <1>; + }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon"; + reg = <0x0 0x303a0000 0x0 0x10000>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + usdhc1: usdhc@30b40000 { + compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + reg = <0x0 0x30b40000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MQ_CLK_USDHC1_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: usdhc@30b50000 { + compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + reg = <0x0 0x30b50000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MQ_CLK_USDHC2_ROOT>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + fec1: ethernet@30be0000 { + compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; + reg = <0x0 0x30be0000 0x0 0x10000>; + interrupts = , + , + ; + clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, + <&clk IMX8MQ_CLK_ENET1_ROOT>, + <&clk IMX8MQ_CLK_ENET_TIMER_DIV>, + <&clk IMX8MQ_CLK_ENET_REF_DIV>, + <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>, + <&clk IMX8MQ_CLK_ENET_TIMER_SRC>, + <&clk IMX8MQ_CLK_ENET_REF_SRC>, + <&clk IMX8MQ_CLK_ENET_TIMER_DIV>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_125M>; + assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + stop-mode = <&gpr 0x10 3>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + fsl,wakeup_irq = <2>; + status = "disabled"; + }; + + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + + i2c1: i2c@30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx21-i2c"; + reg = <0x0 0x30a20000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx21-i2c"; + reg = <0x0 0x30a30000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx21-i2c"; + reg = <0x0 0x30a40000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx21-i2c"; + reg = <0x0 0x30a50000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; + status = "disabled"; + }; + + wdog1: wdog@30280000 { + compatible = "fsl,imx21-wdt"; + reg = <0 0x30280000 0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; + status = "disabled"; + }; + + wdog2: wdog@30290000 { + compatible = "fsl,imx21-wdt"; + reg = <0 0x30290000 0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; + status = "disabled"; + }; + + wdog3: wdog@302a0000 { + compatible = "fsl,imx21-wdt"; + reg = <0 0x302a0000 0 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; + status = "disabled"; + }; + + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + + qspi: qspi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-qspi"; + reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, + <&clk IMX8MQ_CLK_QSPI_ROOT>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; +}; + +&A53_0 { + #cooling-cells = <2>; +}; diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h new file mode 100644 index 0000000000..11dcafcfde --- /dev/null +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -0,0 +1,612 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H +#define __DT_BINDINGS_CLOCK_IMX8MQ_H + +#define IMX8MQ_CLK_DUMMY 0 +#define IMX8MQ_CLK_32K 1 +#define IMX8MQ_CLK_25M 2 +#define IMX8MQ_CLK_27M 3 +#define IMX8MQ_CLK_EXT1 4 +#define IMX8MQ_CLK_EXT2 5 +#define IMX8MQ_CLK_EXT3 6 +#define IMX8MQ_CLK_EXT4 7 + +/* ANAMIX PLL clocks */ +/* FRAC PLLs */ +/* ARM PLL */ +#define IMX8MQ_ARM_PLL_REF_SEL 8 +#define IMX8MQ_ARM_PLL_REF_DIV 9 +#define IMX8MQ_ARM_PLL 10 +#define IMX8MQ_ARM_PLL_BYPASS 11 +#define IMX8MQ_ARM_PLL_OUT 12 + +/* GPU PLL */ +#define IMX8MQ_GPU_PLL_REF_SEL 13 +#define IMX8MQ_GPU_PLL_REF_DIV 14 +#define IMX8MQ_GPU_PLL 15 +#define IMX8MQ_GPU_PLL_BYPASS 16 +#define IMX8MQ_GPU_PLL_OUT 17 + +/* VPU PLL */ +#define IMX8MQ_VPU_PLL_REF_SEL 18 +#define IMX8MQ_VPU_PLL_REF_DIV 19 +#define IMX8MQ_VPU_PLL 20 +#define IMX8MQ_VPU_PLL_BYPASS 21 +#define IMX8MQ_VPU_PLL_OUT 22 + +/* AUDIO PLL1 */ +#define IMX8MQ_AUDIO_PLL1_REF_SEL 23 +#define IMX8MQ_AUDIO_PLL1_REF_DIV 24 +#define IMX8MQ_AUDIO_PLL1 25 +#define IMX8MQ_AUDIO_PLL1_BYPASS 26 +#define IMX8MQ_AUDIO_PLL1_OUT 27 + +/* AUDIO PLL2 */ +#define IMX8MQ_AUDIO_PLL2_REF_SEL 28 +#define IMX8MQ_AUDIO_PLL2_REF_DIV 29 +#define IMX8MQ_AUDIO_PLL2 30 +#define IMX8MQ_AUDIO_PLL2_BYPASS 31 +#define IMX8MQ_AUDIO_PLL2_OUT 32 + +/* VIDEO PLL1 */ +#define IMX8MQ_VIDEO_PLL1_REF_SEL 33 +#define IMX8MQ_VIDEO_PLL1_REF_DIV 34 +#define IMX8MQ_VIDEO_PLL1 35 +#define IMX8MQ_VIDEO_PLL1_BYPASS 36 +#define IMX8MQ_VIDEO_PLL1_OUT 37 + +/* SYS1 PLL */ +#define IMX8MQ_SYS1_PLL1_REF_SEL 38 +#define IMX8MQ_SYS1_PLL1_REF_DIV 39 +#define IMX8MQ_SYS1_PLL1 40 +#define IMX8MQ_SYS1_PLL1_OUT 41 +#define IMX8MQ_SYS1_PLL1_OUT_DIV 42 +#define IMX8MQ_SYS1_PLL2 43 +#define IMX8MQ_SYS1_PLL2_DIV 44 +#define IMX8MQ_SYS1_PLL2_OUT 45 + +/* SYS2 PLL */ +#define IMX8MQ_SYS2_PLL1_REF_SEL 46 +#define IMX8MQ_SYS2_PLL1_REF_DIV 47 +#define IMX8MQ_SYS2_PLL1 48 +#define IMX8MQ_SYS2_PLL1_OUT 49 +#define IMX8MQ_SYS2_PLL1_OUT_DIV 50 +#define IMX8MQ_SYS2_PLL2 51 +#define IMX8MQ_SYS2_PLL2_DIV 52 +#define IMX8MQ_SYS2_PLL2_OUT 53 + +/* SYS3 PLL */ +#define IMX8MQ_SYS3_PLL1_REF_SEL 54 +#define IMX8MQ_SYS3_PLL1_REF_DIV 55 +#define IMX8MQ_SYS3_PLL1 56 +#define IMX8MQ_SYS3_PLL1_OUT 57 +#define IMX8MQ_SYS3_PLL1_OUT_DIV 58 +#define IMX8MQ_SYS3_PLL2 59 +#define IMX8MQ_SYS3_PLL2_DIV 60 +#define IMX8MQ_SYS3_PLL2_OUT 61 + +/* DRAM PLL */ +#define IMX8MQ_DRAM_PLL1_REF_SEL 62 +#define IMX8MQ_DRAM_PLL1_REF_DIV 63 +#define IMX8MQ_DRAM_PLL1 64 +#define IMX8MQ_DRAM_PLL1_OUT 65 +#define IMX8MQ_DRAM_PLL1_OUT_DIV 66 +#define IMX8MQ_DRAM_PLL2 67 +#define IMX8MQ_DRAM_PLL2_DIV 68 +#define IMX8MQ_DRAM_PLL2_OUT 69 + +/* SYS PLL DIV */ +#define IMX8MQ_SYS1_PLL_40M 70 +#define IMX8MQ_SYS1_PLL_80M 71 +#define IMX8MQ_SYS1_PLL_100M 72 +#define IMX8MQ_SYS1_PLL_133M 73 +#define IMX8MQ_SYS1_PLL_160M 74 +#define IMX8MQ_SYS1_PLL_200M 75 +#define IMX8MQ_SYS1_PLL_266M 76 +#define IMX8MQ_SYS1_PLL_400M 77 +#define IMX8MQ_SYS1_PLL_800M 78 + +#define IMX8MQ_SYS2_PLL_50M 79 +#define IMX8MQ_SYS2_PLL_100M 80 +#define IMX8MQ_SYS2_PLL_125M 81 +#define IMX8MQ_SYS2_PLL_166M 82 +#define IMX8MQ_SYS2_PLL_200M 83 +#define IMX8MQ_SYS2_PLL_250M 84 +#define IMX8MQ_SYS2_PLL_333M 85 +#define IMX8MQ_SYS2_PLL_500M 86 +#define IMX8MQ_SYS2_PLL_1000M 87 + +/* CCM ROOT clocks */ +/* A53 */ +#define IMX8MQ_CLK_A53_SRC 88 +#define IMX8MQ_CLK_A53_CG 89 +#define IMX8MQ_CLK_A53_DIV 90 +/* M4 */ +#define IMX8MQ_CLK_M4_SRC 91 +#define IMX8MQ_CLK_M4_CG 92 +#define IMX8MQ_CLK_M4_DIV 93 +/* VPU */ +#define IMX8MQ_CLK_VPU_SRC 94 +#define IMX8MQ_CLK_VPU_CG 95 +#define IMX8MQ_CLK_VPU_DIV 96 +/* GPU CORE */ +#define IMX8MQ_CLK_GPU_CORE_SRC 97 +#define IMX8MQ_CLK_GPU_CORE_CG 98 +#define IMX8MQ_CLK_GPU_CORE_DIV 99 +/* GPU SHADER */ +#define IMX8MQ_CLK_GPU_SHADER_SRC 100 +#define IMX8MQ_CLK_GPU_SHADER_CG 101 +#define IMX8MQ_CLK_GPU_SHADER_DIV 102 + +/* BUS TYPE */ +/* MAIN AXI */ +#define IMX8MQ_CLK_MAIN_AXI_SRC 103 +#define IMX8MQ_CLK_MAIN_AXI_CG 104 +#define IMX8MQ_CLK_MAIN_AXI_PRE_DIV 105 +#define IMX8MQ_CLK_MAIN_AXI_DIV 106 +/* ENET AXI */ +#define IMX8MQ_CLK_ENET_AXI_SRC 107 +#define IMX8MQ_CLK_ENET_AXI_CG 108 +#define IMX8MQ_CLK_ENET_AXI_PRE_DIV 109 +#define IMX8MQ_CLK_ENET_AXI_DIV 110 +/* NAND_USDHC_BUS */ +#define IMX8MQ_CLK_NAND_USDHC_BUS_SRC 111 +#define IMX8MQ_CLK_NAND_USDHC_BUS_CG 112 +#define IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV 113 +#define IMX8MQ_CLK_NAND_USDHC_BUS_DIV 114 +/* VPU BUS */ +#define IMX8MQ_CLK_VPU_BUS_SRC 115 +#define IMX8MQ_CLK_VPU_BUS_CG 116 +#define IMX8MQ_CLK_VPU_BUS_PRE_DIV 117 +#define IMX8MQ_CLK_VPU_BUS_DIV 118 +/* DISP_AXI */ +#define IMX8MQ_CLK_DISP_AXI_SRC 119 +#define IMX8MQ_CLK_DISP_AXI_CG 120 +#define IMX8MQ_CLK_DISP_AXI_PRE_DIV 121 +#define IMX8MQ_CLK_DISP_AXI_DIV 122 +/* DISP APB */ +#define IMX8MQ_CLK_DISP_APB_SRC 123 +#define IMX8MQ_CLK_DISP_APB_CG 124 +#define IMX8MQ_CLK_DISP_APB_PRE_DIV 125 +#define IMX8MQ_CLK_DISP_APB_DIV 126 +/* DISP RTRM */ +#define IMX8MQ_CLK_DISP_RTRM_SRC 127 +#define IMX8MQ_CLK_DISP_RTRM_CG 128 +#define IMX8MQ_CLK_DISP_RTRM_PRE_DIV 129 +#define IMX8MQ_CLK_DISP_RTRM_DIV 130 +/* USB_BUS */ +#define IMX8MQ_CLK_USB_BUS_SRC 131 +#define IMX8MQ_CLK_USB_BUS_CG 132 +#define IMX8MQ_CLK_USB_BUS_PRE_DIV 133 +#define IMX8MQ_CLK_USB_BUS_DIV 134 +/* GPU_AXI */ +#define IMX8MQ_CLK_GPU_AXI_SRC 135 +#define IMX8MQ_CLK_GPU_AXI_CG 136 +#define IMX8MQ_CLK_GPU_AXI_PRE_DIV 137 +#define IMX8MQ_CLK_GPU_AXI_DIV 138 +/* GPU_AHB */ +#define IMX8MQ_CLK_GPU_AHB_SRC 139 +#define IMX8MQ_CLK_GPU_AHB_CG 140 +#define IMX8MQ_CLK_GPU_AHB_PRE_DIV 141 +#define IMX8MQ_CLK_GPU_AHB_DIV 142 +/* NOC */ +#define IMX8MQ_CLK_NOC_SRC 143 +#define IMX8MQ_CLK_NOC_CG 144 +#define IMX8MQ_CLK_NOC_PRE_DIV 145 +#define IMX8MQ_CLK_NOC_DIV 146 +/* NOC_APB */ +#define IMX8MQ_CLK_NOC_APB_SRC 147 +#define IMX8MQ_CLK_NOC_APB_CG 148 +#define IMX8MQ_CLK_NOC_APB_PRE_DIV 149 +#define IMX8MQ_CLK_NOC_APB_DIV 150 + +/* AHB */ +#define IMX8MQ_CLK_AHB_SRC 151 +#define IMX8MQ_CLK_AHB_CG 152 +#define IMX8MQ_CLK_AHB_PRE_DIV 153 +#define IMX8MQ_CLK_AHB_DIV 154 +/* AUDIO AHB */ +#define IMX8MQ_CLK_AUDIO_AHB_SRC 155 +#define IMX8MQ_CLK_AUDIO_AHB_CG 156 +#define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV 157 +#define IMX8MQ_CLK_AUDIO_AHB_DIV 158 + +/* DRAM_ALT */ +#define IMX8MQ_CLK_DRAM_ALT_SRC 159 +#define IMX8MQ_CLK_DRAM_ALT_CG 160 +#define IMX8MQ_CLK_DRAM_ALT_PRE_DIV 161 +#define IMX8MQ_CLK_DRAM_ALT_DIV 162 +/* DRAM APB */ +#define IMX8MQ_CLK_DRAM_APB_SRC 163 +#define IMX8MQ_CLK_DRAM_APB_CG 164 +#define IMX8MQ_CLK_DRAM_APB_PRE_DIV 165 +#define IMX8MQ_CLK_DRAM_APB_DIV 166 +/* VPU_G1 */ +#define IMX8MQ_CLK_VPU_G1_SRC 167 +#define IMX8MQ_CLK_VPU_G1_CG 168 +#define IMX8MQ_CLK_VPU_G1_PRE_DIV 169 +#define IMX8MQ_CLK_VPU_G1_DIV 170 +/* VPU_G2 */ +#define IMX8MQ_CLK_VPU_G2_SRC 171 +#define IMX8MQ_CLK_VPU_G2_CG 172 +#define IMX8MQ_CLK_VPU_G2_PRE_DIV 173 +#define IMX8MQ_CLK_VPU_G2_DIV 174 +/* DISP_DTRC */ +#define IMX8MQ_CLK_DISP_DTRC_SRC 175 +#define IMX8MQ_CLK_DISP_DTRC_CG 176 +#define IMX8MQ_CLK_DISP_DTRC_PRE_DIV 177 +#define IMX8MQ_CLK_DISP_DTRC_DIV 178 +/* DISP_DC8000 */ +#define IMX8MQ_CLK_DISP_DC8000_SRC 179 +#define IMX8MQ_CLK_DISP_DC8000_CG 180 +#define IMX8MQ_CLK_DISP_DC8000_PRE_DIV 181 +#define IMX8MQ_CLK_DISP_DC8000_DIV 182 +/* PCIE_CTRL */ +#define IMX8MQ_CLK_PCIE1_CTRL_SRC 183 +#define IMX8MQ_CLK_PCIE1_CTRL_CG 184 +#define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV 185 +#define IMX8MQ_CLK_PCIE1_CTRL_DIV 186 +/* PCIE_PHY */ +#define IMX8MQ_CLK_PCIE1_PHY_SRC 187 +#define IMX8MQ_CLK_PCIE1_PHY_CG 188 +#define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV 189 +#define IMX8MQ_CLK_PCIE1_PHY_DIV 190 +/* PCIE_AUX */ +#define IMX8MQ_CLK_PCIE1_AUX_SRC 191 +#define IMX8MQ_CLK_PCIE1_AUX_CG 192 +#define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV 193 +#define IMX8MQ_CLK_PCIE1_AUX_DIV 194 +/* DC_PIXEL */ +#define IMX8MQ_CLK_DC_PIXEL_SRC 195 +#define IMX8MQ_CLK_DC_PIXEL_CG 196 +#define IMX8MQ_CLK_DC_PIXEL_PRE_DIV 197 +#define IMX8MQ_CLK_DC_PIXEL_DIV 198 +/* LCDIF_PIXEL */ +#define IMX8MQ_CLK_LCDIF_PIXEL_SRC 199 +#define IMX8MQ_CLK_LCDIF_PIXEL_CG 200 +#define IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV 201 +#define IMX8MQ_CLK_LCDIF_PIXEL_DIV 202 +/* SAI1~6 */ +#define IMX8MQ_CLK_SAI1_SRC 203 +#define IMX8MQ_CLK_SAI1_CG 204 +#define IMX8MQ_CLK_SAI1_PRE_DIV 205 +#define IMX8MQ_CLK_SAI1_DIV 206 + +#define IMX8MQ_CLK_SAI2_SRC 207 +#define IMX8MQ_CLK_SAI2_CG 208 +#define IMX8MQ_CLK_SAI2_PRE_DIV 209 +#define IMX8MQ_CLK_SAI2_DIV 210 + +#define IMX8MQ_CLK_SAI3_SRC 211 +#define IMX8MQ_CLK_SAI3_CG 212 +#define IMX8MQ_CLK_SAI3_PRE_DIV 213 +#define IMX8MQ_CLK_SAI3_DIV 214 + +#define IMX8MQ_CLK_SAI4_SRC 215 +#define IMX8MQ_CLK_SAI4_CG 216 +#define IMX8MQ_CLK_SAI4_PRE_DIV 217 +#define IMX8MQ_CLK_SAI4_DIV 218 + +#define IMX8MQ_CLK_SAI5_SRC 219 +#define IMX8MQ_CLK_SAI5_CG 220 +#define IMX8MQ_CLK_SAI5_PRE_DIV 221 +#define IMX8MQ_CLK_SAI5_DIV 222 + +#define IMX8MQ_CLK_SAI6_SRC 223 +#define IMX8MQ_CLK_SAI6_CG 224 +#define IMX8MQ_CLK_SAI6_PRE_DIV 225 +#define IMX8MQ_CLK_SAI6_DIV 226 +/* SPDIF1 */ +#define IMX8MQ_CLK_SPDIF1_SRC 227 +#define IMX8MQ_CLK_SPDIF1_CG 228 +#define IMX8MQ_CLK_SPDIF1_PRE_DIV 229 +#define IMX8MQ_CLK_SPDIF1_DIV 230 +/* SPDIF2 */ +#define IMX8MQ_CLK_SPDIF2_SRC 231 +#define IMX8MQ_CLK_SPDIF2_CG 232 +#define IMX8MQ_CLK_SPDIF2_PRE_DIV 233 +#define IMX8MQ_CLK_SPDIF2_DIV 234 +/* ENET_REF */ +#define IMX8MQ_CLK_ENET_REF_SRC 235 +#define IMX8MQ_CLK_ENET_REF_CG 236 +#define IMX8MQ_CLK_ENET_REF_PRE_DIV 237 +#define IMX8MQ_CLK_ENET_REF_DIV 238 +/* ENET_TIMER */ +#define IMX8MQ_CLK_ENET_TIMER_SRC 239 +#define IMX8MQ_CLK_ENET_TIMER_CG 240 +#define IMX8MQ_CLK_ENET_TIMER_PRE_DIV 241 +#define IMX8MQ_CLK_ENET_TIMER_DIV 242 +/* ENET_PHY */ +#define IMX8MQ_CLK_ENET_PHY_REF_SRC 243 +#define IMX8MQ_CLK_ENET_PHY_REF_CG 244 +#define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV 245 +#define IMX8MQ_CLK_ENET_PHY_REF_DIV 246 +/* NAND */ +#define IMX8MQ_CLK_NAND_SRC 247 +#define IMX8MQ_CLK_NAND_CG 248 +#define IMX8MQ_CLK_NAND_PRE_DIV 249 +#define IMX8MQ_CLK_NAND_DIV 250 +/* QSPI */ +#define IMX8MQ_CLK_QSPI_SRC 251 +#define IMX8MQ_CLK_QSPI_CG 252 +#define IMX8MQ_CLK_QSPI_PRE_DIV 253 +#define IMX8MQ_CLK_QSPI_DIV 254 +/* USDHC1 */ +#define IMX8MQ_CLK_USDHC1_SRC 255 +#define IMX8MQ_CLK_USDHC1_CG 256 +#define IMX8MQ_CLK_USDHC1_PRE_DIV 257 +#define IMX8MQ_CLK_USDHC1_DIV 258 +/* USDHC2 */ +#define IMX8MQ_CLK_USDHC2_SRC 259 +#define IMX8MQ_CLK_USDHC2_CG 260 +#define IMX8MQ_CLK_USDHC2_PRE_DIV 261 +#define IMX8MQ_CLK_USDHC2_DIV 262 +/* I2C1 */ +#define IMX8MQ_CLK_I2C1_SRC 263 +#define IMX8MQ_CLK_I2C1_CG 264 +#define IMX8MQ_CLK_I2C1_PRE_DIV 265 +#define IMX8MQ_CLK_I2C1_DIV 266 +/* I2C2 */ +#define IMX8MQ_CLK_I2C2_SRC 267 +#define IMX8MQ_CLK_I2C2_CG 268 +#define IMX8MQ_CLK_I2C2_PRE_DIV 269 +#define IMX8MQ_CLK_I2C2_DIV 270 +/* I2C3 */ +#define IMX8MQ_CLK_I2C3_SRC 271 +#define IMX8MQ_CLK_I2C3_CG 272 +#define IMX8MQ_CLK_I2C3_PRE_DIV 273 +#define IMX8MQ_CLK_I2C3_DIV 274 +/* I2C4 */ +#define IMX8MQ_CLK_I2C4_SRC 275 +#define IMX8MQ_CLK_I2C4_CG 276 +#define IMX8MQ_CLK_I2C4_PRE_DIV 277 +#define IMX8MQ_CLK_I2C4_DIV 278 +/* UART1 */ +#define IMX8MQ_CLK_UART1_SRC 279 +#define IMX8MQ_CLK_UART1_CG 280 +#define IMX8MQ_CLK_UART1_PRE_DIV 281 +#define IMX8MQ_CLK_UART1_DIV 282 +/* UART2 */ +#define IMX8MQ_CLK_UART2_SRC 283 +#define IMX8MQ_CLK_UART2_CG 284 +#define IMX8MQ_CLK_UART2_PRE_DIV 285 +#define IMX8MQ_CLK_UART2_DIV 286 +/* UART3 */ +#define IMX8MQ_CLK_UART3_SRC 287 +#define IMX8MQ_CLK_UART3_CG 288 +#define IMX8MQ_CLK_UART3_PRE_DIV 289 +#define IMX8MQ_CLK_UART3_DIV 290 +/* UART4 */ +#define IMX8MQ_CLK_UART4_SRC 291 +#define IMX8MQ_CLK_UART4_CG 292 +#define IMX8MQ_CLK_UART4_PRE_DIV 293 +#define IMX8MQ_CLK_UART4_DIV 294 +/* USB_CORE_REF */ +#define IMX8MQ_CLK_USB_CORE_REF_SRC 295 +#define IMX8MQ_CLK_USB_CORE_REF_CG 296 +#define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV 297 +#define IMX8MQ_CLK_USB_CORE_REF_DIV 298 +/* USB_PHY_REF */ +#define IMX8MQ_CLK_USB_PHY_REF_SRC 299 +#define IMX8MQ_CLK_USB_PHY_REF_CG 300 +#define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV 301 +#define IMX8MQ_CLK_USB_PHY_REF_DIV 302 +/* ECSPI1 */ +#define IMX8MQ_CLK_ECSPI1_SRC 303 +#define IMX8MQ_CLK_ECSPI1_CG 304 +#define IMX8MQ_CLK_ECSPI1_PRE_DIV 305 +#define IMX8MQ_CLK_ECSPI1_DIV 306 +/* ECSPI2 */ +#define IMX8MQ_CLK_ECSPI2_SRC 307 +#define IMX8MQ_CLK_ECSPI2_CG 308 +#define IMX8MQ_CLK_ECSPI2_PRE_DIV 309 +#define IMX8MQ_CLK_ECSPI2_DIV 310 +/* PWM1 */ +#define IMX8MQ_CLK_PWM1_SRC 311 +#define IMX8MQ_CLK_PWM1_CG 312 +#define IMX8MQ_CLK_PWM1_PRE_DIV 313 +#define IMX8MQ_CLK_PWM1_DIV 314 +/* PWM2 */ +#define IMX8MQ_CLK_PWM2_SRC 315 +#define IMX8MQ_CLK_PWM2_CG 316 +#define IMX8MQ_CLK_PWM2_PRE_DIV 317 +#define IMX8MQ_CLK_PWM2_DIV 318 +/* PWM3 */ +#define IMX8MQ_CLK_PWM3_SRC 319 +#define IMX8MQ_CLK_PWM3_CG 320 +#define IMX8MQ_CLK_PWM3_PRE_DIV 321 +#define IMX8MQ_CLK_PWM3_DIV 322 +/* PWM4 */ +#define IMX8MQ_CLK_PWM4_SRC 323 +#define IMX8MQ_CLK_PWM4_CG 324 +#define IMX8MQ_CLK_PWM4_PRE_DIV 325 +#define IMX8MQ_CLK_PWM4_DIV 326 +/* GPT1 */ +#define IMX8MQ_CLK_GPT1_SRC 327 +#define IMX8MQ_CLK_GPT1_CG 328 +#define IMX8MQ_CLK_GPT1_PRE_DIV 329 +#define IMX8MQ_CLK_GPT1_DIV 330 +/* WDOG */ +#define IMX8MQ_CLK_WDOG_SRC 331 +#define IMX8MQ_CLK_WDOG_CG 332 +#define IMX8MQ_CLK_WDOG_PRE_DIV 333 +#define IMX8MQ_CLK_WDOG_DIV 334 +/* WRCLK */ +#define IMX8MQ_CLK_WRCLK_SRC 335 +#define IMX8MQ_CLK_WRCLK_CG 336 +#define IMX8MQ_CLK_WRCLK_PRE_DIV 337 +#define IMX8MQ_CLK_WRCLK_DIV 338 +/* DSI_CORE */ +#define IMX8MQ_CLK_DSI_CORE_SRC 339 +#define IMX8MQ_CLK_DSI_CORE_CG 340 +#define IMX8MQ_CLK_DSI_CORE_PRE_DIV 341 +#define IMX8MQ_CLK_DSI_CORE_DIV 342 +/* DSI_PHY */ +#define IMX8MQ_CLK_DSI_PHY_REF_SRC 343 +#define IMX8MQ_CLK_DSI_PHY_REF_CG 344 +#define IMX8MQ_CLK_DSI_PHY_REF_PRE_DIV 345 +#define IMX8MQ_CLK_DSI_PHY_REF_DIV 346 +/* DSI_DBI */ +#define IMX8MQ_CLK_DSI_DBI_SRC 347 +#define IMX8MQ_CLK_DSI_DBI_CG 348 +#define IMX8MQ_CLK_DSI_DBI_PRE_DIV 349 +#define IMX8MQ_CLK_DSI_DBI_DIV 350 +/*DSI_ESC */ +#define IMX8MQ_CLK_DSI_ESC_SRC 351 +#define IMX8MQ_CLK_DSI_ESC_CG 352 +#define IMX8MQ_CLK_DSI_ESC_PRE_DIV 353 +#define IMX8MQ_CLK_DSI_ESC_DIV 354 +/* CSI1_CORE */ +#define IMX8MQ_CLK_CSI1_CORE_SRC 355 +#define IMX8MQ_CLK_CSI1_CORE_CG 356 +#define IMX8MQ_CLK_CSI1_CORE_PRE_DIV 357 +#define IMX8MQ_CLK_CSI1_CORE_DIV 358 +/* CSI1_PHY */ +#define IMX8MQ_CLK_CSI1_PHY_REF_SRC 359 +#define IMX8MQ_CLK_CSI1_PHY_REF_CG 360 +#define IMX8MQ_CLK_CSI1_PHY_REF_PRE_DIV 361 +#define IMX8MQ_CLK_CSI1_PHY_REF_DIV 362 +/* CSI_ESC */ +#define IMX8MQ_CLK_CSI1_ESC_SRC 363 +#define IMX8MQ_CLK_CSI1_ESC_CG 364 +#define IMX8MQ_CLK_CSI1_ESC_PRE_DIV 365 +#define IMX8MQ_CLK_CSI1_ESC_DIV 366 +/* CSI2_CORE */ +#define IMX8MQ_CLK_CSI2_CORE_SRC 367 +#define IMX8MQ_CLK_CSI2_CORE_CG 368 +#define IMX8MQ_CLK_CSI2_CORE_PRE_DIV 369 +#define IMX8MQ_CLK_CSI2_CORE_DIV 370 +/* CSI2_PHY */ +#define IMX8MQ_CLK_CSI2_PHY_REF_SRC 371 +#define IMX8MQ_CLK_CSI2_PHY_REF_CG 372 +#define IMX8MQ_CLK_CSI2_PHY_REF_PRE_DIV 373 +#define IMX8MQ_CLK_CSI2_PHY_REF_DIV 374 +/* CSI2_ESC */ +#define IMX8MQ_CLK_CSI2_ESC_SRC 375 +#define IMX8MQ_CLK_CSI2_ESC_CG 376 +#define IMX8MQ_CLK_CSI2_ESC_PRE_DIV 377 +#define IMX8MQ_CLK_CSI2_ESC_DIV 378 +/* PCIE2_CTRL */ +#define IMX8MQ_CLK_PCIE2_CTRL_SRC 379 +#define IMX8MQ_CLK_PCIE2_CTRL_CG 380 +#define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV 381 +#define IMX8MQ_CLK_PCIE2_CTRL_DIV 382 +/* PCIE2_PHY */ +#define IMX8MQ_CLK_PCIE2_PHY_SRC 383 +#define IMX8MQ_CLK_PCIE2_PHY_CG 384 +#define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV 385 +#define IMX8MQ_CLK_PCIE2_PHY_DIV 386 +/* PCIE2_AUX */ +#define IMX8MQ_CLK_PCIE2_AUX_SRC 387 +#define IMX8MQ_CLK_PCIE2_AUX_CG 388 +#define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV 389 +#define IMX8MQ_CLK_PCIE2_AUX_DIV 390 +/* ECSPI3 */ +#define IMX8MQ_CLK_ECSPI3_SRC 391 +#define IMX8MQ_CLK_ECSPI3_CG 392 +#define IMX8MQ_CLK_ECSPI3_PRE_DIV 393 +#define IMX8MQ_CLK_ECSPI3_DIV 394 + +/* CCGR clocks */ +#define IMX8MQ_CLK_A53_ROOT 395 +#define IMX8MQ_CLK_DRAM_ROOT 396 +#define IMX8MQ_CLK_ECSPI1_ROOT 397 +#define IMX8MQ_CLK_ECSPI2_ROOT 398 +#define IMX8MQ_CLK_ECSPI3_ROOT 399 +#define IMX8MQ_CLK_ENET1_ROOT 400 +#define IMX8MQ_CLK_GPT1_ROOT 401 +#define IMX8MQ_CLK_I2C1_ROOT 402 +#define IMX8MQ_CLK_I2C2_ROOT 403 +#define IMX8MQ_CLK_I2C3_ROOT 404 +#define IMX8MQ_CLK_I2C4_ROOT 405 +#define IMX8MQ_CLK_M4_ROOT 406 +#define IMX8MQ_CLK_PCIE1_ROOT 407 +#define IMX8MQ_CLK_PCIE2_ROOT 408 +#define IMX8MQ_CLK_PWM1_ROOT 409 +#define IMX8MQ_CLK_PWM2_ROOT 410 +#define IMX8MQ_CLK_PWM3_ROOT 411 +#define IMX8MQ_CLK_PWM4_ROOT 412 +#define IMX8MQ_CLK_QSPI_ROOT 413 +#define IMX8MQ_CLK_SAI1_ROOT 414 +#define IMX8MQ_CLK_SAI2_ROOT 415 +#define IMX8MQ_CLK_SAI3_ROOT 416 +#define IMX8MQ_CLK_SAI4_ROOT 417 +#define IMX8MQ_CLK_SAI5_ROOT 418 +#define IMX8MQ_CLK_SAI6_ROOT 419 +#define IMX8MQ_CLK_UART1_ROOT 420 +#define IMX8MQ_CLK_UART2_ROOT 421 +#define IMX8MQ_CLK_UART3_ROOT 422 +#define IMX8MQ_CLK_UART4_ROOT 423 +#define IMX8MQ_CLK_USB1_CTRL_ROOT 424 +#define IMX8MQ_CLK_USB2_CTRL_ROOT 425 +#define IMX8MQ_CLK_USB1_PHY_ROOT 426 +#define IMX8MQ_CLK_USB2_PHY_ROOT 427 +#define IMX8MQ_CLK_USDHC1_ROOT 428 +#define IMX8MQ_CLK_USDHC2_ROOT 429 +#define IMX8MQ_CLK_WDOG1_ROOT 430 +#define IMX8MQ_CLK_WDOG2_ROOT 431 +#define IMX8MQ_CLK_WDOG3_ROOT 432 +#define IMX8MQ_CLK_GPU_ROOT 433 +#define IMX8MQ_CLK_HEVC_ROOT 434 +#define IMX8MQ_CLK_AVC_ROOT 435 +#define IMX8MQ_CLK_VP9_ROOT 436 +#define IMX8MQ_CLK_HEVC_INTER_ROOT 437 +#define IMX8MQ_CLK_DISP_ROOT 438 +#define IMX8MQ_CLK_HDMI_ROOT 439 +#define IMX8MQ_CLK_HDMI_PHY_ROOT 440 +#define IMX8MQ_CLK_VPU_DEC_ROOT 441 +#define IMX8MQ_CLK_CSI1_ROOT 442 +#define IMX8MQ_CLK_CSI2_ROOT 443 +#define IMX8MQ_CLK_RAWNAND_ROOT 444 +#define IMX8MQ_CLK_SDMA1_ROOT 445 +#define IMX8MQ_CLK_SDMA2_ROOT 446 +#define IMX8MQ_CLK_VPU_G1_ROOT 447 +#define IMX8MQ_CLK_VPU_G2_ROOT 448 + +/* SCCG PLL GATE */ +#define IMX8MQ_SYS1_PLL_OUT 449 +#define IMX8MQ_SYS2_PLL_OUT 450 +#define IMX8MQ_SYS3_PLL_OUT 451 +#define IMX8MQ_DRAM_PLL_OUT 452 + +#define IMX8MQ_GPT_3M_CLK 453 + +#define IMX8MQ_CLK_IPG_ROOT 454 +#define IMX8MQ_CLK_IPG_AUDIO_ROOT 455 +#define IMX8MQ_CLK_SAI1_IPG 456 +#define IMX8MQ_CLK_SAI2_IPG 457 +#define IMX8MQ_CLK_SAI3_IPG 458 +#define IMX8MQ_CLK_SAI4_IPG 459 +#define IMX8MQ_CLK_SAI5_IPG 460 +#define IMX8MQ_CLK_SAI6_IPG 461 + +/* DSI AHB/IPG clocks */ +/* rxesc clock */ +#define IMX8MQ_CLK_DSI_AHB_SRC 462 +#define IMX8MQ_CLK_DSI_AHB_CG 463 +#define IMX8MQ_CLK_DSI_AHB_PRE_DIV 464 +#define IMX8MQ_CLK_DSI_AHB_DIV 465 +/* txesc clock */ +#define IMX8MQ_CLK_DSI_IPG_DIV 466 + +/* VIDEO2 PLL */ +#define IMX8MQ_VIDEO2_PLL1_REF_SEL 467 +#define IMX8MQ_VIDEO2_PLL1_REF_DIV 468 +#define IMX8MQ_VIDEO2_PLL1 469 +#define IMX8MQ_VIDEO2_PLL1_OUT 470 +#define IMX8MQ_VIDEO2_PLL1_OUT_DIV 471 +#define IMX8MQ_VIDEO2_PLL2 472 +#define IMX8MQ_VIDEO2_PLL2_DIV 473 +#define IMX8MQ_VIDEO2_PLL2_OUT 474 +#define IMX8MQ_CLK_TMU_ROOT 475 + +#define IMX8MQ_CLK_END 476 +#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ diff --git a/include/dt-bindings/pinctrl/pins-imx8mq.h b/include/dt-bindings/pinctrl/pins-imx8mq.h new file mode 100644 index 0000000000..0e1d67d414 --- /dev/null +++ b/include/dt-bindings/pinctrl/pins-imx8mq.h @@ -0,0 +1,632 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DTS_IMX8MQ_PINFUNC_H +#define __DTS_IMX8MQ_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ + +#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 +#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 +#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 +#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 +#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 +#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 +#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 +#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 +#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 +#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 +#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 +#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 +#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 +#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 +#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 +#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 +#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 +#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 +#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 +#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 +#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 +#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0 + +#endif /* __DTS_IMX8MQ_PINFUNC_H */ From patchwork Wed Jan 10 05:20:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857972 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="kGP7zr+i"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zGdFt0wkhz9s7n for ; Wed, 10 Jan 2018 16:42:58 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B6DC8C22083; Wed, 10 Jan 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SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jan 2018 05:22:28.9981 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c68d4b20-5461-433c-001f-08d557ea2620 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR04MB3221 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH V5 29/31] power: pmic/regulator allow dm be omitted by SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Allow the dm driver be omitted by SPL. Signed-off-by: Peng Fan Reviewed-by: Simon Glass Cc: Jaehoon Chung Cc: Stefano Babic Reviewed-by: Jaehoon Chung --- drivers/power/pmic/Makefile | 2 +- drivers/power/regulator/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 7d6c583d34..fc19fdc701 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -8,7 +8,7 @@ obj-$(CONFIG_DM_PMIC) += pmic-uclass.o obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o -obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o +obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o obj-$(CONFIG_PMIC_ACT8846) += act8846.o diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 7a2e76dc82..353177d5f4 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o -obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o +obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o From patchwork Wed Jan 10 05:20:47 2018 Content-Type: text/plain; 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Signed-off-by: Peng Fan Cc: Fabio Estevam Cc: Stefano Babic --- arch/arm/include/asm/arch-mx8m/ddr.h | 356 +++++++++++++++++++++++++++++++++++ 1 file changed, 356 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx8m/ddr.h diff --git a/arch/arm/include/asm/arch-mx8m/ddr.h b/arch/arm/include/asm/arch-mx8m/ddr.h new file mode 100644 index 0000000000..b37382eab0 --- /dev/null +++ b/arch/arm/include/asm/arch-mx8m/ddr.h @@ -0,0 +1,356 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MX8M_DDR_H +#define __ASM_ARCH_MX8M_DDR_H + +#define DDRC_DDR_SS_GPR0 0x3d000000 +#define DDRC_IPS_BASE_ADDR_0 0x3f400000 +#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) +#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000) + +struct ddrc_freq { + u32 res0[8]; + u32 derateen; + u32 derateint; + u32 res1[10]; + u32 rfshctl0; + u32 res2[4]; + u32 rfshtmg; + u32 rfshtmg1; + u32 res3[28]; + u32 init3; + u32 init4; + u32 res; + u32 init6; + u32 init7; + u32 res4[4]; + u32 dramtmg0; + u32 dramtmg1; + u32 dramtmg2; + u32 dramtmg3; + u32 dramtmg4; + u32 dramtmg5; + u32 dramtmg6; + u32 dramtmg7; + u32 dramtmg8; + u32 dramtmg9; + u32 dramtmg10; + u32 dramtmg11; + u32 dramtmg12; + u32 dramtmg13; + u32 dramtmg14; + u32 dramtmg15; + u32 dramtmg16; + u32 dramtmg17; + u32 res5[10]; + u32 mramtmg0; + u32 mramtmg1; + u32 mramtmg4; + u32 mramtmg9; + u32 zqctl0; + u32 res6[3]; + u32 dfitmg0; + u32 dfitmg1; + u32 res7[7]; + u32 dfitmg2; + u32 dfitmg3; + u32 res8[33]; + u32 odtcfg; +}; + +struct imx8m_ddrc_regs { + u32 mstr; + u32 stat; + u32 mstr1; + u32 res1; + u32 mrctrl0; + u32 mrctrl1; + u32 mrstat; + u32 mrctrl2; + u32 derateen; + u32 derateint; + u32 mstr2; + u32 res2; + u32 pwrctl; + u32 pwrtmg; + u32 hwlpctl; + u32 hwffcctl; + u32 hwffcstat; + u32 res3[3]; + u32 rfshctl0; + u32 rfshctl1; + u32 rfshctl2; + u32 rfshctl4; + u32 rfshctl3; + u32 rfshtmg; + u32 rfshtmg1; + u32 res4; + u32 ecccfg0; + u32 ecccfg1; + u32 eccstat; + u32 eccclr; + u32 eccerrcnt; + u32 ecccaddr0; + u32 ecccaddr1; + u32 ecccsyn0; + u32 ecccsyn1; + u32 ecccsyn2; + u32 eccbitmask0; + u32 eccbitmask1; + u32 eccbitmask2; + u32 eccuaddr0; + u32 eccuaddr1; + u32 eccusyn0; + u32 eccusyn1; + u32 eccusyn2; + u32 eccpoisonaddr0; + u32 eccpoisonaddr1; + u32 crcparctl0; + u32 crcparctl1; + u32 crcparctl2; + u32 crcparstat; + u32 init0; + u32 init1; + u32 init2; + u32 init3; + u32 init4; + u32 init5; + u32 init6; + u32 init7; + u32 dimmctl; + u32 rankctl; + u32 res5; + u32 chctl; + u32 dramtmg0; + u32 dramtmg1; + u32 dramtmg2; + u32 dramtmg3; + u32 dramtmg4; + u32 dramtmg5; + u32 dramtmg6; + u32 dramtmg7; + u32 dramtmg8; + u32 dramtmg9; + u32 dramtmg10; + u32 dramtmg11; + u32 dramtmg12; + u32 dramtmg13; + u32 dramtmg14; + u32 dramtmg15; + u32 dramtmg16; + u32 dramtmg17; + u32 res6[10]; + u32 mramtmg0; + u32 mramtmg1; + u32 mramtmg4; + u32 mramtmg9; + u32 zqctl0; + u32 zqctl1; + u32 zqctl2; + u32 zqstat; + u32 dfitmg0; + u32 dfitmg1; + u32 dfilpcfg0; + u32 dfilpcfg1; + u32 dfiupd0; + u32 dfiupd1; + u32 dfiupd2; + u32 res7; + u32 dfimisc; + u32 dfitmg2; + u32 dfitmg3; + u32 dfistat; + u32 dbictl; + u32 dfiphymstr; + u32 res8[14]; + u32 addrmap0; + u32 addrmap1; + u32 addrmap2; + u32 addrmap3; + u32 addrmap4; + u32 addrmap5; + u32 addrmap6; + u32 addrmap7; + u32 addrmap8; + u32 addrmap9; + u32 addrmap10; + u32 addrmap11; + u32 res9[4]; + u32 odtcfg; + u32 odtmap; + u32 res10[2]; + u32 sched; + u32 sched1; + u32 sched2; + u32 perfhpr1; + u32 res11; + u32 perflpr1; + u32 res12; + u32 perfwr1; + u32 res13[4]; + u32 dqmap0; + u32 dqmap1; + u32 dqmap2; + u32 dqmap3; + u32 dqmap4; + u32 dqmap5; + u32 res14[26]; + u32 dbg0; + u32 dbg1; + u32 dbgcam; + u32 dbgcmd; + u32 dbgstat; + u32 res15[3]; + u32 swctl; + u32 swstat; + u32 res16[2]; + u32 ocparcfg0; + u32 ocparcfg1; + u32 ocparcfg2; + u32 ocparcfg3; + u32 ocparstat0; + u32 ocparstat1; + u32 ocparwlog0; + u32 ocparwlog1; + u32 ocparwlog2; + u32 ocparawlog0; + u32 ocparawlog1; + u32 ocparrlog0; + u32 ocparrlog1; + u32 ocpararlog0; + u32 ocpararlog1; + u32 poisoncfg; + u32 poisonstat; + u32 adveccindex; + union { + u32 adveccstat; + u32 eccapstat; + }; + u32 eccpoisonpat0; + u32 eccpoisonpat1; + u32 eccpoisonpat2; + u32 res17[6]; + u32 caparpoisonctl; + u32 caparpoisonstat; + u32 res18[2]; + u32 dynbsmstat; + u32 res19[18]; + u32 pstat; + u32 pccfg; + struct { + u32 pcfgr; + u32 pcfgw; + u32 pcfgc; + struct { + u32 pcfgidmaskch0; + u32 pcfidvaluech0; + } pcfgid[16]; + u32 pctrl; + u32 pcfgqos0; + u32 pcfgqos1; + u32 pcfgwqos0; + u32 pcfgwqos1; + u32 res[4]; + } pcfg[16]; + struct { + u32 sarbase; + u32 sarsize; + } sar[4]; + u32 sbrctl; + u32 sbrstat; + u32 sbrwdata0; + u32 sbrwdata1; + u32 pdch; + u32 res20[755]; + /* umctl2_regs_dch1 */ + u32 ch1_stat; + u32 res21[2]; + u32 ch1_mrctrl0; + u32 ch1_mrctrl1; + u32 ch1_mrstat; + u32 ch1_mrctrl2; + u32 res22[4]; + u32 ch1_pwrctl; + u32 ch1_pwrtmg; + u32 ch1_hwlpctl; + u32 res23[15]; + u32 ch1_eccstat; + u32 ch1_eccclr; + u32 ch1_eccerrcnt; + u32 ch1_ecccaddr0; + u32 ch1_ecccaddr1; + u32 ch1_ecccsyn0; + u32 ch1_ecccsyn1; + u32 ch1_ecccsyn2; + u32 ch1_eccbitmask0; + u32 ch1_eccbitmask1; + u32 ch1_eccbitmask2; + u32 ch1_eccuaddr0; + u32 ch1_eccuaddr1; + u32 ch1_eccusyn0; + u32 ch1_eccusyn1; + u32 ch1_eccusyn2; + u32 res24[2]; + u32 ch1_crcparctl0; + u32 res25[2]; + u32 ch1_crcparstat; + u32 res26[46]; + u32 ch1_zqctl2; + u32 ch1_zqstat; + u32 res27[11]; + u32 ch1_dfistat; + u32 res28[33]; + u32 ch1_odtmap; + u32 res29[47]; + u32 ch1_dbg1; + u32 ch1_dbgcam; + u32 ch1_dbgcmd; + u32 ch1_dbgstat; + u32 res30[123]; + /* umctl2_regs_freq1 */ + struct ddrc_freq freq1; + u32 res31[109]; + /* umctl2_regs_addrmap_alt */ + u32 addrmap0_alt; + u32 addrmap1_alt; + u32 addrmap2_alt; + u32 addrmap3_alt; + u32 addrmap4_alt; + u32 addrmap5_alt; + u32 addrmap6_alt; + u32 addrmap7_alt; + u32 addrmap8_alt; + u32 addrmap9_alt; + u32 addrmap10_alt; + u32 addrmap11_alt; + u32 res32[758]; + /* umctl2_regs_freq2 */ + struct ddrc_freq freq2; + u32 res33[879]; + /* umctl2_regs_freq3 */ + struct ddrc_freq freq3; +}; + +struct imx8m_ddrphy_regs { + u32 reg[0xf0000]; +}; + +/* PHY State */ +enum pstate { + PS0, + PS1, + PS2, + PS3, +}; + +enum msg_response { + TRAIN_SUCCESS = 0x7, + TRAIN_STREAM_START = 0x8, + TRAIN_FAIL = 0xff, +}; + +#endif From patchwork Wed Jan 10 05:20:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 857974 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="KWsAsFza"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zGdG51TBkz9s7n for ; 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DB6PR04MB3221; 6:gZsWK9eLK/s0o/hRizRSFf3kHdQ4IBmr8Ww368SsRpmscQAh89m1FKB4aRkfFC4OA3aHmVyFZke4b6JotOp5KzgG1q6N+13WeW1Hle2OSUGnb3hSXR6xuQX8c9WGrkdS60h9sy+Bw7AoYGHgibq6hZ9r6+fWLJ8K8jSv2zh3jNBKUnHvH9cR3bQWkiJZq4xZn7QuxnwgR6TnnxB6KJnAEk44taVa5PtiztTjJEO4Y4493Ju6+mDGY78lZthtQrkYVz3HdUzSAFtAUPR7E/DSAAln8qrhI5d8fapztf8gFfAYvFHPZ8eHgIxL7JjIQoKUW5THvyS2k0UwlFkoV4U0b9fLEWviZIocn5+8lAJIf1k=; 5:f4wFCbupiRaccI+sCBsIFr+ROAlCT+xIsxq7jBk5Sy/PNFDHuGIW9mO6+5wL9wmJsZJJJQSQh0YttBUTJ5Dnm645iivnKqiMAUYmqV0g+hyHlzbGHUUTZPAyt7fhrmRS6nP9EQQ8SNhiC4kKwHZe6tXs9R6R+7ueY3Z/LBfN3+8=; 24:PugkObUn0oF6po6Kcg90XQR8zP82YKPeF+jkttdG7jeeczmm/oPjIYeE2iT2iiWktNwRp9/FW7ci8ch0251JteHjavxx1m7PNH1cLgOTLjc=; 7:CFb8TCgxOHOfOjphl9SiE1ogeQcyvo/JQjl4J3Pp1QJt/eEGAax5oB2NQpeBgpVUqQBKDo7jsMdb0qmH74bz2BNwEi9u5PXSAtymSlxhmh+HNfsHtQ2xSDKE4zj+ON2q7iY8s3DGdqOcDmoUu1+aJ9A1aYDfzu7L73yL6MlO7EDMJwYyGT6TjpPvi10gG2Q8INnRUNP4cVlMj0N24TY+23GSpof18iC9Gl3yfJXV+swntdNtYo9qtsfHw04KO9tk SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jan 2018 05:22:35.1545 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 82e7c210-6742-4efa-b295-08d557ea299b X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR04MB3221 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH V5 31/31] imx: add i.MX8MQ EVK support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to DRAM. The boot log with Arm trusted firmware console enabled: " U-Boot SPL 2018.01-00038-gbd426c08ea (Jan 10 2018 - 13:14:56) PMIC: PFUZE100 ID=0x10 Normal Boot Trying to boot from MMC2 NOTICE: Configureing TZASC380 NOTICE: BL31: v1.4(release):o8.0.0_1.3.0_8m-prc-20171211-6-g54fb0797-dirty NOTICE: BL31: Built : 07:17:16, Jan 8 2018 NOTICE: sip svc init U-Boot 2018.01-00038-gbd426c08ea (Jan 10 2018 - 13:14:56 +0800) CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz Reset cause: POR Model: Freescale i.MX8MQ EVK DRAM: 3 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Using default environment In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 u-boot=> " Signed-off-by: Peng Fan Cc: Fabio Estevam Cc: Stefano Babic --- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-imx8mq-evk.dts | 424 +++++++++ arch/arm/include/asm/arch-mx8m/ddr.h | 9 + arch/arm/mach-imx/mx8m/Kconfig | 12 + board/freescale/mx8mq_evk/Kconfig | 12 + board/freescale/mx8mq_evk/Makefile | 12 + board/freescale/mx8mq_evk/README | 47 + board/freescale/mx8mq_evk/ddr/ddr_init.c | 246 +++++ board/freescale/mx8mq_evk/ddr/ddrphy_train.c | 1272 ++++++++++++++++++++++++++ board/freescale/mx8mq_evk/ddr/helper.c | 101 ++ board/freescale/mx8mq_evk/mx8mq_evk.c | 156 ++++ board/freescale/mx8mq_evk/spl.c | 230 +++++ configs/mx8mq_evk_defconfig | 27 + include/configs/mx8mq_evk.h | 269 ++++++ 14 files changed, 2819 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8mq-evk.dts create mode 100644 board/freescale/mx8mq_evk/Kconfig create mode 100644 board/freescale/mx8mq_evk/Makefile create mode 100644 board/freescale/mx8mq_evk/README create mode 100644 board/freescale/mx8mq_evk/ddr/ddr_init.c create mode 100644 board/freescale/mx8mq_evk/ddr/ddrphy_train.c create mode 100644 board/freescale/mx8mq_evk/ddr/helper.c create mode 100644 board/freescale/mx8mq_evk/mx8mq_evk.c create mode 100644 board/freescale/mx8mq_evk/spl.c create mode 100644 configs/mx8mq_evk_defconfig create mode 100644 include/configs/mx8mq_evk.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a895c70284..299107977f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -391,6 +391,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb +dtb-$(CONFIG_ARCH_MX8M) += fsl-imx8mq-evk.dtb + dtb-$(CONFIG_RCAR_GEN3) += \ r8a7795-h3ulcb.dtb \ r8a7795-salvator-x.dtb \ diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts new file mode 100644 index 0000000000..f0aa3485e6 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq-evk.dts @@ -0,0 +1,424 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x40000000 0x00020000; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ EVK"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + ledpwm2 { + label = "PWM2"; + pwms = <&pwm2 0 50000>; + max-brightness = <255>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mq-evk { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-disabled; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&lcdif { + status = "okay"; + disp-dev = "mipi_dsi_northwest"; + display = <&display0>; + + display0: display@0 { + bits-per-pixel = <24>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: n25q256a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/include/asm/arch-mx8m/ddr.h b/arch/arm/include/asm/arch-mx8m/ddr.h index b37382eab0..11016c9278 100644 --- a/arch/arm/include/asm/arch-mx8m/ddr.h +++ b/arch/arm/include/asm/arch-mx8m/ddr.h @@ -353,4 +353,13 @@ enum msg_response { TRAIN_FAIL = 0xff, }; +enum fw_type { + FW_1D_IMAGE, + FW_2D_IMAGE, +}; + +void ddr_init(void); +void ddr_load_train_code(enum fw_type type); +void lpddr4_800M_cfg_phy(void); +void dram_pll_init(void); #endif diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig index 3a84c2f2b0..e3b57b7915 100644 --- a/arch/arm/mach-imx/mx8m/Kconfig +++ b/arch/arm/mach-imx/mx8m/Kconfig @@ -7,4 +7,16 @@ config MX8M config SYS_SOC default "mx8m" +choice + prompt "NXP i.MX8M board select" + optional + +config TARGET_MX8MQ_EVK + bool "mx8mq_evk" + select MX8M + +endchoice + +source "board/freescale/mx8mq_evk/Kconfig" + endif diff --git a/board/freescale/mx8mq_evk/Kconfig b/board/freescale/mx8mq_evk/Kconfig new file mode 100644 index 0000000000..4e23002803 --- /dev/null +++ b/board/freescale/mx8mq_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX8MQ_EVK + +config SYS_BOARD + default "mx8mq_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx8mq_evk" + +endif diff --git a/board/freescale/mx8mq_evk/Makefile b/board/freescale/mx8mq_evk/Makefile new file mode 100644 index 0000000000..286396ee96 --- /dev/null +++ b/board/freescale/mx8mq_evk/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += mx8mq_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/helper.o +endif diff --git a/board/freescale/mx8mq_evk/README b/board/freescale/mx8mq_evk/README new file mode 100644 index 0000000000..e214401a8a --- /dev/null +++ b/board/freescale/mx8mq_evk/README @@ -0,0 +1,47 @@ +U-Boot for the NXP i.MX8MQ EVK board + +Quick Start +==================== +- Build the ARM Trusted firmware binary +- Build U-Boot +- Get ddr fimware and tools +- Generate flash.bin using imx-mkimage +- Boot + +Get and Build the ARM Trusted firmware +==================== +Get ATF from: https://source.codeaurora.org/external/imx/imx-atf +$ make PLAT=imx8mq bl31 + +Build U-Boot +==================== +$ export ARCH=arm64 +$ export CROSS_COMPILE=aarch64-poky-linux- +$ make mx8mq_evk_defconfig +$ make + +Get the ddr firmware and tools +==================== +Note: Better to use NXP released yocto to get the firmware in case + there is new releases. +https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.2.bin +imx-mkimage: https://source.codeaurora.org/external/imx/imx-mkimage/ + +Generate flash.bin using imx-mkimage +==================== +Copy bl31.bin u-boot-nodtb.bin u-boot-spl.bin fsl-imx8mq-evk.dtb to + imx-mkimage/iMX8M +Copy lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_imem.bin + lpddr4_pmu_train_2d_dmem.bin lpddr4_pmu_train_2d_imem.bin to + imx-mkimage/iMX8M +If you want to run with HDMI, copy signed_hdmi_imx8m.bin to imx-mkimage/iMX8M + +make SOC=iMX8M flash_hdmi_spl_uboot or make SOC=iMX8M flash_spl_uboot to +generate flash.bin. + +Burn the flash.bin to MicroSD card offset 33KB +$sudo dd if=iMX8M/flash.bin of=/dev/sd[x] bs=1024 seek=33 + +Boot +==================== +Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD. diff --git a/board/freescale/mx8mq_evk/ddr/ddr_init.c b/board/freescale/mx8mq_evk/ddr/ddr_init.c new file mode 100644 index 0000000000..9ff4341bd9 --- /dev/null +++ b/board/freescale/mx8mq_evk/ddr/ddr_init.c @@ -0,0 +1,246 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +struct imx8m_ddrc_regs *ddrc_regs = (struct imx8m_ddrc_regs *)DDRC_IPS_BASE_ADDR(0); +static struct gpc_reg *gpc_reg = (struct gpc_reg *)GPC_BASE_ADDR; +static struct src *src = (struct src *)SRC_BASE_ADDR; + +void lpddr4_800mhz_cfg_umctl2(void) +{ + writel(0x00000001, &ddrc_regs->dbg1); + writel(0x00000001, &ddrc_regs->pwrctl); + writel(0x83080020, &ddrc_regs->mstr); + writel(0x006180e0, &ddrc_regs->rfshtmg); + writel(0xc003061b, &ddrc_regs->init0); + writel(0x009d0000, &ddrc_regs->init1); + writel(0x0000fe05, &ddrc_regs->init2); + writel(0x00d4002d, &ddrc_regs->init3); + writel(0x00310008, &ddrc_regs->init4); + writel(0x00040009, &ddrc_regs->init5); + writel(0x0046004d, &ddrc_regs->init6); + writel(0x0005004d, &ddrc_regs->init7); + writel(0x00000979, &ddrc_regs->rankctl); + writel(0x1a203522, &ddrc_regs->dramtmg0); + writel(0x00060630, &ddrc_regs->dramtmg1); + writel(0x070e1214, &ddrc_regs->dramtmg2); + writel(0x00b0c006, &ddrc_regs->dramtmg3); + writel(0x0f04080f, &ddrc_regs->dramtmg4); + writel(0x0d0d0c0c, &ddrc_regs->dramtmg5); + writel(0x01010007, &ddrc_regs->dramtmg6); + writel(0x0000060a, &ddrc_regs->dramtmg7); + writel(0x01010101, &ddrc_regs->dramtmg8); + writel(0x40000008, &ddrc_regs->dramtmg9); + writel(0x00050d01, &ddrc_regs->dramtmg10); + writel(0x01010008, &ddrc_regs->dramtmg11); + writel(0x00020000, &ddrc_regs->dramtmg12); + writel(0x18100002, &ddrc_regs->dramtmg13); + writel(0x00000dc2, &ddrc_regs->dramtmg14); + writel(0x80000000, &ddrc_regs->dramtmg15); + writel(0x00a00050, &ddrc_regs->dramtmg17); + writel(0x53200018, &ddrc_regs->zqctl0); + writel(0x02800070, &ddrc_regs->zqctl1); + writel(0x00000000, &ddrc_regs->zqctl2); + writel(0x0397820a, &ddrc_regs->dfitmg0); + writel(0x0397820a, &ddrc_regs->freq1.dfitmg0); + writel(0x0397820a, &ddrc_regs->freq2.dfitmg0); + writel(0x00020103, &ddrc_regs->dfitmg1); + writel(0xe0400018, &ddrc_regs->dfiupd0); + writel(0x00df00e4, &ddrc_regs->dfiupd1); + writel(0x00000000, &ddrc_regs->dfiupd2); + writel(0x00000011, &ddrc_regs->dfimisc); + writel(0x0000170a, &ddrc_regs->dfitmg2); + writel(0x00000001, &ddrc_regs->dbictl); + writel(0x00000000, &ddrc_regs->dfiphymstr); + /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */ + writel(0x00000015, &ddrc_regs->addrmap0); + writel(0x00001f1f, &ddrc_regs->addrmap4); + /* bank interleave */ + writel(0x00080808, &ddrc_regs->addrmap1); + writel(0x07070707, &ddrc_regs->addrmap5); + writel(0x08080707, &ddrc_regs->addrmap6); + writel(0x020f0c54, &ddrc_regs->odtcfg); + writel(0x00000000, &ddrc_regs->odtmap); + writel(0x00000001, &ddrc_regs->pcfg[0].pctrl); + + /* performance setting */ + writel(0x0b060908, &ddrc_regs->odtcfg); + writel(0x00000000, &ddrc_regs->odtmap); + writel(0x29511505, &ddrc_regs->sched); + writel(0x0000002c, &ddrc_regs->sched1); + writel(0x5900575b, &ddrc_regs->perfhpr1); + writel(0x900093e7, &ddrc_regs->perflpr1); + writel(0x02005574, &ddrc_regs->perfwr1); + writel(0x00000016, &ddrc_regs->dbg0); + writel(0x00000000, &ddrc_regs->dbg1); + writel(0x00000000, &ddrc_regs->dbgcmd); + writel(0x00000001, &ddrc_regs->swctl); + writel(0x00000011, &ddrc_regs->poisoncfg); + writel(0x00000111, &ddrc_regs->pccfg); + writel(0x000010f3, &ddrc_regs->pcfg[0].pcfgr); + writel(0x000072ff, &ddrc_regs->pcfg[0].pcfgw); + writel(0x00000001, &ddrc_regs->pcfg[0].pctrl); + writel(0x01110d00, &ddrc_regs->pcfg[0].pcfgqos0); + writel(0x00620790, &ddrc_regs->pcfg[0].pcfgqos1); + writel(0x00100001, &ddrc_regs->pcfg[0].pcfgwqos0); + writel(0x0000041f, &ddrc_regs->pcfg[0].pcfgwqos1); + writel(0x00000202, &ddrc_regs->freq1.derateen); + writel(0xec78f4b5, &ddrc_regs->freq1.derateint); + writel(0x00618040, &ddrc_regs->freq1.rfshctl0); + writel(0x00610090, &ddrc_regs->freq1.rfshtmg); +} + +void lpddr4_100mhz_cfg_umctl2(void) +{ + writel(0x0d0b010c, &ddrc_regs->freq1.dramtmg0); + writel(0x00030410, &ddrc_regs->freq1.dramtmg1); + writel(0x0305090c, &ddrc_regs->freq1.dramtmg2); + writel(0x00505006, &ddrc_regs->freq1.dramtmg3); + writel(0x05040305, &ddrc_regs->freq1.dramtmg4); + writel(0x0d0e0504, &ddrc_regs->freq1.dramtmg5); + writel(0x0a060004, &ddrc_regs->freq1.dramtmg6); + writel(0x0000090e, &ddrc_regs->freq1.dramtmg7); + writel(0x00000032, &ddrc_regs->freq1.dramtmg14); + writel(0x00000000, &ddrc_regs->freq1.dramtmg15); + writel(0x0036001b, &ddrc_regs->freq1.dramtmg17); + writel(0x7e9fbeb1, &ddrc_regs->freq1.derateint); + writel(0x0020d040, &ddrc_regs->freq1.rfshctl0); + writel(0x03818200, &ddrc_regs->freq1.dfitmg0); + writel(0x0a1a096c, &ddrc_regs->freq1.odtcfg); + writel(0x00000000, &ddrc_regs->freq1.dfitmg2); + writel(0x00038014, &ddrc_regs->freq1.rfshtmg); + writel(0x00840000, &ddrc_regs->freq1.init3); + writel(0x0000004d, &ddrc_regs->freq1.init6); + writel(0x0000004d, &ddrc_regs->freq1.init7); + writel(0x00310000, &ddrc_regs->freq1.init4); +} + +void lpddr4_25mhz_cfg_umctl2(void) +{ + writel(0x0d0b010c, &ddrc_regs->freq2.dramtmg0); + writel(0x00030410, &ddrc_regs->freq2.dramtmg1); + writel(0x0305090c, &ddrc_regs->freq2.dramtmg2); + writel(0x00505006, &ddrc_regs->freq2.dramtmg3); + writel(0x05040305, &ddrc_regs->freq2.dramtmg4); + writel(0x0d0e0504, &ddrc_regs->freq2.dramtmg5); + writel(0x0a060004, &ddrc_regs->freq2.dramtmg6); + writel(0x0000090e, &ddrc_regs->freq2.dramtmg7); + writel(0x00000032, &ddrc_regs->freq2.dramtmg14); + writel(0x00000000, &ddrc_regs->freq2.dramtmg15); + writel(0x0036001b, &ddrc_regs->freq2.dramtmg17); + writel(0x7e9fbeb1, &ddrc_regs->freq2.derateint); + writel(0x0020d040, &ddrc_regs->freq2.rfshctl0); + writel(0x03818200, &ddrc_regs->freq2.dfitmg0); + writel(0x0a1a096c, &ddrc_regs->freq2.odtcfg); + writel(0x00000000, &ddrc_regs->freq2.dfitmg2); + writel(0x0003800c, &ddrc_regs->freq2.rfshtmg); + writel(0x00840000, &ddrc_regs->freq2.init3); + writel(0x0000004d, &ddrc_regs->freq2.init6); + writel(0x0000004d, &ddrc_regs->freq2.init7); + writel(0x00310000, &ddrc_regs->freq2.init4); +} + +void ddr_init(void) +{ + int ret; + u32 val; + + /* change the clock source of dram_apb_clk_root */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(4) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); + + /* disable the clock gating */ + writel(0xFFFF, &gpc_reg->pgc_cpu_0_1_mapping); + setbits_le32(&gpc_reg->pu_pgc_up_trg, BIT(5)); + + writel(SRC_DDR2_ENABLE_MASK, &src->ddr2_rcr); + + dram_pll_init(); + + writel(SRC_DDR1_ENABLE_MASK | SRC_DDR1_RCR_PHY_RESET_MASK | + SRC_DDR1_RCR_CORE_RESET_N_MASK, &src->ddr1_rcr); + + /* Configure uMCTL2's registers */ + lpddr4_800mhz_cfg_umctl2(); + + writel(SRC_DDR1_ENABLE_MASK | SRC_DDR1_RCR_PHY_RESET_MASK, + &src->ddr1_rcr); + writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr); + + writel(0x00000000, &ddrc_regs->dbg1); + writel(0x000000a8, &ddrc_regs->pwrctl); + /* writel(0x0000018a, DDRC_PWRCTL(0), )*/ + writel(0x00000000, &ddrc_regs->swctl); + writel(0x01, DDRC_DDR_SS_GPR0); + writel(0x00000010, &ddrc_regs->dfimisc); + + /* Configure LPDDR4 PHY's registers */ + lpddr4_800M_cfg_phy(); + + writel(0x00000000, &ddrc_regs->rfshctl3); + writel(0x0000, &ddrc_regs->swctl); + /* + * ------------------- 9 ------------------- + * Set DFIMISC.dfi_init_start to 1 + * ----------------------------------------- + */ + writel(0x00000030, &ddrc_regs->dfimisc); + writel(0x0001, &ddrc_regs->swctl); + + /* wait DFISTAT.dfi_init_complete to 1 */ + ret = readl_poll_timeout(&ddrc_regs->dfistat, val, val & BIT(0), 1000); + if (ret) + puts("DFISTAT.dfi_init_complete timeout\n"); + + writel(0x0000, &ddrc_regs->swctl); + + /* clear DFIMISC.dfi_init_complete_en */ + writel(0x00000010, &ddrc_regs->dfimisc); + writel(0x00000011, &ddrc_regs->dfimisc); + writel(0x00000088, &ddrc_regs->pwrctl); + + /* + * set SWCTL.sw_done to enable quasi-dynamic register + * programming outside reset. + */ + writel(0x00000001, &ddrc_regs->swctl); + + /* wait SWSTAT.sw_done_ack to 1 */ + ret = readl_poll_timeout(&ddrc_regs->swstat, val, val & BIT(0), 1000); + if (ret) + puts("SWSTAT.sw_done timeout\n"); + + /* wait STAT.operating_mode([1:0] for ddr3) to normal state */ + ret = readl_poll_timeout(&ddrc_regs->stat, val, (val & 0x3) == 1, 1000); + if (ret) + puts("STAT.operating_mode timeout\n"); + + writel(0x00000088, &ddrc_regs->pwrctl); + + /* enable port 0 */ + writel(0x00000001, &ddrc_regs->pcfg[0].pctrl); + writel(0x00000000, &ddrc_regs->rfshctl3); + + writel(0x0, &ddrc_regs->swctl); + lpddr4_100mhz_cfg_umctl2(); + lpddr4_25mhz_cfg_umctl2(); + writel(0x1, &ddrc_regs->swctl); + + /* wait SWSTAT.sw_done_ack to 1 */ + ret = readl_poll_timeout(&ddrc_regs->swstat, val, val & BIT(0), 1000); + if (ret) + puts("SWSTAT.sw_done timeout\n"); + + writel(0x0, &ddrc_regs->swctl); +} diff --git a/board/freescale/mx8mq_evk/ddr/ddrphy_train.c b/board/freescale/mx8mq_evk/ddr/ddrphy_train.c new file mode 100644 index 0000000000..a2bf8b8449 --- /dev/null +++ b/board/freescale/mx8mq_evk/ddr/ddrphy_train.c @@ -0,0 +1,1272 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR; +static struct imx8m_ddrphy_regs *regs = (struct imx8m_ddrphy_regs *)IP2APB_DDRPHY_IPS_BASE_ADDR(0); +static struct gpc_reg *gpc_reg = (struct gpc_reg *)GPC_BASE_ADDR; + +static inline void poll_pmu_message_ready(void) +{ + int ret; + u32 val; + + /* + * When BIT0 set to 0, the PMU has a message for the user + * 10ms seems not enough for poll message, so use 1s here. + */ + ret = readl_poll_timeout(®s->reg[0xd0004], val, + !(val & BIT(0)), 1000000); + if (ret) + puts("PMU message timeout\n"); +} + +static inline void ack_pmu_message_receive(void) +{ + int ret; + u32 val; + /* + * By setting this register to 0, the user acknowledges the + * receipt of the message. + */ + writel(0x0, ®s->reg[0xd0031]); + + /* When BIT0 set to 0, the PMU has a message for the user*/ + ret = readl_poll_timeout(®s->reg[0xd0004], val, val & BIT(0), 1000); + if (ret) + printf("%s timeout\n", __func__); + + writel(0x1, ®s->reg[0xd0031]); +} + +static inline unsigned int get_mail(void) +{ + unsigned int reg; + + poll_pmu_message_ready(); + + /* Get the major message ID */ + reg = readl(®s->reg[0xd0032]); + + ack_pmu_message_receive(); + + return reg; +} + +static inline unsigned int get_stream_message(void) +{ + unsigned int reg, reg2; + + poll_pmu_message_ready(); + + reg = readl(®s->reg[0xd0032]); + reg2 = readl(®s->reg[0xd0034]); + reg2 = (reg2 << 16) | reg; + + ack_pmu_message_receive(); + + return reg2; +} + +static inline void decode_major_message(unsigned int mail) +{ + debug("[PMU Major message = 0x%08x]\n", mail); +} + +static inline void decode_streaming_message(void) +{ + unsigned int string_index, arg __maybe_unused; + int i = 0; + + string_index = get_stream_message(); + debug(" PMU String index = 0x%08x\n", string_index); + while (i < (string_index & 0xffff)) { + arg = get_stream_message(); + debug(" arg[%d] = 0x%08x\n", i, arg); + i++; + } + + debug("\n"); +} + +static void wait_ddrphy_training_complete(void) +{ + unsigned int mail; + + while (true) { + mail = get_mail(); + decode_major_message(mail); + if (mail == TRAIN_STREAM_START) { + decode_streaming_message(); + } else if (mail == TRAIN_SUCCESS) { + debug("Training PASS\n"); + break; + } else if (mail == TRAIN_FAIL) { + printf("Training FAILED\n"); + break; + } + } +} + +static void ddr_pll_bypass_100mts(void) +{ + /* change the clock source of dram_alt_clk_root to source 2 --100MHZ */ + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(2) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1)); + + /* change the clock source of dram_apb_clk_root to source 2 --40MHZ */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(2) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV2)); + + /* disable the clock gating */ + writel(0xFFFF, &gpc_reg->pgc_cpu_0_1_mapping); + /* configure ddr1_sw_pup_req */ + setbits_le32(&gpc_reg->pu_pgc_up_trg, BIT(5)); + + /* configure pll bypass mode */ + writel(BIT(24), &ccm_reg->dram_sel.target_root_set); + + debug("PLL bypass to 100MTS setting done\n"); +} + +static void ddr_pll_bypass_400mts(void) +{ + /* change the clock source of dram_alt_clk_root to source 2 --400MHZ */ + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(5) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1)); + + /* change the clock source of dram_apb_clk_root to source 2 --40MHZ/2 */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(2) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV2)); + + /* disable the clock gating */ + writel(0xFFFF, &gpc_reg->pgc_cpu_0_1_mapping); + /* configure ddr1_sw_pup_req */ + setbits_le32(&gpc_reg->pu_pgc_up_trg, BIT(5)); + + /* configure pll bypass mode */ + writel(BIT(24), &ccm_reg->dram_sel.target_root_set); + + debug("PLL bypass to 400MTS setting done\n"); +} + +static void dwc_ddrphy_phyinit_usercustom_e_setdficlk(enum pstate state) +{ + if (state == PS2) { + ddr_pll_bypass_100mts(); + } else if (state == PS1) { + ddr_pll_bypass_400mts(); + } else { + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(4) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); + writel(BIT(24), &ccm_reg->dram_sel.target_root_set); + } +} + +void lpddr4_800M_cfg_phy(void) +{ + int ret; + u32 val; + + writel(0x02, ®s->reg[0x20110]); + writel(0x03, ®s->reg[0x20111]); + writel(0x04, ®s->reg[0x20112]); + writel(0x05, ®s->reg[0x20113]); + writel(0x00, ®s->reg[0x20114]); + writel(0x01, ®s->reg[0x20115]); + writel(0x1ff, ®s->reg[0x1005f]); + writel(0x1ff, ®s->reg[0x1015f]); + writel(0x1ff, ®s->reg[0x1105f]); + writel(0x1ff, ®s->reg[0x1115f]); + writel(0x1ff, ®s->reg[0x1205f]); + writel(0x1ff, ®s->reg[0x1215f]); + writel(0x1ff, ®s->reg[0x1305f]); + writel(0x1ff, ®s->reg[0x1315f]); + writel(0x1ff, ®s->reg[0x11005f]); + writel(0x1ff, ®s->reg[0x11015f]); + writel(0x1ff, ®s->reg[0x11105f]); + writel(0x1ff, ®s->reg[0x11115f]); + writel(0x1ff, ®s->reg[0x11205f]); + writel(0x1ff, ®s->reg[0x11215f]); + writel(0x1ff, ®s->reg[0x11305f]); + writel(0x1ff, ®s->reg[0x11315f]); + writel(0x1ff, ®s->reg[0x21005f]); + writel(0x1ff, ®s->reg[0x21015f]); + writel(0x1ff, ®s->reg[0x21105f]); + writel(0x1ff, ®s->reg[0x21115f]); + writel(0x1ff, ®s->reg[0x21205f]); + writel(0x1ff, ®s->reg[0x21215f]); + writel(0x1ff, ®s->reg[0x21305f]); + writel(0x1ff, ®s->reg[0x21315f]); + writel(0x1ff, ®s->reg[0x55]); + writel(0x1ff, ®s->reg[0x1055]); + writel(0x1ff, ®s->reg[0x2055]); + writel(0x1ff, ®s->reg[0x3055]); + writel(0x1ff, ®s->reg[0x4055]); + writel(0x1ff, ®s->reg[0x5055]); + writel(0x1ff, ®s->reg[0x6055]); + writel(0x1ff, ®s->reg[0x7055]); + writel(0x1ff, ®s->reg[0x8055]); + writel(0x1ff, ®s->reg[0x9055]); + writel(0x19, ®s->reg[0x200c5]); + writel(0x7, ®s->reg[0x1200c5]); + writel(0x7, ®s->reg[0x2200c5]); + writel(0x2, ®s->reg[0x2002e]); + writel(0x2, ®s->reg[0x12002e]); + writel(0x2, ®s->reg[0x22002e]); + writel(0x0, ®s->reg[0x90204]); + writel(0x0, ®s->reg[0x190204]); + writel(0x0, ®s->reg[0x290204]); + writel(0xab, ®s->reg[0x20024]); + writel(0x0, ®s->reg[0x2003a]); + writel(0xab, ®s->reg[0x120024]); + writel(0x0, ®s->reg[0x2003a]); + writel(0xab, ®s->reg[0x220024]); + writel(0x0, ®s->reg[0x2003a]); + writel(0x3, ®s->reg[0x20056]); + writel(0xa, ®s->reg[0x120056]); + writel(0xa, ®s->reg[0x220056]); + writel(0xe00, ®s->reg[0x1004d]); + writel(0xe00, ®s->reg[0x1014d]); + writel(0xe00, ®s->reg[0x1104d]); + writel(0xe00, ®s->reg[0x1114d]); + writel(0xe00, ®s->reg[0x1204d]); + writel(0xe00, ®s->reg[0x1214d]); + writel(0xe00, ®s->reg[0x1304d]); + writel(0xe00, ®s->reg[0x1314d]); + writel(0xe00, ®s->reg[0x11004d]); + writel(0xe00, ®s->reg[0x11014d]); + writel(0xe00, ®s->reg[0x11104d]); + writel(0xe00, ®s->reg[0x11114d]); + writel(0xe00, ®s->reg[0x11204d]); + writel(0xe00, ®s->reg[0x11214d]); + writel(0xe00, ®s->reg[0x11304d]); + writel(0xe00, ®s->reg[0x11314d]); + writel(0xe00, ®s->reg[0x21004d]); + writel(0xe00, ®s->reg[0x21014d]); + writel(0xe00, ®s->reg[0x21104d]); + writel(0xe00, ®s->reg[0x21114d]); + writel(0xe00, ®s->reg[0x21204d]); + writel(0xe00, ®s->reg[0x21214d]); + writel(0xe00, ®s->reg[0x21304d]); + writel(0xe00, ®s->reg[0x21314d]); + writel(0xe38, ®s->reg[0x10049]); + writel(0xe38, ®s->reg[0x10149]); + writel(0xe38, ®s->reg[0x11049]); + writel(0xe38, ®s->reg[0x11149]); + writel(0xe38, ®s->reg[0x12049]); + writel(0xe38, ®s->reg[0x12149]); + writel(0xe38, ®s->reg[0x13049]); + writel(0xe38, ®s->reg[0x13149]); + writel(0xe38, ®s->reg[0x110049]); + writel(0xe38, ®s->reg[0x110149]); + writel(0xe38, ®s->reg[0x111049]); + writel(0xe38, ®s->reg[0x111149]); + writel(0xe38, ®s->reg[0x112049]); + writel(0xe38, ®s->reg[0x112149]); + writel(0xe38, ®s->reg[0x113049]); + writel(0xe38, ®s->reg[0x113149]); + writel(0xe38, ®s->reg[0x210049]); + writel(0xe38, ®s->reg[0x210149]); + writel(0xe38, ®s->reg[0x211049]); + writel(0xe38, ®s->reg[0x211149]); + writel(0xe38, ®s->reg[0x212049]); + writel(0xe38, ®s->reg[0x212149]); + writel(0xe38, ®s->reg[0x213049]); + writel(0xe38, ®s->reg[0x213149]); + writel(0x21, ®s->reg[0x43]); + writel(0x21, ®s->reg[0x1043]); + writel(0x21, ®s->reg[0x2043]); + writel(0x21, ®s->reg[0x3043]); + writel(0x21, ®s->reg[0x4043]); + writel(0x21, ®s->reg[0x5043]); + writel(0x21, ®s->reg[0x6043]); + writel(0x21, ®s->reg[0x7043]); + writel(0x21, ®s->reg[0x8043]); + writel(0x21, ®s->reg[0x9043]); + writel(0x3, ®s->reg[0x20018]); + writel(0x4, ®s->reg[0x20075]); + writel(0x0, ®s->reg[0x20050]); + writel(0x320, ®s->reg[0x20008]); + writel(0x64, ®s->reg[0x120008]); + writel(0x19, ®s->reg[0x220008]); + writel(0x9, ®s->reg[0x20088]); + writel(0x19c, ®s->reg[0x200b2]); + writel(0x5a1, ®s->reg[0x10043]); + writel(0x5a1, ®s->reg[0x10143]); + writel(0x5a1, ®s->reg[0x11043]); + writel(0x5a1, ®s->reg[0x11143]); + writel(0x5a1, ®s->reg[0x12043]); + writel(0x5a1, ®s->reg[0x12143]); + writel(0x5a1, ®s->reg[0x13043]); + writel(0x5a1, ®s->reg[0x13143]); + writel(0x19c, ®s->reg[0x1200b2]); + writel(0x5a1, ®s->reg[0x110043]); + writel(0x5a1, ®s->reg[0x110143]); + writel(0x5a1, ®s->reg[0x111043]); + writel(0x5a1, ®s->reg[0x111143]); + writel(0x5a1, ®s->reg[0x112043]); + writel(0x5a1, ®s->reg[0x112143]); + writel(0x5a1, ®s->reg[0x113043]); + writel(0x5a1, ®s->reg[0x113143]); + writel(0x19c, ®s->reg[0x2200b2]); + writel(0x5a1, ®s->reg[0x210043]); + writel(0x5a1, ®s->reg[0x210143]); + writel(0x5a1, ®s->reg[0x211043]); + writel(0x5a1, ®s->reg[0x211143]); + writel(0x5a1, ®s->reg[0x212043]); + writel(0x5a1, ®s->reg[0x212143]); + writel(0x5a1, ®s->reg[0x213043]); + writel(0x5a1, ®s->reg[0x213143]); + writel(0x1, ®s->reg[0x200fa]); + writel(0x1, ®s->reg[0x1200fa]); + writel(0x1, ®s->reg[0x2200fa]); + writel(0x1, ®s->reg[0x20019]); + writel(0x1, ®s->reg[0x120019]); + writel(0x1, ®s->reg[0x220019]); + writel(0x660, ®s->reg[0x200f0]); + writel(0x0, ®s->reg[0x200f1]); + writel(0x4444, ®s->reg[0x200f2]); + writel(0x8888, ®s->reg[0x200f3]); + writel(0x5555, ®s->reg[0x200f4]); + writel(0x0, ®s->reg[0x200f5]); + writel(0x0, ®s->reg[0x200f6]); + writel(0xf000, ®s->reg[0x200f7]); + writel(0x65, ®s->reg[0x2000b]); + writel(0xc9, ®s->reg[0x2000c]); + writel(0x7d1, ®s->reg[0x2000d]); + writel(0x2c, ®s->reg[0x2000e]); + writel(0xd, ®s->reg[0x12000b]); + writel(0x1a, ®s->reg[0x12000c]); + writel(0xfb, ®s->reg[0x12000d]); + writel(0x10, ®s->reg[0x12000e]); + writel(0x4, ®s->reg[0x22000b]); + writel(0x7, ®s->reg[0x22000c]); + writel(0x3f, ®s->reg[0x22000d]); + writel(0x10, ®s->reg[0x22000e]); + writel(0x0, ®s->reg[0x20025]); + writel(0x0, ®s->reg[0x2002d]); + writel(0x0, ®s->reg[0x12002d]); + writel(0x0, ®s->reg[0x22002d]); + writel(0x2, ®s->reg[0x20060]); + writel(0x0, ®s->reg[0xd0000]); + + /* load the 1D training image */ + ddr_load_train_code(FW_1D_IMAGE); + + writel(0x0, ®s->reg[0xd0000]); + writel(0x1, ®s->reg[0xd0000]); + + /* set the PHY input clock to the desired frequency for pstate 2 */ + dwc_ddrphy_phyinit_usercustom_e_setdficlk(PS2); + + writel(0x0, ®s->reg[0xd0000]); + writel(0x0, ®s->reg[0x54000]); + writel(0x0, ®s->reg[0x54001]); + writel(0x102, ®s->reg[0x54002]); + writel(0x64, ®s->reg[0x54003]); + writel(0x2, ®s->reg[0x54004]); + writel(0x2828, ®s->reg[0x54005]); + writel(0x14, ®s->reg[0x54006]); + writel(0x0, ®s->reg[0x54007]); + writel(0x121f, ®s->reg[0x54008]); + writel(0xc8, ®s->reg[0x54009]); + writel(0x0, ®s->reg[0x5400a]); + writel(0x2, ®s->reg[0x5400b]); + writel(0x0, ®s->reg[0x5400c]); + writel(0x0, ®s->reg[0x5400d]); + writel(0x0, ®s->reg[0x5400e]); + writel(0x0, ®s->reg[0x5400f]); + writel(0x0, ®s->reg[0x54010]); + writel(0x0, ®s->reg[0x54011]); + writel(0x310, ®s->reg[0x54012]); + writel(0x0, ®s->reg[0x54013]); + writel(0x0, ®s->reg[0x54014]); + writel(0x0, ®s->reg[0x54015]); + writel(0x0, ®s->reg[0x54016]); + writel(0x0, ®s->reg[0x54017]); + writel(0x0, ®s->reg[0x54018]); + writel(0x4, ®s->reg[0x54019]); + writel(0x31, ®s->reg[0x5401a]); + writel(0x4d46, ®s->reg[0x5401b]); + writel(0x4d08, ®s->reg[0x5401c]); + writel(0x0, ®s->reg[0x5401d]); + writel(0x5, ®s->reg[0x5401e]); + writel(0x4, ®s->reg[0x5401f]); + writel(0x31, ®s->reg[0x54020]); + writel(0x4d46, ®s->reg[0x54021]); + writel(0x4d08, ®s->reg[0x54022]); + writel(0x0, ®s->reg[0x54023]); + writel(0x5, ®s->reg[0x54024]); + writel(0x0, ®s->reg[0x54025]); + writel(0x0, ®s->reg[0x54026]); + writel(0x0, ®s->reg[0x54027]); + writel(0x0, ®s->reg[0x54028]); + writel(0x0, ®s->reg[0x54029]); + writel(0x0, ®s->reg[0x5402a]); + writel(0x1000, ®s->reg[0x5402b]); + writel(0x3, ®s->reg[0x5402c]); + writel(0x0, ®s->reg[0x5402d]); + writel(0x0, ®s->reg[0x5402e]); + writel(0x0, ®s->reg[0x5402f]); + writel(0x0, ®s->reg[0x54030]); + writel(0x0, ®s->reg[0x54031]); + writel(0x400, ®s->reg[0x54032]); + writel(0x3100, ®s->reg[0x54033]); + writel(0x4600, ®s->reg[0x54034]); + writel(0x84d, ®s->reg[0x54035]); + writel(0x4d, ®s->reg[0x54036]); + writel(0x500, ®s->reg[0x54037]); + writel(0x400, ®s->reg[0x54038]); + writel(0x3100, ®s->reg[0x54039]); + writel(0x4600, ®s->reg[0x5403a]); + writel(0x84d, ®s->reg[0x5403b]); + writel(0x4d, ®s->reg[0x5403c]); + writel(0x500, ®s->reg[0x5403d]); + writel(0x1, ®s->reg[0xd0000]); + writel(0x1, ®s->reg[0xd0000]); + writel(0x9, ®s->reg[0xd0099]); + writel(0x1, ®s->reg[0xd0099]); + writel(0x0, ®s->reg[0xd0099]); + + wait_ddrphy_training_complete(); + + writel(0x1, ®s->reg[0xd0099]); + writel(0x0, ®s->reg[0xd0000]); + writel(0x1, ®s->reg[0xd0000]); + + /* set the PHY input clock to the desired frequency for pstate 1 */ + dwc_ddrphy_phyinit_usercustom_e_setdficlk(PS1); + + writel(0x0, ®s->reg[0xd0000]); + writel(0x0, ®s->reg[0x54000]); + writel(0x0, ®s->reg[0x54001]); + writel(0x101, ®s->reg[0x54002]); + writel(0x190, ®s->reg[0x54003]); + writel(0x2, ®s->reg[0x54004]); + writel(0x2828, ®s->reg[0x54005]); + writel(0x14, ®s->reg[0x54006]); + writel(0x0, ®s->reg[0x54007]); + writel(0x121f, ®s->reg[0x54008]); + writel(0xc8, ®s->reg[0x54009]); + writel(0x0, ®s->reg[0x5400a]); + writel(0x2, ®s->reg[0x5400b]); + writel(0x0, ®s->reg[0x5400c]); + writel(0x0, ®s->reg[0x5400d]); + writel(0x0, ®s->reg[0x5400e]); + writel(0x0, ®s->reg[0x5400f]); + writel(0x0, ®s->reg[0x54010]); + writel(0x0, ®s->reg[0x54011]); + writel(0x310, ®s->reg[0x54012]); + writel(0x0, ®s->reg[0x54013]); + writel(0x0, ®s->reg[0x54014]); + writel(0x0, ®s->reg[0x54015]); + writel(0x0, ®s->reg[0x54016]); + writel(0x0, ®s->reg[0x54017]); + writel(0x0, ®s->reg[0x54018]); + writel(0x4, ®s->reg[0x54019]); + writel(0x31, ®s->reg[0x5401a]); + writel(0x4d46, ®s->reg[0x5401b]); + writel(0x4d08, ®s->reg[0x5401c]); + writel(0x0, ®s->reg[0x5401d]); + writel(0x5, ®s->reg[0x5401e]); + writel(0x4, ®s->reg[0x5401f]); + writel(0x31, ®s->reg[0x54020]); + writel(0x4d46, ®s->reg[0x54021]); + writel(0x4d08, ®s->reg[0x54022]); + writel(0x0, ®s->reg[0x54023]); + writel(0x5, ®s->reg[0x54024]); + writel(0x0, ®s->reg[0x54025]); + writel(0x0, ®s->reg[0x54026]); + writel(0x0, ®s->reg[0x54027]); + writel(0x0, ®s->reg[0x54028]); + writel(0x0, ®s->reg[0x54029]); + writel(0x0, ®s->reg[0x5402a]); + writel(0x1000, ®s->reg[0x5402b]); + writel(0x3, ®s->reg[0x5402c]); + writel(0x0, ®s->reg[0x5402d]); + writel(0x0, ®s->reg[0x5402e]); + writel(0x0, ®s->reg[0x5402f]); + writel(0x0, ®s->reg[0x54030]); + writel(0x0, ®s->reg[0x54031]); + writel(0x400, ®s->reg[0x54032]); + writel(0x3100, ®s->reg[0x54033]); + writel(0x4600, ®s->reg[0x54034]); + writel(0x84d, ®s->reg[0x54035]); + writel(0x4d, ®s->reg[0x54036]); + writel(0x500, ®s->reg[0x54037]); + writel(0x400, ®s->reg[0x54038]); + writel(0x3100, ®s->reg[0x54039]); + writel(0x4600, ®s->reg[0x5403a]); + writel(0x84d, ®s->reg[0x5403b]); + writel(0x4d, ®s->reg[0x5403c]); + writel(0x500, ®s->reg[0x5403d]); + writel(0x1, ®s->reg[0xd0000]); + writel(0x1, ®s->reg[0xd0000]); + writel(0x9, ®s->reg[0xd0099]); + writel(0x1, ®s->reg[0xd0099]); + writel(0x0, ®s->reg[0xd0099]); + + wait_ddrphy_training_complete(); + + writel(0x1, ®s->reg[0xd0099]); + writel(0x0, ®s->reg[0xd0000]); + writel(0x1, ®s->reg[0xd0000]); + + /* set the PHY input clock to the desired frequency for pstate 0 */ + dwc_ddrphy_phyinit_usercustom_e_setdficlk(PS0); + + writel(0x0, ®s->reg[0xd0000]); + writel(0x0, ®s->reg[0x54000]); + writel(0x0, ®s->reg[0x54001]); + writel(0x0, ®s->reg[0x54002]); + writel(0xc80, ®s->reg[0x54003]); + writel(0x2, ®s->reg[0x54004]); + writel(0x2828, ®s->reg[0x54005]); + writel(0x14, ®s->reg[0x54006]); + writel(0x0, ®s->reg[0x54007]); + writel(0x131f, ®s->reg[0x54008]); + writel(0x5, ®s->reg[0x54009]); + writel(0x0, ®s->reg[0x5400a]); + writel(0x2, ®s->reg[0x5400b]); + writel(0x0, ®s->reg[0x5400c]); + writel(0x0, ®s->reg[0x5400d]); + writel(0x0, ®s->reg[0x5400e]); + writel(0x0, ®s->reg[0x5400f]); + writel(0x0, ®s->reg[0x54010]); + writel(0x0, ®s->reg[0x54011]); + writel(0x310, ®s->reg[0x54012]); + writel(0x0, ®s->reg[0x54013]); + writel(0x0, ®s->reg[0x54014]); + writel(0x0, ®s->reg[0x54015]); + writel(0x0, ®s->reg[0x54016]); + writel(0x0, ®s->reg[0x54017]); + writel(0x0, ®s->reg[0x54018]); + writel(0x2dd4, ®s->reg[0x54019]); + writel(0x31, ®s->reg[0x5401a]); + writel(0x4d46, ®s->reg[0x5401b]); + writel(0x4d08, ®s->reg[0x5401c]); + writel(0x0, ®s->reg[0x5401d]); + writel(0x5, ®s->reg[0x5401e]); + writel(0x2dd4, ®s->reg[0x5401f]); + writel(0x31, ®s->reg[0x54020]); + writel(0x4d46, ®s->reg[0x54021]); + writel(0x4d08, ®s->reg[0x54022]); + writel(0x0, ®s->reg[0x54023]); + writel(0x5, ®s->reg[0x54024]); + writel(0x0, ®s->reg[0x54025]); + writel(0x0, ®s->reg[0x54026]); + writel(0x0, ®s->reg[0x54027]); + writel(0x0, ®s->reg[0x54028]); + writel(0x0, ®s->reg[0x54029]); + writel(0x0, ®s->reg[0x5402a]); + writel(0x1000, ®s->reg[0x5402b]); + writel(0x3, ®s->reg[0x5402c]); + writel(0x0, ®s->reg[0x5402d]); + writel(0x0, ®s->reg[0x5402e]); + writel(0x0, ®s->reg[0x5402f]); + writel(0x0, ®s->reg[0x54030]); + writel(0x0, ®s->reg[0x54031]); + writel(0xd400, ®s->reg[0x54032]); + writel(0x312d, ®s->reg[0x54033]); + writel(0x4600, ®s->reg[0x54034]); + writel(0x84d, ®s->reg[0x54035]); + writel(0x4d, ®s->reg[0x54036]); + writel(0x500, ®s->reg[0x54037]); + writel(0xd400, ®s->reg[0x54038]); + writel(0x312d, ®s->reg[0x54039]); + writel(0x4600, ®s->reg[0x5403a]); + writel(0x84d, ®s->reg[0x5403b]); + writel(0x4d, ®s->reg[0x5403c]); + writel(0x500, ®s->reg[0x5403d]); + writel(0x1, ®s->reg[0xd0000]); + writel(0x1, ®s->reg[0xd0000]); + writel(0x9, ®s->reg[0xd0099]); + writel(0x1, ®s->reg[0xd0099]); + writel(0x0, ®s->reg[0xd0099]); + + wait_ddrphy_training_complete(); + + writel(0x1, ®s->reg[0xd0099]); + writel(0x0, ®s->reg[0xd0000]); + writel(0x1, ®s->reg[0xd0000]); + writel(0x0, ®s->reg[0xd0000]); + + /* load the 2D training image */ + ddr_load_train_code(FW_2D_IMAGE); + + writel(0x0, ®s->reg[0xd0000]); + writel(0x1, ®s->reg[0xd0000]); + writel(0x0, ®s->reg[0xd0000]); + + writel(0x0, ®s->reg[0x54000]); + writel(0x0, ®s->reg[0x54001]); + writel(0x0, ®s->reg[0x54002]); + writel(0xc80, ®s->reg[0x54003]); + writel(0x2, ®s->reg[0x54004]); + writel(0x2828, ®s->reg[0x54005]); + writel(0x14, ®s->reg[0x54006]); + writel(0x0, ®s->reg[0x54007]); + writel(0x61, ®s->reg[0x54008]); + writel(0xc8, ®s->reg[0x54009]); + writel(0x0, ®s->reg[0x5400a]); + writel(0x2, ®s->reg[0x5400b]); + writel(0x0, ®s->reg[0x5400c]); + writel(0x100, ®s->reg[0x5400d]); + writel(0x0, ®s->reg[0x5400e]); + writel(0x100, ®s->reg[0x5400f]); + writel(0x1f7f, ®s->reg[0x54010]); + writel(0x0, ®s->reg[0x54011]); + writel(0x310, ®s->reg[0x54012]); + writel(0x0, ®s->reg[0x54013]); + writel(0x0, ®s->reg[0x54014]); + writel(0x0, ®s->reg[0x54015]); + writel(0x0, ®s->reg[0x54016]); + writel(0x0, ®s->reg[0x54017]); + writel(0x0, ®s->reg[0x54018]); + writel(0x2dd4, ®s->reg[0x54019]); + writel(0x31, ®s->reg[0x5401a]); + writel(0x4d46, ®s->reg[0x5401b]); + writel(0x4d08, ®s->reg[0x5401c]); + writel(0x0, ®s->reg[0x5401d]); + writel(0x5, ®s->reg[0x5401e]); + writel(0x2dd4, ®s->reg[0x5401f]); + writel(0x31, ®s->reg[0x54020]); + writel(0x4d46, ®s->reg[0x54021]); + writel(0x4d08, ®s->reg[0x54022]); + writel(0x0, ®s->reg[0x54023]); + writel(0x5, ®s->reg[0x54024]); + writel(0x0, ®s->reg[0x54025]); + writel(0x0, ®s->reg[0x54026]); + writel(0x0, ®s->reg[0x54027]); + writel(0x0, ®s->reg[0x54028]); + writel(0x0, ®s->reg[0x54029]); + writel(0x0, ®s->reg[0x5402a]); + writel(0x1000, ®s->reg[0x5402b]); + writel(0x3, ®s->reg[0x5402c]); + writel(0x0, ®s->reg[0x5402d]); + writel(0x0, ®s->reg[0x5402e]); + writel(0x0, ®s->reg[0x5402f]); + writel(0x0, ®s->reg[0x54030]); + writel(0x0, ®s->reg[0x54031]); + writel(0xd400, ®s->reg[0x54032]); + writel(0x312d, ®s->reg[0x54033]); + writel(0x4600, ®s->reg[0x54034]); + writel(0x084d, ®s->reg[0x54035]); + writel(0x4d, ®s->reg[0x54036]); + writel(0x500, ®s->reg[0x54037]); + writel(0xd400, ®s->reg[0x54038]); + writel(0x312d, ®s->reg[0x54039]); + writel(0x4600, ®s->reg[0x5403a]); + writel(0x084d, ®s->reg[0x5403b]); + writel(0x4d, ®s->reg[0x5403c]); + writel(0x500, ®s->reg[0x5403d]); + writel(0x1, ®s->reg[0xd0000]); + /* Execute the Training Firmware */ + writel(0x1, ®s->reg[0xd0000]); + writel(0x9, ®s->reg[0xd0099]); + writel(0x1, ®s->reg[0xd0099]); + writel(0x0, ®s->reg[0xd0099]); + /* wait for 2D training complete */ + wait_ddrphy_training_complete(); + + writel(0x1, ®s->reg[0xd0099]); + writel(0x0, ®s->reg[0xd0000]); + writel(0x1, ®s->reg[0xd0000]); + + /* (I) Load PHY Init Engine Image */ + writel(0x0, ®s->reg[0xd0000]); + writel(0x10, ®s->reg[0x90000]); + writel(0x400, ®s->reg[0x90001]); + writel(0x10e, ®s->reg[0x90002]); + writel(0x0, ®s->reg[0x90003]); + writel(0x0, ®s->reg[0x90004]); + writel(0x8, ®s->reg[0x90005]); + writel(0xb, ®s->reg[0x90029]); + writel(0x480, ®s->reg[0x9002a]); + writel(0x109, ®s->reg[0x9002b]); + writel(0x8, ®s->reg[0x9002c]); + writel(0x448, ®s->reg[0x9002d]); + writel(0x139, ®s->reg[0x9002e]); + writel(0x8, ®s->reg[0x9002f]); + writel(0x478, ®s->reg[0x90030]); + writel(0x109, ®s->reg[0x90031]); + writel(0x0, ®s->reg[0x90032]); + writel(0xe8, ®s->reg[0x90033]); + writel(0x109, ®s->reg[0x90034]); + writel(0x2, ®s->reg[0x90035]); + writel(0x10, ®s->reg[0x90036]); + writel(0x139, ®s->reg[0x90037]); + writel(0xf, ®s->reg[0x90038]); + writel(0x7c0, ®s->reg[0x90039]); + writel(0x139, ®s->reg[0x9003a]); + writel(0x44, ®s->reg[0x9003b]); + writel(0x630, ®s->reg[0x9003c]); + writel(0x159, ®s->reg[0x9003d]); + writel(0x14f, ®s->reg[0x9003e]); + writel(0x630, ®s->reg[0x9003f]); + writel(0x159, ®s->reg[0x90040]); + writel(0x47, ®s->reg[0x90041]); + writel(0x630, ®s->reg[0x90042]); + writel(0x149, ®s->reg[0x90043]); + writel(0x4f, ®s->reg[0x90044]); + writel(0x630, ®s->reg[0x90045]); + writel(0x179, ®s->reg[0x90046]); + writel(0x8, ®s->reg[0x90047]); + writel(0xe0, ®s->reg[0x90048]); + writel(0x109, ®s->reg[0x90049]); + writel(0x0, ®s->reg[0x9004a]); + writel(0x7c8, ®s->reg[0x9004b]); + writel(0x109, ®s->reg[0x9004c]); + writel(0x0, ®s->reg[0x9004d]); + writel(0x1, ®s->reg[0x9004e]); + writel(0x8, ®s->reg[0x9004f]); + writel(0x0, ®s->reg[0x90050]); + writel(0x45a, ®s->reg[0x90051]); + writel(0x9, ®s->reg[0x90052]); + writel(0x0, ®s->reg[0x90053]); + writel(0x448, ®s->reg[0x90054]); + writel(0x109, ®s->reg[0x90055]); + writel(0x40, ®s->reg[0x90056]); + writel(0x630, ®s->reg[0x90057]); + writel(0x179, ®s->reg[0x90058]); + writel(0x1, ®s->reg[0x90059]); + writel(0x618, ®s->reg[0x9005a]); + writel(0x109, ®s->reg[0x9005b]); + writel(0x40c0, ®s->reg[0x9005c]); + writel(0x630, ®s->reg[0x9005d]); + writel(0x149, ®s->reg[0x9005e]); + writel(0x8, ®s->reg[0x9005f]); + writel(0x4, ®s->reg[0x90060]); + writel(0x48, ®s->reg[0x90061]); + writel(0x4040, ®s->reg[0x90062]); + writel(0x630, ®s->reg[0x90063]); + writel(0x149, ®s->reg[0x90064]); + writel(0x0, ®s->reg[0x90065]); + writel(0x4, ®s->reg[0x90066]); + writel(0x48, ®s->reg[0x90067]); + writel(0x40, ®s->reg[0x90068]); + writel(0x630, ®s->reg[0x90069]); + writel(0x149, ®s->reg[0x9006a]); + writel(0x10, ®s->reg[0x9006b]); + writel(0x4, ®s->reg[0x9006c]); + writel(0x18, ®s->reg[0x9006d]); + writel(0x0, ®s->reg[0x9006e]); + writel(0x4, ®s->reg[0x9006f]); + writel(0x78, ®s->reg[0x90070]); + writel(0x549, ®s->reg[0x90071]); + writel(0x630, ®s->reg[0x90072]); + writel(0x159, ®s->reg[0x90073]); + writel(0xd49, ®s->reg[0x90074]); + writel(0x630, ®s->reg[0x90075]); + writel(0x159, ®s->reg[0x90076]); + writel(0x94a, ®s->reg[0x90077]); + writel(0x630, ®s->reg[0x90078]); + writel(0x159, ®s->reg[0x90079]); + writel(0x441, ®s->reg[0x9007a]); + writel(0x630, ®s->reg[0x9007b]); + writel(0x149, ®s->reg[0x9007c]); + writel(0x42, ®s->reg[0x9007d]); + writel(0x630, ®s->reg[0x9007e]); + writel(0x149, ®s->reg[0x9007f]); + writel(0x1, ®s->reg[0x90080]); + writel(0x630, ®s->reg[0x90081]); + writel(0x149, ®s->reg[0x90082]); + writel(0x0, ®s->reg[0x90083]); + writel(0xe0, ®s->reg[0x90084]); + writel(0x109, ®s->reg[0x90085]); + writel(0xa, ®s->reg[0x90086]); + writel(0x10, ®s->reg[0x90087]); + writel(0x109, ®s->reg[0x90088]); + writel(0x9, ®s->reg[0x90089]); + writel(0x3c0, ®s->reg[0x9008a]); + writel(0x149, ®s->reg[0x9008b]); + writel(0x9, ®s->reg[0x9008c]); + writel(0x3c0, ®s->reg[0x9008d]); + writel(0x159, ®s->reg[0x9008e]); + writel(0x18, ®s->reg[0x9008f]); + writel(0x10, ®s->reg[0x90090]); + writel(0x109, ®s->reg[0x90091]); + writel(0x0, ®s->reg[0x90092]); + writel(0x3c0, ®s->reg[0x90093]); + writel(0x109, ®s->reg[0x90094]); + writel(0x18, ®s->reg[0x90095]); + writel(0x4, ®s->reg[0x90096]); + writel(0x48, ®s->reg[0x90097]); + writel(0x18, ®s->reg[0x90098]); + writel(0x4, ®s->reg[0x90099]); + writel(0x58, ®s->reg[0x9009a]); + writel(0xa, ®s->reg[0x9009b]); + writel(0x10, ®s->reg[0x9009c]); + writel(0x109, ®s->reg[0x9009d]); + writel(0x2, ®s->reg[0x9009e]); + writel(0x10, ®s->reg[0x9009f]); + writel(0x109, ®s->reg[0x900a0]); + writel(0x5, ®s->reg[0x900a1]); + writel(0x7c0, ®s->reg[0x900a2]); + writel(0x109, ®s->reg[0x900a3]); + writel(0x10, ®s->reg[0x900a4]); + writel(0x10, ®s->reg[0x900a5]); + writel(0x109, ®s->reg[0x900a6]); + writel(0x811, ®s->reg[0x40000]); + writel(0x880, ®s->reg[0x40020]); + writel(0x0, ®s->reg[0x40040]); + writel(0x0, ®s->reg[0x40060]); + writel(0x4016, ®s->reg[0x40001]); + writel(0x83, ®s->reg[0x40021]); + writel(0x4f, ®s->reg[0x40041]); + writel(0x0, ®s->reg[0x40061]); + writel(0x4040, ®s->reg[0x40002]); + writel(0x83, ®s->reg[0x40022]); + writel(0x51, ®s->reg[0x40042]); + writel(0x0, ®s->reg[0x40062]); + writel(0x811, ®s->reg[0x40003]); + writel(0x880, ®s->reg[0x40023]); + writel(0x0, ®s->reg[0x40043]); + writel(0x0, ®s->reg[0x40063]); + writel(0x720, ®s->reg[0x40004]); + writel(0xf, ®s->reg[0x40024]); + writel(0x1740, ®s->reg[0x40044]); + writel(0x0, ®s->reg[0x40064]); + writel(0x16, ®s->reg[0x40005]); + writel(0x83, ®s->reg[0x40025]); + writel(0x4b, ®s->reg[0x40045]); + writel(0x0, ®s->reg[0x40065]); + writel(0x716, ®s->reg[0x40006]); + writel(0xf, ®s->reg[0x40026]); + writel(0x2001, ®s->reg[0x40046]); + writel(0x0, ®s->reg[0x40066]); + writel(0x716, ®s->reg[0x40007]); + writel(0xf, ®s->reg[0x40027]); + writel(0x2800, ®s->reg[0x40047]); + writel(0x0, ®s->reg[0x40067]); + writel(0x716, ®s->reg[0x40008]); + writel(0xf, ®s->reg[0x40028]); + writel(0xf00, ®s->reg[0x40048]); + writel(0x0, ®s->reg[0x40068]); + writel(0x720, ®s->reg[0x40009]); + writel(0xf, ®s->reg[0x40029]); + writel(0x1400, ®s->reg[0x40049]); + writel(0x0, ®s->reg[0x40069]); + writel(0xe08, ®s->reg[0x4000a]); + writel(0xc15, ®s->reg[0x4002a]); + writel(0x0, ®s->reg[0x4004a]); + writel(0x0, ®s->reg[0x4006a]); + writel(0x623, ®s->reg[0x4000b]); + writel(0x15, ®s->reg[0x4002b]); + writel(0x0, ®s->reg[0x4004b]); + writel(0x0, ®s->reg[0x4006b]); + writel(0x4004, ®s->reg[0x4000c]); + writel(0x80, ®s->reg[0x4002c]); + writel(0x0, ®s->reg[0x4004c]); + writel(0x0, ®s->reg[0x4006c]); + writel(0xe08, ®s->reg[0x4000d]); + writel(0xc1a, ®s->reg[0x4002d]); + writel(0x0, ®s->reg[0x4004d]); + writel(0x0, ®s->reg[0x4006d]); + writel(0x623, ®s->reg[0x4000e]); + writel(0x1a, ®s->reg[0x4002e]); + writel(0x0, ®s->reg[0x4004e]); + writel(0x0, ®s->reg[0x4006e]); + writel(0x4040, ®s->reg[0x4000f]); + writel(0x80, ®s->reg[0x4002f]); + writel(0x0, ®s->reg[0x4004f]); + writel(0x0, ®s->reg[0x4006f]); + writel(0x2604, ®s->reg[0x40010]); + writel(0x15, ®s->reg[0x40030]); + writel(0x0, ®s->reg[0x40050]); + writel(0x0, ®s->reg[0x40070]); + writel(0x708, ®s->reg[0x40011]); + writel(0x5, ®s->reg[0x40031]); + writel(0x0, ®s->reg[0x40051]); + writel(0x2002, ®s->reg[0x40071]); + writel(0x8, ®s->reg[0x40012]); + writel(0x80, ®s->reg[0x40032]); + writel(0x0, ®s->reg[0x40052]); + writel(0x0, ®s->reg[0x40072]); + writel(0x2604, ®s->reg[0x40013]); + writel(0x1a, ®s->reg[0x40033]); + writel(0x0, ®s->reg[0x40053]); + writel(0x0, ®s->reg[0x40073]); + writel(0x708, ®s->reg[0x40014]); + writel(0xa, ®s->reg[0x40034]); + writel(0x0, ®s->reg[0x40054]); + writel(0x2002, ®s->reg[0x40074]); + writel(0x4040, ®s->reg[0x40015]); + writel(0x80, ®s->reg[0x40035]); + writel(0x0, ®s->reg[0x40055]); + writel(0x0, ®s->reg[0x40075]); + writel(0x60a, ®s->reg[0x40016]); + writel(0x15, ®s->reg[0x40036]); + writel(0x1200, ®s->reg[0x40056]); + writel(0x0, ®s->reg[0x40076]); + writel(0x61a, ®s->reg[0x40017]); + writel(0x15, ®s->reg[0x40037]); + writel(0x1300, ®s->reg[0x40057]); + writel(0x0, ®s->reg[0x40077]); + writel(0x60a, ®s->reg[0x40018]); + writel(0x1a, ®s->reg[0x40038]); + writel(0x1200, ®s->reg[0x40058]); + writel(0x0, ®s->reg[0x40078]); + writel(0x642, ®s->reg[0x40019]); + writel(0x1a, ®s->reg[0x40039]); + writel(0x1300, ®s->reg[0x40059]); + writel(0x0, ®s->reg[0x40079]); + writel(0x4808, ®s->reg[0x4001a]); + writel(0x880, ®s->reg[0x4003a]); + writel(0x0, ®s->reg[0x4005a]); + writel(0x0, ®s->reg[0x4007a]); + writel(0x0, ®s->reg[0x900a7]); + writel(0x790, ®s->reg[0x900a8]); + writel(0x11a, ®s->reg[0x900a9]); + writel(0x8, ®s->reg[0x900aa]); + writel(0x7aa, ®s->reg[0x900ab]); + writel(0x2a, ®s->reg[0x900ac]); + writel(0x10, ®s->reg[0x900ad]); + writel(0x7b2, ®s->reg[0x900ae]); + writel(0x2a, ®s->reg[0x900af]); + writel(0x0, ®s->reg[0x900b0]); + writel(0x7c8, ®s->reg[0x900b1]); + writel(0x109, ®s->reg[0x900b2]); + writel(0x10, ®s->reg[0x900b3]); + writel(0x2a8, ®s->reg[0x900b4]); + writel(0x129, ®s->reg[0x900b5]); + writel(0x8, ®s->reg[0x900b6]); + writel(0x370, ®s->reg[0x900b7]); + writel(0x129, ®s->reg[0x900b8]); + writel(0xa, ®s->reg[0x900b9]); + writel(0x3c8, ®s->reg[0x900ba]); + writel(0x1a9, ®s->reg[0x900bb]); + writel(0xc, ®s->reg[0x900bc]); + writel(0x408, ®s->reg[0x900bd]); + writel(0x199, ®s->reg[0x900be]); + writel(0x14, ®s->reg[0x900bf]); + writel(0x790, ®s->reg[0x900c0]); + writel(0x11a, ®s->reg[0x900c1]); + writel(0x8, ®s->reg[0x900c2]); + writel(0x4, ®s->reg[0x900c3]); + writel(0x18, ®s->reg[0x900c4]); + writel(0xc, ®s->reg[0x900c5]); + writel(0x408, ®s->reg[0x900c6]); + writel(0x199, ®s->reg[0x900c7]); + writel(0x8, ®s->reg[0x900c8]); + writel(0x8568, ®s->reg[0x900c9]); + writel(0x108, ®s->reg[0x900ca]); + writel(0x18, ®s->reg[0x900cb]); + writel(0x790, ®s->reg[0x900cc]); + writel(0x16a, ®s->reg[0x900cd]); + writel(0x8, ®s->reg[0x900ce]); + writel(0x1d8, ®s->reg[0x900cf]); + writel(0x169, ®s->reg[0x900d0]); + writel(0x10, ®s->reg[0x900d1]); + writel(0x8558, ®s->reg[0x900d2]); + writel(0x168, ®s->reg[0x900d3]); + writel(0x70, ®s->reg[0x900d4]); + writel(0x788, ®s->reg[0x900d5]); + writel(0x16a, ®s->reg[0x900d6]); + writel(0x1ff8, ®s->reg[0x900d7]); + writel(0x85a8, ®s->reg[0x900d8]); + writel(0x1e8, ®s->reg[0x900d9]); + writel(0x50, ®s->reg[0x900da]); + writel(0x798, ®s->reg[0x900db]); + writel(0x16a, ®s->reg[0x900dc]); + writel(0x60, ®s->reg[0x900dd]); + writel(0x7a0, ®s->reg[0x900de]); + writel(0x16a, ®s->reg[0x900df]); + writel(0x8, ®s->reg[0x900e0]); + writel(0x8310, ®s->reg[0x900e1]); + writel(0x168, ®s->reg[0x900e2]); + writel(0x8, ®s->reg[0x900e3]); + writel(0xa310, ®s->reg[0x900e4]); + writel(0x168, ®s->reg[0x900e5]); + writel(0xa, ®s->reg[0x900e6]); + writel(0x408, ®s->reg[0x900e7]); + writel(0x169, ®s->reg[0x900e8]); + writel(0x6e, ®s->reg[0x900e9]); + writel(0x0, ®s->reg[0x900ea]); + writel(0x68, ®s->reg[0x900eb]); + writel(0x0, ®s->reg[0x900ec]); + writel(0x408, ®s->reg[0x900ed]); + writel(0x169, ®s->reg[0x900ee]); + writel(0x0, ®s->reg[0x900ef]); + writel(0x8310, ®s->reg[0x900f0]); + writel(0x168, ®s->reg[0x900f1]); + writel(0x0, ®s->reg[0x900f2]); + writel(0xa310, ®s->reg[0x900f3]); + writel(0x168, ®s->reg[0x900f4]); + writel(0x1ff8, ®s->reg[0x900f5]); + writel(0x85a8, ®s->reg[0x900f6]); + writel(0x1e8, ®s->reg[0x900f7]); + writel(0x68, ®s->reg[0x900f8]); + writel(0x798, ®s->reg[0x900f9]); + writel(0x16a, ®s->reg[0x900fa]); + writel(0x78, ®s->reg[0x900fb]); + writel(0x7a0, ®s->reg[0x900fc]); + writel(0x16a, ®s->reg[0x900fd]); + writel(0x68, ®s->reg[0x900fe]); + writel(0x790, ®s->reg[0x900ff]); + writel(0x16a, ®s->reg[0x90100]); + writel(0x8, ®s->reg[0x90101]); + writel(0x8b10, ®s->reg[0x90102]); + writel(0x168, ®s->reg[0x90103]); + writel(0x8, ®s->reg[0x90104]); + writel(0xab10, ®s->reg[0x90105]); + writel(0x168, ®s->reg[0x90106]); + writel(0xa, ®s->reg[0x90107]); + writel(0x408, ®s->reg[0x90108]); + writel(0x169, ®s->reg[0x90109]); + writel(0x58, ®s->reg[0x9010a]); + writel(0x0, ®s->reg[0x9010b]); + writel(0x68, ®s->reg[0x9010c]); + writel(0x0, ®s->reg[0x9010d]); + writel(0x408, ®s->reg[0x9010e]); + writel(0x169, ®s->reg[0x9010f]); + writel(0x0, ®s->reg[0x90110]); + writel(0x8b10, ®s->reg[0x90111]); + writel(0x168, ®s->reg[0x90112]); + writel(0x0, ®s->reg[0x90113]); + writel(0xab10, ®s->reg[0x90114]); + writel(0x168, ®s->reg[0x90115]); + writel(0x0, ®s->reg[0x90116]); + writel(0x1d8, ®s->reg[0x90117]); + writel(0x169, ®s->reg[0x90118]); + writel(0x80, ®s->reg[0x90119]); + writel(0x790, ®s->reg[0x9011a]); + writel(0x16a, ®s->reg[0x9011b]); + writel(0x18, ®s->reg[0x9011c]); + writel(0x7aa, ®s->reg[0x9011d]); + writel(0x6a, ®s->reg[0x9011e]); + writel(0xa, ®s->reg[0x9011f]); + writel(0x0, ®s->reg[0x90120]); + writel(0x1e9, ®s->reg[0x90121]); + writel(0x8, ®s->reg[0x90122]); + writel(0x8080, ®s->reg[0x90123]); + writel(0x108, ®s->reg[0x90124]); + writel(0xf, ®s->reg[0x90125]); + writel(0x408, ®s->reg[0x90126]); + writel(0x169, ®s->reg[0x90127]); + writel(0xc, ®s->reg[0x90128]); + writel(0x0, ®s->reg[0x90129]); + writel(0x68, ®s->reg[0x9012a]); + writel(0x9, ®s->reg[0x9012b]); + writel(0x0, ®s->reg[0x9012c]); + writel(0x1a9, ®s->reg[0x9012d]); + writel(0x0, ®s->reg[0x9012e]); + writel(0x408, ®s->reg[0x9012f]); + writel(0x169, ®s->reg[0x90130]); + writel(0x0, ®s->reg[0x90131]); + writel(0x8080, ®s->reg[0x90132]); + writel(0x108, ®s->reg[0x90133]); + writel(0x8, ®s->reg[0x90134]); + writel(0x7aa, ®s->reg[0x90135]); + writel(0x6a, ®s->reg[0x90136]); + writel(0x0, ®s->reg[0x90137]); + writel(0x8568, ®s->reg[0x90138]); + writel(0x108, ®s->reg[0x90139]); + writel(0xb7, ®s->reg[0x9013a]); + writel(0x790, ®s->reg[0x9013b]); + writel(0x16a, ®s->reg[0x9013c]); + writel(0x1d, ®s->reg[0x9013d]); + writel(0x0, ®s->reg[0x9013e]); + writel(0x68, ®s->reg[0x9013f]); + writel(0x8, ®s->reg[0x90140]); + writel(0x8558, ®s->reg[0x90141]); + writel(0x168, ®s->reg[0x90142]); + writel(0xf, ®s->reg[0x90143]); + writel(0x408, ®s->reg[0x90144]); + writel(0x169, ®s->reg[0x90145]); + writel(0xc, ®s->reg[0x90146]); + writel(0x0, ®s->reg[0x90147]); + writel(0x68, ®s->reg[0x90148]); + writel(0x0, ®s->reg[0x90149]); + writel(0x408, ®s->reg[0x9014a]); + writel(0x169, ®s->reg[0x9014b]); + writel(0x0, ®s->reg[0x9014c]); + writel(0x8558, ®s->reg[0x9014d]); + writel(0x168, ®s->reg[0x9014e]); + writel(0x8, ®s->reg[0x9014f]); + writel(0x3c8, ®s->reg[0x90150]); + writel(0x1a9, ®s->reg[0x90151]); + writel(0x3, ®s->reg[0x90152]); + writel(0x370, ®s->reg[0x90153]); + writel(0x129, ®s->reg[0x90154]); + writel(0x20, ®s->reg[0x90155]); + writel(0x2aa, ®s->reg[0x90156]); + writel(0x9, ®s->reg[0x90157]); + writel(0x0, ®s->reg[0x90158]); + writel(0x400, ®s->reg[0x90159]); + writel(0x10e, ®s->reg[0x9015a]); + writel(0x8, ®s->reg[0x9015b]); + writel(0xe8, ®s->reg[0x9015c]); + writel(0x109, ®s->reg[0x9015d]); + writel(0x0, ®s->reg[0x9015e]); + writel(0x8140, ®s->reg[0x9015f]); + writel(0x10c, ®s->reg[0x90160]); + writel(0x10, ®s->reg[0x90161]); + writel(0x8138, ®s->reg[0x90162]); + writel(0x10c, ®s->reg[0x90163]); + writel(0x8, ®s->reg[0x90164]); + writel(0x7c8, ®s->reg[0x90165]); + writel(0x101, ®s->reg[0x90166]); + writel(0x8, ®s->reg[0x90167]); + writel(0x0, ®s->reg[0x90168]); + writel(0x8, ®s->reg[0x90169]); + writel(0x8, ®s->reg[0x9016a]); + writel(0x448, ®s->reg[0x9016b]); + writel(0x109, ®s->reg[0x9016c]); + writel(0xf, ®s->reg[0x9016d]); + writel(0x7c0, ®s->reg[0x9016e]); + writel(0x109, ®s->reg[0x9016f]); + writel(0x0, ®s->reg[0x90170]); + writel(0xe8, ®s->reg[0x90171]); + writel(0x109, ®s->reg[0x90172]); + writel(0x47, ®s->reg[0x90173]); + writel(0x630, ®s->reg[0x90174]); + writel(0x109, ®s->reg[0x90175]); + writel(0x8, ®s->reg[0x90176]); + writel(0x618, ®s->reg[0x90177]); + writel(0x109, ®s->reg[0x90178]); + writel(0x8, ®s->reg[0x90179]); + writel(0xe0, ®s->reg[0x9017a]); + writel(0x109, ®s->reg[0x9017b]); + writel(0x0, ®s->reg[0x9017c]); + writel(0x7c8, ®s->reg[0x9017d]); + writel(0x109, ®s->reg[0x9017e]); + writel(0x8, ®s->reg[0x9017f]); + writel(0x8140, ®s->reg[0x90180]); + writel(0x10c, ®s->reg[0x90181]); + writel(0x0, ®s->reg[0x90182]); + writel(0x1, ®s->reg[0x90183]); + writel(0x8, ®s->reg[0x90184]); + writel(0x8, ®s->reg[0x90185]); + writel(0x4, ®s->reg[0x90186]); + writel(0x8, ®s->reg[0x90187]); + writel(0x8, ®s->reg[0x90188]); + writel(0x7c8, ®s->reg[0x90189]); + writel(0x101, ®s->reg[0x9018a]); + writel(0x0, ®s->reg[0x90006]); + writel(0x0, ®s->reg[0x90007]); + writel(0x8, ®s->reg[0x90008]); + writel(0x0, ®s->reg[0x90009]); + writel(0x0, ®s->reg[0x9000a]); + writel(0x0, ®s->reg[0x9000b]); + writel(0x400, ®s->reg[0xd00e7]); + writel(0x0, ®s->reg[0x90017]); + writel(0x2a, ®s->reg[0x9001f]); + writel(0x6a, ®s->reg[0x90026]); + writel(0x0, ®s->reg[0x400d0]); + writel(0x101, ®s->reg[0x400d1]); + writel(0x105, ®s->reg[0x400d2]); + writel(0x107, ®s->reg[0x400d3]); + writel(0x10f, ®s->reg[0x400d4]); + writel(0x202, ®s->reg[0x400d5]); + writel(0x20a, ®s->reg[0x400d6]); + writel(0x20b, ®s->reg[0x400d7]); + writel(0x2, ®s->reg[0x2003a]); + writel(0x0, ®s->reg[0x9000c]); + writel(0x173, ®s->reg[0x9000d]); + writel(0x60, ®s->reg[0x9000e]); + writel(0x6110, ®s->reg[0x9000f]); + writel(0x2152, ®s->reg[0x90010]); + writel(0xdfbd, ®s->reg[0x90011]); + writel(0x60, ®s->reg[0x90012]); + writel(0x6152, ®s->reg[0x90013]); + writel(0x5a, ®s->reg[0x20010]); + writel(0x3, ®s->reg[0x20011]); + writel(0xe0, ®s->reg[0x40080]); + writel(0x12, ®s->reg[0x40081]); + writel(0xe0, ®s->reg[0x40082]); + writel(0x12, ®s->reg[0x40083]); + writel(0xe0, ®s->reg[0x40084]); + writel(0x12, ®s->reg[0x40085]); + writel(0xf, ®s->reg[0x400fd]); + writel(0x1, ®s->reg[0x10011]); + writel(0x1, ®s->reg[0x10012]); + writel(0x180, ®s->reg[0x10013]); + writel(0x1, ®s->reg[0x10018]); + writel(0x6209, ®s->reg[0x10002]); + writel(0x1, ®s->reg[0x100b2]); + writel(0x1, ®s->reg[0x101b4]); + writel(0x1, ®s->reg[0x102b4]); + writel(0x1, ®s->reg[0x103b4]); + writel(0x1, ®s->reg[0x104b4]); + writel(0x1, ®s->reg[0x105b4]); + writel(0x1, ®s->reg[0x106b4]); + writel(0x1, ®s->reg[0x107b4]); + writel(0x1, ®s->reg[0x108b4]); + writel(0x1, ®s->reg[0x11011]); + writel(0x1, ®s->reg[0x11012]); + writel(0x180, ®s->reg[0x11013]); + writel(0x1, ®s->reg[0x11018]); + writel(0x6209, ®s->reg[0x11002]); + writel(0x1, ®s->reg[0x110b2]); + writel(0x1, ®s->reg[0x111b4]); + writel(0x1, ®s->reg[0x112b4]); + writel(0x1, ®s->reg[0x113b4]); + writel(0x1, ®s->reg[0x114b4]); + writel(0x1, ®s->reg[0x115b4]); + writel(0x1, ®s->reg[0x116b4]); + writel(0x1, ®s->reg[0x117b4]); + writel(0x1, ®s->reg[0x118b4]); + writel(0x1, ®s->reg[0x12011]); + writel(0x1, ®s->reg[0x12012]); + writel(0x180, ®s->reg[0x12013]); + writel(0x1, ®s->reg[0x12018]); + writel(0x6209, ®s->reg[0x12002]); + writel(0x1, ®s->reg[0x120b2]); + writel(0x1, ®s->reg[0x121b4]); + writel(0x1, ®s->reg[0x122b4]); + writel(0x1, ®s->reg[0x123b4]); + writel(0x1, ®s->reg[0x124b4]); + writel(0x1, ®s->reg[0x125b4]); + writel(0x1, ®s->reg[0x126b4]); + writel(0x1, ®s->reg[0x127b4]); + writel(0x1, ®s->reg[0x128b4]); + writel(0x1, ®s->reg[0x13011]); + writel(0x1, ®s->reg[0x13012]); + writel(0x180, ®s->reg[0x13013]); + writel(0x1, ®s->reg[0x13018]); + writel(0x6209, ®s->reg[0x13002]); + writel(0x1, ®s->reg[0x130b2]); + writel(0x1, ®s->reg[0x131b4]); + writel(0x1, ®s->reg[0x132b4]); + writel(0x1, ®s->reg[0x133b4]); + writel(0x1, ®s->reg[0x134b4]); + writel(0x1, ®s->reg[0x135b4]); + writel(0x1, ®s->reg[0x136b4]); + writel(0x1, ®s->reg[0x137b4]); + writel(0x1, ®s->reg[0x138b4]); + writel(0x2, ®s->reg[0x2003a]); + writel(0x2, ®s->reg[0xc0080]); + writel(0x1, ®s->reg[0xd0000]); + writel(0x0, ®s->reg[0x000d0000]); + readl(®s->reg[0x00020010]); + writel(0x6a, ®s->reg[0x00020010]); + readl(®s->reg[0x0002001d]); + writel(0x1, ®s->reg[0x0002001d]); + /* + * CalBusy.0 =1, indicates the calibrator is actively calibrating. + * Wait Calibrating done. + */ + ret = readl_poll_timeout(®s->reg[0x20097], val, + !(val & BIT(1)), 1000); + if (ret) + puts("CalBusy.0 timeout\n"); + + writel(0x0, ®s->reg[0xd0000]); + writel(0x0, ®s->reg[0x2006e]); +} diff --git a/board/freescale/mx8mq_evk/ddr/helper.c b/board/freescale/mx8mq_evk/ddr/helper.c new file mode 100644 index 0000000000..4e87991c7b --- /dev/null +++ b/board/freescale/mx8mq_evk/ddr/helper.c @@ -0,0 +1,101 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define IMEM_LEN 32768 +#define DMEM_LEN 16384 +#define IMEM_2D_OFFSET 49152 + +#define IMEM_OFFSET_ADDR 0x00050000 +#define DMEM_OFFSET_ADDR 0x00054000 +#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) + +/* We need PHY iMEM PHY is 32KB padded */ +void ddr_load_train_code(enum fw_type type) +{ + u32 tmp32, i; + u32 error = 0; + unsigned long pr_to32, pr_from32; + unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0; + unsigned long imem_start = (unsigned long)&_end + fw_offset; + unsigned long dmem_start = imem_start + IMEM_LEN; + + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for (i = 0x0; i < IMEM_LEN; ) { + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for (i = 0x0; i < DMEM_LEN;) { + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + debug("check ddr4_pmu_train_imem code\n"); + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for (i = 0x0; i < IMEM_LEN;) { + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + + if (tmp32 != readl(pr_from32)) { + printf("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + if (error) + printf("check ddr4_pmu_train_imem code fail=%d\n", error); + else + debug("check ddr4_pmu_train_imem code pass\n"); + + debug("check ddr4_pmu_train_dmem code\n"); + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for (i = 0x0; i < DMEM_LEN;) { + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + if (tmp32 != readl(pr_from32)) { + printf("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + + if (error) + printf("check ddr4_pmu_train_dmem code fail=%d", error); + else + debug("check ddr4_pmu_train_dmem code pass\n"); +} diff --git a/board/freescale/mx8mq_evk/mx8mq_evk.c b/board/freescale/mx8mq_evk/mx8mq_evk.c new file mode 100644 index 0000000000..e31678efb7 --- /dev/null +++ b/board/freescale/mx8mq_evk/mx8mq_evk.c @@ -0,0 +1,156 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_QSPI +static iomux_v3_cfg_t const qspi_pads[] = { + IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), +}; + +int board_qspi_init(void) +{ + imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads)); + + set_clk_qspi(); + + return 0; +} +#endif + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + return 0; +} + +int dram_init(void) +{ + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; + else + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +#ifdef CONFIG_FEC_MXC +#define FEC_RST_PAD IMX_GPIO_NR(1, 9) +static iomux_v3_cfg_t const fec1_rst_pads[] = { + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, + ARRAY_SIZE(fec1_rst_pads)); + + gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst"); + gpio_direction_output(IMX_GPIO_NR(1, 9), 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(1, 9), 1); +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + setup_iomux_fec(); + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0); + return set_clk_enet(ENET_125MHZ); +} + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ + board_qspi_init(); + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "EVK"); + env_set("board_rev", "iMX8MQ"); +#endif + + return 0; +} diff --git a/board/freescale/mx8mq_evk/spl.c b/board/freescale/mx8mq_evk/spl.c new file mode 100644 index 0000000000..3e6aa51692 --- /dev/null +++ b/board/freescale/mx8mq_evk/spl.c @@ -0,0 +1,230 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" + +DECLARE_GLOBAL_DATA_PTR; + +void spl_dram_init(void) +{ + /* ddr init */ + ddr_init(); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + return ret; + } + + return 1; +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_FSEL2) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + init_clk_usdhc(0); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: + init_clk_usdhc(1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + default: + printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return -ENODEV; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return -ENODEV; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + pmic_reg_read(p, PFUZE100_SW3AVOL, ®); + if ((reg & 0x3f) != 0x18) { + reg &= ~0x3f; + reg |= 0x18; + pmic_reg_write(p, PFUZE100_SW3AVOL, reg); + } + + ret = pfuze_mode_init(p, APS_PFM); + if (ret < 0) + return ret; + + return 0; +} +#endif + +void spl_board_init(void) +{ + enable_tzc380(); + + /* Adjust pmic voltage to 1.0V for 800M */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + /* Serial download mode */ + if (is_usb_boot()) { + puts("Back to ROM, SDP\n"); + restore_boot_params(); + } + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + init_uart_clk(0); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/configs/mx8mq_evk_defconfig b/configs/mx8mq_evk_defconfig new file mode 100644 index 0000000000..5848168ac3 --- /dev/null +++ b/configs/mx8mq_evk_defconfig @@ -0,0 +1,27 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX8M=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_MX8MQ_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_THERMAL=y +CONFIG_FS_FAT=y diff --git a/include/configs/mx8mq_evk.h b/include/configs/mx8mq_evk.h new file mode 100644 index 0000000000..6fb8669bbe --- /dev/null +++ b/include/configs/mx8mq_evk.h @@ -0,0 +1,269 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8M_EVK_H +#define __IMX8M_EVK_H + +#include +#include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */ +#endif + +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x7E1000 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00182000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE +#define IMX_FEC_BASE 0x30BE0000 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=fsl-imx8mq-evk.dtb\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 +#define CONFIG_SYS_TEXT_BASE 0x40200000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR + +/* Monitor Command Prompt */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "u-boot=> " +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_FSL_QSPI /* enable the QUADSPI driver */ +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +#define FSL_QSPI_FLASH_SIZE (SZ_32M) +#define FSL_QSPI_FLASH_NUM 1 +#endif + +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_OCOTP +#define CONFIG_CMD_FUSE + +/* I2C Configs */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_OF_SYSTEM_SETUP + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DM_PMIC +#endif + +#endif