From patchwork Thu Jan 7 13:43:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1423304 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=JaB0t5Hm; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DBSB01t0gz9sSC for ; Fri, 8 Jan 2021 00:43:34 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8FDC9396EC4C; Thu, 7 Jan 2021 13:43:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8FDC9396EC4C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1610027012; bh=v0Taxrf/WaiZnzuWGocBMOJzwSPN+dMJKK1+zxjnmpI=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=JaB0t5HmrfMLf9L5Ql9YhpIfEj3V/OgF4vUP+V03+hF1F4Z8C1kfVG2pfArtoQP3l 6/dq7phcCa6JIqiOKV7wrLHDEh7HU2wRXBL4J7CEoBiusByC+/fTaiQVwKW8RjO9gi j+t517QnWw0FEqWQX8iQpajPF4KAp/AkPL46o0/8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qk1-x72f.google.com (mail-qk1-x72f.google.com [IPv6:2607:f8b0:4864:20::72f]) by sourceware.org (Postfix) with ESMTPS id 6578B386F417 for ; Thu, 7 Jan 2021 13:43:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 6578B386F417 Received: by mail-qk1-x72f.google.com with SMTP id 19so5376759qkm.8 for ; Thu, 07 Jan 2021 05:43:28 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=v0Taxrf/WaiZnzuWGocBMOJzwSPN+dMJKK1+zxjnmpI=; b=a4VkWJvdMp96sTdqgVYFJg4QvpSmcTAUffa56nuKxsuYIV5bMfiXqTn3DVUX6QmnJ/ 4iHu2FS3/GuLQNOHtTtJs+DJEO3cEWLx+uJenqFX+HPk1fMYoRYonNugu8cVQDWJ0Foz ftKFyBJkERexQsEY0VemQeJY8fhRj0ytBx88de/0CvD0VnG7uY5+aNp8grGlj6uyN4rh RgJ0XLHsy2Lg/S6wdpr6liZw057ny+TT8H+KavvWKsTH3S5nC4MnBt3ngbMHiUJaOK9l ZCE2LKqL8grJlQNPGvoOh3khF5S/kSItMg5mqFaVo/XIsNS/xnRq4VMmRo26+0fe9Gqi laNQ== X-Gm-Message-State: AOAM5307ffTyJkV+cz5DAR/xe30N+i8LlNgeQqOoVGHLgNaf38SlTU9L Zvb0wZN264yFMw1DoUaaA0U5NPTQ04iYdA2YjFkgzI1Vnob68A== X-Google-Smtp-Source: ABdhPJzR5u+i1t6znC2AR3aBkqVv7ftSECIQKbQUx6a3rGLRoAWva4S8Gdk+cskExahAoDJTTqXqn9UUodOpmOyBiKc= X-Received: by 2002:a05:620a:69c:: with SMTP id f28mr8971068qkh.127.1610027007677; Thu, 07 Jan 2021 05:43:27 -0800 (PST) MIME-Version: 1.0 Date: Thu, 7 Jan 2021 14:43:16 +0100 Message-ID: Subject: [PATCH] i386: Merge various insn name mapping code attributes To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" 2021-01-07 Uroš Bizjak No functional changes. gcc/ * config/i386/i386.md (insn): Merge from plusminus_insn, shift_insn, rotate_insn and optab code attributes. Update all uses to merged code attribute. * config/i386/sse.md: Update all uses to merged code attribute. * config/i386/mmx.md: Update all uses to merged code attribute. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Uros. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index cfff16ec07e..6f6af8c3cbf 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -869,7 +869,8 @@ (eq_attr "isa" "avx512vl") (symbol_ref "TARGET_AVX512VL") (eq_attr "isa" "noavx512vl") (symbol_ref "!TARGET_AVX512VL") (eq_attr "isa" "avxvnni") (symbol_ref "TARGET_AVXVNNI") - (eq_attr "isa" "avx512vnnivl") (symbol_ref "TARGET_AVX512VNNI && TARGET_AVX512VL") + (eq_attr "isa" "avx512vnnivl") + (symbol_ref "TARGET_AVX512VNNI && TARGET_AVX512VL") (eq_attr "mmx_isa" "native") (symbol_ref "!TARGET_MMX_WITH_SSE") @@ -894,17 +895,13 @@ (define_code_iterator sat_plusminus [ss_plus us_plus ss_minus us_minus]) -(define_code_iterator multdiv [mult div]) - -;; Base name for define_insn -(define_code_attr plusminus_insn - [(plus "add") (ss_plus "ssadd") (us_plus "usadd") - (minus "sub") (ss_minus "sssub") (us_minus "ussub")]) - ;; Base name for insn mnemonic. (define_code_attr plusminus_mnemonic [(plus "add") (ss_plus "adds") (us_plus "addus") (minus "sub") (ss_minus "subs") (us_minus "subus")]) + +(define_code_iterator multdiv [mult div]) + (define_code_attr multdiv_mnemonic [(mult "mul") (div "div")]) @@ -951,10 +948,6 @@ ;; Mapping of all shift operators (define_code_iterator any_shift [ashift lshiftrt ashiftrt]) -;; Base name for define_insn -(define_code_attr shift_insn - [(ashift "ashl") (lshiftrt "lshr") (ashiftrt "ashr")]) - ;; Base name for insn mnemonic. (define_code_attr shift [(ashift "sll") (lshiftrt "shr") (ashiftrt "sar")]) (define_code_attr vshift [(ashift "sll") (lshiftrt "srl") (ashiftrt "sra")]) @@ -962,9 +955,6 @@ ;; Mapping of rotate operators (define_code_iterator any_rotate [rotate rotatert]) -;; Base name for define_insn -(define_code_attr rotate_insn [(rotate "rotl") (rotatert "rotr")]) - ;; Base name for insn mnemonic. (define_code_attr rotate [(rotate "rol") (rotatert "ror")]) @@ -977,13 +967,9 @@ ;; Base name for x87 insn mnemonic. (define_code_attr absneg_mnemonic [(abs "fabs") (neg "fchs")]) -;; Used in signed and unsigned widening multiplications. +;; Mapping of extend operators (define_code_iterator any_extend [sign_extend zero_extend]) -;; Used for representing standard name for extend -(define_code_attr optab [(sign_extend "extend") - (zero_extend "zero_extend")]) - ;; Prefix for insn menmonic. (define_code_attr sgnprefix [(sign_extend "i") (zero_extend "") (div "i") (udiv "")]) @@ -997,7 +983,8 @@ ;; Used in signed and unsigned truncations. (define_code_iterator any_truncate [ss_truncate truncate us_truncate]) ;; Instruction suffix for truncations. -(define_code_attr trunsuffix [(ss_truncate "s") (truncate "") (us_truncate "us")]) +(define_code_attr trunsuffix + [(ss_truncate "s") (truncate "") (us_truncate "us")]) ;; Used in signed and unsigned fix. (define_code_iterator any_fix [fix unsigned_fix]) @@ -1011,6 +998,14 @@ (define_code_attr floatunssuffix [(float "") (unsigned_float "uns")]) (define_code_attr floatprefix [(float "s") (unsigned_float "u")]) +;; Base name for expression +(define_code_attr insn + [(plus "add") (ss_plus "ssadd") (us_plus "usadd") + (minus "sub") (ss_minus "sssub") (us_minus "ussub") + (sign_extend "extend") (zero_extend "zero_extend") + (ashift "ashl") (lshiftrt "lshr") (ashiftrt "ashr") + (rotate "rotl") (rotatert "rotr")]) + ;; All integer modes. (define_mode_iterator SWI1248x [QI HI SI DI]) @@ -7460,14 +7455,14 @@ ;; The patterns that match these are at the end of this file. -(define_expand "xf3" +(define_expand "xf3" [(set (match_operand:XF 0 "register_operand") (plusminus:XF (match_operand:XF 1 "register_operand") (match_operand:XF 2 "register_operand")))] "TARGET_80387") -(define_expand "3" +(define_expand "3" [(set (match_operand:MODEF 0 "register_operand") (plusminus:MODEF (match_operand:MODEF 1 "register_operand") @@ -11399,7 +11394,7 @@ ;; See comment above `ashl3' about how this works. -(define_expand "3" +(define_expand "3" [(set (match_operand:SDWIM 0 "") (any_shiftrt:SDWIM (match_operand:SDWIM 1 "") (match_operand:QI 2 "nonmemory_operand")))] @@ -11407,7 +11402,7 @@ "ix86_expand_binary_operator (, mode, operands); DONE;") ;; Avoid useless masking of count operand. -(define_insn_and_split "*3_mask" +(define_insn_and_split "*3_mask" [(set (match_operand:SWI48 0 "nonimmediate_operand") (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") @@ -11430,7 +11425,7 @@ "operands[2] = gen_lowpart (QImode, operands[2]);" [(set_attr "isa" "*,bmi2")]) -(define_insn_and_split "*3_mask_1" +(define_insn_and_split "*3_mask_1" [(set (match_operand:SWI48 0 "nonimmediate_operand") (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") @@ -11452,7 +11447,7 @@ "" [(set_attr "isa" "*,bmi2")]) -(define_insn_and_split "*3_doubleword_mask" +(define_insn_and_split "*3_doubleword_mask" [(set (match_operand: 0 "register_operand") (any_shiftrt: (match_operand: 1 "register_operand") @@ -11494,7 +11489,7 @@ emit_move_insn (operands[4], operands[5]); }) -(define_insn_and_split "*3_doubleword_mask_1" +(define_insn_and_split "*3_doubleword_mask_1" [(set (match_operand: 0 "register_operand") (any_shiftrt: (match_operand: 1 "register_operand") @@ -11533,7 +11528,7 @@ emit_move_insn (operands[4], operands[5]); }) -(define_insn_and_split "*3_doubleword" +(define_insn_and_split "*3_doubleword" [(set (match_operand:DWI 0 "register_operand" "=&r") (any_shiftrt:DWI (match_operand:DWI 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "c"))) @@ -11542,7 +11537,7 @@ "#" "epilogue_completed" [(const_int 0)] - "ix86_split_ (operands, NULL_RTX, mode); DONE;" + "ix86_split_ (operands, NULL_RTX, mode); DONE;" [(set_attr "type" "multi")]) ;; By default we don't ask for a scratch register, because when DWImode @@ -11559,7 +11554,7 @@ (match_dup 3)] "TARGET_CMOVE" [(const_int 0)] - "ix86_split_ (operands, operands[3], mode); DONE;") + "ix86_split_ (operands, operands[3], mode); DONE;") (define_insn "x86_64_shrd" [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m") @@ -11663,7 +11658,7 @@ DONE; }) -(define_insn "*bmi2_3_1" +(define_insn "*bmi2_3_1" [(set (match_operand:SWI48 0 "register_operand" "=r") (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm") (match_operand:SWI48 2 "register_operand" "r")))] @@ -11672,7 +11667,7 @@ [(set_attr "type" "ishiftx") (set_attr "mode" "")]) -(define_insn "*3_1" +(define_insn "*3_1" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r") (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0,rm") @@ -11715,7 +11710,7 @@ (any_shiftrt:SWI48 (match_dup 1) (match_dup 2)))] "operands[2] = gen_lowpart (mode, operands[2]);") -(define_insn "*bmi2_si3_1_zext" +(define_insn "*bmi2_si3_1_zext" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "rm") @@ -11725,7 +11720,7 @@ [(set_attr "type" "ishiftx") (set_attr "mode" "SI")]) -(define_insn "*si3_1_zext" +(define_insn "*si3_1_zext" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,rm") @@ -11769,7 +11764,7 @@ (zero_extend:DI (any_shiftrt:SI (match_dup 1) (match_dup 2))))] "operands[2] = gen_lowpart (SImode, operands[2]);") -(define_insn "*3_1" +(define_insn "*3_1" [(set (match_operand:SWI12 0 "nonimmediate_operand" "=m") (any_shiftrt:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "0") @@ -11793,7 +11788,7 @@ (const_string "*"))) (set_attr "mode" "")]) -(define_insn "*3_1_slp" +(define_insn "*3_1_slp" [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+")) (any_shiftrt:SWI12 (match_operand:SWI12 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "cI"))) @@ -11821,7 +11816,7 @@ ;; This pattern can't accept a variable shift count, since shifts by ;; zero don't affect the flags. We assume that shifts by constant ;; zero are optimized away. -(define_insn "*3_cmp" +(define_insn "*3_cmp" [(set (reg FLAGS_REG) (compare (any_shiftrt:SWI @@ -11853,7 +11848,7 @@ (const_string "*"))) (set_attr "mode" "")]) -(define_insn "*si3_cmp_zext" +(define_insn "*si3_cmp_zext" [(set (reg FLAGS_REG) (compare (any_shiftrt:SI (match_operand:SI 1 "register_operand" "0") @@ -11885,7 +11880,7 @@ (const_string "*"))) (set_attr "mode" "SI")]) -(define_insn "*3_cconly" +(define_insn "*3_cconly" [(set (reg FLAGS_REG) (compare (any_shiftrt:SWI @@ -11917,14 +11912,14 @@ ;; Rotate instructions -(define_expand "ti3" +(define_expand "ti3" [(set (match_operand:TI 0 "register_operand") (any_rotate:TI (match_operand:TI 1 "register_operand") (match_operand:QI 2 "nonmemory_operand")))] "TARGET_64BIT" { if (const_1_to_63_operand (operands[2], VOIDmode)) - emit_insn (gen_ix86_ti3_doubleword + emit_insn (gen_ix86_ti3_doubleword (operands[0], operands[1], operands[2])); else FAIL; @@ -11932,7 +11927,7 @@ DONE; }) -(define_expand "di3" +(define_expand "di3" [(set (match_operand:DI 0 "shiftdi_operand") (any_rotate:DI (match_operand:DI 1 "shiftdi_operand") (match_operand:QI 2 "nonmemory_operand")))] @@ -11941,7 +11936,7 @@ if (TARGET_64BIT) ix86_expand_binary_operator (, DImode, operands); else if (const_1_to_31_operand (operands[2], VOIDmode)) - emit_insn (gen_ix86_di3_doubleword + emit_insn (gen_ix86_di3_doubleword (operands[0], operands[1], operands[2])); else FAIL; @@ -11949,7 +11944,7 @@ DONE; }) -(define_expand "3" +(define_expand "3" [(set (match_operand:SWIM124 0 "nonimmediate_operand") (any_rotate:SWIM124 (match_operand:SWIM124 1 "nonimmediate_operand") (match_operand:QI 2 "nonmemory_operand")))] @@ -11957,7 +11952,7 @@ "ix86_expand_binary_operator (, mode, operands); DONE;") ;; Avoid useless masking of count operand. -(define_insn_and_split "*3_mask" +(define_insn_and_split "*3_mask" [(set (match_operand:SWI48 0 "nonimmediate_operand") (any_rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") @@ -11995,7 +11990,7 @@ (subreg:QI (match_dup 2) 0)))] "operands[4] = gen_reg_rtx (mode);") -(define_insn_and_split "*3_mask_1" +(define_insn_and_split "*3_mask_1" [(set (match_operand:SWI48 0 "nonimmediate_operand") (any_rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") @@ -12102,7 +12097,7 @@ [(set_attr "type" "rotatex") (set_attr "mode" "")]) -(define_insn "*3_1" +(define_insn "*3_1" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r") (any_rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0,rm") @@ -12169,7 +12164,7 @@ [(set_attr "type" "rotatex") (set_attr "mode" "SI")]) -(define_insn "*si3_1_zext" +(define_insn "*si3_1_zext" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (any_rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,rm") @@ -12228,7 +12223,7 @@ [(set (match_dup 0) (zero_extend:DI (rotatert:SI (match_dup 1) (match_dup 2))))]) -(define_insn "*3_1" +(define_insn "*3_1" [(set (match_operand:SWI12 0 "nonimmediate_operand" "=m") (any_rotate:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "0") (match_operand:QI 2 "nonmemory_operand" "c"))) @@ -12251,7 +12246,7 @@ (const_string "*"))) (set_attr "mode" "")]) -(define_insn "*3_1_slp" +(define_insn "*3_1_slp" [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+")) (any_rotate:SWI12 (match_operand:SWI12 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "cI"))) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index d5e8df82d44..a6ddc710a84 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1135,7 +1135,7 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_expand "mmx_3" +(define_expand "mmx_3" [(set (match_operand:MMXMODEI8 0 "register_operand") (plusminus:MMXMODEI8 (match_operand:MMXMODEI8 1 "register_mmxmem_operand") @@ -1143,7 +1143,7 @@ "TARGET_MMX || TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_expand "3" +(define_expand "3" [(set (match_operand:MMXMODEI 0 "register_operand") (plusminus:MMXMODEI (match_operand:MMXMODEI 1 "register_operand") @@ -1151,7 +1151,7 @@ "TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*mmx_3" +(define_insn "*mmx_3" [(set (match_operand:MMXMODEI8 0 "register_operand" "=y,x,Yv") (plusminus:MMXMODEI8 (match_operand:MMXMODEI8 1 "register_mmxmem_operand" "0,0,Yv") @@ -1167,7 +1167,7 @@ (set_attr "type" "mmxadd,sseadd,sseadd") (set_attr "mode" "DI,TI,TI")]) -(define_expand "mmx_3" +(define_expand "mmx_3" [(set (match_operand:MMXMODE12 0 "register_operand") (sat_plusminus:MMXMODE12 (match_operand:MMXMODE12 1 "register_mmxmem_operand") @@ -1175,7 +1175,7 @@ "TARGET_MMX || TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*mmx_3" +(define_insn "*mmx_3" [(set (match_operand:MMXMODE12 0 "register_operand" "=y,x,Yv") (sat_plusminus:MMXMODE12 (match_operand:MMXMODE12 1 "register_mmxmem_operand" "0,0,Yv") @@ -1508,7 +1508,7 @@ (match_operand:DI 2 "nonmemory_operand")))] "TARGET_MMX_WITH_SSE") -(define_insn "mmx_3" +(define_insn "mmx_3" [(set (match_operand:MMXMODE248 0 "register_operand" "=y,x,Yv") (any_lshift:MMXMODE248 (match_operand:MMXMODE248 1 "register_operand" "0,0,Yv") @@ -1527,7 +1527,7 @@ (const_string "0"))) (set_attr "mode" "DI,TI,TI")]) -(define_expand "3" +(define_expand "3" [(set (match_operand:MMXMODE248 0 "register_operand") (any_lshift:MMXMODE248 (match_operand:MMXMODE248 1 "register_operand") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 4fd7358dc18..928eff5e05e 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1854,7 +1854,7 @@ } [(set_attr "isa" "noavx,noavx,avx,avx")]) -(define_expand "3" +(define_expand "3" [(set (match_operand:VF 0 "register_operand") (plusminus:VF (match_operand:VF 1 "") @@ -1862,7 +1862,7 @@ "TARGET_SSE && && " "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*3" +(define_insn "*3" [(set (match_operand:VF 0 "register_operand" "=x,v") (plusminus:VF (match_operand:VF 1 "" "0,v") @@ -1879,7 +1879,7 @@ ;; Standard scalar operation patterns which preserve the rest of the ;; vector for combiner. -(define_insn "*_vm3" +(define_insn "*_vm3" [(set (match_operand:VF_128 0 "register_operand" "=x,v") (vec_merge:VF_128 (vec_duplicate:VF_128 @@ -1899,7 +1899,7 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) -(define_insn "_vm3" +(define_insn "_vm3" [(set (match_operand:VF_128 0 "register_operand" "=x,v") (vec_merge:VF_128 (plusminus:VF_128 @@ -2569,7 +2569,7 @@ operands[5] = GEN_INT (ival); }) -(define_insn "avx_hv4df3" +(define_insn "avx_hv4df3" [(set (match_operand:V4DF 0 "register_operand" "=x") (vec_concat:V4DF (vec_concat:V2DF @@ -2698,7 +2698,7 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "V2DF")]) -(define_insn "avx_hv8sf3" +(define_insn "avx_hv8sf3" [(set (match_operand:V8SF 0 "register_operand" "=x") (vec_concat:V8SF (vec_concat:V4SF @@ -2741,7 +2741,7 @@ (set_attr "prefix" "vex") (set_attr "mode" "V8SF")]) -(define_insn "sse3_hv4sf3" +(define_insn "sse3_hv4sf3" [(set (match_operand:V4SF 0 "register_operand" "=x,x") (vec_concat:V4SF (vec_concat:V2SF @@ -11489,7 +11489,7 @@ "TARGET_SSE2" "operands[2] = force_reg (mode, CONST0_RTX (mode));") -(define_expand "3" +(define_expand "3" [(set (match_operand:VI_AVX2 0 "register_operand") (plusminus:VI_AVX2 (match_operand:VI_AVX2 1 "vector_operand") @@ -11497,7 +11497,7 @@ "TARGET_SSE2" "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_expand "3_mask" +(define_expand "3_mask" [(set (match_operand:VI48_AVX512VL 0 "register_operand") (vec_merge:VI48_AVX512VL (plusminus:VI48_AVX512VL @@ -11508,7 +11508,7 @@ "TARGET_AVX512F" "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_expand "3_mask" +(define_expand "3_mask" [(set (match_operand:VI12_AVX512VL 0 "register_operand") (vec_merge:VI12_AVX512VL (plusminus:VI12_AVX512VL @@ -11519,7 +11519,7 @@ "TARGET_AVX512BW" "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*3" +(define_insn "*3" [(set (match_operand:VI_AVX2 0 "register_operand" "=x,v") (plusminus:VI_AVX2 (match_operand:VI_AVX2 1 "bcst_vector_operand" "0,v") @@ -11534,7 +11534,7 @@ (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "")]) -(define_insn "*3_mask" +(define_insn "*3_mask" [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") (vec_merge:VI48_AVX512VL (plusminus:VI48_AVX512VL @@ -11548,7 +11548,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "*3_mask" +(define_insn "*3_mask" [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") (vec_merge:VI12_AVX512VL (plusminus:VI12_AVX512VL @@ -11562,7 +11562,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_expand "_3" +(define_expand "_3" [(set (match_operand:VI12_AVX2_AVX512BW 0 "register_operand") (sat_plusminus:VI12_AVX2_AVX512BW (match_operand:VI12_AVX2_AVX512BW 1 "vector_operand") @@ -11570,7 +11570,7 @@ "TARGET_SSE2 && && " "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*_3" +(define_insn "*_3" [(set (match_operand:VI12_AVX2_AVX512BW 0 "register_operand" "=x,v") (sat_plusminus:VI12_AVX2_AVX512BW (match_operand:VI12_AVX2_AVX512BW 1 "vector_operand" "0,v") @@ -12316,7 +12316,7 @@ (const_string "0"))) (set_attr "mode" "")]) -(define_insn "3" +(define_insn "3" [(set (match_operand:VI248_AVX512BW_2 0 "register_operand" "=v,v") (any_lshift:VI248_AVX512BW_2 (match_operand:VI248_AVX512BW_2 1 "nonimmediate_operand" "v,vm") @@ -12330,7 +12330,7 @@ (const_string "0"))) (set_attr "mode" "")]) -(define_insn "3" +(define_insn "3" [(set (match_operand:VI248_AVX2 0 "register_operand" "=x,x") (any_lshift:VI248_AVX2 (match_operand:VI248_AVX2 1 "register_operand" "0,x") @@ -12349,7 +12349,7 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) -(define_insn "3" +(define_insn "3" [(set (match_operand:VI248_AVX512BW 0 "register_operand" "=v,v") (any_lshift:VI248_AVX512BW (match_operand:VI248_AVX512BW 1 "nonimmediate_operand" "v,m") @@ -12390,7 +12390,7 @@ operands[4] = gen_lowpart (mode, operands[3]); }) -(define_insn "avx512bw_3" +(define_insn "avx512bw_3" [(set (match_operand:VIMAX_AVX512VL 0 "register_operand" "=v") (any_lshift:VIMAX_AVX512VL (match_operand:VIMAX_AVX512VL 1 "nonimmediate_operand" "vm") @@ -12405,7 +12405,7 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "")]) -(define_insn "_3" +(define_insn "_3" [(set (match_operand:VIMAX_AVX2 0 "register_operand" "=x,v") (any_lshift:VIMAX_AVX2 (match_operand:VIMAX_AVX2 1 "register_operand" "0,v") @@ -17611,7 +17611,7 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "OI")]) -(define_expand "v16qiv16hi2" +(define_expand "v16qiv16hi2" [(set (match_operand:V16HI 0 "register_operand") (any_extend:V16HI (match_operand:V16QI 1 "nonimmediate_operand")))] @@ -17628,7 +17628,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_expand "v32qiv32hi2" +(define_expand "v32qiv32hi2" [(set (match_operand:V32HI 0 "register_operand") (any_extend:V32HI (match_operand:V32QI 1 "nonimmediate_operand")))] @@ -17683,7 +17683,7 @@ (any_extend:V8HI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V8QImode, 0);") -(define_expand "v8qiv8hi2" +(define_expand "v8qiv8hi2" [(set (match_operand:V8HI 0 "register_operand") (any_extend:V8HI (match_operand:V8QI 1 "nonimmediate_operand")))] @@ -17707,7 +17707,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_expand "v16qiv16si2" +(define_expand "v16qiv16si2" [(set (match_operand:V16SI 0 "register_operand") (any_extend:V16SI (match_operand:V16QI 1 "nonimmediate_operand")))] @@ -17760,7 +17760,7 @@ (any_extend:V8SI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V8QImode, 0);") -(define_expand "v8qiv8si2" +(define_expand "v8qiv8si2" [(set (match_operand:V8SI 0 "register_operand") (any_extend:V8SI (match_operand:V8QI 1 "nonimmediate_operand")))] @@ -17823,7 +17823,7 @@ (any_extend:V4SI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V4QImode, 0);") -(define_expand "v4qiv4si2" +(define_expand "v4qiv4si2" [(set (match_operand:V4SI 0 "register_operand") (any_extend:V4SI (match_operand:V4QI 1 "nonimmediate_operand")))] @@ -17847,7 +17847,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_expand "v16hiv16si2" +(define_expand "v16hiv16si2" [(set (match_operand:V16SI 0 "register_operand") (any_extend:V16SI (match_operand:V16HI 1 "nonimmediate_operand")))] @@ -17864,7 +17864,7 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "OI")]) -(define_expand "v8hiv8si2" +(define_expand "v8hiv8si2" [(set (match_operand:V8SI 0 "register_operand") (any_extend:V8SI (match_operand:V8HI 1 "nonimmediate_operand")))] @@ -17915,7 +17915,7 @@ (any_extend:V4SI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V4HImode, 0);") -(define_expand "v4hiv4si2" +(define_expand "v4hiv4si2" [(set (match_operand:V4SI 0 "register_operand") (any_extend:V4SI (match_operand:V4HI 1 "nonimmediate_operand")))] @@ -17973,7 +17973,7 @@ (any_extend:V8DI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V8QImode, 0);") -(define_expand "v8qiv8di2" +(define_expand "v8qiv8di2" [(set (match_operand:V8DI 0 "register_operand") (any_extend:V8DI (match_operand:V8QI 1 "nonimmediate_operand")))] @@ -18034,7 +18034,7 @@ (any_extend:V4DI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V4QImode, 0);") -(define_expand "v4qiv4di2" +(define_expand "v4qiv4di2" [(set (match_operand:V4DI 0 "register_operand") (any_extend:V4DI (match_operand:V4QI 1 "nonimmediate_operand")))] @@ -18062,7 +18062,7 @@ (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "TI")]) -(define_expand "v2qiv2di2" +(define_expand "v2qiv2di2" [(set (match_operand:V2DI 0 "register_operand") (any_extend:V2DI (match_operand:V2QI 1 "register_operand")))] @@ -18083,7 +18083,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_expand "v8hiv8di2" +(define_expand "v8hiv8di2" [(set (match_operand:V8DI 0 "register_operand") (any_extend:V8DI (match_operand:V8HI 1 "nonimmediate_operand")))] @@ -18132,7 +18132,7 @@ (any_extend:V4DI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V4HImode, 0);") -(define_expand "v4hiv4di2" +(define_expand "v4hiv4di2" [(set (match_operand:V4DI 0 "register_operand") (any_extend:V4DI (match_operand:V4HI 1 "nonimmediate_operand")))] @@ -18193,7 +18193,7 @@ (any_extend:V2DI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V2HImode, 0);") -(define_expand "v2hiv2di2" +(define_expand "v2hiv2di2" [(set (match_operand:V2DI 0 "register_operand") (any_extend:V2DI (match_operand:V2HI 1 "nonimmediate_operand")))] @@ -18217,7 +18217,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_expand "v8siv8di2" +(define_expand "v8siv8di2" [(set (match_operand:V8DI 0 "register_operand" "=v") (any_extend:V8DI (match_operand:V8SI 1 "nonimmediate_operand" "vm")))] @@ -18234,7 +18234,7 @@ (set_attr "prefix_extra" "1") (set_attr "mode" "OI")]) -(define_expand "v4siv4di2" +(define_expand "v4siv4di2" [(set (match_operand:V4DI 0 "register_operand" "=v") (any_extend:V4DI (match_operand:V4SI 1 "nonimmediate_operand" "vm")))] @@ -18283,7 +18283,7 @@ (any_extend:V2DI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V2SImode, 0);") -(define_expand "v2siv2di2" +(define_expand "v2siv2di2" [(set (match_operand:V2DI 0 "register_operand") (any_extend:V2DI (match_operand:V2SI 1 "nonimmediate_operand")))] @@ -19822,7 +19822,7 @@ (set_attr "prefix_extra" "2") (set_attr "mode" "TI")]) -(define_expand "3" +(define_expand "3" [(set (match_operand:VI1_AVX512 0 "register_operand") (any_shift:VI1_AVX512 (match_operand:VI1_AVX512 1 "register_operand") @@ -21575,7 +21575,7 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "")]) -(define_insn "_v" +(define_insn "_v" [(set (match_operand:VI48_AVX512F 0 "register_operand" "=v") (any_lshift:VI48_AVX512F (match_operand:VI48_AVX512F 1 "register_operand" "v") @@ -21586,7 +21586,7 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "")]) -(define_insn "_v" +(define_insn "_v" [(set (match_operand:VI2_AVX512VL 0 "register_operand" "=v") (any_lshift:VI2_AVX512VL (match_operand:VI2_AVX512VL 1 "register_operand" "v")