From patchwork Wed Dec 23 06:01:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419588 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=q6xztLYw; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D12gp5Q27z9sVm for ; Wed, 23 Dec 2020 17:03:18 +1100 (AEDT) Received: from localhost ([::1]:50126 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxEy-0008QP-Lo for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:03:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39198) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxDy-0008Ot-8D for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:16 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:39799) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxDs-0000KF-Mr for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:11 -0500 Received: by mail-pj1-x1032.google.com with SMTP id hk16so2613492pjb.4 for ; Tue, 22 Dec 2020 22:02:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rAW07Dku/fTSAeGLs/tMwXeih7Omsc2EM7pIkYPifgA=; b=q6xztLYwFw1kzEMs+tCaA80dtPD5X3ysM8Xh1aKZb3jN+8JsyEkbKzA0Xw3ZwztEJ5 0ivL6zXErkq4YT12V1Gls9ImIsq10Ie7/0JYIAS8o/EjXclJ1InarV7dYxi4h8qoWXjr FiL9v37IZ0B6RzTjH1q8dAimn9o5PbhLHg3UmodUPr0N46rOaFMYwa5TaoUvZp5Xu8Vx C8z6gifNFZu1S7dW/7KtOMYwKht3e41rnkkfC+CPwQ5AijtqzIUhPpWViG0LXGYqTBla ltIMZPGnDgzgihWanAuPiGbIPMk9/w8wu2GgkowUXuZGcCo6jvBI7rknlUD94UAxmrdw 5BYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rAW07Dku/fTSAeGLs/tMwXeih7Omsc2EM7pIkYPifgA=; b=VoCCM3MIAXJvhUmIRo2YYG3URNrenpG0OukeCaMuEZmTZ27YOo0w8zFZ2DgXheCL82 NaQr7IJQyTWbD1zH2NvFt218b5S0pWDrZOdzqwoEmNRPefIUqKCU/Xocz5qDsQ6iFDlx UZXJQPsVXLJHUNFqSfZLlrsiCkn7BcE9xCwA8Ec4h62aLdUCzfqwPlOENG2CvyRpHrDj E7FT7sRybWV16x/pWBwTljVHU+lw0AiliDrzWO/Q9oduxUVy6O75nDcVetRCk2GSZ0NI K9myj4RySG9+pGCKI0lJl0eUQfaprMusJ40zxtU2CLhyG20IEW0QLJi4etTi4Khe1M5j hKbg== X-Gm-Message-State: AOAM532Aui3gToICIXLT0oxCY6EtAvxsuzoF9nhLkdC9aazWrrqZAFDD U8BT7yn5ws6kEQEmvqE+gYapkkx1V2lZxg== X-Google-Smtp-Source: ABdhPJwTRG18Ejh6Ybf3yH1Whp+ot+O+8PwT7Os85K8sWaPIsh+UcJJ6q8Ga62y2J9q3dNGV1WU5Xg== X-Received: by 2002:a17:90a:f00f:: with SMTP id bt15mr25500109pjb.209.1608703327270; Tue, 22 Dec 2020 22:02:07 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 01/22] tcg/tci: Drop L and S constraints Date: Tue, 22 Dec 2020 22:01:43 -0800 Message-Id: <20201223060204.576856-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" These are identical to the 'r' constraint. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 231b9b1775..50a08bef03 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -46,11 +46,11 @@ # define R64 "r" #endif #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS -# define L "L", "L" -# define S "S", "S" +# define L "r", "r" +# define S "r", "r" #else -# define L "L" -# define S "S" +# define L "r" +# define S "r" #endif /* TODO: documentation. */ @@ -390,8 +390,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch (*ct_str++) { case 'r': - case 'L': /* qemu_ld constraint */ - case 'S': /* qemu_st constraint */ ct->regs = BIT(TCG_TARGET_NB_REGS) - 1; break; default: From patchwork Wed Dec 23 06:01:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419597 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=cRFinEUE; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D12qt4D0yz9sVm for ; Wed, 23 Dec 2020 17:10:18 +1100 (AEDT) Received: from localhost ([::1]:38782 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxLk-00075O-Ho for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:10:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39216) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxDz-0008P0-1J for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:16 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:43329) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxDv-0000Kw-Kv for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:14 -0500 Received: by mail-pf1-x434.google.com with SMTP id c12so9757276pfo.10 for ; Tue, 22 Dec 2020 22:02:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zGMNyIm+K/W3aZHsjQzBQ/qpcbywBXoHa8cbHlQEpxs=; b=cRFinEUEnaaOyBNCL6bIgGjkVR8WRQ57xQm6lCRFAT+xhIiWua1Em9Ne6WdAb9Ia0M bwz8StynpWlz2n1uxbF34pZQl3pAyqwYKJ8Nb7xKwFPWSrb8O/obHhUALos2IrNIeOE7 bdySv01yNqXW0cKy/fUVOH9JH+a9esF7ldc0tnEibhDlHPxxJkiQKzwOIF6pDbPonpcg KDvqUyEYQVUBtLICrH2QhOF8U7ZPZd+0hZJMg8nOaiXqIGnBrTvDueqiDbmwbOSPQhl8 8cels7ZtbYIAascdCcgKjy+/5vsytp/l1H8YDvUsDb/r2cPZPqLh4ANm4nFApPHZiY/d 4THA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zGMNyIm+K/W3aZHsjQzBQ/qpcbywBXoHa8cbHlQEpxs=; b=Rm+Xs69B8JB84NCDXvb1187/UtHAQvQTgiyJ83Ww84or+f/lDfRjjQT1VfsOqMUvvs to4UFQqGoolfsU6xYdW9ld6q9kVHvChWFfHCCbWlyVHLBClZ34NbaDT/GA6VMVfmqz/O hGvZTkSJzqUbK2BfQgYNxsny0Sw3Qab1JQAmN0sOZZL6QHS634kz+LAfJjhsVSZCqLwy /dHMBZuBxAlKbQxdPTbSIine4IBOi+/HH+t0D412mNcTh+se8iX6g2EkQNInY3Scxynj zo0S5tgMGRMfEABoWB/x4YxXB2Qa7RpeWHc7LN+gS64h1LjyDG+sjU+obPYvD+knhGDQ cDcQ== X-Gm-Message-State: AOAM531wFWUAdvMygGGo9Re4BnSyxD4FXuGIEQucjDivP4qw54MDORG+ 6Je+TdzVjMyjOvZAsBekbk342U9VE9KLYA== X-Google-Smtp-Source: ABdhPJy5RHRchrX1iFOvNZ6xbCLi0jRtBgxwO6xDxPMZz1VtcYCE21Fo3hAvdYkwZR9mqA4MkKem8A== X-Received: by 2002:a63:5d5f:: with SMTP id o31mr23444902pgm.295.1608703328421; Tue, 22 Dec 2020 22:02:08 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 02/22] tcg/i386: Move constraint type check to tcg_target_const_match Date: Tue, 22 Dec 2020 22:01:44 -0800 Message-Id: <20201223060204.576856-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Rather than check the type when filling in the constraint, check it when matching the constant. This removes the only use of the type argument to target_parse_constraint. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index d8797ed398..b73873f715 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -254,13 +254,13 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, break; case 'e': - ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_S32); + ct->ct |= TCG_CT_CONST_S32; break; case 'Z': - ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_U32); + ct->ct |= TCG_CT_CONST_U32; break; case 'I': - ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_I32); + ct->ct |= TCG_CT_CONST_I32; break; default: @@ -277,14 +277,20 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, if (ct & TCG_CT_CONST) { return 1; } - if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { - return 1; - } - if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { - return 1; - } - if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) { - return 1; + if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { + if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | TCG_CT_CONST_I32)) { + return 1; + } + } else { + if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { + return 1; + } + if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { + return 1; + } + if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) { + return 1; + } } if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { return 1; From patchwork Wed Dec 23 06:01:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419592 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=EkExbet/; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D12lr6zYXz9sVm for ; Wed, 23 Dec 2020 17:06:48 +1100 (AEDT) Received: from localhost ([::1]:58772 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxIM-0003bw-9b for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:06:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39294) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxE5-0008Py-Np for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:21 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:35769) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxDv-0000Lc-LG for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:21 -0500 Received: by mail-pj1-x102d.google.com with SMTP id b5so2623339pjl.0 for ; Tue, 22 Dec 2020 22:02:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jwoUkFYPLhkV44osybn2ygv0a2eAfyC9vW2c8OoHcPA=; b=EkExbet/bnqnfCskGFgS7wb90LR0EK+/NfVqjr4l/S1jUmp0y7bAg5LMyvzrnFWIq6 jbg/KGppeVRiqBzamW0SDeVgqcqUTI6QWQxmZLgI2aQU2XhDqQ7QRpeoP+gkomF+Qz6O 22DhLKuBEMUSUD/3iUbTea53NSfuNyfWkKy8LuNAeS+bG0JnxLvQCRoqddPlZXRHhgp8 YjPGR6EOa2z+QWTGNogUm4owEGHvuA7NvfPL4G0zRUEZdYrhf7ppKMGGFrQvjE2iWMbM ZYZPY1JXr81Mx2WiBIkpDbOwUv2EFQAJYMvCNfp5iWu1bnGZ4XkgtEaCr7J9RtER8Ns7 OXDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jwoUkFYPLhkV44osybn2ygv0a2eAfyC9vW2c8OoHcPA=; b=hDw5ankmyDFxiMm1HWwcRq/6qr8w7Plud3PWsI/JC67/3ilVeuBRlO0FH8PvrnyN58 6fJUBrbryTaCuTgJ01kAXzEVTw5uP9g/fjgUndGOUNYFUx+JLNM3LyxuzWHDmERPm2t+ a8+Dv7bbJ11RqLw367gDV0hONLYlsY3fxNA/9i0eoLlbkn++LXoMCJcygbgyAK+VJybX BBJ4Kg6RUNSSW7AfHVr7Li1ca9O1YeVMnVwxtko4toT3UBILPskl9XvfMdtfO6GY5bC9 tYYJcbAWsckkxiqz2undThNVCDA27zCLe5ValMXC0zUpl+X9Kn/UmPQ9s0+fGA4nYxe8 aNmQ== X-Gm-Message-State: AOAM530+wdx6jdpBTR2qtMHUb/pBqvjfkx60RSBHvzULXxjDH2yqUgcM tXPI8iBPe5Mt+8X2g1TLBiKSkDrqHBenVw== X-Google-Smtp-Source: ABdhPJwtaojV4esCYm0nr5++giclTfsXUBPuyMKcKATcuYF3T6KiXFNWR8mLSJjnsoLLuMMBB8Arog== X-Received: by 2002:a17:902:7592:b029:dc:3c87:1c63 with SMTP id j18-20020a1709027592b02900dc3c871c63mr13075102pll.47.1608703329575; Tue, 22 Dec 2020 22:02:09 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 03/22] tcg: Split out target constraints to tcg-target-constr.h Date: Tue, 22 Dec 2020 22:01:45 -0800 Message-Id: <20201223060204.576856-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This eliminates the target-specific function target_parse_constraint and folds it into the single caller, process_op_defs. Since this is done directly into the switch statement, duplicates are compilation errors rather than silently ignored at runtime. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-constr.h | 26 ++++++++++++++ tcg/i386/tcg-target.h | 1 + tcg/tcg.c | 33 ++++++++++++++--- tcg/i386/tcg-target.c.inc | 70 ++---------------------------------- 4 files changed, 58 insertions(+), 72 deletions(-) create mode 100644 tcg/i386/tcg-target-constr.h diff --git a/tcg/i386/tcg-target-constr.h b/tcg/i386/tcg-target-constr.h new file mode 100644 index 0000000000..e4a4886b6c --- /dev/null +++ b/tcg/i386/tcg-target-constr.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: MIT */ +/* + * i386 target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +REGS('a', 1u << TCG_REG_EAX) +REGS('b', 1u << TCG_REG_EBX) +REGS('c', 1u << TCG_REG_ECX) +REGS('d', 1u << TCG_REG_EDX) +REGS('S', 1u << TCG_REG_ESI) +REGS('D', 1u << TCG_REG_EDI) + +REGS('r', ALL_GENERAL_REGS) +REGS('x', ALL_VECTOR_REGS) +/* A register that can be used as a byte operand. */ +REGS('q', ALL_BYTEL_REGS) +/* A register with an addressable second byte (e.g. %ah). */ +REGS('Q', ALL_BYTEH_REGS) +/* qemu_ld/st address constraint */ +REGS('L', ALL_GENERAL_REGS & ~((1 << TCG_REG_L0) | (1 << TCG_REG_L1))) + +CONST('e', TCG_CT_CONST_S32) +CONST('I', TCG_CT_CONST_I32) +CONST('W', TCG_CT_CONST_WSZ) +CONST('Z', TCG_CT_CONST_U32) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index abd4ac7fc0..7c405e166d 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -235,5 +235,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSTR_H #endif diff --git a/tcg/tcg.c b/tcg/tcg.c index 43c6cf8f52..f5b53d739e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -102,8 +102,10 @@ static void tcg_register_jit_int(void *buf, size_t size, __attribute__((unused)); /* Forward declarations for functions declared and used in tcg-target.c.inc. */ +#ifndef TCG_TARGET_CONSTR_H static const char *target_parse_constraint(TCGArgConstraint *ct, const char *ct_str, TCGType type); +#endif static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, intptr_t arg2); static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); @@ -2239,7 +2241,6 @@ static void process_op_defs(TCGContext *s) for (op = 0; op < NB_OPS; op++) { TCGOpDef *def = &tcg_op_defs[op]; const TCGTargetOpDef *tdefs; - TCGType type; int i, nb_args; if (def->flags & TCG_OPF_NOT_PRESENT) { @@ -2255,7 +2256,6 @@ static void process_op_defs(TCGContext *s) /* Missing TCGTargetOpDef entry. */ tcg_debug_assert(tdefs != NULL); - type = (def->flags & TCG_OPF_64BIT ? TCG_TYPE_I64 : TCG_TYPE_I32); for (i = 0; i < nb_args; i++) { const char *ct_str = tdefs->args_ct_str[i]; /* Incomplete TCGTargetOpDef entry. */ @@ -2287,11 +2287,34 @@ static void process_op_defs(TCGContext *s) def->args_ct[i].ct |= TCG_CT_CONST; ct_str++; break; + +#ifdef TCG_TARGET_CONSTR_H + /* Include all of the target-specific constraints. */ + +#undef CONST +#define CONST(CASE, MASK) \ + case CASE: def->args_ct[i].ct |= MASK; ct_str++; break; +#define REGS(CASE, MASK) \ + case CASE: def->args_ct[i].regs |= MASK; ct_str++; break; + +#include "tcg-target-constr.h" + +#undef REGS +#undef CONST default: - ct_str = target_parse_constraint(&def->args_ct[i], - ct_str, type); /* Typo in TCGTargetOpDef constraint. */ - tcg_debug_assert(ct_str != NULL); + g_assert_not_reached(); +#else + default: + { + TCGType type = (def->flags & TCG_OPF_64BIT + ? TCG_TYPE_I64 : TCG_TYPE_I32); + ct_str = target_parse_constraint(&def->args_ct[i], + ct_str, type); + /* Typo in TCGTargetOpDef constraint. */ + tcg_debug_assert(ct_str != NULL); + } +#endif } } } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index b73873f715..981dd9aca4 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -194,81 +194,17 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, return true; } +#define ALL_BYTEH_REGS 0x0000000fu #if TCG_TARGET_REG_BITS == 64 #define ALL_GENERAL_REGS 0x0000ffffu #define ALL_VECTOR_REGS 0xffff0000u +#define ALL_BYTEL_REGS ALL_GENERAL_REGS #else #define ALL_GENERAL_REGS 0x000000ffu #define ALL_VECTOR_REGS 0x00ff0000u +#define ALL_BYTEL_REGS ALL_BYTEH_REGS #endif -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch(*ct_str++) { - case 'a': - tcg_regset_set_reg(ct->regs, TCG_REG_EAX); - break; - case 'b': - tcg_regset_set_reg(ct->regs, TCG_REG_EBX); - break; - case 'c': - tcg_regset_set_reg(ct->regs, TCG_REG_ECX); - break; - case 'd': - tcg_regset_set_reg(ct->regs, TCG_REG_EDX); - break; - case 'S': - tcg_regset_set_reg(ct->regs, TCG_REG_ESI); - break; - case 'D': - tcg_regset_set_reg(ct->regs, TCG_REG_EDI); - break; - case 'q': - /* A register that can be used as a byte operand. */ - ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf; - break; - case 'Q': - /* A register with an addressable second byte (e.g. %ah). */ - ct->regs = 0xf; - break; - case 'r': - /* A general register. */ - ct->regs |= ALL_GENERAL_REGS; - break; - case 'W': - /* With TZCNT/LZCNT, we can have operand-size as an input. */ - ct->ct |= TCG_CT_CONST_WSZ; - break; - case 'x': - /* A vector register. */ - ct->regs |= ALL_VECTOR_REGS; - break; - - /* qemu_ld/st address constraint */ - case 'L': - ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; - tcg_regset_reset_reg(ct->regs, TCG_REG_L0); - tcg_regset_reset_reg(ct->regs, TCG_REG_L1); - break; - - case 'e': - ct->ct |= TCG_CT_CONST_S32; - break; - case 'Z': - ct->ct |= TCG_CT_CONST_U32; - break; - case 'I': - ct->ct |= TCG_CT_CONST_I32; - break; - - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) From patchwork Wed Dec 23 06:01:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419589 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=e1QjAbrD; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D12gq2svPz9sVs for ; Wed, 23 Dec 2020 17:03:19 +1100 (AEDT) Received: from localhost ([::1]:50158 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxEz-0008RN-7P for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:03:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39262) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxE3-0008Pm-E6 for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:21 -0500 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:38060) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxDx-0000Lg-RN for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:19 -0500 Received: by mail-pg1-x52c.google.com with SMTP id e2so9935531pgi.5 for ; Tue, 22 Dec 2020 22:02:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NrM0nd/vAh/xuPN3ZjF7gS1lRQ4hob266SPoNoDOWZg=; b=e1QjAbrDjap8Bhe5I/9ZYUCAgbFvY4cHi6/QGrJca3jf884Qyx621atDZlskr6bnAE M51PajNTADzngm11Kc3hkwpDAAT2yTs8sOWWZPjQTX2c8qLGxKjpFK4i3+PFsGxQ7m0v vkGx9AgMQCEUuAmN1LFWZnzqwadt28EJONNxk6YrtN5joCy9uAq6oXO+Fl8nLZ4GWj9z 0rzbzvJ7saazeUJMgMw/PEJ1AWoDR3r2PkmWaa2YhmXR2csBw+O9qs33JJyRgMDgHSSH dXG1Bmkhs4m4NOWjCYFG3Q9wlCT03Z4Y/I3kUw1VPuh9C4RQxdXIpkFZeVx7qEESLbnQ UPNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NrM0nd/vAh/xuPN3ZjF7gS1lRQ4hob266SPoNoDOWZg=; b=un+Fr87aEm6LR6l0pG+mbTm7ISsZ1b9aHkkx8QYCdw9lwfOObie71+Pi0JCtgIKbev L9obhiTCUF4dfni1EWl9zK34XjtnbVL7H0DsOWSptJKVgQEuPZdVtz3EbEgZePuGKuNL AAUUdKnPCBK8xWeHDGt5ppD7khA0z/lcL/2V/F7H2XWFQllPmZrN2qWGhgWtrC4Hu2W0 BLv/fA7qKhLsTb9AtcewMvUunu7jtT9iUpiAiVD5OMJY6ZAeWopqiUpZuK572YvUvQl5 dBH3e5wKgmPinKAAYMQG9RFfC/gzu0eGxGjNW65MmsTbgIK9uqiBR5bK2woaHV6ijtzS dKkQ== X-Gm-Message-State: AOAM530wgz8fY8OvTw+LvlYtSPeNP+Hjn/kG2K/BlMJGc4fT1/vXjU6l GRCoYQfueza8wVnp3vo6wykyjOCAA3Lwrw== X-Google-Smtp-Source: ABdhPJztYZdPons8yK21ln+cYyXaR2nLQ39QApPopFobtIzGBLGcNA1v2r9VwByIx2vFjt7N9BPw+A== X-Received: by 2002:a63:db57:: with SMTP id x23mr22929793pgi.131.1608703330793; Tue, 22 Dec 2020 22:02:10 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 04/22] tcg/arm: Convert to tcg-target-constr.h Date: Tue, 22 Dec 2020 22:01:46 -0800 Message-Id: <20201223060204.576856-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-constr.h | 31 +++++++++++++++++++ tcg/arm/tcg-target.h | 1 + tcg/arm/tcg-target.c.inc | 60 ------------------------------------- 3 files changed, 32 insertions(+), 60 deletions(-) create mode 100644 tcg/arm/tcg-target-constr.h diff --git a/tcg/arm/tcg-target-constr.h b/tcg/arm/tcg-target-constr.h new file mode 100644 index 0000000000..15c5e53406 --- /dev/null +++ b/tcg/arm/tcg-target-constr.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Arm target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +#define ALL_GENERAL_REGS 0xffffu + +#ifdef CONFIG_SOFTMMU +#define ALL_QLOAD_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \ + (1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \ + (1 << TCG_REG_R14))) +#define ALL_QSTORE_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \ + (1 << TCG_REG_R2) | (1 << TCG_REG_R14) | \ + ((TARGET_LONG_BITS == 64) << TCG_REG_R3))) +#else +#define ALL_QLOAD_REGS ALL_GENERAL_REGS +#define ALL_QSTORE_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1))) +#endif + +REGS('r', ALL_GENERAL_REGS) +REGS('l', ALL_QLOAD_REGS) +REGS('s', ALL_QSTORE_REGS) + +CONST('I', TCG_CT_CONST_ARM) +CONST('K', TCG_CT_CONST_INV) +CONST('N', TCG_CT_CONST_NEG) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 17e771374d..6f058d6d9b 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -146,5 +146,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSTR_H #endif diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 62c37a954b..ab1b295293 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -234,66 +234,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, #define TCG_CT_CONST_NEG 0x400 #define TCG_CT_CONST_ZERO 0x800 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'I': - ct->ct |= TCG_CT_CONST_ARM; - break; - case 'K': - ct->ct |= TCG_CT_CONST_INV; - break; - case 'N': /* The gcc constraint letter is L, already used here. */ - ct->ct |= TCG_CT_CONST_NEG; - break; - case 'Z': - ct->ct |= TCG_CT_CONST_ZERO; - break; - - case 'r': - ct->regs = 0xffff; - break; - - /* qemu_ld address */ - case 'l': - ct->regs = 0xffff; -#ifdef CONFIG_SOFTMMU - /* r0-r2,lr will be overwritten when reading the tlb entry, - so don't use these. */ - tcg_regset_reset_reg(ct->regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->regs, TCG_REG_R1); - tcg_regset_reset_reg(ct->regs, TCG_REG_R2); - tcg_regset_reset_reg(ct->regs, TCG_REG_R3); - tcg_regset_reset_reg(ct->regs, TCG_REG_R14); -#endif - break; - - /* qemu_st address & data */ - case 's': - ct->regs = 0xffff; - /* r0-r2 will be overwritten when reading the tlb entry (softmmu only) - and r0-r1 doing the byte swapping, so don't use these. */ - tcg_regset_reset_reg(ct->regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->regs, TCG_REG_R1); -#if defined(CONFIG_SOFTMMU) - /* Avoid clashes with registers being used for helper args */ - tcg_regset_reset_reg(ct->regs, TCG_REG_R2); -#if TARGET_LONG_BITS == 64 - /* Avoid clashes with registers being used for helper args */ - tcg_regset_reset_reg(ct->regs, TCG_REG_R3); -#endif - tcg_regset_reset_reg(ct->regs, TCG_REG_R14); -#endif - break; - - default: - return NULL; - } - return ct_str; -} - static inline uint32_t rotl(uint32_t val, int n) { return (val << n) | (val >> (32 - n)); From patchwork Wed Dec 23 06:01:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419591 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=ujFg8D9z; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D12lj4tCGz9sVm for ; Wed, 23 Dec 2020 17:06:38 +1100 (AEDT) Received: from localhost ([::1]:58502 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxIB-0003TX-CT for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:06:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39256) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxE3-0008PT-2K for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:19 -0500 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:35131) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxDy-0000Lm-6a for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:18 -0500 Received: by mail-pg1-x535.google.com with SMTP id n7so9945172pgg.2 for ; Tue, 22 Dec 2020 22:02:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=VcKfT6vwgUeZ7feGstLlA+QUgIS4eK/5KKU+ui6/cwM=; b=ujFg8D9zvtNG7kUdwVq9oAg1YD+3UrAP6h105lEW/KukJAKVk9QpsbpeXPe5a9hNJ4 x7U/hXz9UhDDzjJEFkj7sRUNBBuZ0sQKFEQdlu6gPHFrAEDkwlZKU+tZ17uetE2rjn1U cfdb5obpWuAiFOXI9JfWxLeWRr38RsVhLXJqC+388HUsWQZO1J4KP4INoYQj1seQhlfl Z4JHhYQWwy19Ilj3dSop3uUbdxWObBT3uWQ9zUzhZ75DvGjkDFewZC+eg6O5ILzb+FQY P4ZhuVGWLh3Ab1+MzIpuLGhJzZh1RuThMQ7rif/atKwB17Ku84YLX0LExkjqNw5D1j5e MxSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VcKfT6vwgUeZ7feGstLlA+QUgIS4eK/5KKU+ui6/cwM=; b=g+r3m06iuB5toXlSyntNMU0/QPRlsTIpShfGqTCVcKXL4rqDewYDj18+cZtlJ0Dh1v gma3MVhnuW87i59S+RusyrPghJXrEGoHJdrb7Pb+RvCyRHOetGC/y5L9+c0b6zOX/gL0 +gwFnSsCvqaFZSumPP9klNW6UgUK+XmfPSInue1yjobnlJAuUq2w8hkhq4TkpSSof4Sl QLizs+qjlNspkWpTVtf7fe0SRv7tOfOKjdOhiT09GuB1BYPlUYL/w2dJl8sH7HSPCLaD sYZvdkhTi4cxTT+/HTGcUSqz6G1U3P94l4hORNV1hx0dEGdw7fbEYlx1uD7/9FXeZYnI cefA== X-Gm-Message-State: AOAM531x2KBlSQBOH8KJRT8ba5ZIr7vKd/zQajL1qenVHCqnMFgLrQfd BYFdJvuDIsQodvr5+95yNYhnBj//blQDlw== X-Google-Smtp-Source: ABdhPJx3wVOmuhKV9E5a2hGoUbRE8YSORIiSLBJC+p/rgZ8dE+cYgpU4yCwMTyJR0Q8n5Makgq4Xmw== X-Received: by 2002:a63:551f:: with SMTP id j31mr4098850pgb.432.1608703332061; Tue, 22 Dec 2020 22:02:12 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 05/22] tcg/aarch64: Convert to tcg-target-constr.h Date: Tue, 22 Dec 2020 22:01:47 -0800 Message-Id: <20201223060204.576856-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-constr.h | 27 +++++++++++++++++++ tcg/aarch64/tcg-target.h | 1 + tcg/aarch64/tcg-target.c.inc | 46 --------------------------------- 3 files changed, 28 insertions(+), 46 deletions(-) create mode 100644 tcg/aarch64/tcg-target-constr.h diff --git a/tcg/aarch64/tcg-target-constr.h b/tcg/aarch64/tcg-target-constr.h new file mode 100644 index 0000000000..28f7aa6f03 --- /dev/null +++ b/tcg/aarch64/tcg-target-constr.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * AArch64 target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +#define ALL_GENERAL_REGS 0xffffffffu +#define ALL_VECTOR_REGS 0xffffffff00000000ull + +#ifdef CONFIG_SOFTMMU +#define ALL_QLDST_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_X0) | (1 << TCG_REG_X1) | \ + (1 << TCG_REG_X2) | (1 << TCG_REG_X3))) +#else +#define ALL_QLDST_REGS ALL_GENERAL_REGS +#endif + +REGS('r', ALL_GENERAL_REGS) +REGS('l', ALL_QLDST_REGS) +REGS('w', ALL_VECTOR_REGS) + +CONST('A', TCG_CT_CONST_AIMM) +CONST('L', TCG_CT_CONST_LIMM) +CONST('M', TCG_CT_CONST_MONE) +CONST('O', TCG_CT_CONST_ORRI) +CONST('N', TCG_CT_CONST_ANDI) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 663dd0b95e..ca7af5a589 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -159,5 +159,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSTR_H #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 26f71cb599..310bc972e3 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -122,52 +122,6 @@ static inline bool patch_reloc(tcg_insn_unit *code_ptr, int type, #define TCG_CT_CONST_ORRI 0x1000 #define TCG_CT_CONST_ANDI 0x2000 -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'r': /* general registers */ - ct->regs |= 0xffffffffu; - break; - case 'w': /* advsimd registers */ - ct->regs |= 0xffffffff00000000ull; - break; - case 'l': /* qemu_ld / qemu_st address, data_reg */ - ct->regs = 0xffffffffu; -#ifdef CONFIG_SOFTMMU - /* x0 and x1 will be overwritten when reading the tlb entry, - and x2, and x3 for helper args, better to avoid using them. */ - tcg_regset_reset_reg(ct->regs, TCG_REG_X0); - tcg_regset_reset_reg(ct->regs, TCG_REG_X1); - tcg_regset_reset_reg(ct->regs, TCG_REG_X2); - tcg_regset_reset_reg(ct->regs, TCG_REG_X3); -#endif - break; - case 'A': /* Valid for arithmetic immediate (positive or negative). */ - ct->ct |= TCG_CT_CONST_AIMM; - break; - case 'L': /* Valid for logical immediate. */ - ct->ct |= TCG_CT_CONST_LIMM; - break; - case 'M': /* minus one */ - ct->ct |= TCG_CT_CONST_MONE; - break; - case 'O': /* vector orr/bic immediate */ - ct->ct |= TCG_CT_CONST_ORRI; - break; - case 'N': /* vector orr/bic immediate, inverted */ - ct->ct |= TCG_CT_CONST_ANDI; - break; - case 'Z': /* zero */ - ct->ct |= TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* Match a constant valid for addition (12-bit, optionally shifted). */ static inline bool is_aimm(uint64_t val) { From patchwork Wed Dec 23 06:01:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419596 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=kaiq0ERQ; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D12qd6LcRz9sVm for ; Wed, 23 Dec 2020 17:10:05 +1100 (AEDT) Received: from localhost ([::1]:39178 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxLX-0007F4-TU for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:10:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39376) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEC-0008RS-8E for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:34 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:43798) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxE0-0000MI-Nx for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:27 -0500 Received: by mail-pl1-x62f.google.com with SMTP id x12so8589706plr.10 for ; Tue, 22 Dec 2020 22:02:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=G/axsKwIG6T95QPg/jBLY9DS0jhAHEEiPneseNdvWWM=; b=kaiq0ERQx/+EJlrpuuO91ERJ2WAxm/0DD2cLD9eGxVBZeQEueUzAa7KfPwnAJsK74k vbxNd46ufuhPlVf08EBLBGmhBdlhLmcRuS7BSyDVBMvGrd/7HcS2zn8n9eIaK6AwkL0B Stqf9+q9hA4/FATl4hQM6d3dG5YP46SCoZluk8gYS/C7xp1V+3hXLMBtbO0BEdZtXNxi xUYg+AU1kbo3Rqo2Hgyr0zTHgAnhoW6BSGKywZTExNRRBpuxWauqvcaNiofT64yNQl1n qmgsCS8XOUgsUADZGqTgWLLjIwJmreZqGzDT+Oe1SL/0xKWmTaAzIvB2G+S+r/xnUjpf fSwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G/axsKwIG6T95QPg/jBLY9DS0jhAHEEiPneseNdvWWM=; b=g8PYOHmMgZD/hOMe0+Pa03ZpK+HJyDQPU4XYDKEwvxlWllgMsDC/tZorDDhm1AUZa3 rJtNFO9hrTnjr1FqibPPVIBB9mvLj9+8RzCl4HdLi6oBmoYVjvb9wEloua+iiYMaiq/d CIMUQJSCe+qME8EZ9Ai/pXhFmDXJT0inUyUUDHgGdHrJ1zU6zsMGM240khBdTfHtge2F 0squrkJpftvw+AZLWVpPApoSK+IzHrZam0qGGJYKoYJ7acYXksgw+WzLM9Ks7CoAO0hH +Yps7vjBHifGetoN2pXgrZYxAmLAgeAn8MNzbdM/lkxGpO3jdA1Khas9oJrXCUhw8aS6 1gtw== X-Gm-Message-State: AOAM530hdHnYmF2StSCvK6qIaibNmUocOvBJXAjjlJWs3MxyqR7vrZ8F Xoy1JOk04sn+m8l5aMUqEvoHnjothQp/CQ== X-Google-Smtp-Source: ABdhPJzr1mYkFSyGVbwDL4I30WBcTCITe8CrCTCKISvbZVJbEGoN1FpvYXchTj5HvnFlJ4F5Xs/GOg== X-Received: by 2002:a17:902:b706:b029:dc:3817:4da5 with SMTP id d6-20020a170902b706b02900dc38174da5mr1072119pls.23.1608703333687; Tue, 22 Dec 2020 22:02:13 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 06/22] tcg/ppc: Convert to tcg-target-constr.h Date: Tue, 22 Dec 2020 22:01:48 -0800 Message-Id: <20201223060204.576856-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-constr.h | 37 +++++++++++++++++++++++ tcg/ppc/tcg-target.h | 1 + tcg/ppc/tcg-target.c.inc | 58 ------------------------------------- 3 files changed, 38 insertions(+), 58 deletions(-) create mode 100644 tcg/ppc/tcg-target-constr.h diff --git a/tcg/ppc/tcg-target-constr.h b/tcg/ppc/tcg-target-constr.h new file mode 100644 index 0000000000..b4937f37f7 --- /dev/null +++ b/tcg/ppc/tcg-target-constr.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: MIT */ +/* + * PowerPC target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +#define ALL_GENERAL_REGS 0xffffffffu +#define ALL_VECTOR_REGS 0xffffffff00000000ull + +#ifdef CONFIG_SOFTMMU +#define ALL_QLOAD_REGS \ + (ALL_GENERAL_REGS & \ + ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5))) +#define ALL_QSTORE_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \ + (1 << TCG_REG_R5) | (1 << TCG_REG_R6))) +#else +#define ALL_QLOAD_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3)) +#define ALL_QSTORE_REGS ALL_QLOAD_REGS +#endif + +REGS('r', ALL_GENERAL_REGS) +REGS('v', ALL_VECTOR_REGS) +REGS('A', 1u << TCG_REG_R3) +REGS('B', 1u << TCG_REG_R4) +REGS('C', 1u << TCG_REG_R5) +REGS('D', 1u << TCG_REG_R6) +REGS('L', ALL_QLOAD_REGS) +REGS('S', ALL_QSTORE_REGS) + +CONST('I', TCG_CT_CONST_S16) +CONST('J', TCG_CT_CONST_U16) +CONST('M', TCG_CT_CONST_MONE) +CONST('T', TCG_CT_CONST_S32) +CONST('U', TCG_CT_CONST_U32) +CONST('W', TCG_CT_CONST_WSZ) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index be10363956..78d3470f3c 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -185,5 +185,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSTR_H #endif diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 18ee989f95..c97f95f3cf 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -218,64 +218,6 @@ static bool reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target) return false; } -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'A': case 'B': case 'C': case 'D': - tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A'); - break; - case 'r': - ct->regs = 0xffffffff; - break; - case 'v': - ct->regs = 0xffffffff00000000ull; - break; - case 'L': /* qemu_ld constraint */ - ct->regs = 0xffffffff; - tcg_regset_reset_reg(ct->regs, TCG_REG_R3); -#ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->regs, TCG_REG_R4); - tcg_regset_reset_reg(ct->regs, TCG_REG_R5); -#endif - break; - case 'S': /* qemu_st constraint */ - ct->regs = 0xffffffff; - tcg_regset_reset_reg(ct->regs, TCG_REG_R3); -#ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->regs, TCG_REG_R4); - tcg_regset_reset_reg(ct->regs, TCG_REG_R5); - tcg_regset_reset_reg(ct->regs, TCG_REG_R6); -#endif - break; - case 'I': - ct->ct |= TCG_CT_CONST_S16; - break; - case 'J': - ct->ct |= TCG_CT_CONST_U16; - break; - case 'M': - ct->ct |= TCG_CT_CONST_MONE; - break; - case 'T': - ct->ct |= TCG_CT_CONST_S32; - break; - case 'U': - ct->ct |= TCG_CT_CONST_U32; - break; - case 'W': - ct->ct |= TCG_CT_CONST_WSZ; - break; - case 'Z': - ct->ct |= TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) From patchwork Wed Dec 23 06:01:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419590 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=eS9kQpMT; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D12gr72Dlz9sVm for ; Wed, 23 Dec 2020 17:03:20 +1100 (AEDT) Received: from localhost ([::1]:50380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxF0-00006P-JK for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:03:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39346) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxE8-0008Qv-96 for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:24 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:45847) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxE0-0000Mp-OE for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:22 -0500 Received: by mail-pl1-x62b.google.com with SMTP id e2so8583594plt.12 for ; Tue, 22 Dec 2020 22:02:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rh7bsPAA/9+Eab4XLXyBRxwo882az2z0pvk2WgOaAN8=; b=eS9kQpMT7d1nxQeK20G/nwJ/+ZlKzIxNEebr8nosWzKLgX24I2/UoCdF9qN8ooGPM5 JIMJSU+7DUmbDeixpBIifMgs2PpzxEXjHJDiG0/CPScHLGKMUuI+o4oY2RHhklQvnZIm xNdBpsPMvQjHzsbL/j2Eii205W6bzWAT5JsLWK3kjuAleWdlDrItSSzCpE3ncU+5srnc nyCHYHJHyxioNmUUB97lclFY2FOTt2LjJCd8zQp1mEaK5sHVY+1keYqgQImLaMcSEYIo FReKmRrSy4sZvKkanUwOHwg54uTCoIAOFyD7rzRPK9jwX4CK3akcDS0H2bsXE/MQtxzu 6gtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rh7bsPAA/9+Eab4XLXyBRxwo882az2z0pvk2WgOaAN8=; b=eoKs/60HVxG1NqAa3DzwVWwHRVpdRjCdIOGoP/QfD/uDOiVn1X1Sg/YhwLkju+xjQa mntoUyztBRfLvhG4u1oD2czMFq4rjvPuskTckY+wybgdqXGM1c4NonxiBEz4WMr3J8Ep pPbJCmwJHxKUeE8YkmarOt9pfRMO+mOglMaiixX43leee1V+RjzIbxM6I6opXL0V7YLY LbHd4hSDPa3rleHPJwZZ2pfj9xge6F2tZln25OQL4ktlUoth/xJHyRZxHvAyU4oSDfrI Inv6eZ0gr6g09K88Ey6oO2BEI88KKBJ8s61BmuyNRqJ315wP9IfjJlN5o0kkKyWxxnu2 L9gA== X-Gm-Message-State: AOAM5327IC4pZZtSgZzbT3HvlV11KvQa44Cc6imiiX7Nl7/Sn0yqqAlN iqa9LGeHe7NX6jqX7SEZY1WboBnBcy3Cyw== X-Google-Smtp-Source: ABdhPJzHXqcQg47B/NQvvh2/0Wcn1KkSgVSDzWd8e0fjdvhH+iza5r7vekc6BBnL/JnqGZoF8Uorxg== X-Received: by 2002:a17:902:8687:b029:dc:2a2c:e99b with SMTP id g7-20020a1709028687b02900dc2a2ce99bmr23861489plo.37.1608703334983; Tue, 22 Dec 2020 22:02:14 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 07/22] tcg/tci: Convert to tcg-target-constr.h Date: Tue, 22 Dec 2020 22:01:49 -0800 Message-Id: <20201223060204.576856-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-constr.h | 9 +++++++++ tcg/tci/tcg-target.h | 2 ++ tcg/tci/tcg-target.c.inc | 14 -------------- 3 files changed, 11 insertions(+), 14 deletions(-) create mode 100644 tcg/tci/tcg-target-constr.h diff --git a/tcg/tci/tcg-target-constr.h b/tcg/tci/tcg-target-constr.h new file mode 100644 index 0000000000..ddf57ca9d0 --- /dev/null +++ b/tcg/tci/tcg-target-constr.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +/* + * TCI target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS)) +REGS('L', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS)) +REGS('S', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS)) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 8c1c1d265d..cd3dee51bb 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -210,4 +210,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, /* no need to flush icache explicitly */ } +#define TCG_TARGET_CONSTR_H + #endif /* TCG_TARGET_H */ diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 50a08bef03..9ac6da2e21 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -384,20 +384,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, return true; } -/* Parse target specific constraints. */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'r': - ct->regs = BIT(TCG_TARGET_NB_REGS) - 1; - break; - default: - return NULL; - } - return ct_str; -} - #if defined(CONFIG_DEBUG_TCG_INTERPRETER) /* Show current bytecode. Used by tcg interpreter. */ void tci_disas(uint8_t opc) From patchwork Wed Dec 23 06:01:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419598 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=fBmI1DRd; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D12rT2phvz9sVm for ; Wed, 23 Dec 2020 17:10:49 +1100 (AEDT) Received: from localhost ([::1]:39726 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxMF-0007SV-Br for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:10:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39298) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxE5-0008Q8-SA for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:22 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:39001) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxE2-0000Mv-Pz for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:21 -0500 Received: by mail-pl1-x62b.google.com with SMTP id x18so8605105pln.6 for ; Tue, 22 Dec 2020 22:02:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CtwhY3hIgVrDdc8+WsDSaNPBuzHJliRzCFCUKzXl3IE=; b=fBmI1DRdRV4MIZWBG/BYZ/tecK/nmTWnWwfp98toic37VCWkRJyYElfLGR9iTuzDq4 bwhQRf+aXFKyDSQjWuoclCo18GpYudZo+LvKTBwGa0RYfh0Ao+vWVss5rFREkvE7Bm8C DA9EY+mpufSfLGc511Wfnnu8u40puwUoJQdPb0tZZZN4ElcahY/jfmVgCahCKSEfejeb AOXE3c2T11MA4UA6l85HRSZ1Q517QiNn4czWqNjYreIFxlW7vT6WihdkLVYo4PcJhUK+ swLGPHlljLyML4/lyfa6ixKZ2EE3T2gUWSmocFfQqwCKlhWSj8D6b5RZukZdFxMNdJ8z FVRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CtwhY3hIgVrDdc8+WsDSaNPBuzHJliRzCFCUKzXl3IE=; b=OrYU6ddUhlVw3cEG3Uli5vAWNhsoRMks+722BkV38GILjh9FSwZ1VMNhf+NTBjB1G+ C//qJfRirVwjiy+DlDHGRXAOWDMuNWqvvM1loWB2wjlpttL7UFAxlGIrEaHTklFs/D/d au59KruWDaz1wCn/h7vgmTPNCAhyGPJYCEIoPRhTTqkGytdrszgjwsFKFKjJ2SIZ4idD NdhhclJ6HvfpOYVaT6f5nAASjKeujUDYymsNYvagVNsWXfX5b09+L20SgSeytwCNfwkO awq6T/giCc6XhHkIX34GRFY0fgGZfiWjDi7cPmbqm/7uVaj1fyzVot4p9IGfbRpdW7mh mCpw== X-Gm-Message-State: AOAM531si/tmDPTCTaB2Hr/Id8DjYhFwFn6+uPRgmyCstdAyBYfX5Tec a1hIuNlEfDfhuy+uoMBWGXc5jOQaCyFlzA== X-Google-Smtp-Source: ABdhPJxwMK/Mcot+pGx6tgyekqLD2Ix87oolvHD8e/9JZ8VO1jP/l7P6M4NZF44mLT3eAdadOdtq4w== X-Received: by 2002:a17:902:aa43:b029:dc:26a7:7391 with SMTP id c3-20020a170902aa43b02900dc26a77391mr24280121plr.51.1608703336118; Tue, 22 Dec 2020 22:02:16 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 08/22] tcg/mips: Convert to tcg-target-constr.h Date: Tue, 22 Dec 2020 22:01:50 -0800 Message-Id: <20201223060204.576856-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-constr.h | 31 ++++++++++++++++++++ tcg/mips/tcg-target.h | 1 + tcg/mips/tcg-target.c.inc | 56 ------------------------------------ 3 files changed, 32 insertions(+), 56 deletions(-) create mode 100644 tcg/mips/tcg-target-constr.h diff --git a/tcg/mips/tcg-target-constr.h b/tcg/mips/tcg-target-constr.h new file mode 100644 index 0000000000..22f6df0806 --- /dev/null +++ b/tcg/mips/tcg-target-constr.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* + * MIPS target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +#define ALL_GENERAL_REGS 0xffffffffu +#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0)) + +#ifdef CONFIG_SOFTMMU +#define ALL_QLOAD_REGS \ + (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2)) +#define ALL_QSTORE_REGS \ + (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \ + ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \ + : (1 << TCG_REG_A1))) +#else +#define ALL_QLOAD_REGS NOA0_REGS +#define ALL_QSTORE_REGS NOA0_REGS +#endif + +REGS('r', ALL_GENERAL_REGS) +REGS('L', ALL_QLOAD_REGS) +REGS('S', ALL_QSTORE_REGS) + +CONST('I', TCG_CT_CONST_U16) +CONST('J', TCG_CT_CONST_S16) +CONST('K', TCG_CT_CONST_P2M1) +CONST('N', TCG_CT_CONST_N16) +CONST('W', TCG_CT_CONST_WSZ) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c6b091d849..f4a79bcad1 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -217,5 +217,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif +#define TCG_TARGET_CONSTR_H #endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 41be574e89..d0b674582a 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -189,62 +189,6 @@ static inline bool is_p2m1(tcg_target_long val) return val && ((val + 1) & val) == 0; } -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch(*ct_str++) { - case 'r': - ct->regs = 0xffffffff; - break; - case 'L': /* qemu_ld input arg constraint */ - ct->regs = 0xffffffff; - tcg_regset_reset_reg(ct->regs, TCG_REG_A0); -#if defined(CONFIG_SOFTMMU) - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_regset_reset_reg(ct->regs, TCG_REG_A2); - } -#endif - break; - case 'S': /* qemu_st constraint */ - ct->regs = 0xffffffff; - tcg_regset_reset_reg(ct->regs, TCG_REG_A0); -#if defined(CONFIG_SOFTMMU) - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_regset_reset_reg(ct->regs, TCG_REG_A2); - tcg_regset_reset_reg(ct->regs, TCG_REG_A3); - } else { - tcg_regset_reset_reg(ct->regs, TCG_REG_A1); - } -#endif - break; - case 'I': - ct->ct |= TCG_CT_CONST_U16; - break; - case 'J': - ct->ct |= TCG_CT_CONST_S16; - break; - case 'K': - ct->ct |= TCG_CT_CONST_P2M1; - break; - case 'N': - ct->ct |= TCG_CT_CONST_N16; - break; - case 'W': - ct->ct |= TCG_CT_CONST_WSZ; - break; - case 'Z': - /* We are cheating a bit here, using the fact that the register - ZERO is also the register number 0. Hence there is no need - to check for const_args in each instruction. */ - ct->ct |= TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) From patchwork Wed Dec 23 06:01:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419599 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=PjjK3AYM; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D12vf3fkJz9sVn for ; Wed, 23 Dec 2020 17:13:31 +1100 (AEDT) Received: from localhost ([::1]:47428 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxOq-0002Jw-G6 for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:13:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39390) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEE-0008RV-1E for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:34 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:34517) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxE2-0000NZ-RR for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:28 -0500 Received: by mail-pl1-x629.google.com with SMTP id t6so8614650plq.1 for ; Tue, 22 Dec 2020 22:02:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1Y85WkunXwYTbEnJROwkrffmDCY/UpF3UWrZcQqlD/E=; b=PjjK3AYMoheYlh8Onx724Ybsuc879EHOlx9y8DnoKGQOFQraamYPAMF2WwxbHvWlPQ QaIvM/s8dokW6DTHwqV4yQBsC7Y5sXWH7VuIx8+IgPipcMU21P9QMXip2GAynmAMYc2P 3tNBi6k4/LL1MBh7KUw2A/L225uo5J+DpdXIRN3YO5yDWVKWixPZVhsQ9VFleSb4zJBY RxWTQUy0Vp0O4vuB3nMfycvedUZ+ubqWoDBPkiW0cTxfyGc8MtkJ/O93iF86kpXDPUf3 jCGEpMoq2WanRHTXDVGlPfYGZMDncktAZh728ARx2VHniTVjV0t8lpS4iYlQdtpEzSqp Um0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1Y85WkunXwYTbEnJROwkrffmDCY/UpF3UWrZcQqlD/E=; b=ttsCbuRQYwmZdKu4YJ2i2FWsMCvbePhNn3AXZoPXXjImtpCUtjGsKSOk7U212Dm4aK E0kUqHq0H+o+XZ3m9r2YbYqmjdfSpAdbDVxc+sQ8H1YusTWpA4aoVAH4OZ+olt+Mh2cz F16/a3yb9TzTxoESZstgQ66Hj86dG3O0vpqB/7GN6HPVMRYvELnAf3D+zO1eJJZip7Iz nd3Rk5l5zr8HyXwDyfixozqBMyUPuNcb6ONy2p6I5d72o+4bzW4JAgIXHoBP3tgoRP7e BJWwAqGW4I+YADC3WGmxKUbwPqPqyE32Idk/UMu53jV4JKkHK8MnI/shphhHloKBnMj4 uaHQ== X-Gm-Message-State: AOAM533/YJ6/DdoWiXj2OoGo/CWrQXZ1svK22BI5x5I2gx6i16L+/Syq qSYyZsvSuArbFLkKF6llkAk88IefgmcJlQ== X-Google-Smtp-Source: ABdhPJyWRh0yqQtckeqta5jGiPEOHaGqQf9lOqq/WOIiKUaYTG3dCvAIt+nYpeJW2nyTX2cgA90Hgg== X-Received: by 2002:a17:902:6947:b029:db:c7fd:9db3 with SMTP id k7-20020a1709026947b02900dbc7fd9db3mr24051073plt.56.1608703337207; Tue, 22 Dec 2020 22:02:17 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 09/22] tcg/riscv: Convert to tcg-target-constr.h Date: Tue, 22 Dec 2020 22:01:51 -0800 Message-Id: <20201223060204.576856-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Acked-by: Alistair Francis --- tcg/riscv/tcg-target-constr.h | 24 +++++++++++++++++++++ tcg/riscv/tcg-target.h | 1 + tcg/riscv/tcg-target.c.inc | 39 ----------------------------------- 3 files changed, 25 insertions(+), 39 deletions(-) create mode 100644 tcg/riscv/tcg-target-constr.h diff --git a/tcg/riscv/tcg-target-constr.h b/tcg/riscv/tcg-target-constr.h new file mode 100644 index 0000000000..5daf2e6a5b --- /dev/null +++ b/tcg/riscv/tcg-target-constr.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: MIT */ +/* + * RISC-V target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +#define ALL_GENERAL_REGS 0xffffffffu + +#ifdef CONFIG_SOFTMMU +#define ALL_QLDST_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_A0) | (1 << TCG_REG_A1) | \ + (1 << TCG_REG_A2) | (1 << TCG_REG_A3) | \ + (1 << TCG_REG_A5))) +#else +#define ALL_QLDST_REGS ALL_GENERAL_REGS +#endif + +REGS('r', ALL_GENERAL_REGS) +REGS('L', ALL_QLDST_REGS) + +CONST('I', TCG_CT_CONST_S12) +CONST('N', TCG_CT_CONST_N12) +CONST('M', TCG_CT_CONST_M12) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 032439d806..ff8ff43a46 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -175,5 +175,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS #define TCG_TARGET_HAS_MEMORY_BSWAP 0 +#define TCG_TARGET_CONSTR_H #endif diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index d536f3ccc1..33047c1951 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -131,45 +131,6 @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) } } -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'r': - ct->regs = 0xffffffff; - break; - case 'L': - /* qemu_ld/qemu_st constraint */ - ct->regs = 0xffffffff; - /* qemu_ld/qemu_st uses TCG_REG_TMP0 */ -#if defined(CONFIG_SOFTMMU) - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]); - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]); - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]); - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]); - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]); -#endif - break; - case 'I': - ct->ct |= TCG_CT_CONST_S12; - break; - case 'N': - ct->ct |= TCG_CT_CONST_N12; - break; - case 'M': - ct->ct |= TCG_CT_CONST_M12; - break; - case 'Z': - /* we can use a zero immediate as a zero register argument. */ - ct->ct |= TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) From patchwork Wed Dec 23 06:01:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419600 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=UmCh3f9V; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D12vv6jxfz9sVm for ; Wed, 23 Dec 2020 17:13:47 +1100 (AEDT) Received: from localhost ([::1]:48264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxP7-0002eg-Sv for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:13:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39476) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEK-0008Rx-9v for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:37 -0500 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:38948) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxE5-0000Ne-En for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:34 -0500 Received: by mail-pf1-x42f.google.com with SMTP id m6so9764911pfm.6 for ; Tue, 22 Dec 2020 22:02:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7fPp15AvNr8ncHk6m17FiqZ/DKj2/dk6PNRZ0EnN4Pc=; b=UmCh3f9VIPVcHlW5/BlE7xypRWo1QUi2YK5VlWMiF5L50Phi8U9t302nJGDRnEYcEA cdx+6UNt4FkvYBrqAXSKulnfAgx56KdnTdFViWErYQ3e8b9JSmA9TVbMML6sriks6qfl 53JocaCyE4AFHcWfOUq2h91JIRLFatseUaVwthBeCSKnYfSudJh9/LM74ceBOs6uiBst YCD2Ek4f8wYDTT8x2eibzKWb+P2lAZqSuB9EPA33ipiLhYTQBrFKSpHOUnVkel4wtLCI CtF27oK0lKqa9FLAw4qm1yTh6Uu6R+xbjVymp/6QFZCU6SKpNRsu6OJLSP6B4JCK5+pk Gl/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7fPp15AvNr8ncHk6m17FiqZ/DKj2/dk6PNRZ0EnN4Pc=; b=ivveW3/Aj1vcMAqFfYwaWXHALfr6SIabUAwOP3t6QNQIMK4vbtWSoWNkUmaYl9jGFm yFf0HjwVT+GP4L2Msk8dB2l183K0SzHxMAXbmK6q2VCzjaL3Nxoh4vj9tSs/QlmxvWov PP3vTleXzVqJd2HJcnkfWdPF0u133LGD0i+N6zmeNpFCBN9rI+o5/oVKtSawELB9G8Xa XnBFDGlxFSoe4xD6HUG3Sd2qw0yMf+vEhdWix2sVyVACcTXDOYMDPJXCS0xi23ewfBm9 kW4n/PYYoDoUKZy6jiF+/cOV/Ekz7scqHcVU/VaUanvVNbF37mBVAzZRV4DCaOIuDstR AxhA== X-Gm-Message-State: AOAM532Gr+83jZ9SpyV392ulpyj3aEggB/FlfwMzHdn/mloOgd4El6jN rjDRSXjbekOdrO51cAHJLTQFF44bqqRlWQ== X-Google-Smtp-Source: ABdhPJyRf9Mgeu6U2i8HAqRShG1PNrnsyvYTvaMt4m8bexUTJ9AyR8DUG/r/lUNwmPu24unL5MKw1w== X-Received: by 2002:a65:689a:: with SMTP id e26mr23188707pgt.413.1608703338284; Tue, 22 Dec 2020 22:02:18 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 10/22] tcg/s390: Convert to tcg-target-constr.h Date: Tue, 22 Dec 2020 22:01:52 -0800 Message-Id: <20201223060204.576856-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target-constr.h | 15 ++++++++++++++ tcg/s390/tcg-target.h | 1 + tcg/s390/tcg-target.c.inc | 40 ------------------------------------ 3 files changed, 16 insertions(+), 40 deletions(-) create mode 100644 tcg/s390/tcg-target-constr.h diff --git a/tcg/s390/tcg-target-constr.h b/tcg/s390/tcg-target-constr.h new file mode 100644 index 0000000000..885e91e19b --- /dev/null +++ b/tcg/s390/tcg-target-constr.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * S390 target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +REGS('r', 0xffff) +REGS('L', 0xffff & ~((1 << TCG_REG_R2) | (1 << TCG_REG_R3) | (1 << TCG_REG_R4))) +REGS('a', 1u << TCG_REG_R2) +REGS('b', 1u << TCG_REG_R3) + +CONST('A', TCG_CT_CONST_S33) +CONST('I', TCG_CT_CONST_S16) +CONST('J', TCG_CT_CONST_S32) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 63c8797bd3..3aff3cc572 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -162,5 +162,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSTR_H #endif diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index c5e096449b..d00d78f0b9 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -402,46 +402,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, return false; } -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'r': /* all registers */ - ct->regs = 0xffff; - break; - case 'L': /* qemu_ld/st constraint */ - ct->regs = 0xffff; - tcg_regset_reset_reg(ct->regs, TCG_REG_R2); - tcg_regset_reset_reg(ct->regs, TCG_REG_R3); - tcg_regset_reset_reg(ct->regs, TCG_REG_R4); - break; - case 'a': /* force R2 for division */ - ct->regs = 0; - tcg_regset_set_reg(ct->regs, TCG_REG_R2); - break; - case 'b': /* force R3 for division */ - ct->regs = 0; - tcg_regset_set_reg(ct->regs, TCG_REG_R3); - break; - case 'A': - ct->ct |= TCG_CT_CONST_S33; - break; - case 'I': - ct->ct |= TCG_CT_CONST_S16; - break; - case 'J': - ct->ct |= TCG_CT_CONST_S32; - break; - case 'Z': - ct->ct |= TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* Test if a constant matches the constraint. */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) From patchwork Wed Dec 23 06:01:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419594 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=hQiMlJZX; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D12mP02NNz9sVm for ; Wed, 23 Dec 2020 17:07:17 +1100 (AEDT) Received: from localhost ([::1]:58754 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxIo-0003bf-W4 for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:07:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39418) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEG-0008RY-0S for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:34 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:39002) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxE5-0000Np-En for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:29 -0500 Received: by mail-pl1-x62c.google.com with SMTP id x18so8605180pln.6 for ; Tue, 22 Dec 2020 22:02:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7XC/DQ4TKJStS0mIx8J53BbElxWGv8f6A8Dnpnd7zCA=; b=hQiMlJZXhFSdWAIjHfUfg9GWRAX9klPZxJtqc774iHFxgtoL33f3YklwqgxOC45S6A UTtLMZcZ07ym9yaDmKCn5nWBUJjzqXpOGC8aEaHp+xdi6TwQQFVS8quDLVeKB7u/1HM0 4wMNUiUNg5kOz1DCM+NAjsHudsJ3BqPbnakXzEtXMY2bBbwu1SiLtm73DTbBEiQrOPo/ M6m1xjAAJEmek8vWKSjgKFy/fiVLjefYozcdO8VDFpB3A9i87senhHUP9az7JGLUdDXD 2g9fdDLOhpfzdrz5CZ0u9i6z/+t3WGzRIG+ekw8wTtc9aKZRxm67+6EiVGk9mM3W39Bs BJ3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7XC/DQ4TKJStS0mIx8J53BbElxWGv8f6A8Dnpnd7zCA=; b=kBc3N+MjnWoQ2nF75Z1nUijz1GPiriJqpKaQ9u/ASuS7OoQeOzXeoaa/an/6QpWmHY icw8u7CX4NPW5VFcJuSgxoBftcgI85jwY4rOInlR4f77L4JqxfKZWz3gUro7w1eeG8ZD 8uYYD0vjlR5vKZuZnoq7LXCGdl8wPmjluYD6mT99Fu4lipqzrRFDjwHMAWXTiLS9T1kb fC9rgp7pC5yhKu4p8p4rpmXaYPfHfppI21EqaJJqFCremzpkgbfQqF5eA3POkELuGmNk qtv6DtjGDpRRAxaNILAhXMtue33gzLkZVSt5DkN5JntEMIjZ9eIn6RyREW6c49jPaU88 EQPg== X-Gm-Message-State: AOAM530ZV9ARHTNbje+ALG+lwtUc6a6U0VGxljCftnXBjuyp/vuLRrPg zyGB7GyLefehm9AhL728mPHQm+gpDL997Q== X-Google-Smtp-Source: ABdhPJzRyfWRNkQdI1hhezcCOYylzVFwjoZUPZXizOGahr5TdDyvG8q/x/gMFxjPYEGTI5IJkVMcqw== X-Received: by 2002:a17:90a:1bc7:: with SMTP id r7mr25893779pjr.33.1608703339458; Tue, 22 Dec 2020 22:02:19 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 11/22] tcg/sparc: Convert to tcg-target-constr.h Date: Tue, 22 Dec 2020 22:01:53 -0800 Message-Id: <20201223060204.576856-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target-constr.h | 16 ++++++++++++++ tcg/sparc/tcg-target.h | 1 + tcg/sparc/tcg-target.c.inc | 39 ----------------------------------- 3 files changed, 17 insertions(+), 39 deletions(-) create mode 100644 tcg/sparc/tcg-target-constr.h diff --git a/tcg/sparc/tcg-target-constr.h b/tcg/sparc/tcg-target-constr.h new file mode 100644 index 0000000000..379eb83ca4 --- /dev/null +++ b/tcg/sparc/tcg-target-constr.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Sparc target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +#define RESERVE_QLDST (7u << TCG_REG_O0) /* O0, O1, O2 */ + +REGS('r', 0xffffffff) +REGS('R', ALL_64) +REGS('s', 0xffffffff & ~RESERVE_QLDST) +REGS('S', ALL_64 & ~RESERVE_QLDST) + +CONST('I', TCG_CT_CONST_S11) +CONST('J', TCG_CT_CONST_S13) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 633841ebf2..bfee6191b3 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -179,5 +179,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSTR_H #endif diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 6775bd30fc..c92742aaec 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -319,45 +319,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, return true; } -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'r': - ct->regs = 0xffffffff; - break; - case 'R': - ct->regs = ALL_64; - break; - case 'A': /* qemu_ld/st address constraint */ - ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff; - reserve_helpers: - tcg_regset_reset_reg(ct->regs, TCG_REG_O0); - tcg_regset_reset_reg(ct->regs, TCG_REG_O1); - tcg_regset_reset_reg(ct->regs, TCG_REG_O2); - break; - case 's': /* qemu_st data 32-bit constraint */ - ct->regs = 0xffffffff; - goto reserve_helpers; - case 'S': /* qemu_st data 64-bit constraint */ - ct->regs = ALL_64; - goto reserve_helpers; - case 'I': - ct->ct |= TCG_CT_CONST_S11; - break; - case 'J': - ct->ct |= TCG_CT_CONST_S13; - break; - case 'Z': - ct->ct |= TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) From patchwork Wed Dec 23 06:01:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419607 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=GE+Gwgyj; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D135m6cRpz9sVm for ; Wed, 23 Dec 2020 17:22:20 +1100 (AEDT) Received: from localhost ([::1]:36466 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxXO-0001LS-TQ for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:22:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39490) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEL-0008Sb-5Z for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:37 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:37332) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxE8-0000Nv-2k for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:36 -0500 Received: by mail-pl1-x62e.google.com with SMTP id be12so8604907plb.4 for ; Tue, 22 Dec 2020 22:02:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=V4vB0rW5AGYTUzpH9bZPj6pKd188ROq1dP7ocy5w9zA=; b=GE+Gwgyj6oY0a61WS22zqwLII2E100SUH248bc2UY910kYxqqkC0kHVmbu++okZfSu WYSieScYT58mWCKbbJGiCoWIHE5EYzkxvwYqfn8R9GqVVPdnm8PPV1TDDK7gT78Z8o1y bQ0j/FTTWyX+Qn363sSKstlEqogiM3O32epFpiJQrj2+uoxRKtouPvjVIcDlrfxMVdj7 KKNldjyPkNI4dRrgMXKHHoedbik/wYRpO80b7uzu4ZWzSaFet7x8vAi4WaIiZPoEJLoo 8aQ/1CqRQDoAj5/dNwimTWDph0PRRcPC2cKpCcvbBeSpPn/wCyLa8EOSFmqFyRTaaEOi 1DCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V4vB0rW5AGYTUzpH9bZPj6pKd188ROq1dP7ocy5w9zA=; b=q+lwRThBk8EpttuJtNpWUh4nLVNJtJ0kWuOQP0I5DKm0qmbJPig4Y2Qv9ptVvypoyT LB0uN9c1E20+lpxTnFZtt4PUF8G8fsqHVSORMs9oG6Mr3kYDSGAdI+PUdeqCDCqy8QXv 1qOWmto7w3x/qoWNYlp4Tk5X5FN3YFC4R/s6o7Qelvv2g6HJCEHOmuxm3MAarnGsHdcB 9JB6Cb5YbqKI11A2MdfSsjBYgwdWXF7aytXSb3hU8OtAutyoFwCEyezOyd/VmZHu0qW+ iVQa7kpR06tZrKit3NNiQu/HAFf4vnnAVNvXadvonbkWRzaaqATH1zTWMaIN9SOy39yk uF8A== X-Gm-Message-State: AOAM532+oeJB9Bv++Dgc2oEmJYTuo8ItzCj8rXn2xOHvU7AHx7IsYV2c L8xVs7+ny5qWeLLYvYzU76uMQPle2QvA6w== X-Google-Smtp-Source: ABdhPJyAMk2vNGozQ27HnaPF9SIhV5vwxlHSYOnAbQxHnfQFWkLFOQXo5s3ITxrScU/Of5pdK+Ul8Q== X-Received: by 2002:a17:90a:67ce:: with SMTP id g14mr25600413pjm.33.1608703340644; Tue, 22 Dec 2020 22:02:20 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 12/22] tcg: Remove TCG_TARGET_CONSTR_H Date: Tue, 22 Dec 2020 22:01:54 -0800 Message-Id: <20201223060204.576856-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" All backends have now been converted to tcg-target-constr.h, so we can remove the fallback code. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- tcg/aarch64/tcg-target.h | 1 - tcg/arm/tcg-target.h | 1 - tcg/i386/tcg-target.h | 1 - tcg/mips/tcg-target.h | 1 - tcg/ppc/tcg-target.h | 1 - tcg/riscv/tcg-target.h | 1 - tcg/s390/tcg-target.h | 1 - tcg/sparc/tcg-target.h | 1 - tcg/tci/tcg-target.h | 2 -- tcg/tcg.c | 16 ---------------- 10 files changed, 26 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index ca7af5a589..663dd0b95e 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -159,6 +159,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSTR_H #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 6f058d6d9b..17e771374d 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -146,6 +146,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSTR_H #endif diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7c405e166d..abd4ac7fc0 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -235,6 +235,5 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSTR_H #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index f4a79bcad1..c6b091d849 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -217,6 +217,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif -#define TCG_TARGET_CONSTR_H #endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 78d3470f3c..be10363956 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -185,6 +185,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSTR_H #endif diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index ff8ff43a46..032439d806 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -175,6 +175,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS #define TCG_TARGET_HAS_MEMORY_BSWAP 0 -#define TCG_TARGET_CONSTR_H #endif diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 3aff3cc572..63c8797bd3 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -162,6 +162,5 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSTR_H #endif diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index bfee6191b3..633841ebf2 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -179,6 +179,5 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSTR_H #endif diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index cd3dee51bb..8c1c1d265d 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -210,6 +210,4 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, /* no need to flush icache explicitly */ } -#define TCG_TARGET_CONSTR_H - #endif /* TCG_TARGET_H */ diff --git a/tcg/tcg.c b/tcg/tcg.c index f5b53d739e..2bde926315 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -102,10 +102,6 @@ static void tcg_register_jit_int(void *buf, size_t size, __attribute__((unused)); /* Forward declarations for functions declared and used in tcg-target.c.inc. */ -#ifndef TCG_TARGET_CONSTR_H -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type); -#endif static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, intptr_t arg2); static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); @@ -2288,7 +2284,6 @@ static void process_op_defs(TCGContext *s) ct_str++; break; -#ifdef TCG_TARGET_CONSTR_H /* Include all of the target-specific constraints. */ #undef CONST @@ -2304,17 +2299,6 @@ static void process_op_defs(TCGContext *s) default: /* Typo in TCGTargetOpDef constraint. */ g_assert_not_reached(); -#else - default: - { - TCGType type = (def->flags & TCG_OPF_64BIT - ? TCG_TYPE_I64 : TCG_TYPE_I32); - ct_str = target_parse_constraint(&def->args_ct[i], - ct_str, type); - /* Typo in TCGTargetOpDef constraint. */ - tcg_debug_assert(ct_str != NULL); - } -#endif } } } From patchwork Wed Dec 23 06:01:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419605 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=ssywNbmr; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D130k47pfz9sVm for ; Wed, 23 Dec 2020 17:17:58 +1100 (AEDT) Received: from localhost ([::1]:55886 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxTA-0005lj-Cu for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:17:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39432) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEG-0008Ra-PD for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:34 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:35770) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxE8-0000OE-39 for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:31 -0500 Received: by mail-pj1-x102d.google.com with SMTP id b5so2623662pjl.0 for ; Tue, 22 Dec 2020 22:02:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+YifPKBjeNPD3+AdzdyhluVeDh6aW7Lq7n/ZdL+ewjA=; b=ssywNbmrhfbHmx6kvvyMkon5Gxxy/W+yIo1dBlrfE74KjhnDM1+LHQ6/kan98pk9sY MnA6wVb20K3k/qJSAqJ+rDSmG4c+S3NbQAd+9533vAwXOAJt3rfMvJIbdYivAX50x7N+ UkPJpxHfPsaZVtFBxTSOq03XH32Yp9cxwIQ5Bvx2r1Hy16l07S6SHraJMBxNIGoDEEPK ITYPH0B6fkb8MLNGrx0Ff26ab31IErFKHf/kulnEfH6FCxvUeAaYEIXr3XPcI6DQNhhD mFjr38OIHpnPG6cVeFA6/l7AQIU49lCL+mmUhIzvyhui0J1MMoIdYhFoH47OwDVvyd0u ERpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+YifPKBjeNPD3+AdzdyhluVeDh6aW7Lq7n/ZdL+ewjA=; b=OyqQgGEvLJftmLWmBfcyQtCZKG+iT+eAdzq/9pHEbDmd7aaIjnlQaeXu/LHXITQcmb AN+zmE5mDhR74SmkVqsVE6W6g0vS7S0xUywo321BUGZUS8wn0n9hwrqRvro9SIt3TgPI de8wIIS5ED3V44xZjHrG2EDk5UQbgGnWYd47+90aCqjpKUBuaAHpNaeCqaqrgGZCSsTS FOKljLfMpLHTfRlOB3AOLKVNDauxO9G9zJyhJmwCIEOlpZYSTsA3pxC+XizXmvgL9ohK H1fTb8ExuEFbuFzxBVhVJhc7lpO11vqA4gQ4tmj5df7CVkOvwIfV8+iqHsm9xicVwFI1 P9Pw== X-Gm-Message-State: AOAM532F3fzf003S+RruJGf4csIps9LLwrdb38U1z4qfbM1ZrTDZjowf xV6gJ5xbVOLMJNGeDkM0cRJ0M5eJ0gjO/g== X-Google-Smtp-Source: ABdhPJxOAHPBGYhDUrkwmqiMwzTOpSIvnp2r7uXnUBVqokCOSkg9bOnc04zTfpvDVX9YqE1fN2CdJA== X-Received: by 2002:a17:90a:bf05:: with SMTP id c5mr24783970pjs.95.1608703341906; Tue, 22 Dec 2020 22:02:21 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 13/22] tcg: Split out constraint sets to tcg-target-conset.h Date: Tue, 22 Dec 2020 22:01:55 -0800 Message-Id: <20201223060204.576856-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This exports the constraint sets from tcg_target_op_def to a place we will be able to manipulate more in future. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-conset.h | 44 ++++++++ tcg/i386/tcg-target.h | 1 + tcg/tcg.c | 126 +++++++++++++++++++++++ tcg/i386/tcg-target.c.inc | 189 ++++++++++++----------------------- 4 files changed, 236 insertions(+), 124 deletions(-) create mode 100644 tcg/i386/tcg-target-conset.h diff --git a/tcg/i386/tcg-target-conset.h b/tcg/i386/tcg-target-conset.h new file mode 100644 index 0000000000..5a4f991d78 --- /dev/null +++ b/tcg/i386/tcg-target-conset.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: MIT */ +/* + * i386 target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(L, L) +C_O0_I2(qi, r) +C_O0_I2(re, r) +C_O0_I2(ri, r) +C_O0_I2(r, re) +C_O0_I2(x, r) +C_O0_I3(L, L, L) +C_O0_I4(L, L, L, L) +C_O0_I4(r, r, ri, ri) +C_O1_I1(r, 0) +C_O1_I1(r, L) +C_O1_I1(r, q) +C_O1_I1(r, r) +C_O1_I1(x, r) +C_O1_I1(x, x) +C_O1_I2(Q, 0, Q) +C_O1_I2(q, r, re) +C_O1_I2(r, 0, ci) +C_O1_I2(r, 0, r) +C_O1_I2(r, 0, re) +C_O1_I2(r, 0, reZ) +C_O1_I2(r, 0, ri) +C_O1_I2(r, 0, rI) +C_O1_I2(r, L, L) +C_O1_I2(r, r, re) +C_O1_I2(r, r, ri) +C_O1_I2(x, x, x) +C_N1_I2(r, r, r) +C_N1_I2(r, r, rW) +C_O1_I3(x, x, x, x) +C_O1_I4(r, r, re, r, 0) +C_O1_I4(r, r, r, ri, ri) +C_O2_I1(r, r, L) +C_O2_I2(a, d, a, r) +C_O2_I2(r, r, L, L) +C_O2_I3(a, d, 0, 1, r) +C_O2_I4(r, r, 0, 1, re, re) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index abd4ac7fc0..74a2566900 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -235,5 +235,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSET_H #endif diff --git a/tcg/tcg.c b/tcg/tcg.c index 2bde926315..c58d728ca5 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -68,7 +68,11 @@ /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ static void tcg_target_init(TCGContext *s); +#ifdef TCG_TARGET_CONSET_H +static int tcg_target_op_def(TCGOpcode); +#else static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode); +#endif static void tcg_target_qemu_prologue(TCGContext *s); static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend); @@ -340,6 +344,121 @@ static void set_jmp_reset_offset(TCGContext *s, int which) s->tb_jmp_reset_offset[which] = tcg_current_code_size(s); } +#ifdef TCG_TARGET_CONSET_H +#define C_PFX1(P, A) P##A +#define C_PFX2(P, A, B) P##A##_##B +#define C_PFX3(P, A, B, C) P##A##_##B##_##C +#define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D +#define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E +#define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F + +/* Define an enumeration for the various combinations. */ + +#define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1), +#define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2), +#define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3), +#define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4), + +#define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1), +#define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2), +#define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3), +#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4), + +#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2), + +#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1), +#define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2), +#define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3), +#define C_O2_I4(O1, O2, I1, I2, I3, I4) \ + C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4), + +typedef enum { +#include "tcg-target-conset.h" +} TCGConstraintSetIndex; + + +#undef C_O0_I1 +#undef C_O0_I2 +#undef C_O0_I3 +#undef C_O0_I4 +#undef C_O1_I1 +#undef C_O1_I2 +#undef C_O1_I3 +#undef C_O1_I4 +#undef C_N1_I2 +#undef C_O2_I1 +#undef C_O2_I2 +#undef C_O2_I3 +#undef C_O2_I4 + +/* Put all of the constraint sets into an array, indexed by the enum. */ + +#define C_O0_I1(I1) { .args_ct_str = { #I1 } }, +#define C_O0_I2(I1, I2) { .args_ct_str = { #I1, #I2 } }, +#define C_O0_I3(I1, I2, I3) { .args_ct_str = { #I1, #I2, #I3 } }, +#define C_O0_I4(I1, I2, I3, I4) \ + { .args_ct_str = { #I1, #I2, #I3, #I4 } }, + +#define C_O1_I1(O1, I1) { .args_ct_str = { #O1, #I1 } }, +#define C_O1_I2(O1, I1, I2) { .args_ct_str = { #O1, #I1, #I2 } }, +#define C_O1_I3(O1, I1, I2, I3) \ + { .args_ct_str = { #O1, #I1, #I2, #I3 } }, +#define C_O1_I4(O1, I1, I2, I3, I4) \ + { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } }, + +#define C_N1_I2(O1, I1, I2) \ + { .args_ct_str = { "&" #O1, #I1, #I2 } }, + +#define C_O2_I1(O1, O2, I1) \ + { .args_ct_str = { #O1, #O2, #I1 } }, +#define C_O2_I2(O1, O2, I1, I2) \ + { .args_ct_str = { #O1, #O2, #I1, #I2 } }, +#define C_O2_I3(O1, O2, I1, I2, I3) \ + { .args_ct_str = { #O1, #O2, #I1, #I2, #I3 } }, +#define C_O2_I4(O1, O2, I1, I2, I3, I4) \ + { .args_ct_str = { #O1, #O2, #I1, #I2, #I3, #I4 } }, + +static const TCGTargetOpDef constraint_sets[] = { +#include "tcg-target-conset.h" +}; + + +#undef C_O0_I1 +#undef C_O0_I2 +#undef C_O0_I3 +#undef C_O0_I4 +#undef C_O1_I1 +#undef C_O1_I2 +#undef C_O1_I3 +#undef C_O1_I4 +#undef C_N1_I2 +#undef C_O2_I1 +#undef C_O2_I2 +#undef C_O2_I3 +#undef C_O2_I4 + +/* Expand the enumerator to be returned from tcg_target_op_def(). */ + +#define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1) +#define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2) +#define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3) +#define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4) + +#define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1) +#define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2) +#define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3) +#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4) + +#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2) + +#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1) +#define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2) +#define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3) +#define C_O2_I4(O1, O2, I1, I2, I3, I4) \ + C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4) + +#endif /* TCG_TARGET_CONSET_H */ + #include "tcg-target.c.inc" /* compare a pointer @ptr and a tb_tc @s */ @@ -2248,9 +2367,16 @@ static void process_op_defs(TCGContext *s) continue; } +#ifdef TCG_TARGET_CONSET_H + i = tcg_target_op_def(op); + /* Missing TCGTargetOpDef entry. */ + tcg_debug_assert(i >= 0 && i < ARRAY_SIZE(constraint_sets)); + tdefs = &constraint_sets[i]; +#else tdefs = tcg_target_op_def(op); /* Missing TCGTargetOpDef entry. */ tcg_debug_assert(tdefs != NULL); +#endif for (i = 0; i < nb_args; i++) { const char *ct_str = tdefs->args_ct_str[i]; diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 981dd9aca4..708d465cbb 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2903,39 +2903,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, } } -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef ri_r = { .args_ct_str = { "ri", "r" } }; - static const TCGTargetOpDef re_r = { .args_ct_str = { "re", "r" } }; - static const TCGTargetOpDef qi_r = { .args_ct_str = { "qi", "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef r_q = { .args_ct_str = { "r", "q" } }; - static const TCGTargetOpDef r_re = { .args_ct_str = { "r", "re" } }; - static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } }; - static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } }; - static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } }; - static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; - static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } }; - static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } }; - static const TCGTargetOpDef r_r_L_L - = { .args_ct_str = { "r", "r", "L", "L" } }; - static const TCGTargetOpDef L_L_L_L - = { .args_ct_str = { "L", "L", "L", "L" } }; - static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } }; - static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } }; - static const TCGTargetOpDef x_x_x_x - = { .args_ct_str = { "x", "x", "x", "x" } }; - static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: @@ -2949,22 +2921,25 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: - return &r_r; + return C_O1_I1(r, r); case INDEX_op_st8_i32: case INDEX_op_st8_i64: - return &qi_r; + return C_O0_I2(qi, r); + case INDEX_op_st16_i32: case INDEX_op_st16_i64: case INDEX_op_st_i32: case INDEX_op_st32_i64: - return &ri_r; + return C_O0_I2(ri, r); + case INDEX_op_st_i64: - return &re_r; + return C_O0_I2(re, r); case INDEX_op_add_i32: case INDEX_op_add_i64: - return &r_r_re; + return C_O1_I2(r, r, re); + case INDEX_op_sub_i32: case INDEX_op_sub_i64: case INDEX_op_mul_i32: @@ -2973,24 +2948,15 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: - return &r_0_re; + return C_O1_I2(r, 0, re); case INDEX_op_and_i32: case INDEX_op_and_i64: - { - static const TCGTargetOpDef and - = { .args_ct_str = { "r", "0", "reZ" } }; - return ∧ - } - break; + return C_O1_I2(r, 0, reZ); + case INDEX_op_andc_i32: case INDEX_op_andc_i64: - { - static const TCGTargetOpDef andc - = { .args_ct_str = { "r", "r", "rI" } }; - return &andc; - } - break; + return C_O1_I2(r, 0, rI); case INDEX_op_shl_i32: case INDEX_op_shl_i64: @@ -2998,16 +2964,17 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_shr_i64: case INDEX_op_sar_i32: case INDEX_op_sar_i64: - return have_bmi2 ? &r_r_ri : &r_0_ci; + return have_bmi2 ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ci); + case INDEX_op_rotl_i32: case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: - return &r_0_ci; + return C_O1_I2(r, 0, ci); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_re; + return C_O0_I2(r, re); case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -3019,13 +2986,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_not_i32: case INDEX_op_not_i64: case INDEX_op_extrh_i64_i32: - return &r_0; + return C_O1_I1(r, 0); case INDEX_op_ext8s_i32: case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i64: - return &r_q; + return C_O1_I1(r, q); + case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: case INDEX_op_ext16u_i32: @@ -3040,108 +3008,80 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_sextract_i32: case INDEX_op_ctpop_i32: case INDEX_op_ctpop_i64: - return &r_r; + return C_O1_I1(r, r); + case INDEX_op_extract2_i32: case INDEX_op_extract2_i64: - return &r_0_r; + return C_O1_I2(r, 0, r); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - { - static const TCGTargetOpDef dep - = { .args_ct_str = { "Q", "0", "Q" } }; - return &dep; - } + return C_O1_I2(Q, 0, Q); + case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - { - static const TCGTargetOpDef setc - = { .args_ct_str = { "q", "r", "re" } }; - return &setc; - } + return C_O1_I2(q, r, re); + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - { - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "re", "r", "0" } }; - return &movc; - } + return C_O1_I4(r, r, re, r, 0); + case INDEX_op_div2_i32: case INDEX_op_div2_i64: case INDEX_op_divu2_i32: case INDEX_op_divu2_i64: - { - static const TCGTargetOpDef div2 - = { .args_ct_str = { "a", "d", "0", "1", "r" } }; - return &div2; - } + return C_O2_I3(a, d, 0, 1, r); + case INDEX_op_mulu2_i32: case INDEX_op_mulu2_i64: case INDEX_op_muls2_i32: case INDEX_op_muls2_i64: - { - static const TCGTargetOpDef mul2 - = { .args_ct_str = { "a", "d", "a", "r" } }; - return &mul2; - } + return C_O2_I2(a, d, a, r); + case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - { - static const TCGTargetOpDef arith2 - = { .args_ct_str = { "r", "r", "0", "1", "re", "re" } }; - return &arith2; - } + return C_O2_I4(r, r, 0, 1, re, re); + case INDEX_op_ctz_i32: case INDEX_op_ctz_i64: - { - static const TCGTargetOpDef ctz[2] = { - { .args_ct_str = { "&r", "r", "r" } }, - { .args_ct_str = { "&r", "r", "rW" } }, - }; - return &ctz[have_bmi1]; - } + return have_bmi1 ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); + case INDEX_op_clz_i32: case INDEX_op_clz_i64: - { - static const TCGTargetOpDef clz[2] = { - { .args_ct_str = { "&r", "r", "r" } }, - { .args_ct_str = { "&r", "r", "rW" } }, - }; - return &clz[have_lzcnt]; - } + return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); + case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L : &L_L_L; + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + ? C_O0_I2(L, L) : C_O0_I3(L, L, L)); + case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L); + return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L) + : C_O2_I2(r, r, L, L)); + case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS == 64 ? &L_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L_L - : &L_L_L_L); + return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(L, L, L) + : C_O0_I4(L, L, L, L)); case INDEX_op_brcond2_i32: - { - static const TCGTargetOpDef b2 - = { .args_ct_str = { "r", "r", "ri", "ri" } }; - return &b2; - } + return C_O0_I4(r, r, ri, ri); + case INDEX_op_setcond2_i32: - { - static const TCGTargetOpDef s2 - = { .args_ct_str = { "r", "r", "r", "ri", "ri" } }; - return &s2; - } + return C_O1_I4(r, r, r, ri, ri); case INDEX_op_ld_vec: - case INDEX_op_st_vec: case INDEX_op_dupm_vec: - return &x_r; + return C_O1_I1(x, r); + + case INDEX_op_st_vec: + return C_O0_I2(x, r); case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -3176,21 +3116,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) #if TCG_TARGET_REG_BITS == 32 case INDEX_op_dup2_vec: #endif - return &x_x_x; + return C_O1_I2(x, x, x); + case INDEX_op_abs_vec: case INDEX_op_dup_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: case INDEX_op_x86_psrldq_vec: - return &x_x; + return C_O1_I1(x, x); + case INDEX_op_x86_vpblendvb_vec: - return &x_x_x_x; + return C_O1_I3(x, x, x, x); default: - break; + g_assert_not_reached(); } - return NULL; } int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) From patchwork Wed Dec 23 06:01:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419601 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=iHgGoOjd; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D12w10FXfz9sVm for ; Wed, 23 Dec 2020 17:13:53 +1100 (AEDT) Received: from localhost ([::1]:47648 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxPC-0002PN-VB for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:13:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39434) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEG-0008Rc-S4 for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:34 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:34029) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxEA-0000OQ-Tx for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:32 -0500 Received: by mail-pj1-x1035.google.com with SMTP id n3so610589pjm.1 for ; Tue, 22 Dec 2020 22:02:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uRTDlrjsZd2ECIgzVgTpVsKManvsUod3zyWxTNTa0RQ=; b=iHgGoOjdhlF0doqVJuoJTFXDzvBBZFkCC7H1iekTbBVLihleD2Upj/p9778yGzNelV AXT7sDLSoZkVPqAcMmiE3EbA7koq690xX+RBJS1zSzpc+2Qb9u2BT5QGGRrQ3lv/eOeH Mslnd9w/tb0quJzH3MV77MfNRMqnCJoXdmgNMyxuwaRZECXS4dEoDObbRSMcbPopqF84 2oxhwp+YJSdVHGX22Ma9d5VG9dOxSVncBhKKTQ2KSQRjs7MJMkWci4xHDz4NHfuNcXpp j1nx//JirVdg5uxX//sSx0Ub66py5u5e4d2zwVqUZ+zi2h6KTWNLvMgy7sJAL7HlUfjR BhgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uRTDlrjsZd2ECIgzVgTpVsKManvsUod3zyWxTNTa0RQ=; b=ctQ4ZWfvsTNGugdKmsGq9cjM3lQIWR0jsmX4LuiSDMrVboRsT2pnXlVQ1Bo15EFse+ Ypq3Tot6hy+8SkEttYMKbBT81Ei6+FIS2ZiwYHuNcCnRLQVlK1bcKTnKpq4h5zx1P8Lg SbOZ0YpAIFDytaDYBgpF3Mb1osZ/iCTiZptDhm5mWnVxika6LWVepSM5espmt75PiaJT y42SuCMaO90V7ZJXau9f+yKW6BGl2yZWjqDK84sZ/zVV5q6j+KwSlM2W+bbeG3Q8Ee4K OQeG/nWd6r4C5CJJWeEzPaiUI80b2KGru7BGz4cNEUH0TziE0LR4s5vPk1B//q7dbfrJ LiOQ== X-Gm-Message-State: AOAM533ICfX5VGq4bxDDzLyy6dl7YH3aVKqwaVmZCp8EiZA91jgTV+Ta YquJ34VyFpK+6Vdedk8FNLRYUC+7PHar+A== X-Google-Smtp-Source: ABdhPJwdsxRScDshTrNiwG/OkYCo3ZwxO0HPPotUuprTDY06FpBW/FnPwcr8RjJd5KuNR7o3BgaeDA== X-Received: by 2002:a17:902:c155:b029:da:9460:99a0 with SMTP id 21-20020a170902c155b02900da946099a0mr24244590plj.20.1608703343128; Tue, 22 Dec 2020 22:02:23 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 14/22] tcg/aarch64: Convert to tcg-target-conset.h Date: Tue, 22 Dec 2020 22:01:56 -0800 Message-Id: <20201223060204.576856-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-conset.h | 31 ++++++++++++ tcg/aarch64/tcg-target.h | 1 + tcg/aarch64/tcg-target.c.inc | 86 +++++++++++---------------------- 3 files changed, 60 insertions(+), 58 deletions(-) create mode 100644 tcg/aarch64/tcg-target-conset.h diff --git a/tcg/aarch64/tcg-target-conset.h b/tcg/aarch64/tcg-target-conset.h new file mode 100644 index 0000000000..2df8157b15 --- /dev/null +++ b/tcg/aarch64/tcg-target-conset.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * AArch64 target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(lZ, l) +C_O0_I2(r, rA) +C_O0_I2(rZ, r) +C_O0_I2(w, r) +C_O1_I1(r, l) +C_O1_I1(r, r) +C_O1_I1(w, r) +C_O1_I1(w, w) +C_O1_I1(w, wr) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, r, r) +C_O1_I2(r, r, rA) +C_O1_I2(r, r, rAL) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rL) +C_O1_I2(r, rZ, rZ) +C_O1_I2(w, 0, w) +C_O1_I2(w, w, w) +C_O1_I2(w, w, wN) +C_O1_I2(w, w, wO) +C_O1_I2(w, w, wZ) +C_O1_I3(w, w, w, w) +C_O1_I4(r, r, rA, rZ, rZ) +C_O2_I4(r, r, rZ, rZ, rA, rMZ) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 663dd0b95e..a81f6dadf9 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -159,5 +159,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSET_H #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 310bc972e3..aaf8918a4b 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2541,42 +2541,11 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, va_end(va); } -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } }; - static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } }; - static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } }; - static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } }; - static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } }; - static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } }; - static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; - static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } }; - static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } }; - static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } }; - static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } }; - static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } }; - static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } }; - static const TCGTargetOpDef r_r_rAL - = { .args_ct_str = { "r", "r", "rAL" } }; - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "0", "rZ" } }; - static const TCGTargetOpDef ext2 - = { .args_ct_str = { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } }; - static const TCGTargetOpDef add2 - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rA", "rMZ" } }; - static const TCGTargetOpDef w_w_w_w - = { .args_ct_str = { "w", "w", "w", "w" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -2615,7 +2584,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_extract_i64: case INDEX_op_sextract_i32: case INDEX_op_sextract_i64: - return &r_r; + return C_O1_I1(r, r); case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -2624,7 +2593,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); case INDEX_op_add_i32: case INDEX_op_add_i64: @@ -2632,7 +2601,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_sub_i64: case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - return &r_r_rA; + return C_O1_I2(r, r, rA); case INDEX_op_mul_i32: case INDEX_op_mul_i64: @@ -2646,7 +2615,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_remu_i64: case INDEX_op_muluh_i64: case INDEX_op_mulsh_i64: - return &r_r_r; + return C_O1_I2(r, r, r); case INDEX_op_and_i32: case INDEX_op_and_i64: @@ -2660,7 +2629,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_orc_i64: case INDEX_op_eqv_i32: case INDEX_op_eqv_i64: - return &r_r_rL; + return C_O1_I2(r, r, rL); case INDEX_op_shl_i32: case INDEX_op_shr_i32: @@ -2672,42 +2641,42 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_sar_i64: case INDEX_op_rotl_i64: case INDEX_op_rotr_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); case INDEX_op_clz_i32: case INDEX_op_ctz_i32: case INDEX_op_clz_i64: case INDEX_op_ctz_i64: - return &r_r_rAL; + return C_O1_I2(r, r, rAL); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_rA; + return C_O0_I2(r, rA); case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return &movc; + return C_O1_I4(r, r, rA, rZ, rZ); case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return &r_l; + return C_O1_I1(r, l); case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - return &lZ_l; + return C_O0_I2(lZ, l); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_extract2_i32: case INDEX_op_extract2_i64: - return &ext2; + return C_O1_I2(r, rZ, rZ); case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - return &add2; + return C_O2_I4(r, r, rZ, rZ, rA, rMZ); case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -2725,35 +2694,36 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: case INDEX_op_aa64_sshl_vec: - return &w_w_w; + return C_O1_I2(w, w, w); case INDEX_op_not_vec: case INDEX_op_neg_vec: case INDEX_op_abs_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: - return &w_w; + return C_O1_I1(w, w); case INDEX_op_ld_vec: - case INDEX_op_st_vec: case INDEX_op_dupm_vec: - return &w_r; + return C_O1_I1(w, r); + case INDEX_op_st_vec: + return C_O0_I2(w, r); case INDEX_op_dup_vec: - return &w_wr; + return C_O1_I1(w, wr); case INDEX_op_or_vec: case INDEX_op_andc_vec: - return &w_w_wO; + return C_O1_I2(w, w, wO); case INDEX_op_and_vec: case INDEX_op_orc_vec: - return &w_w_wN; + return C_O1_I2(w, w, wN); case INDEX_op_cmp_vec: - return &w_w_wZ; + return C_O1_I2(w, w, wZ); case INDEX_op_bitsel_vec: - return &w_w_w_w; + return C_O1_I3(w, w, w, w); case INDEX_op_aa64_sli_vec: - return &w_0_w; + return C_O1_I2(w, 0, w); default: - return NULL; + g_assert_not_reached(); } } From patchwork Wed Dec 23 06:01:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419604 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=h/LtO7PQ; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D130J4FfWz9sVm for ; Wed, 23 Dec 2020 17:17:36 +1100 (AEDT) Received: from localhost ([::1]:56806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxSo-0006JZ-IV for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:17:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39518) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEP-0008Tt-Nm for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:41 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:50296) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxEA-0000Py-Vk for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:41 -0500 Received: by mail-pj1-x1031.google.com with SMTP id lj6so2483606pjb.0 for ; Tue, 22 Dec 2020 22:02:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=yGmI0QnYWg43jv8xLi9von8FNP2RJruA54pGCztFbJA=; b=h/LtO7PQ/tFSMA8xl3uEzC3ctNYiaQ6mzu2nSRkCRKnl1CLmxOuID7J9Upec+kQQkP aHagMK+vlmaLECk8TNZCQxNcQPJsnOpFGsKPuhz9/OvAYWkkgHo+gvyzM0VNv9Xgi2SE VYVuNcLjtq4YnsHAQCsg7o34K568UHY5gc5IGZi4wL1nRvWDfyKgTthv9bIojsq0Nv2V Y9du5ISmOvpdPJ4Q6g8sML5UE/goa++pLrgTRFJZR6sLhfRtqFAZpxCetnR2usSlN7zO IBEPW09QrHf1h6pjpCaIvCD3WzwkPE+kgMA6Hec9DShFfOkrF4CYKOYO81YLoahwG/OK 9RwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yGmI0QnYWg43jv8xLi9von8FNP2RJruA54pGCztFbJA=; b=MgqiqtFL0HhcIrJUhCsmuhm6H1oDdIhi7Nxb+RhDghnyBnc6wFc93DKwSSsVfZY3W+ Z+boOEGnDyit0n0xZeO9t+bgN7fwDfC1XDZ5A5TaeJ9U0JFRfqE4qXGanta0jhuUnBnp CeFNqdDYe4lkNzsJ5X6DNLjXGsSRI+0viDgkCBuTxT0ZIoL4LghzFcMfLMApLM6e5iTr skaj8cpmVEZ8qK0E2xbAptD3eLJummHFTnb6NwPWDI4n18R6hFJMwF858h0sJi3XvNDe HmP67DHLDydjAB4GMmJR/6NGgBGRT8Bvt1lbJ4UYGImWRVD55EAsBnIxmqrPlhScNfVO NNxg== X-Gm-Message-State: AOAM530MZPResQOzFzcJzqo07dOBsEguLmS3DnLhEM0LamXPQKCJuCMx EXXI+Nkyr2upRagYE+rM7FWVDNGeV9vhEQ== X-Google-Smtp-Source: ABdhPJyqfDH/eg68Wym9h2XMMvvopjduw6cZkwt9t3qOdkSlstlgGj/2isdW4ZcjO69KlEzkfU1FFw== X-Received: by 2002:a17:902:7b84:b029:da:60e0:9d38 with SMTP id w4-20020a1709027b84b02900da60e09d38mr23965631pll.55.1608703344329; Tue, 22 Dec 2020 22:02:24 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 15/22] tcg/arm: Convert to tcg-target-conset.h Date: Tue, 22 Dec 2020 22:01:57 -0800 Message-Id: <20201223060204.576856-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-conset.h | 30 ++++++++++++ tcg/arm/tcg-target.h | 1 + tcg/arm/tcg-target.c.inc | 94 +++++++++++++------------------------ 3 files changed, 63 insertions(+), 62 deletions(-) create mode 100644 tcg/arm/tcg-target-conset.h diff --git a/tcg/arm/tcg-target-conset.h b/tcg/arm/tcg-target-conset.h new file mode 100644 index 0000000000..7e972e70e0 --- /dev/null +++ b/tcg/arm/tcg-target-conset.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Arm target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(r, r) +C_O0_I2(r, rIN) +C_O0_I2(s, s) +C_O0_I3(s, s, s) +C_O0_I4(r, r, rI, rI) +C_O0_I4(s, s, s, s) +C_O1_I1(r, l) +C_O1_I1(r, r) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, l, l) +C_O1_I2(r, r, r) +C_O1_I2(r, r, rI) +C_O1_I2(r, r, rIK) +C_O1_I2(r, r, rIN) +C_O1_I2(r, r, ri) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, r, r, rI, rI) +C_O1_I4(r, r, rIN, rIK, 0) +C_O2_I1(r, r, l) +C_O2_I2(r, r, l, l) +C_O2_I2(r, r, r, r) +C_O2_I4(r, r, r, r, rIN, rIK) +C_O2_I4(r, r, rI, rI, rIN, rIK) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 17e771374d..918f09239a 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -146,5 +146,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSET_H #endif diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index ab1b295293..029d58e4b7 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2012,57 +2012,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } } -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } }; - static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } }; - static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; - static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } }; - static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } }; - static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; - static const TCGTargetOpDef r_r_rIN - = { .args_ct_str = { "r", "r", "rIN" } }; - static const TCGTargetOpDef r_r_rIK - = { .args_ct_str = { "r", "r", "rIK" } }; - static const TCGTargetOpDef r_r_r_r - = { .args_ct_str = { "r", "r", "r", "r" } }; - static const TCGTargetOpDef r_r_l_l - = { .args_ct_str = { "r", "r", "l", "l" } }; - static const TCGTargetOpDef s_s_s_s - = { .args_ct_str = { "s", "s", "s", "s" } }; - static const TCGTargetOpDef br - = { .args_ct_str = { "r", "rIN" } }; - static const TCGTargetOpDef ext2 - = { .args_ct_str = { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "0", "rZ" } }; - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "rIN", "rIK", "0" } }; - static const TCGTargetOpDef add2 - = { .args_ct_str = { "r", "r", "r", "r", "rIN", "rIK" } }; - static const TCGTargetOpDef sub2 - = { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } }; - static const TCGTargetOpDef br2 - = { .args_ct_str = { "r", "r", "rI", "rI" } }; - static const TCGTargetOpDef setc2 - = { .args_ct_str = { "r", "r", "r", "rI", "rI" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: case INDEX_op_ld16s_i32: case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: case INDEX_op_neg_i32: case INDEX_op_not_i32: case INDEX_op_bswap16_i32: @@ -2072,62 +2032,72 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ext16u_i32: case INDEX_op_extract_i32: case INDEX_op_sextract_i32: - return &r_r; + return C_O1_I1(r, r); + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + return C_O0_I2(r, r); case INDEX_op_add_i32: case INDEX_op_sub_i32: case INDEX_op_setcond_i32: - return &r_r_rIN; + return C_O1_I2(r, r, rIN); + case INDEX_op_and_i32: case INDEX_op_andc_i32: case INDEX_op_clz_i32: case INDEX_op_ctz_i32: - return &r_r_rIK; + return C_O1_I2(r, r, rIK); + case INDEX_op_mul_i32: case INDEX_op_div_i32: case INDEX_op_divu_i32: - return &r_r_r; + return C_O1_I2(r, r, r); + case INDEX_op_mulu2_i32: case INDEX_op_muls2_i32: - return &r_r_r_r; + return C_O2_I2(r, r, r, r); + case INDEX_op_or_i32: case INDEX_op_xor_i32: - return &r_r_rI; + return C_O1_I2(r, r, rI); + case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: case INDEX_op_rotl_i32: case INDEX_op_rotr_i32: - return &r_r_ri; + return C_O1_I2(r, r, ri); case INDEX_op_brcond_i32: - return &br; + return C_O0_I2(r, rIN); case INDEX_op_deposit_i32: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_extract2_i32: - return &ext2; + return C_O1_I2(r, rZ, rZ); case INDEX_op_movcond_i32: - return &movc; + return C_O1_I4(r, r, rIN, rIK, 0); case INDEX_op_add2_i32: - return &add2; + return C_O2_I4(r, r, r, r, rIN, rIK); case INDEX_op_sub2_i32: - return &sub2; + return C_O2_I4(r, r, rI, rI, rIN, rIK); case INDEX_op_brcond2_i32: - return &br2; + return C_O0_I4(r, r, rI, rI); case INDEX_op_setcond2_i32: - return &setc2; + return C_O1_I4(r, r, r, rI, rI); case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l; + return TARGET_LONG_BITS == 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, l); case INDEX_op_qemu_ld_i64: - return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l; + return TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, l) : C_O2_I2(r, r, l, l); case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s; + return TARGET_LONG_BITS == 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, s); case INDEX_op_qemu_st_i64: - return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s; + return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s); default: - return NULL; + g_assert_not_reached(); } } From patchwork Wed Dec 23 06:01:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419611 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Er2JoGa/; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D13BY5xD7z9sVm for ; Wed, 23 Dec 2020 17:26:29 +1100 (AEDT) Received: from localhost ([::1]:44850 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxbP-0004sQ-Pd for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:26:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39516) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEP-0008Tl-KB for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:41 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:40056) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxEB-0000Q4-JR for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:39 -0500 Received: by mail-pl1-x634.google.com with SMTP id q4so8596856plr.7 for ; Tue, 22 Dec 2020 22:02:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=X758HD6K1J6obb9plyMDfKBI50GFn/H1bBv6I/APYbM=; b=Er2JoGa/KxiBTlhJjrZ0DNAnCKsHKrwM3JuCQgsGqmij6wIzATl26lelqage4oFBDs 0hQEQtArB/6n88nq8f1FJe2qkbUa+O4CzXh2x8JjZycmCdijkkWB1uWmiXyeGeo2jwO9 3XE3KKByV9sH6F6tJt60S/U7kLSeNhb3/hdFt9LN8g+UlMjx5FQfkigj/eKy7qpsv6Yv /Vvro0frIsxXw5u2C0lhcweG2wDDTwj5w/4dM/Fv2wEDPYU7yJafVYstjPRjqiHLOUQY f9qeZDpRMwh3hzDqXaAWJi85meXo1Oavj1ZjXjqperAkZV28hr1Uo2z9iG4OTNioWfRB 5Xww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X758HD6K1J6obb9plyMDfKBI50GFn/H1bBv6I/APYbM=; b=tNnLAf4TSgOyDmrf0Df7WUzbsPrymPeo1ZjCOLR8jJY/8jdxmgWjsaTR7r45K3UqR1 p7kWbqjh+BNcmfxu/QmM4A3IFp9dSWkU7wD42H3K8NtHmEk4PCDISvGuabGohSARJwmD UD3UjyrSBSh6oUV4rru8Mlygu3XAgdZ6kplo/swwVcKLZheFlQYIKG6aiV7XMytIssab OidkMHJ/AUJWN8E8agUoPp2s/ILDTSU4o9/Af0VtuJm4ioJ7Nk1qe7zWLds9XjlPb1+u vnkWE0lhXBBNs5PyEtL83Z/eK5EU0w6bWjeqXxDifjHkJ51P29OMjSP9DVe957pqXWSu OXqA== X-Gm-Message-State: AOAM532sqfdQYN8FiCSaLeh7f0pNWeTBb55Y8a053nkbwKdvtGgb+hDc b8jBl+Al+GUXV0UG+eVHct5TaeUlDijOyA== X-Google-Smtp-Source: ABdhPJwQx0zCNLpiCYhG50QAOc0YJNe77xM9Q6oXwd74sN3eZp8zDuSrJprEDULzRoI4LJSm2V4KMw== X-Received: by 2002:a17:902:820a:b029:da:f380:8629 with SMTP id x10-20020a170902820ab02900daf3808629mr2106726pln.54.1608703345558; Tue, 22 Dec 2020 22:02:25 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 16/22] tcg/mips: Convert to tcg-target-conset.h Date: Tue, 22 Dec 2020 22:01:58 -0800 Message-Id: <20201223060204.576856-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-conset.h | 31 ++++++++++++ tcg/mips/tcg-target.h | 1 + tcg/mips/tcg-target.c.inc | 96 +++++++++++------------------------- 3 files changed, 61 insertions(+), 67 deletions(-) create mode 100644 tcg/mips/tcg-target-conset.h diff --git a/tcg/mips/tcg-target-conset.h b/tcg/mips/tcg-target-conset.h new file mode 100644 index 0000000000..94f8f5f683 --- /dev/null +++ b/tcg/mips/tcg-target-conset.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* + * MIPS target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(rZ, r) +C_O0_I2(rZ, rZ) +C_O0_I2(SZ, S) +C_O0_I3(SZ, S, S) +C_O0_I3(SZ, SZ, S) +C_O0_I4(rZ, rZ, rZ, rZ) +C_O0_I4(SZ, SZ, S, S) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, L, L) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, r, rIK) +C_O1_I2(r, r, rJ) +C_O1_I2(r, r, rWZ) +C_O1_I2(r, rZ, rN) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, rZ, rZ, rZ, 0) +C_O1_I4(r, rZ, rZ, rZ, rZ) +C_O2_I1(r, r, L) +C_O2_I2(r, r, L, L) +C_O2_I2(r, r, r, r) +C_O2_I4(r, r, rZ, rZ, rN, rN) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c6b091d849..688d691cda 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -217,5 +217,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif +#define TCG_TARGET_CONSET_H #endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index d0b674582a..2ec1d6ac05 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2104,52 +2104,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } } -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } }; - static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } }; - static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; - static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } }; - static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } }; - static const TCGTargetOpDef SZ_SZ_S - = { .args_ct_str = { "SZ", "SZ", "S" } }; - static const TCGTargetOpDef SZ_SZ_S_S - = { .args_ct_str = { "SZ", "SZ", "S", "S" } }; - static const TCGTargetOpDef r_rZ_rN - = { .args_ct_str = { "r", "rZ", "rN" } }; - static const TCGTargetOpDef r_rZ_rZ - = { .args_ct_str = { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_rIK - = { .args_ct_str = { "r", "r", "rIK" } }; - static const TCGTargetOpDef r_r_rWZ - = { .args_ct_str = { "r", "r", "rWZ" } }; - static const TCGTargetOpDef r_r_r_r - = { .args_ct_str = { "r", "r", "r", "r" } }; - static const TCGTargetOpDef r_r_L_L - = { .args_ct_str = { "r", "r", "L", "L" } }; - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "0", "rZ" } }; - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } }; - static const TCGTargetOpDef movc_r6 - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef add2 - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } }; - static const TCGTargetOpDef br2 - = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef setc2 - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -2182,7 +2141,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: case INDEX_op_extract_i64: - return &r_r; + return C_O1_I1(r, r); case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -2191,14 +2150,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); case INDEX_op_add_i32: case INDEX_op_add_i64: - return &r_r_rJ; + return C_O1_I2(r, r, rJ); case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return &r_rZ_rN; + return C_O1_I2(r, rZ, rN); case INDEX_op_mul_i32: case INDEX_op_mulsh_i32: case INDEX_op_muluh_i32: @@ -2217,20 +2176,20 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_remu_i64: case INDEX_op_nor_i64: case INDEX_op_setcond_i64: - return &r_rZ_rZ; + return C_O1_I2(r, rZ, rZ); case INDEX_op_muls2_i32: case INDEX_op_mulu2_i32: case INDEX_op_muls2_i64: case INDEX_op_mulu2_i64: - return &r_r_r_r; + return C_O2_I2(r, r, r, r); case INDEX_op_and_i32: case INDEX_op_and_i64: - return &r_r_rIK; + return C_O1_I2(r, r, rIK); case INDEX_op_or_i32: case INDEX_op_xor_i32: case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: @@ -2241,44 +2200,47 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_sar_i64: case INDEX_op_rotr_i64: case INDEX_op_rotl_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); case INDEX_op_clz_i32: case INDEX_op_clz_i64: - return &r_r_rWZ; + return C_O1_I2(r, r, rWZ); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &rZ_rZ; + return C_O0_I2(rZ, rZ); case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return use_mips32r6_instructions ? &movc_r6 : &movc; - + return (use_mips32r6_instructions + ? C_O1_I4(r, rZ, rZ, rZ, rZ) + : C_O1_I4(r, rZ, rZ, rZ, 0)); case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return &add2; + return C_O2_I4(r, r, rZ, rZ, rN, rN); case INDEX_op_setcond2_i32: - return &setc2; + return C_O1_I4(r, rZ, rZ, rZ, rZ); case INDEX_op_brcond2_i32: - return &br2; + return C_O0_I4(rZ, rZ, rZ, rZ); case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? &r_L : &r_L_L); + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? &SZ_S : &SZ_S_S); + ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S)); case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L); + return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L) + : C_O2_I2(r, r, L, L)); case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS == 64 ? &SZ_S - : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S); + return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S) + : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S) + : C_O0_I4(SZ, SZ, S, S)); default: - return NULL; + g_assert_not_reached(); } } From patchwork Wed Dec 23 06:01:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419603 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=IDWfEujj; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D12zq4LqKz9sVm for ; Wed, 23 Dec 2020 17:17:11 +1100 (AEDT) Received: from localhost ([::1]:56346 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxSP-00065P-JD for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:17:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39544) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxET-0008WN-Bd for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:45 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:36128) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxED-0000QE-QY for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:45 -0500 Received: by mail-pf1-x429.google.com with SMTP id t22so9787553pfl.3 for ; Tue, 22 Dec 2020 22:02:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=I5Jif50OCQX6bqPE3vNJ6iG9LjkUrr2qR3pVG1LDHQI=; b=IDWfEujjhzS2HMDPMraEVXOnImNegx9XkYCnPJnt1RsRj00NYcwEbNe404PIUUNUEM po1KTbHB4W29mS9cIhCdr4AbTQeTD+edZYJRQaMwOUjj7BrYwLNc9YO/49csNorqxcrA u+mm4Tr0Bfqa61sde499E9brTsELdMgNVIutqgLw7N9wWpeI4iAviMB2a/JoGnJMMjDD gsrwfIawNrr5awn1um+UbFms+bJxoDS1t+/lJnorp10ZGhw4n27CrogRegRwBSPxEsAh RiWw2MjuW9edO8fIfdV70hce3wwwcd+qsOCQEgwKqPUcPdFCAF9GZcMqkyv+HOoN3J6h QmRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I5Jif50OCQX6bqPE3vNJ6iG9LjkUrr2qR3pVG1LDHQI=; b=Knqz8xWezTLf++W+lUDNVbMg9CM7jSEexxHfoNt05Xga/Rvv6sMResmiyQseFV3xv0 hTA2OHgfriSw2DlUNXUL4QtJBmQqhBrle1Ms4cmC5AFeDeevQjqABIy4+7e4NlLlc96D /gc/t7NEMo/EZq7IaDlzPv2ZVc9XKG9v4b5sAMHC0xLmsy4OsOfDRilGKgb7l+swZO+4 GV3679O05JW2VMYCBLgPNamynIIM8f3zTJEJmcXSvyGmLgW7JL4yxiZEssC5RkkUKXwy J5Ih48P9gCxSAeVlSW0JyqSuAGuxaKv0yx7YhYuaxdqAQxXDnXEy0bZgjDqP6m6VAHuV Zk0A== X-Gm-Message-State: AOAM5317kNUfimt1Y9pIt+paierTJjXFegxvwoHqbfrHVI+Nx+h4mm38 zySTYigvYZJT0GQbL9v4zMnXYMlMWaCAtQ== X-Google-Smtp-Source: ABdhPJy1oDzqyTFM3ZfrZ5EPCYEwMxk+BgXSz9KeGx2idoYDpv26Mj1X0krrSvRQPixa2RDzzJtGuA== X-Received: by 2002:a63:da50:: with SMTP id l16mr7704970pgj.447.1608703346806; Tue, 22 Dec 2020 22:02:26 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 17/22] tcg/ppc: Convert to tcg-target-conset.h Date: Tue, 22 Dec 2020 22:01:59 -0800 Message-Id: <20201223060204.576856-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-conset.h | 37 ++++++++++ tcg/ppc/tcg-target.h | 1 + tcg/ppc/tcg-target.c.inc | 136 +++++++++++++++--------------------- 3 files changed, 94 insertions(+), 80 deletions(-) create mode 100644 tcg/ppc/tcg-target-conset.h diff --git a/tcg/ppc/tcg-target-conset.h b/tcg/ppc/tcg-target-conset.h new file mode 100644 index 0000000000..448ac6d155 --- /dev/null +++ b/tcg/ppc/tcg-target-conset.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: MIT */ +/* + * PowerPC target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(r, r) +C_O0_I2(r, ri) +C_O0_I2(S, S) +C_O0_I2(v, r) +C_O0_I3(S, S, S) +C_O0_I4(r, r, ri, ri) +C_O0_I4(S, S, S, S) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I1(v, r) +C_O1_I1(v, v) +C_O1_I1(v, vr) +C_O1_I2(r, 0, rZ) +C_O1_I2(r, L, L) +C_O1_I2(r, rI, ri) +C_O1_I2(r, rI, rT) +C_O1_I2(r, r, r) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, r, rT) +C_O1_I2(r, r, rU) +C_O1_I2(r, r, rZW) +C_O1_I2(v, v, v) +C_O1_I3(v, v, v, v) +C_O1_I4(r, r, ri, rZ, rZ) +C_O1_I4(r, r, r, ri, ri) +C_O2_I1(L, L, L) +C_O2_I2(L, L, L, L) +C_O2_I4(r, r, rI, rZM, r, r) +C_O2_I4(r, r, r, r, rI, rZM) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index be10363956..c958faffb7 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -185,5 +185,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSET_H #endif diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index c97f95f3cf..eb8a626ad4 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3425,62 +3425,17 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, va_end(va); } -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } }; - static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } }; - static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; - static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } }; - static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; - static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } }; - static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } }; - static const TCGTargetOpDef r_rI_ri - = { .args_ct_str = { "r", "rI", "ri" } }; - static const TCGTargetOpDef r_rI_rT - = { .args_ct_str = { "r", "rI", "rT" } }; - static const TCGTargetOpDef r_r_rZW - = { .args_ct_str = { "r", "r", "rZW" } }; - static const TCGTargetOpDef L_L_L_L - = { .args_ct_str = { "L", "L", "L", "L" } }; - static const TCGTargetOpDef S_S_S_S - = { .args_ct_str = { "S", "S", "S", "S" } }; - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } }; - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "0", "rZ" } }; - static const TCGTargetOpDef br2 - = { .args_ct_str = { "r", "r", "ri", "ri" } }; - static const TCGTargetOpDef setc2 - = { .args_ct_str = { "r", "r", "r", "ri", "ri" } }; - static const TCGTargetOpDef add2 - = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } }; - static const TCGTargetOpDef sub2 - = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } }; - static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } }; - static const TCGTargetOpDef v_vr = { .args_ct_str = { "v", "vr" } }; - static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } }; - static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } }; - static const TCGTargetOpDef v_v_v_v - = { .args_ct_str = { "v", "v", "v", "v" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: case INDEX_op_ld16s_i32: case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: case INDEX_op_ctpop_i32: case INDEX_op_neg_i32: case INDEX_op_not_i32: @@ -3496,10 +3451,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: case INDEX_op_ctpop_i64: case INDEX_op_neg_i64: case INDEX_op_not_i64: @@ -3512,7 +3463,16 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_bswap32_i64: case INDEX_op_bswap64_i64: case INDEX_op_extract_i64: - return &r_r; + return C_O1_I1(r, r); + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return C_O0_I2(r, r); case INDEX_op_add_i32: case INDEX_op_and_i32: @@ -3535,10 +3495,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_rotl_i64: case INDEX_op_rotr_i64: case INDEX_op_setcond_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); + case INDEX_op_mul_i32: case INDEX_op_mul_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); + case INDEX_op_div_i32: case INDEX_op_divu_i32: case INDEX_op_nand_i32: @@ -3553,55 +3515,63 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_divu_i64: case INDEX_op_mulsh_i64: case INDEX_op_muluh_i64: - return &r_r_r; + return C_O1_I2(r, r, r); + case INDEX_op_sub_i32: - return &r_rI_ri; + return C_O1_I2(r, rI, ri); case INDEX_op_add_i64: - return &r_r_rT; + return C_O1_I2(r, r, rT); case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rU; + return C_O1_I2(r, r, rU); case INDEX_op_sub_i64: - return &r_rI_rT; + return C_O1_I2(r, rI, rT); case INDEX_op_clz_i32: case INDEX_op_ctz_i32: case INDEX_op_clz_i64: case INDEX_op_ctz_i64: - return &r_r_rZW; + return C_O1_I2(r, r, rZW); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_ri; + return C_O0_I2(r, ri); case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return &movc; + return C_O1_I4(r, r, ri, rZ, rZ); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_brcond2_i32: - return &br2; + return C_O0_I4(r, r, ri, ri); case INDEX_op_setcond2_i32: - return &setc2; + return C_O1_I4(r, r, r, ri, ri); case INDEX_op_add2_i64: case INDEX_op_add2_i32: - return &add2; + return C_O2_I4(r, r, r, r, rI, rZM); case INDEX_op_sub2_i64: case INDEX_op_sub2_i32: - return &sub2; + return C_O2_I4(r, r, rI, rZM, r, r); case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? &r_L : &r_L_L); + ? C_O1_I1(r, L) + : C_O1_I2(r, L, L)); + case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? &S_S : &S_S_S); + ? C_O0_I2(S, S) + : C_O0_I3(S, S, S)); + case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L); + return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS == 32 ? C_O2_I1(L, L, L) + : C_O2_I2(L, L, L, L)); + case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS == 64 ? &S_S - : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S); + return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(S, S) + : TARGET_LONG_BITS == 32 ? C_O0_I3(S, S, S) + : C_O0_I4(S, S, S, S)); case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -3631,22 +3601,28 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ppc_mulou_vec: case INDEX_op_ppc_pkum_vec: case INDEX_op_dup2_vec: - return &v_v_v; + return C_O1_I2(v, v, v); + case INDEX_op_not_vec: case INDEX_op_neg_vec: - return &v_v; + return C_O1_I1(v, v); + case INDEX_op_dup_vec: - return have_isa_3_00 ? &v_vr : &v_v; + return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v); + case INDEX_op_ld_vec: - case INDEX_op_st_vec: case INDEX_op_dupm_vec: - return &v_r; + return C_O1_I1(v, r); + + case INDEX_op_st_vec: + return C_O0_I2(v, r); + case INDEX_op_bitsel_vec: case INDEX_op_ppc_msum_vec: - return &v_v_v_v; + return C_O1_I3(v, v, v, v); default: - return NULL; + g_assert_not_reached(); } } From patchwork Wed Dec 23 06:02:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419608 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=jncAwTjJ; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D135t309kz9sVm for ; Wed, 23 Dec 2020 17:22:26 +1100 (AEDT) Received: from localhost ([::1]:36654 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxXU-0001QS-Au for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:22:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39546) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEU-00006C-VB for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:47 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:55878) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxED-0000Qw-RV for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:46 -0500 Received: by mail-pj1-x102d.google.com with SMTP id lb18so2473933pjb.5 for ; Tue, 22 Dec 2020 22:02:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0q5ANbZEj0KFtnrT7+j+pQ6Kp2i0ZGMJCtKydc5+1vo=; b=jncAwTjJUX9ZtO9H9CkUrKTXSR4MqhRFb1K9irwUKWw6lu3yyuLjpNA6u9dgit78VQ Vl1yHzVqQVPLd6sdPby8zdnbA9R9GUmLFmxVFXGwLrIe1SVmjExq3SNtEnDzV8GwTTK5 D/1i41hQH9QA8HgthaSfnQVCCiVlh0giqdsiEcm1ClHHLvBSSuwaeBdi9Tv7Rg29Bify f0cNqQJfYGa7oX60TP7VCqZGmKYmjNahtjIJjPohfeeQTLnq0LbZMKYI5xHnzsMgkbIh diNMY/nuQqvzBe7Nbk5cEPivdE/6P8icYq6HODCZM0zwGbGVWCOi4rYz16EAAs57uhhE aLiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0q5ANbZEj0KFtnrT7+j+pQ6Kp2i0ZGMJCtKydc5+1vo=; b=kR/JVii2GKkCLDXmHsulpc/Dvd8qcq1BDLczwJrlhHlIhYXmcCznhg+Ow8OcWV05Yp 9RhBwmIqRqCa6GBzFumn8RiLXZLLJn7yo/RfUA7W+7zd66IgJvsnQQiGVn+LpTmlzEMk 4GtQxYp5h67D1hrqWPctbdxTJQSALCMIwM3ClkptEZVCm5iWthVwFdsi0WpDnNzNA+O9 xBko2ZVzIhuOdV0G4hTIE9VzJ9dTs+xAn9cvzITbwDFuEhanGx+ZQiov7jrJLeAStN2p LFQRPpkOIS97uZM7JkungAG8j2WIZOAI7ZaeEzxHuFF4lR9/RUiFc/thBHg+G46U/Ka9 1LdQ== X-Gm-Message-State: AOAM530rUKjYI+0X0EiBj7TY3L/YMJmkaVzwM9K+iOlOR6dwsRfz+9gp 6avbsfHGT4sIKBMHQnOApFJAbvgTr3GOfw== X-Google-Smtp-Source: ABdhPJwHmlMrl1nObblAeW59+YxWxmhQHDlX+wrhM2/mx+ZvnTDx/NvH4386VPI5LX741/M07jOeVw== X-Received: by 2002:a17:90b:217:: with SMTP id fy23mr25324210pjb.199.1608703348016; Tue, 22 Dec 2020 22:02:28 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 18/22] tcg/riscv: Convert to tcg-target-conset.h Date: Tue, 22 Dec 2020 22:02:00 -0800 Message-Id: <20201223060204.576856-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- tcg/riscv/tcg-target-conset.h | 25 +++++++++++ tcg/riscv/tcg-target.h | 1 + tcg/riscv/tcg-target.c.inc | 83 ++++++++++------------------------- 3 files changed, 49 insertions(+), 60 deletions(-) create mode 100644 tcg/riscv/tcg-target-conset.h diff --git a/tcg/riscv/tcg-target-conset.h b/tcg/riscv/tcg-target-conset.h new file mode 100644 index 0000000000..116dd75db2 --- /dev/null +++ b/tcg/riscv/tcg-target-conset.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ +/* + * RISC-V target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(LZ, L) +C_O0_I2(rZ, r) +C_O0_I2(rZ, rZ) +C_O0_I3(LZ, L, L) +C_O0_I3(LZ, LZ, L) +C_O0_I4(LZ, LZ, L, L) +C_O0_I4(rZ, rZ, rZ, rZ) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, L, L) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, rZ, rN) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, rZ, rZ, rZ, rZ) +C_O2_I1(r, r, L) +C_O2_I2(r, r, L, L) +C_O2_I4(r, r, rZ, rZ, rM, rM) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 032439d806..a357962e01 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -175,5 +175,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS #define TCG_TARGET_HAS_MEMORY_BSWAP 0 +#define TCG_TARGET_CONSET_H #endif diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 33047c1951..d222692704 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1571,50 +1571,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } } -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r - = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r - = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef rZ_r - = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef rZ_rZ - = { .args_ct_str = { "rZ", "rZ" } }; - static const TCGTargetOpDef rZ_rZ_rZ_rZ - = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_ri - = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI - = { .args_ct_str = { "r", "r", "rI" } }; - static const TCGTargetOpDef r_rZ_rN - = { .args_ct_str = { "r", "rZ", "rN" } }; - static const TCGTargetOpDef r_rZ_rZ - = { .args_ct_str = { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef r_rZ_rZ_rZ_rZ - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef r_L - = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef r_r_L - = { .args_ct_str = { "r", "r", "L" } }; - static const TCGTargetOpDef r_L_L - = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_L_L - = { .args_ct_str = { "r", "r", "L", "L" } }; - static const TCGTargetOpDef LZ_L - = { .args_ct_str = { "LZ", "L" } }; - static const TCGTargetOpDef LZ_L_L - = { .args_ct_str = { "LZ", "L", "L" } }; - static const TCGTargetOpDef LZ_LZ_L - = { .args_ct_str = { "LZ", "LZ", "L" } }; - static const TCGTargetOpDef LZ_LZ_L_L - = { .args_ct_str = { "LZ", "LZ", "L", "L" } }; - static const TCGTargetOpDef r_r_rZ_rZ_rM_rM - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -1646,7 +1607,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: case INDEX_op_ext_i32_i64: - return &r_r; + return C_O1_I1(r, r); case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -1655,7 +1616,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); case INDEX_op_add_i32: case INDEX_op_and_i32: @@ -1665,11 +1626,11 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_and_i64: case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return &r_rZ_rN; + return C_O1_I2(r, rZ, rN); case INDEX_op_mul_i32: case INDEX_op_mulsh_i32: @@ -1687,7 +1648,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_rem_i64: case INDEX_op_remu_i64: case INDEX_op_setcond_i64: - return &r_rZ_rZ; + return C_O1_I2(r, rZ, rZ); case INDEX_op_shl_i32: case INDEX_op_shr_i32: @@ -1695,39 +1656,41 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_shl_i64: case INDEX_op_shr_i64: case INDEX_op_sar_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &rZ_rZ; + return C_O0_I2(rZ, rZ); case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - return &r_r_rZ_rZ_rM_rM; + return C_O2_I4(r, r, rZ, rZ, rM, rM); case INDEX_op_brcond2_i32: - return &rZ_rZ_rZ_rZ; + return C_O0_I4(rZ, rZ, rZ, rZ); case INDEX_op_setcond2_i32: - return &r_rZ_rZ_rZ_rZ; + return C_O1_I4(r, rZ, rZ, rZ, rZ); case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L; + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L)); case INDEX_op_qemu_ld_i64: - return TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L; + return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L) + : C_O2_I2(r, r, L, L)); case INDEX_op_qemu_st_i64: - return TCG_TARGET_REG_BITS == 64 ? &LZ_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L - : &LZ_LZ_L_L; + return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L) + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L) + : C_O0_I4(LZ, LZ, L, L)); default: - return NULL; + g_assert_not_reached(); } } From patchwork Wed Dec 23 06:02:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419595 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=s3lOdW4M; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D12qc1kZkz9sVm for ; Wed, 23 Dec 2020 17:10:04 +1100 (AEDT) Received: from localhost ([::1]:38996 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxLW-0007Ae-5D for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:10:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39494) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEM-0008TF-5l for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:39 -0500 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:39428) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxEF-0000R7-Op for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:37 -0500 Received: by mail-pg1-x533.google.com with SMTP id f17so9926630pge.6 for ; Tue, 22 Dec 2020 22:02:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=D1cssy5nr73dcyGZN4wFfC1KpMYyeCV3YiIqsmzd9bY=; b=s3lOdW4Ms3Cy6CryoiMNjNLMe57uoy1GUhbXHhQHbCmikV7k7+ngbOCDF65huOHTJu AEBgUW44HOs7wJR97ddONpig5+TnwDirnCbe9tL1uiuTDWAS2iNY5+hdTW/b3W2xyxzc KrPzD/AGXNVI3tZLjkMS+8UQ2mcisUSP6ML+8HNObUQB/fBPr70hNq85eTwSGnE7Z2Ji AY5aRaufZpKNcLbVj5DMieCqmcpSO7cWsM2naz0VGOVDzYi7Luxz0PY5XpKQZRK30Whs /UPgUu0ZSvY6Hs1oBkAcaNRdYbh4/ysM0aoQnUp4dvAJPmGq0XGYnyY9lm1/EGbHuXzP ew4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D1cssy5nr73dcyGZN4wFfC1KpMYyeCV3YiIqsmzd9bY=; b=pdAiO6C743TQe2UvqmtBHI12Jthmpjpqo9TEPYf3gU2hGiICeuEtTZIwIX/P1x7+eD IylW6SpcZk/5eN+UmbQtOCT87mp2P17sSXzPKFhQQjcl6/flh3fiCXuQa0PjLaZ03/t0 073fHlHjB3xMtSnimMZFTu30zSgK/hPIm7eVFplxK8zOgww86xXVG7tR1+3MEsSF6jyL BWPmPRxs6VJeir086gCCB6gqkbtE4bpZWGHR2kZjkNN36fqNeMlgiWEkCgp9fSX5rp9G yghXe61YqZvSIc5S6sa05QmTifDKdNwcNGQsS8PhfZQlKJgOGk6/7nybxfVxEvX0GI71 t5cA== X-Gm-Message-State: AOAM532gH/+bPb7j/JbajhDbQO+SUJvB4HC3fD3GQW+k/kzO6w5k0vJR /dEVfLZPbzquKIXvgs2zXIbpVayFvFA+bg== X-Google-Smtp-Source: ABdhPJzl+MJZBtU1wSVYmRVofl8koGATRJfplO7r2ZkZGWg+qgkJOxVv1ki7w56W8/2Y1qieW+42Nw== X-Received: by 2002:a65:4bc2:: with SMTP id p2mr15657425pgr.169.1608703349280; Tue, 22 Dec 2020 22:02:29 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 19/22] tcg/s390: Convert to tcg-target-conset.h Date: Tue, 22 Dec 2020 22:02:01 -0800 Message-Id: <20201223060204.576856-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target-conset.h | 24 +++++++ tcg/s390/tcg-target.h | 1 + tcg/s390/tcg-target.c.inc | 121 +++++++++++++++-------------------- 3 files changed, 76 insertions(+), 70 deletions(-) create mode 100644 tcg/s390/tcg-target-conset.h diff --git a/tcg/s390/tcg-target-conset.h b/tcg/s390/tcg-target-conset.h new file mode 100644 index 0000000000..e68baabbfd --- /dev/null +++ b/tcg/s390/tcg-target-conset.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: MIT */ +/* + * S390 target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(L, L) +C_O0_I2(r, r) +C_O0_I2(r, ri) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, 0, ri) +C_O1_I2(r, 0, rI) +C_O1_I2(r, 0, rJ) +C_O1_I2(r, r, ri) +C_O1_I2(r, rZ, r) +C_O1_I4(r, r, ri, r, 0) +C_O1_I4(r, r, ri, rI, 0) +C_O2_I2(b, a, 0, r) +C_O2_I3(b, a, 0, 1, r) +C_O2_I4(r, r, 0, 1, rA, r) +C_O2_I4(r, r, 0, 1, ri, r) +C_O2_I4(r, r, 0, 1, r, r) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 63c8797bd3..78277a8d07 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -162,5 +162,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSET_H #endif diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index d00d78f0b9..410f63104f 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -2274,27 +2274,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } } -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; - static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } }; - static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } }; - static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } }; - static const TCGTargetOpDef a2_r - = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } }; - static const TCGTargetOpDef a2_ri - = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } }; - static const TCGTargetOpDef a2_rA - = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: @@ -2308,6 +2292,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: + return C_O1_I1(r, r); + case INDEX_op_st8_i32: case INDEX_op_st8_i64: case INDEX_op_st16_i32: @@ -2315,11 +2301,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_st_i32: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &r_r; + return C_O0_I2(r, r); case INDEX_op_add_i32: case INDEX_op_add_i64: - return &r_r_ri; + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + case INDEX_op_clz_i64: + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + return C_O1_I2(r, r, ri); + case INDEX_op_sub_i32: case INDEX_op_sub_i64: case INDEX_op_and_i32: @@ -2328,35 +2325,33 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: - return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); + return (s390_facilities & FACILITY_DISTINCT_OPS + ? C_O1_I2(r, r, ri) + : C_O1_I2(r, 0, ri)); case INDEX_op_mul_i32: /* If we have the general-instruction-extensions, then we have MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ - return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI); + return (s390_facilities & FACILITY_GEN_INST_EXT + ? C_O1_I2(r, 0, ri) + : C_O1_I2(r, 0, rI)); + case INDEX_op_mul_i64: - return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI); + return (s390_facilities & FACILITY_GEN_INST_EXT + ? C_O1_I2(r, 0, rJ) + : C_O1_I2(r, 0, rI)); case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: - return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); - - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - return &r_r_ri; - - case INDEX_op_rotl_i32: - case INDEX_op_rotl_i64: - case INDEX_op_rotr_i32: - case INDEX_op_rotr_i64: - return &r_r_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS + ? C_O1_I2(r, r, ri) + : C_O1_I2(r, 0, ri)); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_ri; + return C_O0_I2(r, ri); case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -2379,63 +2374,49 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_extu_i32_i64: case INDEX_op_extract_i32: case INDEX_op_extract_i64: - return &r_r; - - case INDEX_op_clz_i64: - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - return &r_r_ri; + return C_O1_I1(r, r); case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return &r_L; + return C_O1_I1(r, L); case INDEX_op_qemu_st_i64: case INDEX_op_qemu_st_i32: - return &L_L; + return C_O0_I2(L, L); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - { - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "rZ", "r" } }; - return &dep; - } + return C_O1_I2(r, rZ, r); + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - { - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "ri", "r", "0" } }; - static const TCGTargetOpDef movc_l - = { .args_ct_str = { "r", "r", "ri", "rI", "0" } }; - return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc); - } + return (s390_facilities & FACILITY_LOAD_ON_COND2 + ? C_O1_I4(r, r, ri, rI, 0) + : C_O1_I4(r, r, ri, r, 0)); + case INDEX_op_div2_i32: case INDEX_op_div2_i64: case INDEX_op_divu2_i32: case INDEX_op_divu2_i64: - { - static const TCGTargetOpDef div2 - = { .args_ct_str = { "b", "a", "0", "1", "r" } }; - return &div2; - } + return C_O2_I3(b, a, 0, 1, r); + case INDEX_op_mulu2_i64: - { - static const TCGTargetOpDef mul2 - = { .args_ct_str = { "b", "a", "0", "r" } }; - return &mul2; - } + return C_O2_I2(b, a, 0, r); case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r); + return (s390_facilities & FACILITY_EXT_IMM + ? C_O2_I4(r, r, 0, 1, ri, r) + : C_O2_I4(r, r, 0, 1, r, r)); + case INDEX_op_add2_i64: case INDEX_op_sub2_i64: - return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r); + return (s390_facilities & FACILITY_EXT_IMM + ? C_O2_I4(r, r, 0, 1, rA, r) + : C_O2_I4(r, r, 0, 1, r, r)); default: - break; + g_assert_not_reached(); } - return NULL; } static void query_s390_facilities(void) From patchwork Wed Dec 23 06:02:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419606 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=RS82DjbK; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D130q6Rk3z9sVn for ; Wed, 23 Dec 2020 17:18:03 +1100 (AEDT) Received: from localhost ([::1]:56264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxTF-00063G-L4 for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:18:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39548) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEW-00006U-Em for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:48 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:36705) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxEG-0000RC-Dt for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:48 -0500 Received: by mail-pj1-x102d.google.com with SMTP id l23so2621728pjg.1 for ; Tue, 22 Dec 2020 22:02:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=i8gt3VnD/hjlZ07ZVemULHRXuFsYp1d7hadsdqF1IbM=; b=RS82DjbK7TVVEyHjugFCFWvTniKIn1MhdsZILVAmH2z9Nb/AMcolVL46EOUzXMRz1U SnKYvgyENFS4sO+xOcA4qgAb5S2ST5pHndnz3QWapXMVkcMDioI6tGuedSQ0UfrAYU0X fBZhrnaggiRrf1PstlNPH3rL4h8t44ZIe36WtQxBFU3GEpkkUxwATIlnN81rHimrQ4p7 DfFYG5OLxI1fNHuczoumF+1TFjJDqEF/oNoZfqO7V+4cyBDRmeu5mmRPtk02sZgwOfwy izOd+MowQqprohLOilbUZtTk4OUhkuqyC955S0q3pxC4WBYpzFh/95eEu4bEE1+jNiIi uoCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i8gt3VnD/hjlZ07ZVemULHRXuFsYp1d7hadsdqF1IbM=; b=PNB2CRbkAhrb2pMxXAwjIPk8ZtvmmuUq5LQIpyo9H0gkzFTQ5aVjUzN3uRQ3aXBP+h EZPKfB5CkYqujzgnp8/xSYc2ZDRRIq9MrjNrac8CLBuF3hqJ5912fOls1+EU7C63H3xx v8sBz1YkBa+aoMKBKkop+2iB/eR9oxuTlJenuD9ZxmO9cXM5grh91E8x5YcUOYMFRPEI U5iUpOfWcBglC8UsBKEnEiOD11bBhfnLUptXWqx5AQL0m+Co8QY8Nu8cFMSShGzDruHH brsiF4cV39ui4BNjPLFwygguhdIrO0qffldB5/lKK67buFvrtxl9ht6+GCSrR/o5W771 aMzg== X-Gm-Message-State: AOAM530C3jKb+slR5MEfG73Pf0zhB0NygM//S+JK8tgh7/7QBSTfLwQr hJWE9zoQ3GI9EeIZ6qqGQZre+Z7BFE+l9g== X-Google-Smtp-Source: ABdhPJwxMzbvuVSuYDA1UYLLTceT7BpOWzZ5oJKUDZpBlXF5oBdlXcGPSNsWSKfizCXSRcSTj5r64Q== X-Received: by 2002:a17:90a:6f01:: with SMTP id d1mr23902111pjk.155.1608703350486; Tue, 22 Dec 2020 22:02:30 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 20/22] tcg/sparc: Convert to tcg-target-conset.h Date: Tue, 22 Dec 2020 22:02:02 -0800 Message-Id: <20201223060204.576856-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target-conset.h | 27 +++++++++++++ tcg/sparc/tcg-target.h | 1 + tcg/sparc/tcg-target.c.inc | 75 +++++++++++------------------------ 3 files changed, 51 insertions(+), 52 deletions(-) create mode 100644 tcg/sparc/tcg-target-conset.h diff --git a/tcg/sparc/tcg-target-conset.h b/tcg/sparc/tcg-target-conset.h new file mode 100644 index 0000000000..fe7324af9a --- /dev/null +++ b/tcg/sparc/tcg-target-conset.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Sparc target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(rZ, r) +C_O0_I2(RZ, r) +C_O0_I2(rZ, rJ) +C_O0_I2(RZ, RJ) +C_O0_I2(sZ, A) +C_O0_I2(SZ, A) +C_O1_I1(r, A) +C_O1_I1(R, A) +C_O1_I1(r, r) +C_O1_I1(r, R) +C_O1_I1(R, r) +C_O1_I1(R, R) +C_O1_I2(R, R, R) +C_O1_I2(r, rZ, rJ) +C_O1_I2(R, RZ, RJ) +C_O1_I4(r, rZ, rJ, rI, 0) +C_O1_I4(R, RZ, RJ, RI, 0) +C_O2_I2(r, r, rZ, rJ) +C_O2_I4(R, R, RZ, RZ, RJ, RI) +C_O2_I4(r, r, rZ, rZ, rJ, rJ) diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 633841ebf2..1304c225b1 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -179,5 +179,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CONSET_H #endif diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index c92742aaec..c225bdd7bd 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1555,40 +1555,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } } -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef R_r = { .args_ct_str = { "R", "r" } }; - static const TCGTargetOpDef r_R = { .args_ct_str = { "r", "R" } }; - static const TCGTargetOpDef R_R = { .args_ct_str = { "R", "R" } }; - static const TCGTargetOpDef r_A = { .args_ct_str = { "r", "A" } }; - static const TCGTargetOpDef R_A = { .args_ct_str = { "R", "A" } }; - static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef RZ_r = { .args_ct_str = { "RZ", "r" } }; - static const TCGTargetOpDef sZ_A = { .args_ct_str = { "sZ", "A" } }; - static const TCGTargetOpDef SZ_A = { .args_ct_str = { "SZ", "A" } }; - static const TCGTargetOpDef rZ_rJ = { .args_ct_str = { "rZ", "rJ" } }; - static const TCGTargetOpDef RZ_RJ = { .args_ct_str = { "RZ", "RJ" } }; - static const TCGTargetOpDef R_R_R = { .args_ct_str = { "R", "R", "R" } }; - static const TCGTargetOpDef r_rZ_rJ - = { .args_ct_str = { "r", "rZ", "rJ" } }; - static const TCGTargetOpDef R_RZ_RJ - = { .args_ct_str = { "R", "RZ", "RJ" } }; - static const TCGTargetOpDef r_r_rZ_rJ - = { .args_ct_str = { "r", "r", "rZ", "rJ" } }; - static const TCGTargetOpDef movc_32 - = { .args_ct_str = { "r", "rZ", "rJ", "rI", "0" } }; - static const TCGTargetOpDef movc_64 - = { .args_ct_str = { "R", "RZ", "RJ", "RI", "0" } }; - static const TCGTargetOpDef add2_32 - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rJ", "rJ" } }; - static const TCGTargetOpDef add2_64 - = { .args_ct_str = { "R", "R", "RZ", "RZ", "RJ", "RI" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -1597,12 +1568,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ld_i32: case INDEX_op_neg_i32: case INDEX_op_not_i32: - return &r_r; + return C_O1_I1(r, r); case INDEX_op_st8_i32: case INDEX_op_st16_i32: case INDEX_op_st_i32: - return &rZ_r; + return C_O0_I2(rZ, r); case INDEX_op_add_i32: case INDEX_op_mul_i32: @@ -1618,18 +1589,18 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_shr_i32: case INDEX_op_sar_i32: case INDEX_op_setcond_i32: - return &r_rZ_rJ; + return C_O1_I2(r, rZ, rJ); case INDEX_op_brcond_i32: - return &rZ_rJ; + return C_O0_I2(rZ, rJ); case INDEX_op_movcond_i32: - return &movc_32; + return C_O1_I4(r, rZ, rJ, rI, 0); case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return &add2_32; + return C_O2_I4(r, r, rZ, rZ, rJ, rJ); case INDEX_op_mulu2_i32: case INDEX_op_muls2_i32: - return &r_r_rZ_rJ; + return C_O2_I2(r, r, rZ, rJ); case INDEX_op_ld8u_i64: case INDEX_op_ld8s_i64: @@ -1640,13 +1611,13 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ld_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: - return &R_r; + return C_O1_I1(R, r); case INDEX_op_st8_i64: case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &RZ_r; + return C_O0_I2(RZ, r); case INDEX_op_add_i64: case INDEX_op_mul_i64: @@ -1662,39 +1633,39 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_shr_i64: case INDEX_op_sar_i64: case INDEX_op_setcond_i64: - return &R_RZ_RJ; + return C_O1_I2(R, RZ, RJ); case INDEX_op_neg_i64: case INDEX_op_not_i64: case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: - return &R_R; + return C_O1_I1(R, R); case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: - return &r_R; + return C_O1_I1(r, R); case INDEX_op_brcond_i64: - return &RZ_RJ; + return C_O0_I2(RZ, RJ); case INDEX_op_movcond_i64: - return &movc_64; + return C_O1_I4(R, RZ, RJ, RI, 0); case INDEX_op_add2_i64: case INDEX_op_sub2_i64: - return &add2_64; + return C_O2_I4(R, R, RZ, RZ, RJ, RI); case INDEX_op_muluh_i64: - return &R_R_R; + return C_O1_I2(R, R, R); case INDEX_op_qemu_ld_i32: - return &r_A; + return C_O1_I1(r, A); case INDEX_op_qemu_ld_i64: - return &R_A; + return C_O1_I1(R, A); case INDEX_op_qemu_st_i32: - return &sZ_A; + return C_O0_I2(sZ, A); case INDEX_op_qemu_st_i64: - return &SZ_A; + return C_O0_I2(SZ, A); default: - return NULL; + g_assert_not_reached(); } } From patchwork Wed Dec 23 06:02:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419602 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=hzl6wnpe; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D12w11M18z9sVn for ; Wed, 23 Dec 2020 17:13:53 +1100 (AEDT) Received: from localhost ([::1]:47588 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxPC-0002Ns-Cv for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:13:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39528) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxEQ-0008Up-VG for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:42 -0500 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:33716) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxEI-0000RO-Sj for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:42 -0500 Received: by mail-pf1-x42d.google.com with SMTP id h186so9795952pfe.0 for ; Tue, 22 Dec 2020 22:02:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LM+ixEH8S5xhbIyjTdMFVRGEOmMUxSrxvI2DWExWedA=; b=hzl6wnpeD1h72Bx5n0AVg00ZMZoSY/hiK6KnZGC9AMUk1v66ckEOnxY9lVWgPT4lJT 2ViqDKRZNsL0RdWQ5xRZpYnjemKqchP84zuMaYRn56EaP43VPz1cHxpJ6Tu6p5gS5mzN ysIR5l5AKC4pEljeipPnqxxwzzNdaVFoChy//HS/hDQfrBTNW+y75VqO5IVXrS+ycs5U csmP5yuK+d+X1q6QinO/A3EjvujIZCyoXAKWgphiksGx24cDiI8LOTetZs2QxdjPM5Ed bGCNd3sQDJZ/+SeV1JFmmn708IoJMszS74wWiTdXnwRwMZjng9JsMLCBebLhTIvFSq9Z 4ljA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LM+ixEH8S5xhbIyjTdMFVRGEOmMUxSrxvI2DWExWedA=; b=IggJHKfpwptbaZjGvYRonkua/a9y9ECOjxHxqasjE8Wm0Wms8aEpi2H3fNjlbJKO+J IU6CTFq/lbGH9+5zn3cuDBv9hXL5BVR7KToTymx8Ukoj4vR/3mdSnpUACtSotKwdTNR8 dOWoK5XUEQLX5PEsO58yKPE1FeDVi94e+NfgNgqtlf7V2CHKacPzArOnArqfS3benQry k9hQNyJa1/rdATKgT9+xiYH9JZkwjpreoohq00XaDA13herGBYeSkgtr5dI9obPj4Bn9 opSe/wTA8Rc6s0XZlBnS/1j0oOZ699CkWOipPCb/KS/CpzV3Z5IzmCpKocaefWZH8eqi bqxg== X-Gm-Message-State: AOAM53369zgdZbospkgZQ41+EDnNiZ1ZvTk6hcM12x7aKYvUlxA/vB42 O9phD9xuEKyZ4YCh1LZx5SQ94lbTYI/iFA== X-Google-Smtp-Source: ABdhPJyFxTmqKMU7/wCeI0+hNBB+3nEbhMBSIA7oS0JkBglQZ6HrrR9RUp+HgOlY1ss1VCe/Pc+Bow== X-Received: by 2002:a62:8f0e:0:b029:1aa:1268:fa4e with SMTP id n14-20020a628f0e0000b02901aa1268fa4emr22738274pfd.18.1608703351723; Tue, 22 Dec 2020 22:02:31 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 21/22] tcg/tci: Convert to tcg-target-conset.h Date: Tue, 22 Dec 2020 22:02:03 -0800 Message-Id: <20201223060204.576856-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This does require finishing the conversion to tcg_target_op_def. Remove quite a lot of ifdefs, since we can reference opcodes even if they are not implemented. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-conset.h | 20 +++ tcg/tci/tcg-target.h | 2 + tcg/tci/tcg-target.c.inc | 343 +++++++++++++----------------------- 3 files changed, 147 insertions(+), 218 deletions(-) create mode 100644 tcg/tci/tcg-target-conset.h diff --git a/tcg/tci/tcg-target-conset.h b/tcg/tci/tcg-target-conset.h new file mode 100644 index 0000000000..efcefab37e --- /dev/null +++ b/tcg/tci/tcg-target-conset.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: MIT */ +/* + * TCI target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I2(r, r) +C_O0_I2(r, ri) +C_O0_I3(r, r, r) +C_O0_I4(r, r, ri, ri) +C_O0_I4(r, r, r, r) +C_O1_I1(r, r) +C_O1_I2(r, 0, r) +C_O1_I2(r, ri, ri) +C_O1_I2(r, r, r) +C_O1_I2(r, r, ri) +C_O1_I4(r, r, r, ri, ri) +C_O2_I1(r, r, r) +C_O2_I2(r, r, r, r) +C_O2_I4(r, r, r, r, r, r) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 8c1c1d265d..42b84a0e87 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -210,4 +210,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, /* no need to flush icache explicitly */ } +#define TCG_TARGET_CONSET_H + #endif /* TCG_TARGET_H */ diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 9ac6da2e21..f9fb6cb399 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -37,236 +37,143 @@ /* Bitfield n...m (in 32 bit value). */ #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) -/* Macros used in tcg_target_op_defs. */ -#define R "r" -#define RI "ri" -#if TCG_TARGET_REG_BITS == 32 -# define R64 "r", "r" -#else -# define R64 "r" -#endif -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS -# define L "r", "r" -# define S "r", "r" -#else -# define L "r" -# define S "r" -#endif +static int tcg_target_op_def(TCGOpcode op) +{ + switch (op) { + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_not_i32: + case INDEX_op_not_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + return C_O1_I1(r, r); -/* TODO: documentation. */ -static const TCGTargetOpDef tcg_target_op_defs[] = { - { INDEX_op_exit_tb, { NULL } }, - { INDEX_op_goto_tb, { NULL } }, - { INDEX_op_br, { NULL } }, + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return C_O0_I2(r, r); - { INDEX_op_ld8u_i32, { R, R } }, - { INDEX_op_ld8s_i32, { R, R } }, - { INDEX_op_ld16u_i32, { R, R } }, - { INDEX_op_ld16s_i32, { R, R } }, - { INDEX_op_ld_i32, { R, R } }, - { INDEX_op_st8_i32, { R, R } }, - { INDEX_op_st16_i32, { R, R } }, - { INDEX_op_st_i32, { R, R } }, + case INDEX_op_div_i32: + case INDEX_op_div_i64: + case INDEX_op_divu_i32: + case INDEX_op_divu_i64: + case INDEX_op_rem_i32: + case INDEX_op_rem_i64: + case INDEX_op_remu_i32: + case INDEX_op_remu_i64: + return C_O1_I2(r, r, r); - { INDEX_op_add_i32, { R, RI, RI } }, - { INDEX_op_sub_i32, { R, RI, RI } }, - { INDEX_op_mul_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_div_i32 - { INDEX_op_div_i32, { R, R, R } }, - { INDEX_op_divu_i32, { R, R, R } }, - { INDEX_op_rem_i32, { R, R, R } }, - { INDEX_op_remu_i32, { R, R, R } }, -#elif TCG_TARGET_HAS_div2_i32 - { INDEX_op_div2_i32, { R, R, "0", "1", R } }, - { INDEX_op_divu2_i32, { R, R, "0", "1", R } }, -#endif - /* TODO: Does R, RI, RI result in faster code than R, R, RI? - If both operands are constants, we can optimize. */ - { INDEX_op_and_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_andc_i32 - { INDEX_op_andc_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_eqv_i32 - { INDEX_op_eqv_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nand_i32 - { INDEX_op_nand_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nor_i32 - { INDEX_op_nor_i32, { R, RI, RI } }, -#endif - { INDEX_op_or_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_orc_i32 - { INDEX_op_orc_i32, { R, RI, RI } }, -#endif - { INDEX_op_xor_i32, { R, RI, RI } }, - { INDEX_op_shl_i32, { R, RI, RI } }, - { INDEX_op_shr_i32, { R, RI, RI } }, - { INDEX_op_sar_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_rot_i32 - { INDEX_op_rotl_i32, { R, RI, RI } }, - { INDEX_op_rotr_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_deposit_i32 - { INDEX_op_deposit_i32, { R, "0", R } }, -#endif + case INDEX_op_add_i32: + case INDEX_op_add_i64: + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + case INDEX_op_and_i32: + case INDEX_op_and_i64: + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + case INDEX_op_eqv_i32: + case INDEX_op_eqv_i64: + case INDEX_op_nand_i32: + case INDEX_op_nand_i64: + case INDEX_op_nor_i32: + case INDEX_op_nor_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + case INDEX_op_shl_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i32: + case INDEX_op_shr_i64: + case INDEX_op_sar_i32: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + /* TODO: Does R, RI, RI result in faster code than R, R, RI? */ + return C_O1_I2(r, ri, ri); - { INDEX_op_brcond_i32, { R, RI } }, + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + return C_O1_I2(r, 0, r); - { INDEX_op_setcond_i32, { R, R, RI } }, -#if TCG_TARGET_REG_BITS == 64 - { INDEX_op_setcond_i64, { R, R, RI } }, -#endif /* TCG_TARGET_REG_BITS == 64 */ + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return C_O0_I2(r, ri); + + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + return C_O1_I2(r, r, ri); #if TCG_TARGET_REG_BITS == 32 /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ - { INDEX_op_add2_i32, { R, R, R, R, R, R } }, - { INDEX_op_sub2_i32, { R, R, R, R, R, R } }, - { INDEX_op_brcond2_i32, { R, R, RI, RI } }, - { INDEX_op_mulu2_i32, { R, R, R, R } }, - { INDEX_op_setcond2_i32, { R, R, R, RI, RI } }, + case INDEX_op_add2_i32: + case INDEX_op_sub2_i32: + return C_O2_I4(r, r, r, r, r, r); + case INDEX_op_brcond2_i32: + return C_O0_I4(r, r, ri, ri); + case INDEX_op_mulu2_i32: + return C_O2_I2(r, r, r, r); + case INDEX_op_setcond2_i32 + return C_O1_I4(r, r, r, ri, ri); #endif -#if TCG_TARGET_HAS_not_i32 - { INDEX_op_not_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_neg_i32 - { INDEX_op_neg_i32, { R, R } }, -#endif + case INDEX_op_qemu_ld_i32: + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + ? C_O1_I1(r, r) + : C_O1_I2(r, r, r)); + case INDEX_op_qemu_ld_i64: + return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, r) + : C_O2_I2(r, r, r, r)); + case INDEX_op_qemu_st_i32: + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + ? C_O0_I2(r, r) + : C_O0_I3(r, r, r)); + case INDEX_op_qemu_st_i64: + return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(r, r, r) + : C_O0_I4(r, r, r, r)); -#if TCG_TARGET_REG_BITS == 64 - { INDEX_op_ld8u_i64, { R, R } }, - { INDEX_op_ld8s_i64, { R, R } }, - { INDEX_op_ld16u_i64, { R, R } }, - { INDEX_op_ld16s_i64, { R, R } }, - { INDEX_op_ld32u_i64, { R, R } }, - { INDEX_op_ld32s_i64, { R, R } }, - { INDEX_op_ld_i64, { R, R } }, - - { INDEX_op_st8_i64, { R, R } }, - { INDEX_op_st16_i64, { R, R } }, - { INDEX_op_st32_i64, { R, R } }, - { INDEX_op_st_i64, { R, R } }, - - { INDEX_op_add_i64, { R, RI, RI } }, - { INDEX_op_sub_i64, { R, RI, RI } }, - { INDEX_op_mul_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_div_i64 - { INDEX_op_div_i64, { R, R, R } }, - { INDEX_op_divu_i64, { R, R, R } }, - { INDEX_op_rem_i64, { R, R, R } }, - { INDEX_op_remu_i64, { R, R, R } }, -#elif TCG_TARGET_HAS_div2_i64 - { INDEX_op_div2_i64, { R, R, "0", "1", R } }, - { INDEX_op_divu2_i64, { R, R, "0", "1", R } }, -#endif - { INDEX_op_and_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_andc_i64 - { INDEX_op_andc_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_eqv_i64 - { INDEX_op_eqv_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nand_i64 - { INDEX_op_nand_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nor_i64 - { INDEX_op_nor_i64, { R, RI, RI } }, -#endif - { INDEX_op_or_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_orc_i64 - { INDEX_op_orc_i64, { R, RI, RI } }, -#endif - { INDEX_op_xor_i64, { R, RI, RI } }, - { INDEX_op_shl_i64, { R, RI, RI } }, - { INDEX_op_shr_i64, { R, RI, RI } }, - { INDEX_op_sar_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_rot_i64 - { INDEX_op_rotl_i64, { R, RI, RI } }, - { INDEX_op_rotr_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_deposit_i64 - { INDEX_op_deposit_i64, { R, "0", R } }, -#endif - { INDEX_op_brcond_i64, { R, RI } }, - -#if TCG_TARGET_HAS_ext8s_i64 - { INDEX_op_ext8s_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16s_i64 - { INDEX_op_ext16s_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext32s_i64 - { INDEX_op_ext32s_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext8u_i64 - { INDEX_op_ext8u_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16u_i64 - { INDEX_op_ext16u_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext32u_i64 - { INDEX_op_ext32u_i64, { R, R } }, -#endif - { INDEX_op_ext_i32_i64, { R, R } }, - { INDEX_op_extu_i32_i64, { R, R } }, -#if TCG_TARGET_HAS_bswap16_i64 - { INDEX_op_bswap16_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_bswap32_i64 - { INDEX_op_bswap32_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_bswap64_i64 - { INDEX_op_bswap64_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_not_i64 - { INDEX_op_not_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_neg_i64 - { INDEX_op_neg_i64, { R, R } }, -#endif -#endif /* TCG_TARGET_REG_BITS == 64 */ - - { INDEX_op_qemu_ld_i32, { R, L } }, - { INDEX_op_qemu_ld_i64, { R64, L } }, - - { INDEX_op_qemu_st_i32, { R, S } }, - { INDEX_op_qemu_st_i64, { R64, S } }, - -#if TCG_TARGET_HAS_ext8s_i32 - { INDEX_op_ext8s_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16s_i32 - { INDEX_op_ext16s_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext8u_i32 - { INDEX_op_ext8u_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16u_i32 - { INDEX_op_ext16u_i32, { R, R } }, -#endif - -#if TCG_TARGET_HAS_bswap16_i32 - { INDEX_op_bswap16_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_bswap32_i32 - { INDEX_op_bswap32_i32, { R, R } }, -#endif - - { INDEX_op_mb, { } }, - { -1 }, -}; - -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) -{ - int i, n = ARRAY_SIZE(tcg_target_op_defs); - - for (i = 0; i < n; ++i) { - if (tcg_target_op_defs[i].op == op) { - return &tcg_target_op_defs[i]; - } + default: + g_assert_not_reached(); } - return NULL; } static const int tcg_target_reg_alloc_order[] = { From patchwork Wed Dec 23 06:02:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1419615 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=CJ1TSbyS; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D13G10xfFz9sVn for ; Wed, 23 Dec 2020 17:29:29 +1100 (AEDT) Received: from localhost ([::1]:53210 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1krxeJ-0008VG-3W for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2020 01:29:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39536) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1krxER-0008Vg-Gh for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:44 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:46672) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1krxEJ-0000Ra-U4 for qemu-devel@nongnu.org; Wed, 23 Dec 2020 01:02:43 -0500 Received: by mail-pl1-x634.google.com with SMTP id v3so8579979plz.13 for ; Tue, 22 Dec 2020 22:02:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nk60H3yRhOTIra88/cLIs2xseWbxfALm0i3pKXgYJOM=; b=CJ1TSbySDLhtl/YbmGtWQfFNI9ZnElrA0jkVVcP1qZ9CDt6rrXkkB4CtWYDh8jI4b2 JSbzQnGMZMgK3PxOLxzmC04Ywzo5z7/Td+y85iFUGcgNlhebGN0GyLis5hc4VXbWYwho J3uR2/OXtBLNGsmp3lHvUMP4z//5lH1cg+3hxk0c46/ogBDW0H3cSc7Qw8HUg7Jt1HfK 42pOOq87CyvZQ0+EKJ8Nuwek+D3PHiYGxwvUQMJU1YeyttLLw2lML10lFIfyUlracgLX CjNJJjCETimU7BB3wnL9SSIofM33Aqm9XLPlbFd9dWPgVCd7wB+SaEWKY7DCtmG8XoKx UqEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nk60H3yRhOTIra88/cLIs2xseWbxfALm0i3pKXgYJOM=; b=YJdsiPtATwcy9UY1jii4PgphoU3PyacRIKdgnI7NzXdNRGaRzbxMKZ3JHDO/PW/ea6 KFn56gp2W/fIGZjPmpRxMuOT3r56qFgzt4zpL2XkzmfJk9pfv8Wq4xWzYN23pNuvIP72 L8Srp1qm4eJz5Lp9Hl8i1mj7+m0qbIPlMThMVCt72P8hNp2P6w9NofEVbmtPkOxM5KnD yChU3dxr9Kx6uHGkFbqMT0dfAg2jHJjXsEF3BBnYTtoJy1DUCvVM52MTd0wz/CmLTfRx Xgnb+Zrwn02uyCwUIqxkM3QErNuR11dCnlRkEGOCyDwYB7YfA8UT/G11OLLfIZLRx4Ze kA/A== X-Gm-Message-State: AOAM5314/RnjVgZ3lXKQWX1nEMefgaxh/c+fQDRnB1Ft/m3NUwpb/vH8 jZReb/tK+g4QUMg0UqYp/QYRT1b3In2mug== X-Google-Smtp-Source: ABdhPJzk8m1ussJ2yCNVl5DAVV0C2AfGUhfDfUF4aJfB2vM4jX6NzJnWbwU8Hhjuevb4VIMy0KfZPg== X-Received: by 2002:a17:90b:4d0e:: with SMTP id mw14mr25494265pjb.92.1608703352954; Tue, 22 Dec 2020 22:02:32 -0800 (PST) Received: from localhost.localdomain (174-21-139-177.tukw.qwest.net. [174.21.139.177]) by smtp.gmail.com with ESMTPSA id s1sm21943620pfb.103.2020.12.22.22.02.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Dec 2020 22:02:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 22/22] tcg: Remove TCG_TARGET_CONSET_H Date: Tue, 22 Dec 2020 22:02:04 -0800 Message-Id: <20201223060204.576856-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223060204.576856-1-richard.henderson@linaro.org> References: <20201223060204.576856-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" All backends have now been converted to tcg-target-conset.h, so we can remove the fallback code. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- tcg/aarch64/tcg-target.h | 1 - tcg/arm/tcg-target.h | 1 - tcg/i386/tcg-target.h | 1 - tcg/mips/tcg-target.h | 1 - tcg/ppc/tcg-target.h | 1 - tcg/riscv/tcg-target.h | 1 - tcg/s390/tcg-target.h | 1 - tcg/sparc/tcg-target.h | 1 - tcg/tci/tcg-target.h | 2 -- tcg/tcg.c | 13 ------------- 10 files changed, 23 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index a81f6dadf9..663dd0b95e 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -159,6 +159,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSET_H #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 918f09239a..17e771374d 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -146,6 +146,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSET_H #endif diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 74a2566900..abd4ac7fc0 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -235,6 +235,5 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSET_H #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 688d691cda..c6b091d849 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -217,6 +217,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif -#define TCG_TARGET_CONSET_H #endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index c958faffb7..be10363956 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -185,6 +185,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSET_H #endif diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index a357962e01..032439d806 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -175,6 +175,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS #define TCG_TARGET_HAS_MEMORY_BSWAP 0 -#define TCG_TARGET_CONSET_H #endif diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 78277a8d07..63c8797bd3 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -162,6 +162,5 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSET_H #endif diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 1304c225b1..633841ebf2 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -179,6 +179,5 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_CONSET_H #endif diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 42b84a0e87..8c1c1d265d 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -210,6 +210,4 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, /* no need to flush icache explicitly */ } -#define TCG_TARGET_CONSET_H - #endif /* TCG_TARGET_H */ diff --git a/tcg/tcg.c b/tcg/tcg.c index c58d728ca5..dd5b045d88 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -68,11 +68,7 @@ /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ static void tcg_target_init(TCGContext *s); -#ifdef TCG_TARGET_CONSET_H static int tcg_target_op_def(TCGOpcode); -#else -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode); -#endif static void tcg_target_qemu_prologue(TCGContext *s); static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend); @@ -344,7 +340,6 @@ static void set_jmp_reset_offset(TCGContext *s, int which) s->tb_jmp_reset_offset[which] = tcg_current_code_size(s); } -#ifdef TCG_TARGET_CONSET_H #define C_PFX1(P, A) P##A #define C_PFX2(P, A, B) P##A##_##B #define C_PFX3(P, A, B, C) P##A##_##B##_##C @@ -457,8 +452,6 @@ static const TCGTargetOpDef constraint_sets[] = { #define C_O2_I4(O1, O2, I1, I2, I3, I4) \ C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4) -#endif /* TCG_TARGET_CONSET_H */ - #include "tcg-target.c.inc" /* compare a pointer @ptr and a tb_tc @s */ @@ -2367,16 +2360,10 @@ static void process_op_defs(TCGContext *s) continue; } -#ifdef TCG_TARGET_CONSET_H i = tcg_target_op_def(op); /* Missing TCGTargetOpDef entry. */ tcg_debug_assert(i >= 0 && i < ARRAY_SIZE(constraint_sets)); tdefs = &constraint_sets[i]; -#else - tdefs = tcg_target_op_def(op); - /* Missing TCGTargetOpDef entry. */ - tcg_debug_assert(tdefs != NULL); -#endif for (i = 0; i < nb_args; i++) { const char *ct_str = tdefs->args_ct_str[i];