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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id s25sm4023579wrs.49.2020.12.16.08.27.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 08:27:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 01/12] target/mips/mips-defs: Reorder CPU_MIPS5 definition Date: Wed, 16 Dec 2020 17:27:33 +0100 Message-Id: <20201216162744.895920-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216162744.895920-1-f4bug@amsat.org> References: <20201216162744.895920-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Move CPU_MIPS5 after CPU_MIPS4 :) Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/mips-defs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 805034b8956..f4d76e562d1 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -70,13 +70,12 @@ #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) +#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) #define CPU_R5900 (CPU_MIPS3 | INSN_R5900) #define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) -#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) - /* MIPS Technologies "Release 1" */ #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) From patchwork Wed Dec 16 16:27:34 2020 Content-Type: text/plain; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id j13sm3337149wmi.36.2020.12.16.08.27.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 08:27:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 02/12] target/mips/mips-defs: Use ISA_MIPS3 for ISA_MIPS64 Date: Wed, 16 Dec 2020 17:27:34 +0100 Message-Id: <20201216162744.895920-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216162744.895920-1-f4bug@amsat.org> References: <20201216162744.895920-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" MIPS 64-bit ISA is introduced with MIPS3. No need for another bit/definition to check for 64-bit. Suggested-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h | 2 +- hw/mips/boston.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index f4d76e562d1..ab621a750d5 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -19,7 +19,7 @@ */ #define ISA_MIPS1 0x0000000000000001ULL #define ISA_MIPS2 0x0000000000000002ULL -#define ISA_MIPS3 0x0000000000000004ULL +#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */ #define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS32 0x0000000000000020ULL diff --git a/hw/mips/boston.c b/hw/mips/boston.c index c3b94c68e1b..f44f681fab5 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -463,7 +463,7 @@ static void boston_mach_init(MachineState *machine) exit(1); } - is_64b = cpu_type_supports_isa(machine->cpu_type, ISA_MIPS64); + is_64b = cpu_type_supports_isa(machine->cpu_type, ISA_MIPS3); object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, From patchwork Wed Dec 16 16:27:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1417275 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=IUowv9fq; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Cx16H5Z5Qz9sSs for ; Thu, 17 Dec 2020 03:38:47 +1100 (AEDT) Received: from localhost ([::1]:34206 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpZp7-0006ft-Nj for incoming@patchwork.ozlabs.org; Wed, 16 Dec 2020 11:38:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32950) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpZen-0004Ub-QE for qemu-devel@nongnu.org; Wed, 16 Dec 2020 11:28:05 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:50785) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpZem-0007i8-7t for qemu-devel@nongnu.org; Wed, 16 Dec 2020 11:28:05 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 190so2948320wmz.0 for ; Wed, 16 Dec 2020 08:28:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L+8pzijn52zFNvnTsp0BOKURgiDqajyPik6Q5epzma8=; b=IUowv9fquZB8meq7j2d0fnFjKCx3YZ6dki/fzvSGYdeBvMCjYIObPkc2mkRFItLrZK D2yWdWQY2mqWzjqcJpk0qF8rBFPnimRysYFdFeqh5QKcmF/tO/Kdeo22dh/qQ7hmlPma p0woDnO3S3SKV8vysfetQN5P+R671X4yT4v767fDrwslp3u6de3jnYE3erk5TKSkKJ/K xapcLYWbmT7VXePsXMNJ8uKjFsvRHEMAYBPFETXkzMHMA/qbbTH+u7MSnLE/QUxmsHy8 HBvejJi5XKHbfSnuwO9DXOGnOeHCWY5XVEvDA5M63tqUEnNmd1GaC6B4pxzevoXHQTWr KS+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=L+8pzijn52zFNvnTsp0BOKURgiDqajyPik6Q5epzma8=; b=UncPbs/Iw54IyKQIa4X72ugKbENL5NOaQBTZr+uyugMym+NQYzPnY7F66bai7CNb7S ldp8ue4HPpDKEXLNlN4seSWcYyuy9PMtp/n9y5iTnBp9EMYZdox9UTREjjWPZCO3yaJM 0L2gwzlthe5uMsiGTto9HUqevfQTNToQFJNbn5MKYQEvc3BcgRo3CFFOFQHxwb/PI6Or qnqJpOqJqQDhrCbcYr2/c5XlrWUASqcAg5Oqh6Cx8/oOc0jw41mGgb3ZF4BYniIwx0xA vId/3W8COqB7VT7PS3W8zA6eI0Xn+qba8B/9gCUBqltpXruONC7IX4x0hPdQEjF/eEbL 39aQ== X-Gm-Message-State: AOAM530dClVztiTVV56tDq1/lEXvApFNEdKHaXcTrbYNvpLd/pVx0T5P FX4DrNhWN12ijzjDfqfLDRaOgnHrnyM= X-Google-Smtp-Source: ABdhPJyV1NcWKH2yZzIX19z9Lx05aHxbOTWqSHDL17DZJLBQEBX0PS8z3Tp3CXtLrgCr28S69rcYGQ== X-Received: by 2002:a1c:3b02:: with SMTP id i2mr3750460wma.141.1608136082253; Wed, 16 Dec 2020 08:28:02 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id c81sm3756241wmd.6.2020.12.16.08.28.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 08:28:01 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 03/12] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 Date: Wed, 16 Dec 2020 17:27:35 +0100 Message-Id: <20201216162744.895920-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216162744.895920-1-f4bug@amsat.org> References: <20201216162744.895920-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Use the single ISA_MIPS32 definition to check if the Release 1 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R1 in few commits. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/mips-defs.h | 3 +-- target/mips/translate.c | 10 +++++----- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index ab621a750d5..2756e72a9d6 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -24,7 +24,6 @@ #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL -#define ISA_MIPS64 0x0000000000000080ULL #define ISA_MIPS64R2 0x0000000000000100ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS64R3 0x0000000000000400ULL @@ -78,7 +77,7 @@ /* MIPS Technologies "Release 1" */ #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) -#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) +#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32) /* MIPS Technologies "Release 2" */ #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) diff --git a/target/mips/translate.c b/target/mips/translate.c index 15265485f76..12b01d4c35d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -8538,7 +8538,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) const char *register_name = "invalid"; if (sel != 0) { - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); } switch (reg) { @@ -9264,7 +9264,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) const char *register_name = "invalid"; if (sel != 0) { - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); } if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { @@ -14502,12 +14502,12 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) break; #if defined(TARGET_MIPS64) case RR_RY_CNVT_ZEW: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); check_mips_64(ctx); tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]); break; case RR_RY_CNVT_SEW: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); check_mips_64(ctx); tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); break; @@ -27203,7 +27203,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) #if defined(TARGET_MIPS64) case OPC_DCLO: case OPC_DCLZ: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); break; From patchwork Wed Dec 16 16:27:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1417273 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=A9W7gsxa; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Cx13L1t90z9sRR for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id 189sm3625351wma.22.2020.12.16.08.28.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 08:28:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 04/12] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 Date: Wed, 16 Dec 2020 17:27:36 +0100 Message-Id: <20201216162744.895920-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216162744.895920-1-f4bug@amsat.org> References: <20201216162744.895920-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x336.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Use the single ISA_MIPS32R2 definition to check if the Release 2 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R2 in few commits. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/mips-defs.h | 3 +-- linux-user/mips/cpu_loop.c | 1 - target/mips/translate.c | 4 ++-- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 2756e72a9d6..9cfa4c346bf 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -24,7 +24,6 @@ #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL -#define ISA_MIPS64R2 0x0000000000000100ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS64R3 0x0000000000000400ULL #define ISA_MIPS32R5 0x0000000000000800ULL @@ -81,7 +80,7 @@ /* MIPS Technologies "Release 2" */ #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) -#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) +#define CPU_MIPS64R2 (CPU_MIPS64 | ISA_MIPS32R2) /* MIPS Technologies "Release 3" */ #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index b58dbeb83d1..a2aa8167210 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -386,7 +386,6 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) prog_req.fre &= interp_req.fre; bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 || - env->insn_flags & ISA_MIPS64R2 || env->insn_flags & ISA_MIPS32R6 || env->insn_flags & ISA_MIPS64R6; diff --git a/target/mips/translate.c b/target/mips/translate.c index 12b01d4c35d..de3a6b5ed65 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28212,7 +28212,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) case OPC_DINSM: case OPC_DINSU: case OPC_DINS: - check_insn(ctx, ISA_MIPS64R2); + check_insn(ctx, ISA_MIPS32R2); check_mips_64(ctx); gen_bitops(ctx, op1, rt, rs, sa, rd); break; @@ -28232,7 +28232,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) decode_opc_special3_r6(env, ctx); break; default: - check_insn(ctx, ISA_MIPS64R2); + check_insn(ctx, ISA_MIPS32R2); check_mips_64(ctx); op2 = MASK_DBSHFL(ctx->opcode); gen_bshfl(ctx, op2, rt, rd); From patchwork Wed Dec 16 16:27:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1417276 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id b12sm6845045wmj.2.2020.12.16.08.28.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 08:28:11 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 05/12] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 Date: Wed, 16 Dec 2020 17:27:37 +0100 Message-Id: <20201216162744.895920-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216162744.895920-1-f4bug@amsat.org> References: <20201216162744.895920-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Use the single ISA_MIPS32R3 definition to check if the Release 3 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R3 in few commits. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/mips-defs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 9cfa4c346bf..0d906ca64b3 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -25,7 +25,6 @@ #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL -#define ISA_MIPS64R3 0x0000000000000400ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS64R5 0x0000000000001000ULL #define ISA_MIPS32R6 0x0000000000002000ULL @@ -84,7 +83,7 @@ /* MIPS Technologies "Release 3" */ #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) -#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) +#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) /* MIPS Technologies "Release 5" */ #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) From patchwork Wed Dec 16 16:27:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1417280 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=CoCqj2lq; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Cx1G41DH6z9sRR for ; Thu, 17 Dec 2020 03:45:32 +1100 (AEDT) Received: from localhost ([::1]:48962 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpZvd-0004zW-5F for incoming@patchwork.ozlabs.org; Wed, 16 Dec 2020 11:45:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33128) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpZfC-0005KO-5Y for qemu-devel@nongnu.org; Wed, 16 Dec 2020 11:28:31 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:43430) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpZf0-0007lw-ND for qemu-devel@nongnu.org; Wed, 16 Dec 2020 11:28:29 -0500 Received: by mail-wr1-x42a.google.com with SMTP id y17so23758608wrr.10 for ; Wed, 16 Dec 2020 08:28:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ygBBalz5UyiuOJifXXOKc1oAnXdEKjBaVDLqLiZUgIE=; b=CoCqj2lqXTBH2HuAzlG1pavCoRzJlYRxksEzR+BBFsENCCnbq1ABkV8muqsz4/MH5k hFIivC078hf3cIRAXOBaw+iacRNLVj+J8rvYqJnybij4KsgcT1D5Ees9EVzqbbDiH/9k F0iTOlvDq9mLZxFkbyON4ug2K0IjyNjh5wT+LyTsiu7iByBks27oNYDjHdD9kwP3LSxf svfbRt4+3UYEZaLip6AMgliY9D3SsLa9OhOcMvSXPA7vUmAtmPI5+cCNCKBdE5A3UOp7 uWbvnSUBVvP2cRJgoiGR1qWSOeuKrhSDCsumTNL8Qy5w1SajPbb4vA6Ll509ShWyx84l 2ntQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ygBBalz5UyiuOJifXXOKc1oAnXdEKjBaVDLqLiZUgIE=; b=FMVdKtrMb0XoOpnX/u1c7ZEG+JQS2aixz4bk0fq5ZEo3GaowK79J4HPMtLnUCXvvAY aU6q3rG2K8IOgm8DofwcOXgXXC+NDS5CdeSz32lYaVx3z+PZaBqYkaoSrGWr2Chrqnkj S5bWQ61moFvO4jOC7MvVEc8CKso/KbYk8XfzYf3vdVUTWtCsz/345Dz5/7K6RNmOIza/ lcq7rF+lgAA6KLf/+AqTLMuX/v2fZhIt3dnFBBrSApdkOZXrjAAwPUEHTaStRmC6aKp4 qcL0FnjdOppiCLjExXdEYn6+uBCyp+73FcA99oZcXN+DBEjx6FJ1UWaV527EzLi/fb41 Q1sA== X-Gm-Message-State: AOAM531rj+KsaCnu9cY8qYmCd9lFQXFwvFu8o8RpI8HpvpRgrCe3rsCo VRdNZ2UTF3YzqPVjnRo7LTw1Z/WJzs8= X-Google-Smtp-Source: ABdhPJwr/3+0r+LcnvK0BoElawyXj35BzNGcA7uvAEF3dh8UIlHb5q/dcsXxHQ+C4/XY+rqK1umB/A== X-Received: by 2002:adf:97dd:: with SMTP id t29mr39063941wrb.357.1608136097116; Wed, 16 Dec 2020 08:28:17 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id h14sm4000636wrx.37.2020.12.16.08.28.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 08:28:16 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 06/12] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 Date: Wed, 16 Dec 2020 17:27:38 +0100 Message-Id: <20201216162744.895920-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216162744.895920-1-f4bug@amsat.org> References: <20201216162744.895920-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Use the single ISA_MIPS32R5 definition to check if the Release 5 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R5 in few commits. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/mips-defs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 0d906ca64b3..ea9dcc7c98e 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -26,7 +26,6 @@ #define ISA_MIPS32R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL -#define ISA_MIPS64R5 0x0000000000001000ULL #define ISA_MIPS32R6 0x0000000000002000ULL #define ISA_MIPS64R6 0x0000000000004000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL @@ -87,7 +86,7 @@ /* MIPS Technologies "Release 5" */ #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) -#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5) +#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5) /* MIPS Technologies "Release 6" */ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) From patchwork Wed Dec 16 16:27:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1417278 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=MdBF0PV/; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Cx1B63WRHz9sRR for ; Thu, 17 Dec 2020 03:42:06 +1100 (AEDT) Received: from localhost ([::1]:41140 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpZsK-0001Kq-Fs for incoming@patchwork.ozlabs.org; Wed, 16 Dec 2020 11:42:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33108) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpZf7-00058d-FM for qemu-devel@nongnu.org; Wed, 16 Dec 2020 11:28:25 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:35371) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpZf5-0007mJ-My for qemu-devel@nongnu.org; Wed, 16 Dec 2020 11:28:25 -0500 Received: by mail-wm1-x32f.google.com with SMTP id e25so3057805wme.0 for ; Wed, 16 Dec 2020 08:28:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nnfnPGeSTecm92WN/NMVfeabAYZsekuzz7oGOoZfca0=; b=MdBF0PV/G+JX3bs2j8zQ5YG4Fm8/Y4WvLFKGsyvZdLsIhqc5zWP7MX5Qxc6g/Qw+rq k5XwejhgdDWwK2JCMYVnbKk6KcOmKtyNoEZJ1RJoi5qYUyxvot6Dhw2MZMarnbNqarua MVzxu9LkB/iygz1pUDr1t6CXFGDz6TkL7r3APlXGkE9OuPIhJkLkb1X8g4j6rd/FBlnE j6tGM5PJV3Tq10N9gBglC2ebx0eFNQs9ROkFr/mdqaO4CFsyvffhVf1XwHrVjjN0me9A IJA4LiRASkxS9ycLyQumR1ZDJW4DY1xzpHJjKEC/ztKmY0HuA1K5hD5aXJ5btWeSVqQX Sypg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=nnfnPGeSTecm92WN/NMVfeabAYZsekuzz7oGOoZfca0=; b=FI847+rCscgFlabZc6sSC3J7PDpv7XArYxdqg3qqPdOeZn4Is0lnquPf7/Nu7835rQ 4Nv0gEzsIvQyfR39tttDe3AscB3n/7GnO9CdhRIyLTXOQMuXqRabp8ID6DRwoLNLOsEU 61PCJypYpLON3S7MSQamjw7ccqKSEBTk2vprC43zTAvC8jGPVFzlJ2gjU9dl0aUOeHbL w+RmAT3cwOARavb8OzmaOL2Q0bsrrkOAnE6luHuO+K4U1yMMBH8vplJQ69GmfOJfLnpz VSUeiM+e1vKvHT0dlXsECnP/xI3MLypkmATxcTPmUk9BOJ6kPE2LkhgoxTCh6kKgS12q +1wQ== X-Gm-Message-State: AOAM533BPuFnVs0240CCyOjD9cnj4PbiaZbVq9OCgGWgvPskrXrZoyfa rUjkeEWztQCDZNYof3be4944a3HFAW0= X-Google-Smtp-Source: ABdhPJzP4NYJT5XeWd1Dc4SQyH0MvRfshFo/f6yobW8EX9dj5KXLQY9/jHQ4lNwj0/av9YGkYZCymQ== X-Received: by 2002:a1c:2605:: with SMTP id m5mr4166103wmm.111.1608136102128; Wed, 16 Dec 2020 08:28:22 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id u66sm3660173wmg.2.2020.12.16.08.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 08:28:21 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 07/12] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 Date: Wed, 16 Dec 2020 17:27:39 +0100 Message-Id: <20201216162744.895920-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216162744.895920-1-f4bug@amsat.org> References: <20201216162744.895920-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Use the single ISA_MIPS32R6 definition to check if the Release 6 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R6 in few commits. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 3 +-- linux-user/elfload.c | 2 +- linux-user/mips/cpu_loop.c | 3 +-- target/mips/tlb_helper.c | 6 +++--- target/mips/translate.c | 2 +- 6 files changed, 8 insertions(+), 10 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 76269cfc7bb..97899dbd3c8 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -308,7 +308,7 @@ static inline void compute_hflags(CPUMIPSState *env) } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && !(env->CP0_Status & (1 << CP0St_UX))) { env->hflags |= MIPS_HFLAG_AWRAP; - } else if (env->insn_flags & ISA_MIPS64R6) { + } else if (env->insn_flags & ISA_MIPS32R6) { /* Address wrapping for Supervisor and Kernel is specified in R6 */ if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) && !(env->CP0_Status & (1 << CP0St_SX))) || diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index ea9dcc7c98e..df2ffae5718 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -27,7 +27,6 @@ #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R6 0x0000000000002000ULL -#define ISA_MIPS64R6 0x0000000000004000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* * bits 24-39: MIPS ASEs @@ -90,7 +89,7 @@ /* MIPS Technologies "Release 6" */ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) -#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) +#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) /* Wave Computing: "nanoMIPS" */ #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 0b02a926025..e875a5387cc 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -997,7 +997,7 @@ static uint32_t get_elf_hwcap(void) #define GET_FEATURE(flag, hwcap) \ do { if (cpu->env.insn_flags & (flag)) { hwcaps |= hwcap; } } while (0) - GET_FEATURE(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6); + GET_FEATURE(ISA_MIPS32R6, HWCAP_MIPS_R6); GET_FEATURE(ASE_MSA, HWCAP_MIPS_MSA); #undef GET_FEATURE diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index a2aa8167210..1e4acf3d6e3 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -386,8 +386,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) prog_req.fre &= interp_req.fre; bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 || - env->insn_flags & ISA_MIPS32R6 || - env->insn_flags & ISA_MIPS64R6; + env->insn_flags & ISA_MIPS32R6; if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { env->CP0_Config5 |= (1 << CP0C5_FRE); diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 94a482e3dbe..68d766f90a3 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -1025,7 +1025,7 @@ void mips_cpu_do_interrupt(CPUState *cs) enter_debug_mode: if (env->insn_flags & ISA_MIPS3) { env->hflags |= MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &= ~MIPS_HFLAG_AWRAP; } @@ -1054,7 +1054,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); if (env->insn_flags & ISA_MIPS3) { env->hflags |= MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &= ~MIPS_HFLAG_AWRAP; } @@ -1240,7 +1240,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |= (1 << CP0St_EXL); if (env->insn_flags & ISA_MIPS3) { env->hflags |= MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &= ~MIPS_HFLAG_AWRAP; } diff --git a/target/mips/translate.c b/target/mips/translate.c index de3a6b5ed65..f32b5ebdd7e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29078,7 +29078,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #else ctx->mem_idx = hflags_mmu_index(ctx->hflags); #endif - ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 | ISA_MIPS64R6 | + ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 | INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN; LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, From patchwork Wed Dec 16 16:27:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1417271 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=k6nMyNMw; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Cx11W17Pzz9sRR for ; Thu, 17 Dec 2020 03:34:39 +1100 (AEDT) Received: from localhost ([::1]:51820 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpZl7-0001yH-2p for incoming@patchwork.ozlabs.org; Wed, 16 Dec 2020 11:34:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33134) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpZfE-0005L7-4R for qemu-devel@nongnu.org; Wed, 16 Dec 2020 11:28:33 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:40122) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpZfA-0007mh-Qw for qemu-devel@nongnu.org; Wed, 16 Dec 2020 11:28:30 -0500 Received: by mail-wr1-x433.google.com with SMTP id 91so23770111wrj.7 for ; Wed, 16 Dec 2020 08:28:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qN7CTgScsw9dE+yAsjz79vuuM7MiYVm5Hm+COo7pFZM=; b=k6nMyNMwTTIv1edKkvBC+ENYUirkoIEt4DHnbebGBg0b59z6PQgnwA4WWhwD/dIlh3 w08tJSpqUaRu+EGofLusn1cYN5Cr7OqU6MZ4wFaHkwQR6cZrbZfH2G/4rr/15tK+GjW3 pRCw3u5eXnIEQCsyvtXFRGM6sv7zHiQrNeuAkUWdB8eahynlWVOApUpi/vW2CJvUXEvJ flNTTKTd5ReucjlEr4D4imGkRN+pHAYlvZn1eHslKviisshytQAkIdT5x4jOD0tUfFUK PojYs8YJkIwejMYux0B97qE5mcRgciHSyXXreTb3NsclYH7h3ZDd6HMUwkw2Zo2d2GdL M//g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=qN7CTgScsw9dE+yAsjz79vuuM7MiYVm5Hm+COo7pFZM=; b=EmOSODG2l+KsF0B66/+P6sku2TXv2lmbkIU7n9tPkrNz/XDL4AEjCp0do+imjb7Ism QutdzIhvzHh+WIAACu/NFzp7AY0Q94HJEo3Fkz5tPQhXMeBTwFw4ckFBjhpvrEz2rDEb Qw+bX/Pj2SOmwjxkYoIDp14wos8BRXXU08QZAZJuIN5ppXANyXg8GJDE5oWeDG76hcic /zE/mUXALIwV4IV1vE936ga93puQXCXrGo+lpHQU/twAoHpapB+t1P8TlOGa8p0NPuEa AneViGCqCNgSJxsF6HTZQ0p9qX7payB8eUFajy2uBDmjtbX+henzSXXvtzrswd2c/SgT O6OA== X-Gm-Message-State: AOAM530IYBY0jbxjmQDSdA5RhZbsmjM0PV52uf7K+dlTrIjyonn3pcE+ FK3UMNIzdtXt7K+2COvsxARKtb+nwxY= X-Google-Smtp-Source: ABdhPJxs5e70LYcTrZ3DyJBsmrw10W25I/WZOP5HdWLaHv+FUh33wYHGxHgNl2W+EJn5dqlIMT5yyw== X-Received: by 2002:adf:8143:: with SMTP id 61mr38235728wrm.318.1608136107076; Wed, 16 Dec 2020 08:28:27 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id x25sm3312251wmc.3.2020.12.16.08.28.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 08:28:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 08/12] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 Date: Wed, 16 Dec 2020 17:27:40 +0100 Message-Id: <20201216162744.895920-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216162744.895920-1-f4bug@amsat.org> References: <20201216162744.895920-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The MIPS ISA release '1' is common to 32/64-bit CPUs. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 4 +-- target/mips/translate.c | 54 ++++++++++++++++++++--------------------- 3 files changed, 30 insertions(+), 30 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 97899dbd3c8..f71c617a1fe 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -365,7 +365,7 @@ static inline void compute_hflags(CPUMIPSState *env) if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { env->hflags |= MIPS_HFLAG_COP1X; } - } else if (env->insn_flags & ISA_MIPS32) { + } else if (env->insn_flags & ISA_MIPS_R1) { if (env->hflags & MIPS_HFLAG_64) { env->hflags |= MIPS_HFLAG_COP1X; } diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index df2ffae5718..31c02cc20ef 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -22,7 +22,7 @@ #define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */ #define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS5 0x0000000000000010ULL -#define ISA_MIPS32 0x0000000000000020ULL +#define ISA_MIPS_R1 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL @@ -72,7 +72,7 @@ #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) /* MIPS Technologies "Release 1" */ -#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) +#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS_R1) #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32) /* MIPS Technologies "Release 2" */ diff --git a/target/mips/translate.c b/target/mips/translate.c index f32b5ebdd7e..62825dba2fd 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7006,7 +7006,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) const char *register_name = "invalid"; if (sel != 0) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } switch (reg) { @@ -7774,7 +7774,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) const char *register_name = "invalid"; if (sel != 0) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { @@ -8538,7 +8538,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) const char *register_name = "invalid"; if (sel != 0) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } switch (reg) { @@ -9264,7 +9264,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) const char *register_name = "invalid"; if (sel != 0) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { @@ -10601,7 +10601,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, break; case OPC_DERET: opn = "deret"; - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; @@ -10616,7 +10616,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, break; case OPC_WAIT: opn = "wait"; - check_insn(ctx, ISA_MIPS3 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; @@ -10651,7 +10651,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, } if (cc != 0) { - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); } btarget = ctx->base.pc_next + 4 + offset; @@ -14020,7 +14020,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm); break; case I8_SVRS: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); { int xsregs = (ctx->opcode >> 24) & 0x7; int aregs = (ctx->opcode >> 16) & 0xf; @@ -14270,7 +14270,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) ((int8_t)ctx->opcode) << 3); break; case I8_SVRS: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); { int do_ra = ctx->opcode & (1 << 6); int do_s0 = ctx->opcode & (1 << 5); @@ -14414,7 +14414,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) int ra = (ctx->opcode >> 5) & 0x1; if (nd) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } if (link) { @@ -14435,7 +14435,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) * XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); generate_exception_end(ctx, EXCP_DBp); } break; @@ -14486,7 +14486,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) gen_HILO(ctx, OPC_MFHI, 0, rx); break; case RR_CNVT: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); switch (cnvt_op) { case RR_RY_CNVT_ZEB: tcg_gen_ext8u_tl(cpu_gpr[rx], cpu_gpr[rx]); @@ -14502,12 +14502,12 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) break; #if defined(TARGET_MIPS64) case RR_RY_CNVT_ZEW: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); check_mips_64(ctx); tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]); break; case RR_RY_CNVT_SEW: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); check_mips_64(ctx); tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); break; @@ -15426,7 +15426,7 @@ static void gen_pool16c_insn(DisasContext *ctx) * XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); generate_exception_end(ctx, EXCP_DBp); } break; @@ -15770,7 +15770,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) case CLZ: mips32_op = OPC_CLZ; do_cl: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_cl(ctx, mips32_op, rt, rs); break; case RDHWR: @@ -15797,7 +15797,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) mips32_op = OPC_DIVU; goto do_div; do_div: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_muldiv(ctx, mips32_op, 0, rs, rt); break; case MADD: @@ -15816,7 +15816,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) check_insn_opc_removed(ctx, ISA_MIPS32R6); mips32_op = OPC_MSUBU; do_mul: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_muldiv(ctx, mips32_op, 0, rs, rt); break; default: @@ -15964,7 +15964,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) if (is_uhi(extract32(ctx->opcode, 16, 10))) { gen_helper_do_semihosting(cpu_env); } else { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_SBRI) { gen_reserved_instruction(ctx); } else { @@ -24482,7 +24482,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) switch (op1) { case OPC_MOVN: /* Conditional move */ case OPC_MOVZ: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 | + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_LOONGSON2E | INSN_LOONGSON2F); gen_cond_move(ctx, op1, rd, rs, rt); break; @@ -24495,7 +24495,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) gen_HILO(ctx, op1, rd & 3, rs); break; case OPC_MOVCI: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); if (env->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, @@ -27168,7 +27168,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_MADDU: case OPC_MSUB: case OPC_MSUBU: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_muldiv(ctx, op1, rd & 3, rs, rt); break; case OPC_MUL: @@ -27185,7 +27185,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) break; case OPC_CLO: case OPC_CLZ: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_cl(ctx, op1, rd, rs); break; case OPC_SDBBP: @@ -27196,14 +27196,14 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) * XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); generate_exception_end(ctx, EXCP_DBp); } break; #if defined(TARGET_MIPS64) case OPC_DCLO: case OPC_DCLZ: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); break; @@ -28643,7 +28643,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_CACHE: check_insn_opc_removed(ctx, ISA_MIPS32R6); check_cp0_enabled(ctx); - check_insn(ctx, ISA_MIPS3 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { gen_cache_operation(ctx, rt, rs, imm); } @@ -28654,7 +28654,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) if (ctx->insn_flags & INSN_R5900) { /* Treat as NOP. */ } else { - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); /* Treat as NOP. */ } break; From patchwork Wed Dec 16 16:27:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1417277 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id w4sm3425026wmc.13.2020.12.16.08.28.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 08:28:31 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 09/12] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 Date: Wed, 16 Dec 2020 17:27:41 +0100 Message-Id: <20201216162744.895920-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216162744.895920-1-f4bug@amsat.org> References: <20201216162744.895920-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The MIPS ISA release 2 is common to 32/64-bit CPUs. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 6 +- linux-user/mips/cpu_loop.c | 2 +- target/mips/cp0_timer.c | 4 +- target/mips/cpu.c | 2 +- target/mips/translate.c | 138 ++++++++++++++++++------------------- 6 files changed, 77 insertions(+), 77 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index f71c617a1fe..b14671a9a51 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -361,7 +361,7 @@ static inline void compute_hflags(CPUMIPSState *env) } } - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { env->hflags |= MIPS_HFLAG_COP1X; } diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 31c02cc20ef..9ef3f517aaa 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -23,7 +23,7 @@ #define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS_R1 0x0000000000000020ULL -#define ISA_MIPS32R2 0x0000000000000040ULL +#define ISA_MIPS_R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R6 0x0000000000002000ULL @@ -76,8 +76,8 @@ #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32) /* MIPS Technologies "Release 2" */ -#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) -#define CPU_MIPS64R2 (CPU_MIPS64 | ISA_MIPS32R2) +#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS_R2) +#define CPU_MIPS64R2 (CPU_MIPS64 | ISA_MIPS_R2) /* MIPS Technologies "Release 3" */ #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 1e4acf3d6e3..fc5446ade37 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -385,7 +385,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) prog_req.frdefault &= interp_req.frdefault; prog_req.fre &= interp_req.fre; - bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 || + bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 || env->insn_flags & ISA_MIPS32R6; if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index 5ec0d6249e9..70de95d338f 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -44,7 +44,7 @@ static void cpu_mips_timer_update(CPUMIPSState *env) static void cpu_mips_timer_expire(CPUMIPSState *env) { cpu_mips_timer_update(env); - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { env->CP0_Cause |= 1 << CP0Ca_TI; } qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); @@ -93,7 +93,7 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value) if (!(env->CP0_Cause & (1 << CP0Ca_DC))) { cpu_mips_timer_update(env); } - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { env->CP0_Cause &= ~(1 << CP0Ca_TI); } qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 112eb0d9f47..5c571434134 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -111,7 +111,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) uint32_t old = env->CP0_Cause; int i; - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { mask |= 1 << CP0Ca_DC; } if (env->insn_flags & ISA_MIPS32R6) { diff --git a/target/mips/translate.c b/target/mips/translate.c index 62825dba2fd..34bc083c813 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7207,7 +7207,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) register_name = "PageMask"; break; case CP0_REG05__PAGEGRAIN: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); register_name = "PageGrain"; break; @@ -7255,27 +7255,27 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) register_name = "Wired"; break; case CP0_REG06__SRSCONF0: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); register_name = "SRSConf0"; break; case CP0_REG06__SRSCONF1: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); register_name = "SRSConf1"; break; case CP0_REG06__SRSCONF2: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); register_name = "SRSConf2"; break; case CP0_REG06__SRSCONF3: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); register_name = "SRSConf3"; break; case CP0_REG06__SRSCONF4: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); register_name = "SRSConf4"; break; @@ -7291,7 +7291,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) case CP0_REGISTER_07: switch (sel) { case CP0_REG07__HWRENA: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); register_name = "HWREna"; break; @@ -7386,17 +7386,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) register_name = "Status"; break; case CP0_REG12__INTCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); register_name = "IntCtl"; break; case CP0_REG12__SRSCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); register_name = "SRSCtl"; break; case CP0_REG12__SRSMAP: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); register_name = "SRSMap"; break; @@ -7432,13 +7432,13 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) register_name = "PRid"; break; case CP0_REG15__EBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); tcg_gen_ext32s_tl(arg, arg); register_name = "EBase"; break; case CP0_REG15__CMGCRBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); CP0_CHECK(ctx->cmgcr); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase)); tcg_gen_ext32s_tl(arg, arg); @@ -7952,7 +7952,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) register_name = "PageMask"; break; case CP0_REG05__PAGEGRAIN: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_pagegrain(cpu_env, arg); register_name = "PageGrain"; ctx->base.is_jmp = DISAS_STOP; @@ -7998,27 +7998,27 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) register_name = "Wired"; break; case CP0_REG06__SRSCONF0: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf0(cpu_env, arg); register_name = "SRSConf0"; break; case CP0_REG06__SRSCONF1: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf1(cpu_env, arg); register_name = "SRSConf1"; break; case CP0_REG06__SRSCONF2: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf2(cpu_env, arg); register_name = "SRSConf2"; break; case CP0_REG06__SRSCONF3: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf3(cpu_env, arg); register_name = "SRSConf3"; break; case CP0_REG06__SRSCONF4: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf4(cpu_env, arg); register_name = "SRSConf4"; break; @@ -8034,7 +8034,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) case CP0_REGISTER_07: switch (sel) { case CP0_REG07__HWRENA: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_hwrena(cpu_env, arg); ctx->base.is_jmp = DISAS_STOP; register_name = "HWREna"; @@ -8117,21 +8117,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) register_name = "Status"; break; case CP0_REG12__INTCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode */ ctx->base.is_jmp = DISAS_STOP; register_name = "IntCtl"; break; case CP0_REG12__SRSCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode */ ctx->base.is_jmp = DISAS_STOP; register_name = "SRSCtl"; break; case CP0_REG12__SRSMAP: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode */ ctx->base.is_jmp = DISAS_STOP; @@ -8176,7 +8176,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) register_name = "PRid"; break; case CP0_REG15__EBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_ebase(cpu_env, arg); register_name = "EBase"; break; @@ -8715,7 +8715,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) register_name = "PageMask"; break; case CP0_REG05__PAGEGRAIN: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); register_name = "PageGrain"; break; @@ -8760,27 +8760,27 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) register_name = "Wired"; break; case CP0_REG06__SRSCONF0: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); register_name = "SRSConf0"; break; case CP0_REG06__SRSCONF1: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); register_name = "SRSConf1"; break; case CP0_REG06__SRSCONF2: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); register_name = "SRSConf2"; break; case CP0_REG06__SRSCONF3: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); register_name = "SRSConf3"; break; case CP0_REG06__SRSCONF4: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); register_name = "SRSConf4"; break; @@ -8796,7 +8796,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) case CP0_REGISTER_07: switch (sel) { case CP0_REG07__HWRENA: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); register_name = "HWREna"; break; @@ -8889,17 +8889,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) register_name = "Status"; break; case CP0_REG12__INTCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); register_name = "IntCtl"; break; case CP0_REG12__SRSCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); register_name = "SRSCtl"; break; case CP0_REG12__SRSMAP: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); register_name = "SRSMap"; break; @@ -8934,12 +8934,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) register_name = "PRid"; break; case CP0_REG15__EBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); register_name = "EBase"; break; case CP0_REG15__CMGCRBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); CP0_CHECK(ctx->cmgcr); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase)); register_name = "CMGCRBase"; @@ -9442,7 +9442,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) register_name = "PageMask"; break; case CP0_REG05__PAGEGRAIN: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_pagegrain(cpu_env, arg); register_name = "PageGrain"; break; @@ -9487,27 +9487,27 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) register_name = "Wired"; break; case CP0_REG06__SRSCONF0: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf0(cpu_env, arg); register_name = "SRSConf0"; break; case CP0_REG06__SRSCONF1: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf1(cpu_env, arg); register_name = "SRSConf1"; break; case CP0_REG06__SRSCONF2: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf2(cpu_env, arg); register_name = "SRSConf2"; break; case CP0_REG06__SRSCONF3: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf3(cpu_env, arg); register_name = "SRSConf3"; break; case CP0_REG06__SRSCONF4: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf4(cpu_env, arg); register_name = "SRSConf4"; break; @@ -9523,7 +9523,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) case CP0_REGISTER_07: switch (sel) { case CP0_REG07__HWRENA: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_hwrena(cpu_env, arg); ctx->base.is_jmp = DISAS_STOP; register_name = "HWREna"; @@ -9610,21 +9610,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) register_name = "Status"; break; case CP0_REG12__INTCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode */ ctx->base.is_jmp = DISAS_STOP; register_name = "IntCtl"; break; case CP0_REG12__SRSCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode */ ctx->base.is_jmp = DISAS_STOP; register_name = "SRSCtl"; break; case CP0_REG12__SRSMAP: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode */ ctx->base.is_jmp = DISAS_STOP; @@ -9669,7 +9669,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) register_name = "PRid"; break; case CP0_REG15__EBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_ebase(cpu_env, arg); register_name = "EBase"; break; @@ -13048,7 +13048,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) * The Linux kernel will emulate rdhwr if it's not supported natively. * Therefore only check the ISA in system mode. */ - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); #endif t0 = tcg_temp_new(); @@ -15864,12 +15864,12 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) switch (minor) { case RDPGPR: check_cp0_enabled(ctx); - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_load_srsgpr(rs, rt); break; case WRPGPR: check_cp0_enabled(ctx); - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_store_srsgpr(rs, rt); break; default: @@ -24577,7 +24577,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) switch ((ctx->opcode >> 21) & 0x1f) { case 1: /* rotr is decoded as srl on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 = OPC_ROTR; } /* Fallthrough */ @@ -24603,7 +24603,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) switch ((ctx->opcode >> 6) & 0x1f) { case 1: /* rotrv is decoded as srlv on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 = OPC_ROTRV; } /* Fallthrough */ @@ -24675,7 +24675,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) switch ((ctx->opcode >> 21) & 0x1f) { case 1: /* drotr is decoded as dsrl on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 = OPC_DROTR; } /* Fallthrough */ @@ -24693,7 +24693,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) switch ((ctx->opcode >> 21) & 0x1f) { case 1: /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 = OPC_DROTR32; } /* Fallthrough */ @@ -24725,7 +24725,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) switch ((ctx->opcode >> 6) & 0x1f) { case 1: /* drotrv is decoded as dsrlv on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 = OPC_DROTRV; } /* Fallthrough */ @@ -28185,7 +28185,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) switch (op1) { case OPC_EXT: case OPC_INS: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_bitops(ctx, op1, rt, rs, sa, rd); break; case OPC_BSHFL: @@ -28200,7 +28200,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) decode_opc_special3_r6(env, ctx); break; default: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_bshfl(ctx, op2, rt, rd); break; } @@ -28212,7 +28212,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) case OPC_DINSM: case OPC_DINSU: case OPC_DINS: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); check_mips_64(ctx); gen_bitops(ctx, op1, rt, rs, sa, rd); break; @@ -28232,7 +28232,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) decode_opc_special3_r6(env, ctx); break; default: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); check_mips_64(ctx); op2 = MASK_DBSHFL(ctx->opcode); gen_bshfl(ctx, op2, rt, rd); @@ -28359,7 +28359,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) gen_reserved_instruction(ctx); break; case OPC_SYNCI: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); /* * Break the TB to be able to sync copied instructions * immediately. @@ -28476,7 +28476,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) } break; case OPC_DI: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); save_cpu_state(ctx, 1); gen_helper_di(t0, cpu_env); gen_store_gpr(t0, rt); @@ -28487,7 +28487,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) ctx->base.is_jmp = DISAS_STOP; break; case OPC_EI: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); save_cpu_state(ctx, 1); gen_helper_ei(t0, cpu_env); gen_store_gpr(t0, rt); @@ -28508,11 +28508,11 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) #endif /* !CONFIG_USER_ONLY */ break; case OPC_RDPGPR: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_load_srsgpr(rt, rd); break; case OPC_WRPGPR: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_store_srsgpr(rt, rd); break; default: @@ -28674,7 +28674,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_MFHC1: case OPC_MTHC1: check_cp1_enabled(ctx); - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); /* fall through */ case OPC_MFC1: case OPC_CFC1: @@ -28855,21 +28855,21 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) switch (op1) { case OPC_LUXC1: case OPC_SUXC1: - check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); /* Fallthrough */ case OPC_LWXC1: case OPC_LDXC1: case OPC_SWXC1: case OPC_SDXC1: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); gen_flt3_ldst(ctx, op1, sa, rd, rs, rt); break; case OPC_PREFX: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); /* Treat as NOP. */ break; case OPC_ALNV_PS: - check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); /* Fallthrough */ case OPC_MADD_S: case OPC_MADD_D: @@ -28883,7 +28883,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_NMSUB_S: case OPC_NMSUB_D: case OPC_NMSUB_PS: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); gen_flt3_arith(ctx, op1, sa, rs, rd, rt); break; default: From patchwork Wed Dec 16 16:27:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1417281 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id s133sm3409510wmf.38.2020.12.16.08.28.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 08:28:36 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 10/12] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 Date: Wed, 16 Dec 2020 17:27:42 +0100 Message-Id: <20201216162744.895920-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216162744.895920-1-f4bug@amsat.org> References: <20201216162744.895920-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The MIPS ISA release 3 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/mips-defs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 9ef3f517aaa..171d94c16dc 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -24,7 +24,7 @@ #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS_R1 0x0000000000000020ULL #define ISA_MIPS_R2 0x0000000000000040ULL -#define ISA_MIPS32R3 0x0000000000000200ULL +#define ISA_MIPS_R3 0x0000000000000080ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R6 0x0000000000002000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL @@ -80,7 +80,7 @@ #define CPU_MIPS64R2 (CPU_MIPS64 | ISA_MIPS_R2) /* MIPS Technologies "Release 3" */ -#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) +#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS_R3) #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) /* MIPS Technologies "Release 5" */ From patchwork Wed Dec 16 16:27:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1417285 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=po+A8HHz; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Cx1NZ2kJ4z9sRR for ; Thu, 17 Dec 2020 03:51:10 +1100 (AEDT) Received: from localhost ([::1]:33886 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpa16-0002F2-9r for incoming@patchwork.ozlabs.org; Wed, 16 Dec 2020 11:51:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33246) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpZfV-0005W1-3p for qemu-devel@nongnu.org; Wed, 16 Dec 2020 11:28:49 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:34215) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpZfQ-0007oH-1x for qemu-devel@nongnu.org; Wed, 16 Dec 2020 11:28:46 -0500 Received: by mail-wm1-x329.google.com with SMTP id g25so2268217wmh.1 for ; Wed, 16 Dec 2020 08:28:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/D7zdCflSZ6xA7e0uhMvc28vP/CHUGVea2/tI230T3c=; b=po+A8HHzMBToeB1ahSUSPCF1wCQsyz2HGMurriWshBekLN5VU3823tB4PDYDn2X8q0 6LPqQZV+miLhPwOOw17nIJNEgSBlejYvWx6TKTN8oo1h1tHJL2D5uUDBewWMGXT00rt1 eSRuz05f8wx/mH3KCp8CBvegd+1LG+VwK0GFz4LQq3Dd5z0FswoTGPg5pxsdaGr5EIWB Ao6tPXc6veMRzdqEcRkhVH6iwKZkyNxbyoec9YrKekdLHutup2yLvnm81Z3djwO5g4UX weSSiyIA6lokAZm4hK9SLY8XEoZp74YxR+I/Yi9I5QZYtgnTbr4sqbHGDT9gkbqXLVNP 5DiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=/D7zdCflSZ6xA7e0uhMvc28vP/CHUGVea2/tI230T3c=; b=QaYumb6mDe8zM54P7hjfjiST8OTBTPD7Ysg16LCMzfcTjYlUszUudGKOK90vn/CJXO p8Am8PegA81Ukeiy5Yux1N+BKQ4/eDCkIeNbAYPB9m43xXfmeOpUoFdNbfVklUgKbq1X 6gsPT+bonC9DS/FqYTOY7A4vjLBYe5h+dFVV25QIjCc3CePidlwDS5vduRo5UVwVBNew 6zt61ZFuFi3KoVD3ImeqrNY4kHFKSkiLJytxZ/8Np4jOqyIZ7D6tYVWsTZ71sTjMbu/9 mJZaclu0nXOOPuo8bGHFmj1yTnbIQeQ2pj/Qhe8Wv2YLQrDlCB5rBNX0qZY4CGmLvK7W CV8w== X-Gm-Message-State: AOAM532AePcAP2xbfqYb8W+k/Tg3xTep/NU6lcLd8DMUomwK0mzdq/Na s/5gZSvQnrjUUjOsSFOL5bwizD8BVrA= X-Google-Smtp-Source: ABdhPJxoPN5e7I0CW51aNBncTh0ZzURIfknV9IiFMnEJdJaIGNhNs82F1T4VkI1GYIjSn7NYNehRHw== X-Received: by 2002:a1c:2182:: with SMTP id h124mr4135400wmh.25.1608136121841; Wed, 16 Dec 2020 08:28:41 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id r20sm3892217wrg.66.2020.12.16.08.28.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 08:28:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 11/12] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 Date: Wed, 16 Dec 2020 17:27:43 +0100 Message-Id: <20201216162744.895920-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216162744.895920-1-f4bug@amsat.org> References: <20201216162744.895920-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The MIPS ISA release 5 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/mips-defs.h | 4 ++-- target/mips/translate.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 171d94c16dc..068fe9c8a19 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -25,7 +25,7 @@ #define ISA_MIPS_R1 0x0000000000000020ULL #define ISA_MIPS_R2 0x0000000000000040ULL #define ISA_MIPS_R3 0x0000000000000080ULL -#define ISA_MIPS32R5 0x0000000000000800ULL +#define ISA_MIPS_R5 0x0000000000000100ULL #define ISA_MIPS32R6 0x0000000000002000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* @@ -84,7 +84,7 @@ #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) /* MIPS Technologies "Release 5" */ -#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) +#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS_R5) #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5) /* MIPS Technologies "Release 6" */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 34bc083c813..43462c195fe 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -10588,7 +10588,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, if (ctx->opcode & (1 << bit_shift)) { /* OPC_ERETNC */ opn = "eretnc"; - check_insn(ctx, ISA_MIPS32R5); + check_insn(ctx, ISA_MIPS_R5); gen_helper_eretnc(cpu_env); } else { /* OPC_ERET */ From patchwork Wed Dec 16 16:27:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1417279 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=d2i5onlo; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Cx1D05XTfz9sRR for ; Thu, 17 Dec 2020 03:43:44 +1100 (AEDT) Received: from localhost ([::1]:43870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpZtu-0002Yl-Oh for incoming@patchwork.ozlabs.org; Wed, 16 Dec 2020 11:43:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpZfZ-0005f6-QR for qemu-devel@nongnu.org; Wed, 16 Dec 2020 11:28:53 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:35874) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpZfV-0007ox-Ta for qemu-devel@nongnu.org; Wed, 16 Dec 2020 11:28:53 -0500 Received: by mail-wm1-x331.google.com with SMTP id y23so3040663wmi.1 for ; Wed, 16 Dec 2020 08:28:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=norb8dQ+xJwKoal/3EHfxVZttVNBNqEacXt2awvcnek=; b=d2i5onloNoWPwHKD7AEqwpxW64yJ3BxvcnmEebmj5Yu8MbOj8CElpw2zvOJNnTu8Wi 2v6KzrgmJfabvOnHMVg1BJ5IPnlI+euKmmiU/7rcTkX3uHpjW/rfyJpYPcyj93wlFSxJ OZL/2qgcZydjdjCLF1XDaJW27RfaT9+eROK6O/saCCTkD2ZCrXEwuwzKIotdofJ0sYq9 WU80c9pCMc6lsUkJ32M/WtNBUTooST1eXkHYLLjJlR0aM0NN3S4zOSf+08rSqMG3iK/I 8dkzNkf0zTy5Aw1TLndCl89eDWdYK64LLWXT/FpPJxO/1BIJgqN41DeBK5/A2N+J1af6 KYUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=norb8dQ+xJwKoal/3EHfxVZttVNBNqEacXt2awvcnek=; b=pFiceJ/ak4aQ8RhpB4NPbrFsX71IUL0IO74q6C4GA3K14FVa6I34XMWKkEvWwav3N1 PEtlJGmT8cuN9XNBRcNVN0LNp2mL7H3FfpTk8iq7xouwEtM+GOSWMF7F6LCvl5jS05or Xr5OBrl6pTwFu5AXlQAQ1Xixhk0fXO5U2H4dcTfGnKlryJTjJlW+QtPoegl9BbU6EyCt u47mIEs0wdZvyo0zzqi4Bbs7HgLUVdLdaZMSiabim0bh33KHTaaynkJ/zYVN/fny0Z6R HXeNlnZPkBy0gTGNDFUG5Pz+/RxLTShjqaUCLgFV8QE5BLGarKOzg+ltB3XMfqhHBvOp tNfA== X-Gm-Message-State: AOAM531oySJoAZRyWEOEKUXgHej24VbBBSiRzUO/4CwjoBEvvK1VPLbm NEpDORV8TZwg1088QlxOzLsY/zLNUEU= X-Google-Smtp-Source: ABdhPJx0UUL//Ai4LO9fC8diCUic4c7PFsHe1lE6TPgIkQvOkSEBGQ8f8ZmsGwi0yPmIT6x0DbKGfA== X-Received: by 2002:a7b:c4d5:: with SMTP id g21mr4159260wmk.92.1608136127001; Wed, 16 Dec 2020 08:28:47 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id c10sm3939308wrb.92.2020.12.16.08.28.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 08:28:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 12/12] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 Date: Wed, 16 Dec 2020 17:27:44 +0100 Message-Id: <20201216162744.895920-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216162744.895920-1-f4bug@amsat.org> References: <20201216162744.895920-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The MIPS ISA release 6 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/internal.h | 4 +- target/mips/mips-defs.h | 4 +- linux-user/elfload.c | 2 +- linux-user/mips/cpu_loop.c | 2 +- target/mips/cp0_helper.c | 18 +- target/mips/cpu.c | 10 +- target/mips/fpu_helper.c | 4 +- target/mips/tlb_helper.c | 6 +- target/mips/translate.c | 426 ++++++++++++++++++------------------- 9 files changed, 238 insertions(+), 238 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index b14671a9a51..5dd17ff7333 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -308,7 +308,7 @@ static inline void compute_hflags(CPUMIPSState *env) } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && !(env->CP0_Status & (1 << CP0St_UX))) { env->hflags |= MIPS_HFLAG_AWRAP; - } else if (env->insn_flags & ISA_MIPS32R6) { + } else if (env->insn_flags & ISA_MIPS_R6) { /* Address wrapping for Supervisor and Kernel is specified in R6 */ if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) && !(env->CP0_Status & (1 << CP0St_SX))) || @@ -319,7 +319,7 @@ static inline void compute_hflags(CPUMIPSState *env) } #endif if (((env->CP0_Status & (1 << CP0St_CU0)) && - !(env->insn_flags & ISA_MIPS32R6)) || + !(env->insn_flags & ISA_MIPS_R6)) || !(env->hflags & MIPS_HFLAG_KSU)) { env->hflags |= MIPS_HFLAG_CP0; } diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 068fe9c8a19..32c4c5cf6c4 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -26,7 +26,7 @@ #define ISA_MIPS_R2 0x0000000000000040ULL #define ISA_MIPS_R3 0x0000000000000080ULL #define ISA_MIPS_R5 0x0000000000000100ULL -#define ISA_MIPS32R6 0x0000000000002000ULL +#define ISA_MIPS_R6 0x0000000000000200ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* * bits 24-39: MIPS ASEs @@ -88,7 +88,7 @@ #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5) /* MIPS Technologies "Release 6" */ -#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) +#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6) #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) /* Wave Computing: "nanoMIPS" */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index e875a5387cc..5f8bc98e5c5 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -997,7 +997,7 @@ static uint32_t get_elf_hwcap(void) #define GET_FEATURE(flag, hwcap) \ do { if (cpu->env.insn_flags & (flag)) { hwcaps |= hwcap; } } while (0) - GET_FEATURE(ISA_MIPS32R6, HWCAP_MIPS_R6); + GET_FEATURE(ISA_MIPS_R6, HWCAP_MIPS_R6); GET_FEATURE(ASE_MSA, HWCAP_MIPS_MSA); #undef GET_FEATURE diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index fc5446ade37..9d813ece4e7 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -386,7 +386,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) prog_req.fre &= interp_req.fre; bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 || - env->insn_flags & ISA_MIPS32R6; + env->insn_flags & ISA_MIPS_R6; if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { env->CP0_Config5 |= (1 << CP0C5_FRE); diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index 36a92857bfb..aae2af6eccc 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -527,7 +527,7 @@ void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) uint32_t index_p = env->CP0_Index & 0x80000000; uint32_t tlb_index = arg1 & 0x7fffffff; if (tlb_index < env->tlb->nb_tlb) { - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { index_p |= arg1 & 0x80000000; } env->CP0_Index = index_p | tlb_index; @@ -960,7 +960,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1) uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL; uint32_t new_ptei = (arg1 >> CP0PF_PTEI) & 0x3FULL; - if ((env->insn_flags & ISA_MIPS32R6)) { + if ((env->insn_flags & ISA_MIPS_R6)) { if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) { mask &= ~(0x3FULL << CP0PF_BDI); } @@ -980,7 +980,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1) env->CP0_PWField = arg1 & mask; if ((new_ptei >= 32) || - ((env->insn_flags & ISA_MIPS32R6) && + ((env->insn_flags & ISA_MIPS_R6) && (new_ptei == 0 || new_ptei == 1))) { env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) | (old_ptei << CP0PF_PTEI); @@ -990,7 +990,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1) uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; uint32_t new_ptew = (arg1 >> CP0PF_PTEW) & 0x3F; - if ((env->insn_flags & ISA_MIPS32R6)) { + if ((env->insn_flags & ISA_MIPS_R6)) { if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) { mask &= ~(0x3F << CP0PF_GDW); } @@ -1007,7 +1007,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1) env->CP0_PWField = arg1 & mask; if ((new_ptew >= 32) || - ((env->insn_flags & ISA_MIPS32R6) && + ((env->insn_flags & ISA_MIPS_R6) && (new_ptew == 0 || new_ptew == 1))) { env->CP0_PWField = (env->CP0_PWField & ~0x3F) | (old_ptew << CP0PF_PTEW); @@ -1026,7 +1026,7 @@ void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) { - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { if (arg1 < env->tlb->nb_tlb) { env->CP0_Wired = arg1; } @@ -1075,10 +1075,10 @@ void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1) uint32_t mask = 0x0000000F; if ((env->CP0_Config1 & (1 << CP0C1_PC)) && - (env->insn_flags & ISA_MIPS32R6)) { + (env->insn_flags & ISA_MIPS_R6)) { mask |= (1 << 4); } - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { mask |= (1 << 5); } if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { @@ -1149,7 +1149,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) /* 1k pages not implemented */ #if defined(TARGET_MIPS64) - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { int entryhi_r = extract64(arg1, 62, 2); int config0_at = extract32(env->CP0_Config0, 13, 2); bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 5c571434134..905772a394b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -77,7 +77,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) uint32_t mask = env->CP0_Status_rw_bitmask; target_ulong old = env->CP0_Status; - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; #if defined(TARGET_MIPS64) uint32_t ksux = (1 << CP0St_KX) & val; @@ -114,7 +114,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) if (env->insn_flags & ISA_MIPS_R2) { mask |= 1 << CP0Ca_DC; } - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { mask &= ~((1 << CP0Ca_WP) & val); } @@ -281,7 +281,7 @@ static bool mips_cpu_has_work(CPUState *cs) if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { if (cpu_mips_hw_interrupts_enabled(env) || - (env->insn_flags & ISA_MIPS32R6)) { + (env->insn_flags & ISA_MIPS_R6)) { has_work = true; } } @@ -503,13 +503,13 @@ static void mips_cpu_reset(DeviceState *dev) /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */ env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM); #endif /* !CONFIG_USER_ONLY */ - if ((env->insn_flags & ISA_MIPS32R6) && + if ((env->insn_flags & ISA_MIPS_R6) && (env->active_fpu.fcr0 & (1 << FCR0_F64))) { /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ env->CP0_Status |= (1 << CP0St_FR); } - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { /* PTW = 1 */ env->CP0_PWSize = 0x40; /* GDI = 12 */ diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index a3c05160b35..6dd853259e2 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -146,7 +146,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt) } break; case 25: - if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) { + if ((env->insn_flags & ISA_MIPS_R6) || (arg1 & 0xffffff00)) { return; } env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | @@ -173,7 +173,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt) (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask)); break; default: - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { do_raise_exception(env, EXCP_RI, GETPC()); } return; diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 68d766f90a3..082c17928d3 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -1025,7 +1025,7 @@ void mips_cpu_do_interrupt(CPUState *cs) enter_debug_mode: if (env->insn_flags & ISA_MIPS3) { env->hflags |= MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS32R6) || + if (!(env->insn_flags & ISA_MIPS_R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &= ~MIPS_HFLAG_AWRAP; } @@ -1054,7 +1054,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); if (env->insn_flags & ISA_MIPS3) { env->hflags |= MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS32R6) || + if (!(env->insn_flags & ISA_MIPS_R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &= ~MIPS_HFLAG_AWRAP; } @@ -1240,7 +1240,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |= (1 << CP0St_EXL); if (env->insn_flags & ISA_MIPS3) { env->hflags |= MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS32R6) || + if (!(env->insn_flags & ISA_MIPS_R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &= ~MIPS_HFLAG_AWRAP; } diff --git a/target/mips/translate.c b/target/mips/translate.c index 43462c195fe..c7bbf15c5aa 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -3634,7 +3634,7 @@ static void gen_logic_imm(DisasContext *ctx, uint32_t opc, } break; case OPC_LUI: - if (rs != 0 && (ctx->insn_flags & ISA_MIPS32R6)) { + if (rs != 0 && (ctx->insn_flags & ISA_MIPS_R6)) { /* OPC_AUI */ tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16); tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); @@ -6994,7 +6994,7 @@ cp0_unimplemented: static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg) { - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { tcg_gen_movi_tl(arg, 0); } else { tcg_gen_movi_tl(arg, ~0); @@ -7043,7 +7043,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) case CP0_REGISTER_01: switch (sel) { case CP0_REG01__RANDOM: - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); gen_helper_mfc0_random(arg, cpu_env); register_name = "Random"; break; @@ -7559,7 +7559,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask)); @@ -8304,7 +8304,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: gen_helper_mtc0_framemask(cpu_env, arg); @@ -8575,7 +8575,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) case CP0_REGISTER_01: switch (sel) { case CP0_REG01__RANDOM: - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); gen_helper_mfc0_random(arg, cpu_env); register_name = "Random"; break; @@ -9056,7 +9056,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask)); @@ -9786,7 +9786,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: gen_helper_mtc0_framemask(cpu_env, arg); @@ -10580,7 +10580,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, gen_helper_tlbr(cpu_env); break; case OPC_ERET: /* OPC_ERETNC */ - if ((ctx->insn_flags & ISA_MIPS32R6) && + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; } else { @@ -10602,7 +10602,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, case OPC_DERET: opn = "deret"; check_insn(ctx, ISA_MIPS_R1); - if ((ctx->insn_flags & ISA_MIPS32R6) && + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; } @@ -10617,7 +10617,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, case OPC_WAIT: opn = "wait"; check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); - if ((ctx->insn_flags & ISA_MIPS32R6) && + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; } @@ -10645,7 +10645,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, target_ulong btarget; TCGv_i32 t0 = tcg_temp_new_i32(); - if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { gen_reserved_instruction(ctx); goto out; } @@ -11501,23 +11501,23 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_SEL_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_s(ctx, op1, fd, ft, fs); break; case OPC_SELEQZ_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_s(ctx, op1, fd, ft, fs); break; case OPC_SELNEZ_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_s(ctx, op1, fd, ft, fs); break; case OPC_MOVCF_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); break; case OPC_MOVZ_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); { TCGLabel *l1 = gen_new_label(); TCGv_i32 fp0; @@ -11533,7 +11533,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_MOVN_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); { TCGLabel *l1 = gen_new_label(); TCGv_i32 fp0; @@ -11569,7 +11569,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_MADDF_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); @@ -11585,7 +11585,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_MSUBF_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); @@ -11601,7 +11601,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_RINT_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); @@ -11611,7 +11611,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_CLASS_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); @@ -11621,7 +11621,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_MIN_S: /* OPC_RECIP2_S */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MIN_S */ TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); @@ -11650,7 +11650,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_MINA_S: /* OPC_RECIP1_S */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MINA_S */ TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); @@ -11676,7 +11676,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_MAX_S: /* OPC_RSQRT1_S */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MAX_S */ TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); @@ -11700,7 +11700,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_MAXA_S: /* OPC_RSQRT2_S */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MAXA_S */ TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); @@ -11802,7 +11802,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, case OPC_CMP_NGE_S: case OPC_CMP_LE_S: case OPC_CMP_NGT_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->opcode & (1 << 6)) { gen_cmpabs_s(ctx, func - 48, ft, fs, cc); } else { @@ -12045,23 +12045,23 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_SEL_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_d(ctx, op1, fd, ft, fs); break; case OPC_SELEQZ_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_d(ctx, op1, fd, ft, fs); break; case OPC_SELNEZ_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_d(ctx, op1, fd, ft, fs); break; case OPC_MOVCF_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); break; case OPC_MOVZ_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); { TCGLabel *l1 = gen_new_label(); TCGv_i64 fp0; @@ -12077,7 +12077,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_MOVN_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); { TCGLabel *l1 = gen_new_label(); TCGv_i64 fp0; @@ -12115,7 +12115,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_MADDF_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp1 = tcg_temp_new_i64(); @@ -12131,7 +12131,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_MSUBF_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp1 = tcg_temp_new_i64(); @@ -12147,7 +12147,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_RINT_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); @@ -12157,7 +12157,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_CLASS_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); @@ -12167,7 +12167,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_MIN_D: /* OPC_RECIP2_D */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MIN_D */ TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp1 = tcg_temp_new_i64(); @@ -12194,7 +12194,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_MINA_D: /* OPC_RECIP1_D */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MINA_D */ TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp1 = tcg_temp_new_i64(); @@ -12218,7 +12218,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_MAX_D: /* OPC_RSQRT1_D */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MAX_D */ TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp1 = tcg_temp_new_i64(); @@ -12242,7 +12242,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } break; case OPC_MAXA_D: /* OPC_RSQRT2_D */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MAXA_D */ TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp1 = tcg_temp_new_i64(); @@ -12284,7 +12284,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, case OPC_CMP_NGE_D: case OPC_CMP_LE_D: case OPC_CMP_NGT_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->opcode & (1 << 6)) { gen_cmpabs_d(ctx, func - 48, ft, fs, cc); } else { @@ -13080,7 +13080,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) gen_store_gpr(t0, rt); break; case 4: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (sel != 0) { /* * Performance counter registers are not implemented other than @@ -13092,7 +13092,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) gen_store_gpr(t0, rt); break; case 5: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_helper_rdhwr_xnp(t0, cpu_env); gen_store_gpr(t0, rt); break; @@ -15755,7 +15755,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) case 0x2c: switch (minor) { case BITSWAP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_bitswap(ctx, OPC_BITSWAP, rs, rt); break; case SEB: @@ -15774,26 +15774,26 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) gen_cl(ctx, mips32_op, rt, rs); break; case RDHWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_rdhwr(ctx, rt, rs, 0); break; case WSBH: gen_bshfl(ctx, OPC_WSBH, rs, rt); break; case MULT: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_MULT; goto do_mul; case MULTU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_MULTU; goto do_mul; case DIV: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_DIV; goto do_div; case DIVU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_DIVU; goto do_div; do_div: @@ -15801,19 +15801,19 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) gen_muldiv(ctx, mips32_op, 0, rs, rt); break; case MADD: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_MADD; goto do_mul; case MADDU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_MADDU; goto do_mul; case MSUB: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_MSUB; goto do_mul; case MSUBU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_MSUBU; do_mul: check_insn(ctx, ISA_MIPS_R1); @@ -15841,7 +15841,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) switch (minor) { case JALR: /* JALRC */ case JALR_HB: /* JALRC_HB */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* JALRC, JALRC_HB */ gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0); } else { @@ -15852,7 +15852,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) break; case JALRS: case JALRS_HB: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2); ctx->hflags |= MIPS_HFLAG_BDS_STRICT; break; @@ -15995,7 +15995,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) } break; case 0x35: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); switch (minor) { case MFHI32: gen_HILO(ctx, OPC_MFHI, 0, rs); @@ -16269,7 +16269,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs) case COND_FLOAT_MOV(MOVT, 5): case COND_FLOAT_MOV(MOVT, 6): case COND_FLOAT_MOV(MOVT, 7): - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 1); break; case COND_FLOAT_MOV(MOVF, 0): @@ -16280,7 +16280,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs) case COND_FLOAT_MOV(MOVF, 5): case COND_FLOAT_MOV(MOVF, 6): case COND_FLOAT_MOV(MOVF, 7): - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 0); break; default: @@ -16331,15 +16331,15 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) gen_shift_imm(ctx, mips32_op, rt, rs, rd); break; case SELEQZ: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_cond_move(ctx, OPC_SELEQZ, rd, rs, rt); break; case SELNEZ: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_cond_move(ctx, OPC_SELNEZ, rd, rs, rt); break; case R6_RDHWR: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3)); break; default: @@ -16363,7 +16363,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) mips32_op = OPC_SUBU; goto do_arith; case MUL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_MUL; do_arith: gen_arith(ctx, mips32_op, rd, rs, rt); @@ -16416,7 +16416,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) switch (minor) { /* Conditional moves */ case MOVN: /* MUL */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* MUL */ gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt); } else { @@ -16425,7 +16425,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case MOVZ: /* MUH */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* MUH */ gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt); } else { @@ -16434,15 +16434,15 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case MULU: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt); break; case MUHU: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt); break; case LWXS: /* DIV */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* DIV */ gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt); } else { @@ -16451,15 +16451,15 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case MOD: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt); break; case R6_DIVU: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt); break; case MODU: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt); break; default: @@ -16470,11 +16470,11 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) gen_bitops(ctx, OPC_INS, rt, rs, rr, rd); return; case LSA: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_LSA(ctx, rd, rs, rt, extract32(ctx->opcode, 9, 2)); break; case ALIGN: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2)); break; case EXT: @@ -16487,7 +16487,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) generate_exception_end(ctx, EXCP_BREAK); break; case SIGRIE: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_reserved_instruction(ctx); break; default: @@ -16545,61 +16545,61 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) check_cp1_enabled(ctx); switch (minor) { case ALNV_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_ALNV_PS; goto do_madd; case MADD_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_MADD_S; goto do_madd; case MADD_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_MADD_D; goto do_madd; case MADD_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_MADD_PS; goto do_madd; case MSUB_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_MSUB_S; goto do_madd; case MSUB_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_MSUB_D; goto do_madd; case MSUB_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_MSUB_PS; goto do_madd; case NMADD_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_NMADD_S; goto do_madd; case NMADD_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_NMADD_D; goto do_madd; case NMADD_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_NMADD_PS; goto do_madd; case NMSUB_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_NMSUB_S; goto do_madd; case NMSUB_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_NMSUB_D; goto do_madd; case NMSUB_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_NMSUB_PS; do_madd: gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt); break; case CABS_COND_FMT: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); cond = (ctx->opcode >> 6) & 0xf; cc = (ctx->opcode >> 13) & 0x7; fmt = (ctx->opcode >> 10) & 0x3; @@ -16618,7 +16618,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case C_COND_FMT: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); cond = (ctx->opcode >> 6) & 0xf; cc = (ctx->opcode >> 13) & 0x7; fmt = (ctx->opcode >> 10) & 0x3; @@ -16637,11 +16637,11 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case CMP_CONDN_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); break; case CMP_CONDN_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); break; case POOL32FXF: @@ -16663,7 +16663,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) mips32_op = OPC_PUU_PS; goto do_ps; case CVT_PS_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_CVT_PS_S; do_ps: gen_farith(ctx, mips32_op, rt, rs, rd, 0); @@ -16673,7 +16673,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case MIN_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0); @@ -16689,27 +16689,27 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) /* [LS][WDU]XC1 */ switch ((ctx->opcode >> 6) & 0x7) { case LWXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_LWXC1; goto do_ldst_cp1; case SWXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_SWXC1; goto do_ldst_cp1; case LDXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_LDXC1; goto do_ldst_cp1; case SDXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_SDXC1; goto do_ldst_cp1; case LUXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_LUXC1; goto do_ldst_cp1; case SUXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_SUXC1; do_ldst_cp1: gen_flt3_ldst(ctx, mips32_op, rd, rd, rt, rs); @@ -16719,7 +16719,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case MAX_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0); @@ -16733,7 +16733,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) break; case 0x18: /* 3D insns */ - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); fmt = (ctx->opcode >> 9) & 0x3; switch ((ctx->opcode >> 6) & 0x7) { case RSQRT2_FMT: @@ -16784,7 +16784,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) fmt = (ctx->opcode >> 9) & 0x3; switch ((ctx->opcode >> 6) & 0x7) { case MOVF_FMT: /* RINT_FMT */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* RINT_FMT */ switch (fmt) { case FMT_SDPS_S: @@ -16815,7 +16815,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case MOVT_FMT: /* CLASS_FMT */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* CLASS_FMT */ switch (fmt) { case FMT_SDPS_S: @@ -16846,7 +16846,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case PREFX: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); break; default: goto pool32f_invalid; @@ -16868,7 +16868,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) goto pool32f_invalid; \ } case MINA_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0); @@ -16881,7 +16881,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case MAXA_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0); @@ -16923,7 +16923,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) /* cmovs */ switch ((ctx->opcode >> 6) & 0x7) { case MOVN_FMT: /* SELEQZ_FMT */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* SELEQZ_FMT */ switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: @@ -16941,11 +16941,11 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case MOVN_FMT_04: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); FINSN_3ARG_SDPS(MOVN); break; case MOVZ_FMT: /* SELNEZ_FMT */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* SELNEZ_FMT */ switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: @@ -16963,11 +16963,11 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case MOVZ_FMT_05: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); FINSN_3ARG_SDPS(MOVZ); break; case SEL_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs); @@ -16980,7 +16980,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case MADDF_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: mips32_op = OPC_MADDF_S; @@ -16993,7 +16993,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case MSUBF_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: mips32_op = OPC_MSUBF_S; @@ -17026,45 +17026,45 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) minor = (ctx->opcode >> 21) & 0x1f; switch (minor) { case BLTZ: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BLTZ, 4, rs, -1, imm << 1, 4); break; case BLTZAL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 4); ctx->hflags |= MIPS_HFLAG_BDS_STRICT; break; case BLTZALS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 2); ctx->hflags |= MIPS_HFLAG_BDS_STRICT; break; case BGEZ: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BGEZ, 4, rs, -1, imm << 1, 4); break; case BGEZAL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 4); ctx->hflags |= MIPS_HFLAG_BDS_STRICT; break; case BGEZALS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 2); ctx->hflags |= MIPS_HFLAG_BDS_STRICT; break; case BLEZ: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BLEZ, 4, rs, -1, imm << 1, 4); break; case BGTZ: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BGTZ, 4, rs, -1, imm << 1, 4); break; /* Traps */ case TLTI: /* BC1EQZC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* BC1EQZC */ check_cp1_enabled(ctx); gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rs, imm << 1, 0); @@ -17075,7 +17075,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case TGEI: /* BC1NEZC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* BC1NEZC */ check_cp1_enabled(ctx); gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rs, imm << 1, 0); @@ -17086,15 +17086,15 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case TLTIU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_TLTIU; goto do_trapi; case TGEIU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_TGEIU; goto do_trapi; case TNEI: /* SYNCI */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* SYNCI */ /* * Break the TB to be able to sync copied instructions @@ -17108,7 +17108,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case TEQI: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_TEQI; do_trapi: gen_trap(ctx, mips32_op, rs, -1, imm); @@ -17116,7 +17116,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) case BNEZC: case BEQZC: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, minor == BNEZC ? OPC_BNE : OPC_BEQ, 4, rs, 0, imm << 1, 0); /* @@ -17126,11 +17126,11 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) */ break; case LUI: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_logic_imm(ctx, OPC_LUI, rs, 0, imm); break; case SYNCI: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* * Break the TB to be able to sync copied instructions * immediately. @@ -17139,24 +17139,24 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) break; case BC2F: case BC2T: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* COP2: Not implemented. */ generate_exception_err(ctx, EXCP_CpU, 2); break; case BC1F: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1FANY2 : OPC_BC1F; goto do_cp1branch; case BC1T: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1TANY2 : OPC_BC1T; goto do_cp1branch; case BC1ANY4F: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_BC1FANY4; goto do_cp1mips3d; case BC1ANY4T: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_BC1TANY4; do_cp1mips3d: check_cop1x(ctx); @@ -17184,47 +17184,47 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) case POOL32C: minor = (ctx->opcode >> 12) & 0xf; offset = sextract32(ctx->opcode, 0, - (ctx->insn_flags & ISA_MIPS32R6) ? 9 : 12); + (ctx->insn_flags & ISA_MIPS_R6) ? 9 : 12); switch (minor) { case LWL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_LWL; goto do_ld_lr; case SWL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_SWL; goto do_st_lr; case LWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_LWR; goto do_ld_lr; case SWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_SWR; goto do_st_lr; #if defined(TARGET_MIPS64) case LDL: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_LDL; goto do_ld_lr; case SDL: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_SDL; goto do_st_lr; case LDR: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_LDR; goto do_ld_lr; case SDR: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_SDR; goto do_st_lr; case LWU: @@ -17275,11 +17275,11 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) mips32_op = OPC_LHUE; goto do_ld_lr; case LWLE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_LWLE; goto do_ld_lr; case LWRE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_LWRE; goto do_ld_lr; case LBE: @@ -17308,16 +17308,16 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) offset = sextract32(ctx->opcode, 0, 9); switch (minor2) { case SWLE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_SWLE; goto do_st_lr; case SWRE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op = OPC_SWRE; goto do_st_lr; case PREFE: /* Treat as no-op */ - if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >= 24)) { + if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) { /* hint codes 24-31 are reserved and signal RI */ generate_exception(ctx, EXCP_RI); } @@ -17344,7 +17344,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) break; case PREF: /* Treat as no-op */ - if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >= 24)) { + if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) { /* hint codes 24-31 are reserved and signal RI */ generate_exception(ctx, EXCP_RI); } @@ -17356,7 +17356,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case ADDI32: /* AUI, LUI */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* AUI, LUI */ gen_logic_imm(ctx, OPC_LUI, rt, rs, imm); } else { @@ -17394,13 +17394,13 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) gen_slt_imm(ctx, mips32_op, rt, rs, imm); break; case JALX32: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset, 4); ctx->hflags |= MIPS_HFLAG_BDS_STRICT; break; case JALS32: /* BOVC, BEQC, BEQZALC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs >= rt) { /* BOVC */ mips32_op = OPC_BOVC; @@ -17420,7 +17420,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case BEQ32: /* BC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* BC */ gen_compute_compact_branch(ctx, OPC_BC, 0, 0, sextract32(ctx->opcode << 1, 0, 27)); @@ -17430,7 +17430,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case BNE32: /* BALC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* BALC */ gen_compute_compact_branch(ctx, OPC_BALC, 0, 0, sextract32(ctx->opcode << 1, 0, 27)); @@ -17440,7 +17440,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case J32: /* BGTZC, BLTZC, BLTC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs == 0 && rt != 0) { /* BGTZC */ mips32_op = OPC_BGTZC; @@ -17459,7 +17459,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case JAL32: /* BLEZC, BGEZC, BGEC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs == 0 && rt != 0) { /* BLEZC */ mips32_op = OPC_BLEZC; @@ -17494,7 +17494,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) gen_cop1_ldst(ctx, mips32_op, rt, rs, imm); break; case ADDIUPC: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */ switch ((ctx->opcode >> 16) & 0x1f) { case ADDIUPC_00: @@ -17536,7 +17536,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case BNVC: /* BNEC, BNEZALC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rs >= rt) { /* BNVC */ mips32_op = OPC_BNVC; @@ -17550,7 +17550,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); break; case R6_BNEZC: /* JIALC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rt != 0) { /* BNEZC */ gen_compute_compact_branch(ctx, OPC_BNEZC, rt, 0, @@ -17561,7 +17561,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case R6_BEQZC: /* JIC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rt != 0) { /* BEQZC */ gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0, @@ -17572,7 +17572,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } break; case BLEZALC: /* BGEZALC, BGEUC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rs == 0 && rt != 0) { /* BLEZALC */ mips32_op = OPC_BLEZALC; @@ -17586,7 +17586,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); break; case BGTZALC: /* BLTZALC, BLTUC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rs == 0 && rt != 0) { /* BGTZALC */ mips32_op = OPC_BGTZALC; @@ -17708,7 +17708,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx) opc = OPC_SUBU; break; } - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* * In the Release 6, the register number location in * the instruction encoding has changed. @@ -17740,7 +17740,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx) } break; case POOL16C: - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { gen_pool16c_r6_insn(ctx); } else { gen_pool16c_insn(ctx); @@ -17756,7 +17756,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx) } break; case POOL16F: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->opcode & 1) { gen_reserved_instruction(ctx); } else { @@ -17874,14 +17874,14 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx) case B16: /* BC16 */ gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, sextract32(ctx->opcode, 0, 10) << 1, - (ctx->insn_flags & ISA_MIPS32R6) ? 0 : 4); + (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4); break; case BNEZ16: /* BNEZC16 */ case BEQZ16: /* BEQZC16 */ gen_compute_branch(ctx, op == BNEZ16 ? OPC_BNE : OPC_BEQ, 2, mmreg(uMIPS_RD(ctx->opcode)), 0, sextract32(ctx->opcode, 0, 7) << 1, - (ctx->insn_flags & ISA_MIPS32R6) ? 0 : 4); + (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4); break; case LI16: @@ -24563,7 +24563,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) case OPC_SLL: /* Shift with immediate */ if (sa == 5 && rd == 0 && rs == 0 && rt == 0) { /* PAUSE */ - if ((ctx->insn_flags & ISA_MIPS32R6) && + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { gen_reserved_instruction(ctx); break; @@ -24638,7 +24638,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) gen_trap(ctx, op1, rs, rt, -1); break; case OPC_LSA: /* OPC_PMON */ - if ((ctx->insn_flags & ISA_MIPS32R6) || ase_msa_available(env)) { + if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) { decode_opc_special_r6(env, ctx); } else { /* Pmon entry point, also R4010 selsl */ @@ -24740,13 +24740,13 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) } break; case OPC_DLSA: - if ((ctx->insn_flags & ISA_MIPS32R6) || ase_msa_available(env)) { + if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) { decode_opc_special_r6(env, ctx); } break; #endif default: - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { decode_opc_special_r6(env, ctx); } else if (ctx->insn_flags & INSN_R5900) { decode_opc_special_tx79(env, ctx); @@ -27156,7 +27156,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) int rs, rt, rd; uint32_t op1; - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); rs = (ctx->opcode >> 21) & 0x1f; rt = (ctx->opcode >> 16) & 0x1f; @@ -28143,7 +28143,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) switch (op1) { case OPC_LWLE: case OPC_LWRE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_LBUE: case OPC_LHUE: @@ -28156,7 +28156,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) return; case OPC_SWLE: case OPC_SWRE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_SBE: case OPC_SHE: @@ -28196,7 +28196,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) case OPC_ALIGN_2: case OPC_ALIGN_3: case OPC_BITSWAP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); decode_opc_special3_r6(env, ctx); break; default: @@ -28228,7 +28228,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) case OPC_DALIGN_6: case OPC_DALIGN_7: case OPC_DBITSWAP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); decode_opc_special3_r6(env, ctx); break; default: @@ -28268,7 +28268,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) } break; default: - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { decode_opc_special3_r6(env, ctx); } else { decode_opc_special3_legacy(env, ctx); @@ -28324,7 +28324,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_BLTZALL: case OPC_BGEZALL: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* Fallthrough */ case OPC_BLTZ: case OPC_BGEZ: @@ -28332,7 +28332,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) break; case OPC_BLTZAL: case OPC_BGEZAL: - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs == 0) { /* OPC_NAL, OPC_BAL */ gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4); @@ -28351,11 +28351,11 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_TNEI: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_trap(ctx, op1, rs, -1, imm); break; case OPC_SIGRIE: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_reserved_instruction(ctx); break; case OPC_SYNCI: @@ -28375,14 +28375,14 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) break; #if defined(TARGET_MIPS64) case OPC_DAHI: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); check_mips_64(ctx); if (rs != 0) { tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 32); } break; case OPC_DATI: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); check_mips_64(ctx); if (rs != 0) { tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 48); @@ -28462,14 +28462,14 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) gen_store_gpr(t0, rt); break; case OPC_DVP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (ctx->vp) { gen_helper_dvp(t0, cpu_env); gen_store_gpr(t0, rt); } break; case OPC_EVP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (ctx->vp) { gen_helper_evp(t0, cpu_env); gen_store_gpr(t0, rt); @@ -28522,7 +28522,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) } break; case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */ gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } else { @@ -28551,7 +28551,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) break; /* Branch */ case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rt == 0) { gen_reserved_instruction(ctx); break; @@ -28564,7 +28564,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) } break; case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rt == 0) { gen_reserved_instruction(ctx); break; @@ -28581,7 +28581,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) /* OPC_BLEZ */ gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); } else { - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); /* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */ gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } @@ -28591,7 +28591,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) /* OPC_BGTZ */ gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); } else { - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); /* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */ gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } @@ -28599,7 +28599,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_BEQL: case OPC_BNEL: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* Fallthrough */ case OPC_BEQ: case OPC_BNE: @@ -28613,7 +28613,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) /* Fallthrough */ case OPC_LWL: case OPC_LWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* Fallthrough */ case OPC_LB: case OPC_LH: @@ -28625,7 +28625,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) break; case OPC_SWL: case OPC_SWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_SB: case OPC_SH: @@ -28634,14 +28634,14 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) break; case OPC_SC: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); } gen_st_cond(ctx, rt, rs, imm, MO_TESL, false); break; case OPC_CACHE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); check_cp0_enabled(ctx); check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { @@ -28650,7 +28650,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) /* Treat as NOP. */ break; case OPC_PREF: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->insn_flags & INSN_R5900) { /* Treat as NOP. */ } else { @@ -28694,7 +28694,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) #endif case OPC_BC1EQZ: /* OPC_BC1ANY2 */ check_cp1_enabled(ctx); - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_BC1EQZ */ gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), rt, imm << 2, 4); @@ -28708,19 +28708,19 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) break; case OPC_BC1NEZ: check_cp1_enabled(ctx); - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), rt, imm << 2, 4); break; case OPC_BC1ANY4: check_cp1_enabled(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); check_cop1x(ctx); check_insn(ctx, ASE_MIPS3D); /* fall through */ case OPC_BC1: check_cp1_enabled(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), (rt >> 2) & 0x7, imm << 2); break; @@ -28738,7 +28738,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) { int r6_op = ctx->opcode & FOP(0x3f, 0x1f); check_cp1_enabled(ctx); - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { switch (r6_op) { case R6_OPC_CMP_AF_S: case R6_OPC_CMP_UN_S: @@ -28810,7 +28810,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) /* Compact branches [R6] and COP2 [non-R6] */ case OPC_BC: /* OPC_LWC2 */ case OPC_BALC: /* OPC_SWC2 */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_BC, OPC_BALC */ gen_compute_compact_branch(ctx, op, 0, 0, sextract32(ctx->opcode << 2, 0, 28)); @@ -28824,7 +28824,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) break; case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */ case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs != 0) { /* OPC_BEQZC, OPC_BNEZC */ gen_compute_compact_branch(ctx, op, rs, 0, @@ -28848,7 +28848,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) break; case OPC_CP3: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); op1 = MASK_CP3(ctx->opcode); @@ -28905,7 +28905,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) /* fall through */ case OPC_LDL: case OPC_LDR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_LWU: case OPC_LD: @@ -28915,7 +28915,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) break; case OPC_SDL: case OPC_SDR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_SD: check_insn(ctx, ISA_MIPS3); @@ -28923,7 +28923,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) gen_st(ctx, op, rt, rs, imm); break; case OPC_SCD: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); check_insn(ctx, ISA_MIPS3); if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); @@ -28932,7 +28932,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) gen_st_cond(ctx, rt, rs, imm, MO_TEQ, false); break; case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */ gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } else { @@ -28949,7 +28949,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) break; #else case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } else { MIPS_INVAL("major opcode"); @@ -28958,7 +28958,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) break; #endif case OPC_DAUI: /* OPC_JALX */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { #if defined(TARGET_MIPS64) /* OPC_DAUI */ check_mips_64(ctx); @@ -28991,7 +28991,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) } break; case OPC_PCREL: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs); break; default: /* Invalid */ @@ -29078,7 +29078,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #else ctx->mem_idx = hflags_mmu_index(ctx->hflags); #endif - ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 | + ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 | INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN; LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,