From patchwork Tue Jan 9 06:57:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Leroy X-Patchwork-Id: 857252 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zG3161X4Jz9s82 for ; Tue, 9 Jan 2018 17:59:54 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zG3153SlpzF0cq for ; Tue, 9 Jan 2018 17:59:53 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=c-s.fr (client-ip=93.17.236.30; helo=pegase1.c-s.fr; envelope-from=christophe.leroy@c-s.fr; receiver=) Received: from pegase1.c-s.fr (pegase1.c-s.fr [93.17.236.30]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zG2z102GNzF0QH for ; Tue, 9 Jan 2018 17:58:03 +1100 (AEDT) Received: from localhost (mailhub1-int [192.168.12.234]) by localhost (Postfix) with ESMTP id 3zG2ym0VBYz9ttgT; Tue, 9 Jan 2018 07:57:52 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at c-s.fr Received: from pegase1.c-s.fr ([192.168.12.234]) by localhost (pegase1.c-s.fr [192.168.12.234]) (amavisd-new, port 10024) with ESMTP id Z43JRfFyjLE1; Tue, 9 Jan 2018 07:57:52 +0100 (CET) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase1.c-s.fr (Postfix) with ESMTP id 3zG2ym024mz9ttg5; Tue, 9 Jan 2018 07:57:52 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id B393F8B867; Tue, 9 Jan 2018 07:57:59 +0100 (CET) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id k1tyzpHDXCK0; Tue, 9 Jan 2018 07:57:59 +0100 (CET) Received: from PO15451.localdomain (po15451.idsi0.si.c-s.fr [172.25.231.40]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 7987F8B787; Tue, 9 Jan 2018 07:57:59 +0100 (CET) Received: by localhost.localdomain (Postfix, from userid 0) id 4E54B6C73D; Tue, 9 Jan 2018 07:57:59 +0100 (CET) From: Christophe Leroy Subject: [PATCH] powerpc/32: Remove memory clobber asm constraint on dcbX() functions To: Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Scott Wood Message-Id: <20180109065759.4E54B6C73D@localhost.localdomain> Date: Tue, 9 Jan 2018 07:57:59 +0100 (CET) X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Instead of just telling GCC that dcbz(), dcbi(), dcbf() and dcbst() clobber memory, tell it what it clobbers: * dcbz(), dcbi() and dcbf() clobbers one cacheline as output * dcbf() and dcbst() clobbers one cacheline as input Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/cache.h | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index c1d257aa4c2d..fc8fe18acf8c 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -82,22 +82,31 @@ extern void _set_L3CR(unsigned long); static inline void dcbz(void *addr) { - __asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory"); + __asm__ __volatile__ ("dcbz 0, %1" : + "=m"(*(char (*)[L1_CACHE_BYTES])addr) : + "r"(addr) :); } static inline void dcbi(void *addr) { - __asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory"); + __asm__ __volatile__ ("dcbi 0, %1" : + "=m"(*(char (*)[L1_CACHE_BYTES])addr) : + "r"(addr) :); } static inline void dcbf(void *addr) { - __asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory"); + __asm__ __volatile__ ("dcbf 0, %1" : + "=m"(*(char (*)[L1_CACHE_BYTES])addr) : + "r"(addr), "m"(*(char (*)[L1_CACHE_BYTES])addr) : + ); } static inline void dcbst(void *addr) { - __asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory"); + __asm__ __volatile__ ("dcbst 0, %0" : : + "r"(addr), "m"(*(char (*)[L1_CACHE_BYTES])addr) : + ); } #endif /* !__ASSEMBLY__ */ #endif /* __KERNEL__ */