From patchwork Wed Dec 9 08:00:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WW9uZyBXdSAo5ZC05YuHKQ==?= X-Patchwork-Id: 1413243 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CrV030tKXz9sWP for ; Wed, 9 Dec 2020 19:02:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726212AbgLIICT (ORCPT ); Wed, 9 Dec 2020 03:02:19 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:49288 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726073AbgLIICR (ORCPT ); Wed, 9 Dec 2020 03:02:17 -0500 X-UUID: 7ebbd66466264caeb55234e58979ed57-20201209 X-UUID: 7ebbd66466264caeb55234e58979ed57-20201209 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1326156518; Wed, 09 Dec 2020 16:01:30 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Dec 2020 16:01:28 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 9 Dec 2020 16:01:27 +0800 From: Yong Wu To: Joerg Roedel , Matthias Brugger , Rob Herring , Will Deacon , Robin Murphy CC: Krzysztof Kozlowski , Evan Green , Tomasz Figa , , , , , , , , , Nicolas Boichat , , Subject: [PATCH v5 01/27] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema Date: Wed, 9 Dec 2020 16:00:36 +0800 Message-ID: <20201209080102.26626-2-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201209080102.26626-1-yong.wu@mediatek.com> References: <20201209080102.26626-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert MediaTek IOMMU to DT schema. Signed-off-by: Yong Wu Reviewed-by: Rob Herring --- .../bindings/iommu/mediatek,iommu.txt | 105 ----------- .../bindings/iommu/mediatek,iommu.yaml | 167 ++++++++++++++++++ 2 files changed, 167 insertions(+), 105 deletions(-) delete mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.txt create mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt deleted file mode 100644 index ac949f7fe3d4..000000000000 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt +++ /dev/null @@ -1,105 +0,0 @@ -* Mediatek IOMMU Architecture Implementation - - Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and -this M4U have two generations of HW architecture. Generation one uses flat -pagetable, and only supports 4K size page mapping. Generation two uses the -ARM Short-Descriptor translation table format for address translation. - - About the M4U Hardware Block Diagram, please check below: - - EMI (External Memory Interface) - | - m4u (Multimedia Memory Management Unit) - | - +--------+ - | | - gals0-rx gals1-rx (Global Async Local Sync rx) - | | - | | - gals0-tx gals1-tx (Global Async Local Sync tx) - | | Some SoCs may have GALS. - +--------+ - | - SMI Common(Smart Multimedia Interface Common) - | - +----------------+------- - | | - | gals-rx There may be GALS in some larbs. - | | - | | - | gals-tx - | | - SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). - (display) (vdec) - | | - | | - +-----+-----+ +----+----+ - | | | | | | - | | |... | | | ... There are different ports in each larb. - | | | | | | -OVL0 RDMA0 WDMA0 MC PP VLD - - As above, The Multimedia HW will go through SMI and M4U while it -access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain -smi local arbiter and smi common. It will control whether the Multimedia -HW should go though the m4u for translation or bypass it and talk -directly with EMI. And also SMI help control the power domain and clocks for -each local arbiter. - Normally we specify a local arbiter(larb) for each multimedia HW -like display, video decode, and camera. And there are different ports -in each larb. Take a example, There are many ports like MC, PP, VLD in the -video decode local arbiter, all these ports are according to the video HW. - In some SoCs, there may be a GALS(Global Async Local Sync) module between -smi-common and m4u, and additional GALS module between smi-larb and -smi-common. GALS can been seen as a "asynchronous fifo" which could help -synchronize for the modules in different clock frequency. - -Required properties: -- compatible : must be one of the following string: - "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. - "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. - "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. - "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses - generation one m4u HW. - "mediatek,mt8167-m4u" for mt8167 which uses generation two m4u HW. - "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. - "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW. -- reg : m4u register base and size. -- interrupts : the interrupt of m4u. -- clocks : must contain one entry for each clock-names. -- clock-names : Only 1 optional clock: - - "bclk": the block clock of m4u. - Here is the list which require this "bclk": - - mt2701, mt2712, mt7623 and mt8173. - Note that m4u use the EMI clock which always has been enabled before kernel - if there is no this "bclk". -- mediatek,larbs : List of phandle to the local arbiters in the current Socs. - Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort - according to the local arbiter index, like larb0, larb1, larb2... -- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. - Specifies the mtk_m4u_id as defined in - dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 - dt-binding/memory/mt2712-larb-port.h for mt2712, - dt-binding/memory/mt6779-larb-port.h for mt6779, - dt-binding/memory/mt8167-larb-port.h for mt8167, - dt-binding/memory/mt8173-larb-port.h for mt8173, and - dt-binding/memory/mt8183-larb-port.h for mt8183. - -Example: - iommu: iommu@10205000 { - compatible = "mediatek,mt8173-m4u"; - reg = <0 0x10205000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>; - #iommu-cells = <1>; - }; - -Example for a client device: - display { - compatible = "mediatek,mt8173-disp"; - iommus = <&iommu M4U_PORT_DISP_OVL0>, - <&iommu M4U_PORT_DISP_RDMA0>; - ... - }; diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml new file mode 100644 index 000000000000..b9946809fc2b --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek IOMMU Architecture Implementation + +maintainers: + - Yong Wu + +description: |+ + Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and + this M4U have two generations of HW architecture. Generation one uses flat + pagetable, and only supports 4K size page mapping. Generation two uses the + ARM Short-Descriptor translation table format for address translation. + + About the M4U Hardware Block Diagram, please check below: + + EMI (External Memory Interface) + | + m4u (Multimedia Memory Management Unit) + | + +--------+ + | | + gals0-rx gals1-rx (Global Async Local Sync rx) + | | + | | + gals0-tx gals1-tx (Global Async Local Sync tx) + | | Some SoCs may have GALS. + +--------+ + | + SMI Common(Smart Multimedia Interface Common) + | + +----------------+------- + | | + | gals-rx There may be GALS in some larbs. + | | + | | + | gals-tx + | | + SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). + (display) (vdec) + | | + | | + +-----+-----+ +----+----+ + | | | | | | + | | |... | | | ... There are different ports in each larb. + | | | | | | + OVL0 RDMA0 WDMA0 MC PP VLD + + As above, The Multimedia HW will go through SMI and M4U while it + access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain + smi local arbiter and smi common. It will control whether the Multimedia + HW should go though the m4u for translation or bypass it and talk + directly with EMI. And also SMI help control the power domain and clocks for + each local arbiter. + + Normally we specify a local arbiter(larb) for each multimedia HW + like display, video decode, and camera. And there are different ports + in each larb. Take a example, There are many ports like MC, PP, VLD in the + video decode local arbiter, all these ports are according to the video HW. + + In some SoCs, there may be a GALS(Global Async Local Sync) module between + smi-common and m4u, and additional GALS module between smi-larb and + smi-common. GALS can been seen as a "asynchronous fifo" which could help + synchronize for the modules in different clock frequency. + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2701-m4u # generation one + - mediatek,mt2712-m4u # generation two + - mediatek,mt6779-m4u # generation two + - mediatek,mt8167-m4u # generation two + - mediatek,mt8173-m4u # generation two + - mediatek,mt8183-m4u # generation two + + - description: mt7623 generation one + items: + - const: mediatek,mt7623-m4u + - const: mediatek,mt2701-m4u + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: bclk is the block clock. + + clock-names: + items: + - const: bclk + + mediatek,larbs: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 16 + description: | + List of phandle to the local arbiters in the current Socs. + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort + according to the local arbiter index, like larb0, larb1, larb2... + + '#iommu-cells': + const: 1 + description: | + This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as + defined in + dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, + dt-binding/memory/mt2712-larb-port.h for mt2712, + dt-binding/memory/mt6779-larb-port.h for mt6779, + dt-binding/memory/mt8167-larb-port.h for mt8167, + dt-binding/memory/mt8173-larb-port.h for mt8173, + dt-binding/memory/mt8183-larb-port.h for mt8183. + +required: + - compatible + - reg + - interrupts + - mediatek,larbs + - '#iommu-cells' + +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt2701-m4u + - mediatek,mt2712-m4u + - mediatek,mt8173-m4u + + then: + required: + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + iommu: iommu@10205000 { + compatible = "mediatek,mt8173-m4u"; + reg = <0x10205000 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + mediatek,larbs = <&larb0 &larb1 &larb2 + &larb3 &larb4 &larb5>; + #iommu-cells = <1>; + }; + + - | + #include + + /* Example for a client device */ + display { + compatible = "mediatek,mt8173-disp"; + iommus = <&iommu M4U_PORT_DISP_OVL0>, + <&iommu M4U_PORT_DISP_RDMA0>; + }; From patchwork Wed Dec 9 08:00:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WW9uZyBXdSAo5ZC05YuHKQ==?= X-Patchwork-Id: 1413258 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CrV8g5WkVz9sWK for ; Wed, 9 Dec 2020 19:10:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728431AbgLIIC3 (ORCPT ); Wed, 9 Dec 2020 03:02:29 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:44982 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728429AbgLIIC2 (ORCPT ); Wed, 9 Dec 2020 03:02:28 -0500 X-UUID: 5260d6350f5640418054bb1740d83192-20201209 X-UUID: 5260d6350f5640418054bb1740d83192-20201209 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 747838699; Wed, 09 Dec 2020 16:01:43 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Dec 2020 16:01:41 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 9 Dec 2020 16:01:41 +0800 From: Yong Wu To: Joerg Roedel , Matthias Brugger , Rob Herring , Will Deacon , Robin Murphy CC: Krzysztof Kozlowski , Evan Green , Tomasz Figa , , , , , , , , , Nicolas Boichat , , Subject: [PATCH v5 02/27] dt-bindings: memory: mediatek: Add a common larb-port header file Date: Wed, 9 Dec 2020 16:00:37 +0800 Message-ID: <20201209080102.26626-3-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201209080102.26626-1-yong.wu@mediatek.com> References: <20201209080102.26626-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Put all the macros about smi larb/port togethers, this is a preparing patch for extending LARB_NR and adding new dom-id support. Signed-off-by: Yong Wu Acked-by: Rob Herring Acked-by: Krzysztof Kozlowski --- include/dt-bindings/memory/mt2712-larb-port.h | 2 +- include/dt-bindings/memory/mt6779-larb-port.h | 2 +- include/dt-bindings/memory/mt8167-larb-port.h | 2 +- include/dt-bindings/memory/mt8173-larb-port.h | 2 +- include/dt-bindings/memory/mt8183-larb-port.h | 2 +- include/dt-bindings/memory/mtk-smi-larb-port.h | 15 +++++++++++++++ 6 files changed, 20 insertions(+), 5 deletions(-) create mode 100644 include/dt-bindings/memory/mtk-smi-larb-port.h diff --git a/include/dt-bindings/memory/mt2712-larb-port.h b/include/dt-bindings/memory/mt2712-larb-port.h index 6f9aa7349cef..b6b2c6bf4459 100644 --- a/include/dt-bindings/memory/mt2712-larb-port.h +++ b/include/dt-bindings/memory/mt2712-larb-port.h @@ -6,7 +6,7 @@ #ifndef __DTS_IOMMU_PORT_MT2712_H #define __DTS_IOMMU_PORT_MT2712_H -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) +#include #define M4U_LARB0_ID 0 #define M4U_LARB1_ID 1 diff --git a/include/dt-bindings/memory/mt6779-larb-port.h b/include/dt-bindings/memory/mt6779-larb-port.h index 2ad0899fbf2f..60f57f54393e 100644 --- a/include/dt-bindings/memory/mt6779-larb-port.h +++ b/include/dt-bindings/memory/mt6779-larb-port.h @@ -7,7 +7,7 @@ #ifndef _DTS_IOMMU_PORT_MT6779_H_ #define _DTS_IOMMU_PORT_MT6779_H_ -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) +#include #define M4U_LARB0_ID 0 #define M4U_LARB1_ID 1 diff --git a/include/dt-bindings/memory/mt8167-larb-port.h b/include/dt-bindings/memory/mt8167-larb-port.h index 000fb299a408..fcb9a49ec60e 100644 --- a/include/dt-bindings/memory/mt8167-larb-port.h +++ b/include/dt-bindings/memory/mt8167-larb-port.h @@ -8,7 +8,7 @@ #ifndef __DTS_IOMMU_PORT_MT8167_H #define __DTS_IOMMU_PORT_MT8167_H -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) +#include #define M4U_LARB0_ID 0 #define M4U_LARB1_ID 1 diff --git a/include/dt-bindings/memory/mt8173-larb-port.h b/include/dt-bindings/memory/mt8173-larb-port.h index 9f31ccfeca21..d8c99c946053 100644 --- a/include/dt-bindings/memory/mt8173-larb-port.h +++ b/include/dt-bindings/memory/mt8173-larb-port.h @@ -6,7 +6,7 @@ #ifndef __DTS_IOMMU_PORT_MT8173_H #define __DTS_IOMMU_PORT_MT8173_H -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) +#include #define M4U_LARB0_ID 0 #define M4U_LARB1_ID 1 diff --git a/include/dt-bindings/memory/mt8183-larb-port.h b/include/dt-bindings/memory/mt8183-larb-port.h index 2c579f305162..275c095a6fd6 100644 --- a/include/dt-bindings/memory/mt8183-larb-port.h +++ b/include/dt-bindings/memory/mt8183-larb-port.h @@ -6,7 +6,7 @@ #ifndef __DTS_IOMMU_PORT_MT8183_H #define __DTS_IOMMU_PORT_MT8183_H -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) +#include #define M4U_LARB0_ID 0 #define M4U_LARB1_ID 1 diff --git a/include/dt-bindings/memory/mtk-smi-larb-port.h b/include/dt-bindings/memory/mtk-smi-larb-port.h new file mode 100644 index 000000000000..53354cf4f6e3 --- /dev/null +++ b/include/dt-bindings/memory/mtk-smi-larb-port.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Yong Wu + */ +#ifndef __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ +#define __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ + +#define MTK_LARB_NR_MAX 16 + +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) +#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf) +#define MTK_M4U_TO_PORT(id) ((id) & 0x1f) + +#endif From patchwork Wed Dec 9 08:00:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WW9uZyBXdSAo5ZC05YuHKQ==?= X-Patchwork-Id: 1413260 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CrV962Yxcz9sWL for ; Wed, 9 Dec 2020 19:10:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728442AbgLIIC3 (ORCPT ); Wed, 9 Dec 2020 03:02:29 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:49110 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726439AbgLIIC0 (ORCPT ); Wed, 9 Dec 2020 03:02:26 -0500 X-UUID: 11f65a8277044b48bb537140e873d4a4-20201209 X-UUID: 11f65a8277044b48bb537140e873d4a4-20201209 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2091856922; Wed, 09 Dec 2020 16:01:53 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Dec 2020 16:01:49 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 9 Dec 2020 16:01:52 +0800 From: Yong Wu To: Joerg Roedel , Matthias Brugger , Rob Herring , Will Deacon , Robin Murphy CC: Krzysztof Kozlowski , Evan Green , Tomasz Figa , , , , , , , , , Nicolas Boichat , , Subject: [PATCH v5 03/27] dt-bindings: memory: mediatek: Extend LARB_NR_MAX to 32 Date: Wed, 9 Dec 2020 16:00:38 +0800 Message-ID: <20201209080102.26626-4-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201209080102.26626-1-yong.wu@mediatek.com> References: <20201209080102.26626-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Extend the max larb number definition as mt8192 has larb_nr over 16. Signed-off-by: Yong Wu Acked-by: Rob Herring Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +- include/dt-bindings/memory/mtk-smi-larb-port.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index b9946809fc2b..ba6626347381 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -99,7 +99,7 @@ properties: mediatek,larbs: $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 - maxItems: 16 + maxItems: 32 description: | List of phandle to the local arbiters in the current Socs. Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort diff --git a/include/dt-bindings/memory/mtk-smi-larb-port.h b/include/dt-bindings/memory/mtk-smi-larb-port.h index 53354cf4f6e3..7d64103209af 100644 --- a/include/dt-bindings/memory/mtk-smi-larb-port.h +++ b/include/dt-bindings/memory/mtk-smi-larb-port.h @@ -6,10 +6,10 @@ #ifndef __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ #define __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ -#define MTK_LARB_NR_MAX 16 +#define MTK_LARB_NR_MAX 32 #define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) -#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf) +#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x1f) #define MTK_M4U_TO_PORT(id) ((id) & 0x1f) #endif From patchwork Wed Dec 9 08:00:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WW9uZyBXdSAo5ZC05YuHKQ==?= X-Patchwork-Id: 1413255 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CrV7y1xN6z9sWL for ; Wed, 9 Dec 2020 19:09:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728497AbgLIICt (ORCPT ); Wed, 9 Dec 2020 03:02:49 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:45258 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726449AbgLIICm (ORCPT ); Wed, 9 Dec 2020 03:02:42 -0500 X-UUID: bda078e12a65473a8c6ec9539b6e132c-20201209 X-UUID: bda078e12a65473a8c6ec9539b6e132c-20201209 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1960935038; Wed, 09 Dec 2020 16:01:59 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Dec 2020 16:01:58 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 9 Dec 2020 16:01:58 +0800 From: Yong Wu To: Joerg Roedel , Matthias Brugger , Rob Herring , Will Deacon , Robin Murphy CC: Krzysztof Kozlowski , Evan Green , Tomasz Figa , , , , , , , , , Nicolas Boichat , , Subject: [PATCH v5 04/27] dt-bindings: memory: mediatek: Add domain definition Date: Wed, 9 Dec 2020 16:00:39 +0800 Message-ID: <20201209080102.26626-5-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201209080102.26626-1-yong.wu@mediatek.com> References: <20201209080102.26626-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the latest SoC, there are several HW IP require a sepecial iova range, mainly CCU and VPU has this requirement. Take CCU as a example, CCU require its iova locate in the range(0x4000_0000 ~ 0x43ff_ffff). In this patch we add a domain definition for the special port. In the example of CCU, If we preassign CCU port in domain1, then iommu driver will prepare a independent iommu domain of the special iova range for it, then the iova got from dma_alloc_attrs(ccu-dev) will locate in its special range. This is a preparing patch for multi-domain support. Signed-off-by: Yong Wu Acked-by: Krzysztof Kozlowski Acked-by: Rob Herring --- include/dt-bindings/memory/mtk-smi-larb-port.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/memory/mtk-smi-larb-port.h b/include/dt-bindings/memory/mtk-smi-larb-port.h index 7d64103209af..2d4c973c174f 100644 --- a/include/dt-bindings/memory/mtk-smi-larb-port.h +++ b/include/dt-bindings/memory/mtk-smi-larb-port.h @@ -7,9 +7,16 @@ #define __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ #define MTK_LARB_NR_MAX 32 +#define MTK_M4U_DOM_NR_MAX 8 + +#define MTK_M4U_DOM_ID(domid, larb, port) \ + (((domid) & 0x7) << 16 | (((larb) & 0x1f) << 5) | ((port) & 0x1f)) + +/* The default dom id is 0. */ +#define MTK_M4U_ID(larb, port) MTK_M4U_DOM_ID(0, larb, port) -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) #define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x1f) #define MTK_M4U_TO_PORT(id) ((id) & 0x1f) +#define MTK_M4U_TO_DOM(id) (((id) >> 16) & 0x7) #endif From patchwork Wed Dec 9 08:00:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WW9uZyBXdSAo5ZC05YuHKQ==?= X-Patchwork-Id: 1413244 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CrV0b15Jbz9sWK for ; Wed, 9 Dec 2020 19:03:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728487AbgLIICy (ORCPT ); Wed, 9 Dec 2020 03:02:54 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:44982 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728489AbgLIICu (ORCPT ); Wed, 9 Dec 2020 03:02:50 -0500 X-UUID: 49c9e5100ff546779371ca6321fdc86f-20201209 X-UUID: 49c9e5100ff546779371ca6321fdc86f-20201209 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1512407944; Wed, 09 Dec 2020 16:02:10 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Dec 2020 16:02:09 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 9 Dec 2020 16:02:08 +0800 From: Yong Wu To: Joerg Roedel , Matthias Brugger , Rob Herring , Will Deacon , Robin Murphy CC: Krzysztof Kozlowski , Evan Green , Tomasz Figa , , , , , , , , , Nicolas Boichat , , Subject: [PATCH v5 05/27] dt-bindings: memory: mediatek: Rename header guard for SMI header file Date: Wed, 9 Dec 2020 16:00:40 +0800 Message-ID: <20201209080102.26626-6-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201209080102.26626-1-yong.wu@mediatek.com> References: <20201209080102.26626-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Only rename the header guard for all the SoC larb port header file. No funtional change. Suggested-by: Krzysztof Kozlowski Signed-off-by: Yong Wu Acked-by: Krzysztof Kozlowski Acked-by: Rob Herring --- include/dt-bindings/memory/mt2701-larb-port.h | 4 ++-- include/dt-bindings/memory/mt2712-larb-port.h | 4 ++-- include/dt-bindings/memory/mt6779-larb-port.h | 4 ++-- include/dt-bindings/memory/mt8167-larb-port.h | 4 ++-- include/dt-bindings/memory/mt8173-larb-port.h | 4 ++-- include/dt-bindings/memory/mt8183-larb-port.h | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/include/dt-bindings/memory/mt2701-larb-port.h b/include/dt-bindings/memory/mt2701-larb-port.h index 2d85c2ec6cfd..25d03526f142 100644 --- a/include/dt-bindings/memory/mt2701-larb-port.h +++ b/include/dt-bindings/memory/mt2701-larb-port.h @@ -4,8 +4,8 @@ * Author: Honghui Zhang */ -#ifndef _MT2701_LARB_PORT_H_ -#define _MT2701_LARB_PORT_H_ +#ifndef _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_ /* * Mediatek m4u generation 1 such as mt2701 has flat m4u port numbers, diff --git a/include/dt-bindings/memory/mt2712-larb-port.h b/include/dt-bindings/memory/mt2712-larb-port.h index b6b2c6bf4459..5c7f303f078c 100644 --- a/include/dt-bindings/memory/mt2712-larb-port.h +++ b/include/dt-bindings/memory/mt2712-larb-port.h @@ -3,8 +3,8 @@ * Copyright (c) 2017 MediaTek Inc. * Author: Yong Wu */ -#ifndef __DTS_IOMMU_PORT_MT2712_H -#define __DTS_IOMMU_PORT_MT2712_H +#ifndef _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_ #include diff --git a/include/dt-bindings/memory/mt6779-larb-port.h b/include/dt-bindings/memory/mt6779-larb-port.h index 60f57f54393e..bc93757df2bf 100644 --- a/include/dt-bindings/memory/mt6779-larb-port.h +++ b/include/dt-bindings/memory/mt6779-larb-port.h @@ -4,8 +4,8 @@ * Author: Chao Hao */ -#ifndef _DTS_IOMMU_PORT_MT6779_H_ -#define _DTS_IOMMU_PORT_MT6779_H_ +#ifndef _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_ #include diff --git a/include/dt-bindings/memory/mt8167-larb-port.h b/include/dt-bindings/memory/mt8167-larb-port.h index fcb9a49ec60e..8570aab09db8 100644 --- a/include/dt-bindings/memory/mt8167-larb-port.h +++ b/include/dt-bindings/memory/mt8167-larb-port.h @@ -5,8 +5,8 @@ * Author: Honghui Zhang * Author: Fabien Parent */ -#ifndef __DTS_IOMMU_PORT_MT8167_H -#define __DTS_IOMMU_PORT_MT8167_H +#ifndef _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_ #include diff --git a/include/dt-bindings/memory/mt8173-larb-port.h b/include/dt-bindings/memory/mt8173-larb-port.h index d8c99c946053..1b568973fc2d 100644 --- a/include/dt-bindings/memory/mt8173-larb-port.h +++ b/include/dt-bindings/memory/mt8173-larb-port.h @@ -3,8 +3,8 @@ * Copyright (c) 2015-2016 MediaTek Inc. * Author: Yong Wu */ -#ifndef __DTS_IOMMU_PORT_MT8173_H -#define __DTS_IOMMU_PORT_MT8173_H +#ifndef _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_ #include diff --git a/include/dt-bindings/memory/mt8183-larb-port.h b/include/dt-bindings/memory/mt8183-larb-port.h index 275c095a6fd6..3095630bb190 100644 --- a/include/dt-bindings/memory/mt8183-larb-port.h +++ b/include/dt-bindings/memory/mt8183-larb-port.h @@ -3,8 +3,8 @@ * Copyright (c) 2018 MediaTek Inc. * Author: Yong Wu */ -#ifndef __DTS_IOMMU_PORT_MT8183_H -#define __DTS_IOMMU_PORT_MT8183_H +#ifndef _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_ #include From patchwork Wed Dec 9 08:00:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WW9uZyBXdSAo5ZC05YuHKQ==?= X-Patchwork-Id: 1413247 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CrV1H243kz9sWP for ; Wed, 9 Dec 2020 19:03:47 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728537AbgLIIDS (ORCPT ); Wed, 9 Dec 2020 03:03:18 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:50360 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728532AbgLIIDM (ORCPT ); Wed, 9 Dec 2020 03:03:12 -0500 X-UUID: ebe6fe1ee71440289125d7a58bfdae6d-20201209 X-UUID: ebe6fe1ee71440289125d7a58bfdae6d-20201209 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 362568923; Wed, 09 Dec 2020 16:02:19 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Dec 2020 16:02:18 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 9 Dec 2020 16:02:16 +0800 From: Yong Wu To: Joerg Roedel , Matthias Brugger , Rob Herring , Will Deacon , Robin Murphy CC: Krzysztof Kozlowski , Evan Green , Tomasz Figa , , , , , , , , , Nicolas Boichat , , Subject: [PATCH v5 06/27] dt-bindings: mediatek: Add binding for mt8192 IOMMU Date: Wed, 9 Dec 2020 16:00:41 +0800 Message-ID: <20201209080102.26626-7-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201209080102.26626-1-yong.wu@mediatek.com> References: <20201209080102.26626-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds decriptions for mt8192 IOMMU and SMI. mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation table format. The M4U-SMI HW diagram is as below: EMI | M4U | ------------ SMI Common ------------ | +-------+------+------+----------------------+-------+ | | | | ...... | | | | | | | | larb0 larb1 larb2 larb4 ...... larb19 larb20 disp0 disp1 mdp vdec IPE IPE All the connections are HW fixed, SW can NOT adjust it. mt8192 M4U support 0~16GB iova range. we preassign different engines into different iova ranges: domain-id module iova-range larbs 0 disp 0 ~ 4G larb0/1 1 vcodec 4G ~ 8G larb4/5/7 2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 3 CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10 4 CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5 The iova range for CCU0/1(camera control unit) is HW requirement. Signed-off-by: Yong Wu Reviewed-by: Rob Herring Acked-by: Krzysztof Kozlowski --- .../bindings/iommu/mediatek,iommu.yaml | 18 +- include/dt-bindings/memory/mt8192-larb-port.h | 240 ++++++++++++++++++ 2 files changed, 257 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index ba6626347381..0f26fe14c8e2 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -76,6 +76,7 @@ properties: - mediatek,mt8167-m4u # generation two - mediatek,mt8173-m4u # generation two - mediatek,mt8183-m4u # generation two + - mediatek,mt8192-m4u # generation two - description: mt7623 generation one items: @@ -115,7 +116,11 @@ properties: dt-binding/memory/mt6779-larb-port.h for mt6779, dt-binding/memory/mt8167-larb-port.h for mt8167, dt-binding/memory/mt8173-larb-port.h for mt8173, - dt-binding/memory/mt8183-larb-port.h for mt8183. + dt-binding/memory/mt8183-larb-port.h for mt8183, + dt-binding/memory/mt8192-larb-port.h for mt8192. + + power-domains: + maxItems: 1 required: - compatible @@ -133,11 +138,22 @@ allOf: - mediatek,mt2701-m4u - mediatek,mt2712-m4u - mediatek,mt8173-m4u + - mediatek,mt8192-m4u then: required: - clocks + - if: + properties: + compatible: + enum: + - mediatek,mt8192-m4u + + then: + required: + - power-domains + additionalProperties: false examples: diff --git a/include/dt-bindings/memory/mt8192-larb-port.h b/include/dt-bindings/memory/mt8192-larb-port.h new file mode 100644 index 000000000000..ec1ac2ba7094 --- /dev/null +++ b/include/dt-bindings/memory/mt8192-larb-port.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020 MediaTek Inc. + * + * Author: Chao Hao + * Author: Yong Wu + */ +#ifndef _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_ + +#include + +/* + * MM IOMMU: + * domain 0: display: larb0, larb1. + * domain 1: vcodec: larb4, larb5, larb7. + * domain 2: CAM/MDP: larb2, larb9, larb11, larb13, larb14, larb16, + * larb17, larb18, larb19, larb20, + * domain 3: CCU0: larb13 - port9/10. + * domain 4: CCU1: larb14 - port4/5. + * + * larb3/6/8/10/12/15 is null. + */ + +/* larb0 */ +#define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_DOM_ID(0, 0, 0) +#define M4U_PORT_L0_OVL_RDMA0_HDR MTK_M4U_DOM_ID(0, 0, 1) +#define M4U_PORT_L0_OVL_RDMA0 MTK_M4U_DOM_ID(0, 0, 2) +#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_DOM_ID(0, 0, 3) +#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_DOM_ID(0, 0, 4) +#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_DOM_ID(0, 0, 5) + +/* larb1 */ +#define M4U_PORT_L1_OVL_2L_RDMA0_HDR MTK_M4U_DOM_ID(0, 1, 0) +#define M4U_PORT_L1_OVL_2L_RDMA2_HDR MTK_M4U_DOM_ID(0, 1, 1) +#define M4U_PORT_L1_OVL_2L_RDMA0 MTK_M4U_DOM_ID(0, 1, 2) +#define M4U_PORT_L1_OVL_2L_RDMA2 MTK_M4U_DOM_ID(0, 1, 3) +#define M4U_PORT_L1_DISP_MDP_RDMA4 MTK_M4U_DOM_ID(0, 1, 4) +#define M4U_PORT_L1_DISP_RDMA4 MTK_M4U_DOM_ID(0, 1, 5) +#define M4U_PORT_L1_DISP_UFBC_WDMA0 MTK_M4U_DOM_ID(0, 1, 6) +#define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_DOM_ID(0, 1, 7) + +/* larb2 */ +#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_DOM_ID(2, 2, 0) +#define M4U_PORT_L2_MDP_RDMA1 MTK_M4U_DOM_ID(2, 2, 1) +#define M4U_PORT_L2_MDP_WROT0 MTK_M4U_DOM_ID(2, 2, 2) +#define M4U_PORT_L2_MDP_WROT1 MTK_M4U_DOM_ID(2, 2, 3) +#define M4U_PORT_L2_MDP_DISP_FAKE0 MTK_M4U_DOM_ID(2, 2, 4) + +/* larb3: null */ + +/* larb4 */ +#define M4U_PORT_L4_VDEC_MC_EXT MTK_M4U_DOM_ID(1, 4, 0) +#define M4U_PORT_L4_VDEC_UFO_EXT MTK_M4U_DOM_ID(1, 4, 1) +#define M4U_PORT_L4_VDEC_PP_EXT MTK_M4U_DOM_ID(1, 4, 2) +#define M4U_PORT_L4_VDEC_PRED_RD_EXT MTK_M4U_DOM_ID(1, 4, 3) +#define M4U_PORT_L4_VDEC_PRED_WR_EXT MTK_M4U_DOM_ID(1, 4, 4) +#define M4U_PORT_L4_VDEC_PPWRAP_EXT MTK_M4U_DOM_ID(1, 4, 5) +#define M4U_PORT_L4_VDEC_TILE_EXT MTK_M4U_DOM_ID(1, 4, 6) +#define M4U_PORT_L4_VDEC_VLD_EXT MTK_M4U_DOM_ID(1, 4, 7) +#define M4U_PORT_L4_VDEC_VLD2_EXT MTK_M4U_DOM_ID(1, 4, 8) +#define M4U_PORT_L4_VDEC_AVC_MV_EXT MTK_M4U_DOM_ID(1, 4, 9) +#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT MTK_M4U_DOM_ID(1, 4, 10) + +/* larb5 */ +#define M4U_PORT_L5_VDEC_LAT0_VLD_EXT MTK_M4U_DOM_ID(1, 5, 0) +#define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT MTK_M4U_DOM_ID(1, 5, 1) +#define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT MTK_M4U_DOM_ID(1, 5, 2) +#define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT MTK_M4U_DOM_ID(1, 5, 3) +#define M4U_PORT_L5_VDEC_LAT0_TILE_EXT MTK_M4U_DOM_ID(1, 5, 4) +#define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT MTK_M4U_DOM_ID(1, 5, 5) +#define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT MTK_M4U_DOM_ID(1, 5, 6) +#define M4U_PORT_L5_VDEC_UFO_ENC_EXT MTK_M4U_DOM_ID(1, 5, 7) + +/* larb6: null */ + +/* larb7 */ +#define M4U_PORT_L7_VENC_RCPU MTK_M4U_DOM_ID(1, 7, 0) +#define M4U_PORT_L7_VENC_REC MTK_M4U_DOM_ID(1, 7, 1) +#define M4U_PORT_L7_VENC_BSDMA MTK_M4U_DOM_ID(1, 7, 2) +#define M4U_PORT_L7_VENC_SV_COMV MTK_M4U_DOM_ID(1, 7, 3) +#define M4U_PORT_L7_VENC_RD_COMV MTK_M4U_DOM_ID(1, 7, 4) +#define M4U_PORT_L7_VENC_CUR_LUMA MTK_M4U_DOM_ID(1, 7, 5) +#define M4U_PORT_L7_VENC_CUR_CHROMA MTK_M4U_DOM_ID(1, 7, 6) +#define M4U_PORT_L7_VENC_REF_LUMA MTK_M4U_DOM_ID(1, 7, 7) +#define M4U_PORT_L7_VENC_REF_CHROMA MTK_M4U_DOM_ID(1, 7, 8) +#define M4U_PORT_L7_JPGENC_Y_RDMA MTK_M4U_DOM_ID(1, 7, 9) +#define M4U_PORT_L7_JPGENC_Q_RDMA MTK_M4U_DOM_ID(1, 7, 10) +#define M4U_PORT_L7_JPGENC_C_TABLE MTK_M4U_DOM_ID(1, 7, 11) +#define M4U_PORT_L7_JPGENC_BSDMA MTK_M4U_DOM_ID(1, 7, 12) +#define M4U_PORT_L7_VENC_SUB_R_LUMA MTK_M4U_DOM_ID(1, 7, 13) +#define M4U_PORT_L7_VENC_SUB_W_LUMA MTK_M4U_DOM_ID(1, 7, 14) + +/* larb8: null */ + +/* larb9 */ +#define M4U_PORT_L9_IMG_IMGI_D1 MTK_M4U_DOM_ID(2, 9, 0) +#define M4U_PORT_L9_IMG_IMGBI_D1 MTK_M4U_DOM_ID(2, 9, 1) +#define M4U_PORT_L9_IMG_DMGI_D1 MTK_M4U_DOM_ID(2, 9, 2) +#define M4U_PORT_L9_IMG_DEPI_D1 MTK_M4U_DOM_ID(2, 9, 3) +#define M4U_PORT_L9_IMG_ICE_D1 MTK_M4U_DOM_ID(2, 9, 4) +#define M4U_PORT_L9_IMG_SMTI_D1 MTK_M4U_DOM_ID(2, 9, 5) +#define M4U_PORT_L9_IMG_SMTO_D2 MTK_M4U_DOM_ID(2, 9, 6) +#define M4U_PORT_L9_IMG_SMTO_D1 MTK_M4U_DOM_ID(2, 9, 7) +#define M4U_PORT_L9_IMG_CRZO_D1 MTK_M4U_DOM_ID(2, 9, 8) +#define M4U_PORT_L9_IMG_IMG3O_D1 MTK_M4U_DOM_ID(2, 9, 9) +#define M4U_PORT_L9_IMG_VIPI_D1 MTK_M4U_DOM_ID(2, 9, 10) +#define M4U_PORT_L9_IMG_SMTI_D5 MTK_M4U_DOM_ID(2, 9, 11) +#define M4U_PORT_L9_IMG_TIMGO_D1 MTK_M4U_DOM_ID(2, 9, 12) +#define M4U_PORT_L9_IMG_UFBC_W0 MTK_M4U_DOM_ID(2, 9, 13) +#define M4U_PORT_L9_IMG_UFBC_R0 MTK_M4U_DOM_ID(2, 9, 14) + +/* larb10: null */ + +/* larb11 */ +#define M4U_PORT_L11_IMG_IMGI_D1 MTK_M4U_DOM_ID(2, 11, 0) +#define M4U_PORT_L11_IMG_IMGBI_D1 MTK_M4U_DOM_ID(2, 11, 1) +#define M4U_PORT_L11_IMG_DMGI_D1 MTK_M4U_DOM_ID(2, 11, 2) +#define M4U_PORT_L11_IMG_DEPI_D1 MTK_M4U_DOM_ID(2, 11, 3) +#define M4U_PORT_L11_IMG_ICE_D1 MTK_M4U_DOM_ID(2, 11, 4) +#define M4U_PORT_L11_IMG_SMTI_D1 MTK_M4U_DOM_ID(2, 11, 5) +#define M4U_PORT_L11_IMG_SMTO_D2 MTK_M4U_DOM_ID(2, 11, 6) +#define M4U_PORT_L11_IMG_SMTO_D1 MTK_M4U_DOM_ID(2, 11, 7) +#define M4U_PORT_L11_IMG_CRZO_D1 MTK_M4U_DOM_ID(2, 11, 8) +#define M4U_PORT_L11_IMG_IMG3O_D1 MTK_M4U_DOM_ID(2, 11, 9) +#define M4U_PORT_L11_IMG_VIPI_D1 MTK_M4U_DOM_ID(2, 11, 10) +#define M4U_PORT_L11_IMG_SMTI_D5 MTK_M4U_DOM_ID(2, 11, 11) +#define M4U_PORT_L11_IMG_TIMGO_D1 MTK_M4U_DOM_ID(2, 11, 12) +#define M4U_PORT_L11_IMG_UFBC_W0 MTK_M4U_DOM_ID(2, 11, 13) +#define M4U_PORT_L11_IMG_UFBC_R0 MTK_M4U_DOM_ID(2, 11, 14) +#define M4U_PORT_L11_IMG_WPE_RDMA1 MTK_M4U_DOM_ID(2, 11, 15) +#define M4U_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_DOM_ID(2, 11, 16) +#define M4U_PORT_L11_IMG_WPE_WDMA MTK_M4U_DOM_ID(2, 11, 17) +#define M4U_PORT_L11_IMG_MFB_RDMA0 MTK_M4U_DOM_ID(2, 11, 18) +#define M4U_PORT_L11_IMG_MFB_RDMA1 MTK_M4U_DOM_ID(2, 11, 19) +#define M4U_PORT_L11_IMG_MFB_RDMA2 MTK_M4U_DOM_ID(2, 11, 20) +#define M4U_PORT_L11_IMG_MFB_RDMA3 MTK_M4U_DOM_ID(2, 11, 21) +#define M4U_PORT_L11_IMG_MFB_RDMA4 MTK_M4U_DOM_ID(2, 11, 22) +#define M4U_PORT_L11_IMG_MFB_RDMA5 MTK_M4U_DOM_ID(2, 11, 23) +#define M4U_PORT_L11_IMG_MFB_WDMA0 MTK_M4U_DOM_ID(2, 11, 24) +#define M4U_PORT_L11_IMG_MFB_WDMA1 MTK_M4U_DOM_ID(2, 11, 25) + +/* larb12: null */ + +/* larb13 */ +#define M4U_PORT_L13_CAM_MRAWI MTK_M4U_DOM_ID(2, 13, 0) +#define M4U_PORT_L13_CAM_MRAWO0 MTK_M4U_DOM_ID(2, 13, 1) +#define M4U_PORT_L13_CAM_MRAWO1 MTK_M4U_DOM_ID(2, 13, 2) +#define M4U_PORT_L13_CAM_CAMSV1 MTK_M4U_DOM_ID(2, 13, 3) +#define M4U_PORT_L13_CAM_CAMSV2 MTK_M4U_DOM_ID(2, 13, 4) +#define M4U_PORT_L13_CAM_CAMSV3 MTK_M4U_DOM_ID(2, 13, 5) +#define M4U_PORT_L13_CAM_CAMSV4 MTK_M4U_DOM_ID(2, 13, 6) +#define M4U_PORT_L13_CAM_CAMSV5 MTK_M4U_DOM_ID(2, 13, 7) +#define M4U_PORT_L13_CAM_CAMSV6 MTK_M4U_DOM_ID(2, 13, 8) +#define M4U_PORT_L13_CAM_CCUI MTK_M4U_DOM_ID(3, 13, 9) +#define M4U_PORT_L13_CAM_CCUO MTK_M4U_DOM_ID(3, 13, 10) +#define M4U_PORT_L13_CAM_FAKE MTK_M4U_DOM_ID(2, 13, 11) + +/* larb14 */ +#define M4U_PORT_L14_CAM_RESERVE1 MTK_M4U_DOM_ID(2, 14, 0) +#define M4U_PORT_L14_CAM_RESERVE2 MTK_M4U_DOM_ID(2, 14, 1) +#define M4U_PORT_L14_CAM_RESERVE3 MTK_M4U_DOM_ID(2, 14, 2) +#define M4U_PORT_L14_CAM_CAMSV0 MTK_M4U_DOM_ID(2, 14, 3) +#define M4U_PORT_L14_CAM_CCUI MTK_M4U_DOM_ID(4, 14, 4) +#define M4U_PORT_L14_CAM_CCUO MTK_M4U_DOM_ID(4, 14, 5) + +/* larb15: null */ + +/* larb16 */ +#define M4U_PORT_L16_CAM_IMGO_R1_A MTK_M4U_DOM_ID(2, 16, 0) +#define M4U_PORT_L16_CAM_RRZO_R1_A MTK_M4U_DOM_ID(2, 16, 1) +#define M4U_PORT_L16_CAM_CQI_R1_A MTK_M4U_DOM_ID(2, 16, 2) +#define M4U_PORT_L16_CAM_BPCI_R1_A MTK_M4U_DOM_ID(2, 16, 3) +#define M4U_PORT_L16_CAM_YUVO_R1_A MTK_M4U_DOM_ID(2, 16, 4) +#define M4U_PORT_L16_CAM_UFDI_R2_A MTK_M4U_DOM_ID(2, 16, 5) +#define M4U_PORT_L16_CAM_RAWI_R2_A MTK_M4U_DOM_ID(2, 16, 6) +#define M4U_PORT_L16_CAM_RAWI_R3_A MTK_M4U_DOM_ID(2, 16, 7) +#define M4U_PORT_L16_CAM_AAO_R1_A MTK_M4U_DOM_ID(2, 16, 8) +#define M4U_PORT_L16_CAM_AFO_R1_A MTK_M4U_DOM_ID(2, 16, 9) +#define M4U_PORT_L16_CAM_FLKO_R1_A MTK_M4U_DOM_ID(2, 16, 10) +#define M4U_PORT_L16_CAM_LCESO_R1_A MTK_M4U_DOM_ID(2, 16, 11) +#define M4U_PORT_L16_CAM_CRZO_R1_A MTK_M4U_DOM_ID(2, 16, 12) +#define M4U_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_DOM_ID(2, 16, 13) +#define M4U_PORT_L16_CAM_RSSO_R1_A MTK_M4U_DOM_ID(2, 16, 14) +#define M4U_PORT_L16_CAM_AAHO_R1_A MTK_M4U_DOM_ID(2, 16, 15) +#define M4U_PORT_L16_CAM_LSCI_R1_A MTK_M4U_DOM_ID(2, 16, 16) + +/* larb17 */ +#define M4U_PORT_L17_CAM_IMGO_R1_B MTK_M4U_DOM_ID(2, 17, 0) +#define M4U_PORT_L17_CAM_RRZO_R1_B MTK_M4U_DOM_ID(2, 17, 1) +#define M4U_PORT_L17_CAM_CQI_R1_B MTK_M4U_DOM_ID(2, 17, 2) +#define M4U_PORT_L17_CAM_BPCI_R1_B MTK_M4U_DOM_ID(2, 17, 3) +#define M4U_PORT_L17_CAM_YUVO_R1_B MTK_M4U_DOM_ID(2, 17, 4) +#define M4U_PORT_L17_CAM_UFDI_R2_B MTK_M4U_DOM_ID(2, 17, 5) +#define M4U_PORT_L17_CAM_RAWI_R2_B MTK_M4U_DOM_ID(2, 17, 6) +#define M4U_PORT_L17_CAM_RAWI_R3_B MTK_M4U_DOM_ID(2, 17, 7) +#define M4U_PORT_L17_CAM_AAO_R1_B MTK_M4U_DOM_ID(2, 17, 8) +#define M4U_PORT_L17_CAM_AFO_R1_B MTK_M4U_DOM_ID(2, 17, 9) +#define M4U_PORT_L17_CAM_FLKO_R1_B MTK_M4U_DOM_ID(2, 17, 10) +#define M4U_PORT_L17_CAM_LCESO_R1_B MTK_M4U_DOM_ID(2, 17, 11) +#define M4U_PORT_L17_CAM_CRZO_R1_B MTK_M4U_DOM_ID(2, 17, 12) +#define M4U_PORT_L17_CAM_LTMSO_R1_B MTK_M4U_DOM_ID(2, 17, 13) +#define M4U_PORT_L17_CAM_RSSO_R1_B MTK_M4U_DOM_ID(2, 17, 14) +#define M4U_PORT_L17_CAM_AAHO_R1_B MTK_M4U_DOM_ID(2, 17, 15) +#define M4U_PORT_L17_CAM_LSCI_R1_B MTK_M4U_DOM_ID(2, 17, 16) + +/* larb18 */ +#define M4U_PORT_L18_CAM_IMGO_R1_C MTK_M4U_DOM_ID(2, 18, 0) +#define M4U_PORT_L18_CAM_RRZO_R1_C MTK_M4U_DOM_ID(2, 18, 1) +#define M4U_PORT_L18_CAM_CQI_R1_C MTK_M4U_DOM_ID(2, 18, 2) +#define M4U_PORT_L18_CAM_BPCI_R1_C MTK_M4U_DOM_ID(2, 18, 3) +#define M4U_PORT_L18_CAM_YUVO_R1_C MTK_M4U_DOM_ID(2, 18, 4) +#define M4U_PORT_L18_CAM_UFDI_R2_C MTK_M4U_DOM_ID(2, 18, 5) +#define M4U_PORT_L18_CAM_RAWI_R2_C MTK_M4U_DOM_ID(2, 18, 6) +#define M4U_PORT_L18_CAM_RAWI_R3_C MTK_M4U_DOM_ID(2, 18, 7) +#define M4U_PORT_L18_CAM_AAO_R1_C MTK_M4U_DOM_ID(2, 18, 8) +#define M4U_PORT_L18_CAM_AFO_R1_C MTK_M4U_DOM_ID(2, 18, 9) +#define M4U_PORT_L18_CAM_FLKO_R1_C MTK_M4U_DOM_ID(2, 18, 10) +#define M4U_PORT_L18_CAM_LCESO_R1_C MTK_M4U_DOM_ID(2, 18, 11) +#define M4U_PORT_L18_CAM_CRZO_R1_C MTK_M4U_DOM_ID(2, 18, 12) +#define M4U_PORT_L18_CAM_LTMSO_R1_C MTK_M4U_DOM_ID(2, 18, 13) +#define M4U_PORT_L18_CAM_RSSO_R1_C MTK_M4U_DOM_ID(2, 18, 14) +#define M4U_PORT_L18_CAM_AAHO_R1_C MTK_M4U_DOM_ID(2, 18, 15) +#define M4U_PORT_L18_CAM_LSCI_R1_C MTK_M4U_DOM_ID(2, 18, 16) + +/* larb19 */ +#define M4U_PORT_L19_IPE_DVS_RDMA MTK_M4U_DOM_ID(2, 19, 0) +#define M4U_PORT_L19_IPE_DVS_WDMA MTK_M4U_DOM_ID(2, 19, 1) +#define M4U_PORT_L19_IPE_DVP_RDMA MTK_M4U_DOM_ID(2, 19, 2) +#define M4U_PORT_L19_IPE_DVP_WDMA MTK_M4U_DOM_ID(2, 19, 3) + +/* larb20 */ +#define M4U_PORT_L20_IPE_FDVT_RDA MTK_M4U_DOM_ID(2, 20, 0) +#define M4U_PORT_L20_IPE_FDVT_RDB MTK_M4U_DOM_ID(2, 20, 1) +#define M4U_PORT_L20_IPE_FDVT_WRA MTK_M4U_DOM_ID(2, 20, 2) +#define M4U_PORT_L20_IPE_FDVT_WRB MTK_M4U_DOM_ID(2, 20, 3) +#define M4U_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_DOM_ID(2, 20, 4) +#define M4U_PORT_L20_IPE_RSC_WDMA MTK_M4U_DOM_ID(2, 20, 5) + +#endif