From patchwork Thu Dec 3 13:34:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1410413 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=gdWUdjwx; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CmxhQ5Cqzz9sXd for ; Fri, 4 Dec 2020 00:36:54 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2436936AbgLCNfv (ORCPT ); Thu, 3 Dec 2020 08:35:51 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:17819 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2437051AbgLCNfs (ORCPT ); Thu, 3 Dec 2020 08:35:48 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Thu, 03 Dec 2020 05:35:07 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 3 Dec 2020 13:35:03 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Thu, 3 Dec 2020 13:35:00 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , , Subject: [PATCH V5 1/5] PCI: tegra: Fix ASPM-L1SS advertisement disable code Date: Thu, 3 Dec 2020 19:04:47 +0530 Message-ID: <20201203133451.17716-2-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201203133451.17716-1-vidyas@nvidia.com> References: <20201203133451.17716-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1607002507; bh=BFek7vJlaZbrownN3cTAQ+IV1PMfDMjoJ5+0cXFWPq0=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=gdWUdjwxas0SmsqWfjKaTyJd5HToix6Xtl6KFDsOgeCywv+NscQ7pHuHkM0lhfnBc 2pG41qOJXmmC4KflZYRyK+1MNbfKZvQacfcimA8nBkzRNGNAVyLb4K1M2uRH/19viB 667Gr36e+KVheMuo2kvg30BwKGB6tLPjPIhlzW1Ec0BHWf7ryPco7Cj0A+MZcwuNlx hLDtV7dv8gUDryHjmBT3CaGYt7s3MQjHANlSKb6oroK3L7Ovu3p2VmOHCtOB/4qXcy xgyR2Om49uW/PiqbuwpeMoTDORUzyMI04n77KobNT0yA+le35Z8DvkCV99cvb1XB0i orLtIiy0Tn0EA== Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org If the absence of CLKREQ# signal is indicated by the absence of "supports-clkreq" in the device-tree node, current driver is disabling the advertisement of ASPM-L1 Sub-States *before* the ASPM-L1 Sub-States offset is correctly initialized. Since default value of the ASPM-L1SS offset is zero, this is causing the Vendor-ID wrongly programmed to 0x10d2 instead of Nvidia's 0x10de thereby the quirks applicable for Tegra194 are not being applied. This patch fixes this issue by refactoring the code that disables the ASPM-L1SS advertisement. Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Vidya Sagar --- V5: * Rebased on top of the tree code V4: * None V3: * None V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 648e731bccfa..4c966e9adb2b 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -863,12 +863,6 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp) pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); - /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ - if (!pcie->supports_clkreq) { - disable_aspm_l11(pcie); - disable_aspm_l12(pcie); - } - val = dw_pcie_readl_dbi(pci, PCI_IO_BASE); val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8); dw_pcie_writel_dbi(pci, PCI_IO_BASE, val); @@ -897,6 +891,12 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp) init_host_aspm(pcie); + /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ + if (!pcie->supports_clkreq) { + disable_aspm_l11(pcie); + disable_aspm_l12(pcie); + } + val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); From patchwork Thu Dec 3 13:34:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1410415 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=PvPeQ3/Y; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CmxhS6mXhz9sXS for ; Fri, 4 Dec 2020 00:36:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2437173AbgLCNf5 (ORCPT ); Thu, 3 Dec 2020 08:35:57 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:15235 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2437051AbgLCNf4 (ORCPT ); Thu, 3 Dec 2020 08:35:56 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Thu, 03 Dec 2020 05:35:16 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 3 Dec 2020 13:35:14 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Thu, 3 Dec 2020 13:35:10 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , , Subject: [PATCH V5 2/5] PCI: tegra: Set DesignWare IP version Date: Thu, 3 Dec 2020 19:04:48 +0530 Message-ID: <20201203133451.17716-3-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201203133451.17716-1-vidyas@nvidia.com> References: <20201203133451.17716-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1607002516; bh=9xJCFbRLjmFSLiJtC9Hodz4spFE7fDQoE22+vvQYdWM=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=PvPeQ3/YJ15PpOUhN9Zk9MjTF6j51mUIyC+glTZA2Mrg+hMVq12c/Kv0wrL9CTVWm Js77ajnIsVNdCQFMkD8DFeEXjkKideZnKHIZZ1YerY8iobDLUSVCv2QwNPj3iei6P7 1SKN+24ufUDZcx8GBuZcN4bhA5C3EByf+YhYdeC57pd3MwXlqrwzkiXSJEpG+b1DrV 1Ty4eB5l8mV/4RlkOz4PJ8/d8qqRCpVi9GIp9YCTGspDXNYxZSDTdC8VlezH7DEwCF iBmkON5rjRcXaeqC95c5eFA1lsGltzx4nPjQlrMRzooCeOdALyVUirD8KLVg5IXLeH vna4nISSrjqHg== Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Set the DesignWare IP version for Tegra194 to 0x490A. This would be used by the DesigWare sub-system to do any version specific configuration (Ex:- TD bit programming for ECRC). Tested-by: Thierry Reding Signed-off-by: Vidya Sagar Acked-by: Thierry Reding --- V5: * Added Tested-by and Acked-by from Thierry Reding V4: * None V3: * None V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 4c966e9adb2b..59163b735c96 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1984,6 +1984,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) pci->ops = &tegra_dw_pcie_ops; pci->n_fts[0] = N_FTS_VAL; pci->n_fts[1] = FTS_VAL; + pci->version = 0x490A; pp = &pci->pp; pp->num_vectors = MAX_MSI_IRQS; From patchwork Thu Dec 3 13:34:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1410418 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=r7/XY33E; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CmxhZ1hjLz9sWY for ; Fri, 4 Dec 2020 00:37:02 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2437189AbgLCNgJ (ORCPT ); Thu, 3 Dec 2020 08:36:09 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:1686 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2436676AbgLCNgH (ORCPT ); Thu, 3 Dec 2020 08:36:07 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Thu, 03 Dec 2020 05:35:26 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 3 Dec 2020 13:35:23 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Thu, 3 Dec 2020 13:35:20 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , , Subject: [PATCH V5 3/5] PCI: tegra: Continue unconfig sequence even if parts fail Date: Thu, 3 Dec 2020 19:04:49 +0530 Message-ID: <20201203133451.17716-4-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201203133451.17716-1-vidyas@nvidia.com> References: <20201203133451.17716-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1607002526; bh=uES3XIrwD3FA2DwwQr0e/GhmJLQIg4AE4uT2d2D9XMM=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=r7/XY33EYrG/A8us8UnJlSVVrPw9Oq/qF0Q2w0TLAswlVrk+H2me9KT5e6d18s37z EE/pD60l+aFwTtyC8QZlx138xOUD41KiWHt0tHH/jd3bmUkId3CG3zsRY3wRrrqrxt eG3w2ZsZvs5F94FkrjwVPhOIs6q3oKuZSAWTLYmEgb7/8x14XOmHw6D9C1+rUyKmoH Q6N2wiF0sH01aFgS2ZfyYQ5x5To+t5h2PVoczIAEbtxDBT9CEL5zauun6TAviUsMwh PiAid3xF+v4mV9r+eYX0JzGchuQsXGl097+YgP/ijXLkEMwhw3x5SJ25Ew//s4ekeP Ch0pYEsUBfHUg== Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Currently the driver checks for error value of different APIs during the uninitialization sequence. It just returns from there if there is any error observed for one of those calls. Comparatively it is better to continue the uninitialization sequence irrespective of whether some of them are returning error. That way, it is more closer to complete uninitialization. Tested-by: Thierry Reding Signed-off-by: Vidya Sagar Acked-by: Thierry Reding --- V5: * Added Tested-by and Acked-by from Thierry Reding V4: * None V3: * Modified subject as per Bjorn's suggestion * Removed tegra_pcie_init_controller()'s error checking part and pushed a separate patch for it V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 39 +++++++++------------- 1 file changed, 15 insertions(+), 24 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 59163b735c96..471c6d725c70 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1415,43 +1415,32 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, return ret; } -static int __deinit_controller(struct tegra_pcie_dw *pcie) +static void tegra_pcie_unconfig_controller(struct tegra_pcie_dw *pcie) { int ret; ret = reset_control_assert(pcie->core_rst); - if (ret) { - dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", - ret); - return ret; - } + if (ret) + dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", ret); tegra_pcie_disable_phy(pcie); ret = reset_control_assert(pcie->core_apb_rst); - if (ret) { + if (ret) dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret); - return ret; - } clk_disable_unprepare(pcie->core_clk); ret = regulator_disable(pcie->pex_ctl_supply); - if (ret) { + if (ret) dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret); - return ret; - } tegra_pcie_disable_slot_regulators(pcie); ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false); - if (ret) { + if (ret) dev_err(pcie->dev, "Failed to disable controller %d: %d\n", pcie->cid, ret); - return ret; - } - - return ret; } static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie) @@ -1475,7 +1464,8 @@ static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie) return 0; fail_host_init: - return __deinit_controller(pcie); + tegra_pcie_unconfig_controller(pcie); + return ret; } static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie) @@ -1544,13 +1534,12 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) appl_writel(pcie, data, APPL_PINMUX); } -static int tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) +static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) { tegra_pcie_downstream_dev_to_D0(pcie); dw_pcie_host_deinit(&pcie->pci.pp); tegra_pcie_dw_pme_turnoff(pcie); - - return __deinit_controller(pcie); + tegra_pcie_unconfig_controller(pcie); } static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) @@ -2197,8 +2186,9 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev) PORT_LOGIC_MSI_CTRL_INT_0_EN); tegra_pcie_downstream_dev_to_D0(pcie); tegra_pcie_dw_pme_turnoff(pcie); + tegra_pcie_unconfig_controller(pcie); - return __deinit_controller(pcie); + return 0; } static int tegra_pcie_dw_resume_noirq(struct device *dev) @@ -2226,7 +2216,8 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev) return 0; fail_host_init: - return __deinit_controller(pcie); + tegra_pcie_unconfig_controller(pcie); + return ret; } static int tegra_pcie_dw_resume_early(struct device *dev) @@ -2264,7 +2255,7 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev) disable_irq(pcie->pci.pp.msi_irq); tegra_pcie_dw_pme_turnoff(pcie); - __deinit_controller(pcie); + tegra_pcie_unconfig_controller(pcie); } static const struct tegra_pcie_dw_of_data tegra_pcie_dw_rc_of_data = { From patchwork Thu Dec 3 13:34:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1410422 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=Sv5rUZow; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Cmxhh5rN3z9sXS for ; Fri, 4 Dec 2020 00:37:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2437005AbgLCNgS (ORCPT ); Thu, 3 Dec 2020 08:36:18 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:1738 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2437200AbgLCNgN (ORCPT ); Thu, 3 Dec 2020 08:36:13 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Thu, 03 Dec 2020 05:35:33 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 3 Dec 2020 13:35:30 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Thu, 3 Dec 2020 13:35:26 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , , Subject: [PATCH V5 4/5] PCI: tegra: Check return value of tegra_pcie_init_controller() Date: Thu, 3 Dec 2020 19:04:50 +0530 Message-ID: <20201203133451.17716-5-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201203133451.17716-1-vidyas@nvidia.com> References: <20201203133451.17716-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1607002533; bh=BTzR7woRzzvRS3LBZ31mu1SNUmEESjnajUG8HVArlEM=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=Sv5rUZowcqV6/czAkhbk41+JPfgsVr+9GC4rnO1lG8o8DRksvqZlIsXnfCdfayarg FlPfsUXRAKeL/LT39qNAWDu4mJ15ajF35RY44f6GLKbsGCznPLF/7t7pr1XiFK6Yf4 YcmbyRe/uuWp7+Qd9QV+9NkEFxgyWyHWO5zggsP8J5o0H21OOlREPKQ8f4kFN/sJ3w QGAmpKdIzONthv4iAlx5rWJHbtm/5Cag0o6dko8VD23tnqLf5Nhl3P9YTFTYKgOySD 3Y7zcL1puUZQnqYehIwh/9Dy1SB1XxGpUy/z+F65Z/9/8TUyTBbKvgZIviY60vwLdn 6s50s80aywfyA== Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The return value of tegra_pcie_init_controller() must be checked before PCIe link up check and registering debugfs entries subsequently as it doesn't make sense to do these when the controller initialization itself has failed. Tested-by: Thierry Reding Signed-off-by: Vidya Sagar Acked-by: Thierry Reding --- V5: * Added Tested-by and Acked-by from Thierry Reding V4: * None V3: * New patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 471c6d725c70..f4109d71f20b 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1563,7 +1563,11 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) goto fail_pm_get_sync; } - tegra_pcie_init_controller(pcie); + ret = tegra_pcie_init_controller(pcie); + if (ret < 0) { + dev_err(dev, "Failed to initialize controller: %d\n", ret); + goto fail_pm_get_sync; + } pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); if (!pcie->link_state) { From patchwork Thu Dec 3 13:34:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1410420 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=HGh5gkIB; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Cmxhc506cz9sXf for ; Fri, 4 Dec 2020 00:37:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2437216AbgLCNgW (ORCPT ); Thu, 3 Dec 2020 08:36:22 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:1789 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2437207AbgLCNgV (ORCPT ); Thu, 3 Dec 2020 08:36:21 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Thu, 03 Dec 2020 05:35:41 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 3 Dec 2020 13:35:36 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Thu, 3 Dec 2020 13:35:33 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , , Subject: [PATCH V5 5/5] PCI: tegra: Disable LTSSM during L2 entry Date: Thu, 3 Dec 2020 19:04:51 +0530 Message-ID: <20201203133451.17716-6-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201203133451.17716-1-vidyas@nvidia.com> References: <20201203133451.17716-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1607002541; bh=FzOTD9Je2Yb9E4ZN56eudlZMA2FxlWvUtl9VQXv+GOA=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=HGh5gkIBOrXR5PJjElyACgO0DgKyFHJsX5F54nDbKrnXRswivgXyxNsUCb/mCokBc ZET/9ku76GNr5W2VN+OeFF2yQQkGGJdYHzpdbKqiiIDtHbZXuvIIZRbZdAV2qku0VE krk+vDrsd20yMJCSqHTj5mD5Hfa5GPFvOIk9qZUL2ZYlJr2V+z0gB4pVM4qBexjgJ0 JIVJelMgGza+DuctzTGnKGD/QUIyVdA64Uo+EmHFZbG1L5khatmk3sphVbJFztazpT 6Vq8AnSzROH98OmQQQqhigtXyLQFrt9wRvp+W3Wuo36Q79QLYO1FUJiZtKAJ2Sza9l h/uISq3u4FWTQ== Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org PCIe cards like Marvell SATA controller and some of the Samsung NVMe drives don't support taking the link to L2 state. When the link doesn't go to L2 state, Tegra194 requires the LTSSM to be disabled to allow PHY to start the next link up process cleanly during suspend/resume sequence. Failing to disable LTSSM results in the PCIe link not coming up in the next resume cycle. Tested-by: Thierry Reding Signed-off-by: Vidya Sagar Acked-by: Thierry Reding --- V5: * Added Tested-by and Acked-by from Thierry Reding V4: * New patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index f4109d71f20b..5597b2a49598 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1506,6 +1506,14 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) data &= ~APPL_PINMUX_PEX_RST; appl_writel(pcie, data, APPL_PINMUX); + /* + * Some cards do not go to detect state even after de-asserting + * PERST#. So, de-assert LTSSM to bring link to detect state. + */ + data = readl(pcie->appl_base + APPL_CTRL); + data &= ~APPL_CTRL_LTSSM_EN; + writel(data, pcie->appl_base + APPL_CTRL); + err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, data, ((data & @@ -1513,14 +1521,8 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) APPL_DEBUG_LTSSM_STATE_SHIFT) == LTSSM_STATE_PRE_DETECT, 1, LTSSM_TIMEOUT); - if (err) { + if (err) dev_info(pcie->dev, "Link didn't go to detect state\n"); - } else { - /* Disable LTSSM after link is in detect state */ - data = appl_readl(pcie, APPL_CTRL); - data &= ~APPL_CTRL_LTSSM_EN; - appl_writel(pcie, data, APPL_CTRL); - } } /* * DBI registers may not be accessible after this as PLL-E would be