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Mon, 30 Nov 2020 10:36:36 +0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06avi18878370.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 0AUAaYW451577112 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 30 Nov 2020 10:36:34 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7394411C058; Mon, 30 Nov 2020 10:36:34 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A146511C052; Mon, 30 Nov 2020 10:36:32 +0000 (GMT) Received: from KewenLins-MacBook-Pro.local (unknown [9.197.231.10]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 30 Nov 2020 10:36:32 +0000 (GMT) Subject: [PATCH v2] rs6000: Disable HTM for Power10 and later To: Segher Boessenkool , GCC Patches References: <84e1df49-0509-461a-f5dd-765de1b83610@linux.ibm.com> <20201126211159.GF2672@gate.crashing.org> Message-ID: Date: Mon, 30 Nov 2020 18:36:30 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.0; rv:68.0) Gecko/20100101 Thunderbird/68.9.0 MIME-Version: 1.0 In-Reply-To: <20201126211159.GF2672@gate.crashing.org> Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-30_02:2020-11-30, 2020-11-30 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 impostorscore=0 mlxscore=0 suspectscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011300063 X-Spam-Status: No, score=-9.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, MIME_CHARSET_FARAWAY, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Kewen.Lin via Gcc-patches" From: "Kewen.Lin" Reply-To: "Kewen.Lin" Cc: Bill Schmidt , David Edelsohn Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi Segher, on 2020/11/27 上午5:11, Segher Boessenkool wrote: > Hi! > > On Thu, Nov 26, 2020 at 06:15:04PM +0800, Kewen.Lin wrote: >> During previous Power10 testing, I noticed that ISA 3.1 has >> dropped TM support. I think we should not generate TM >> related instructions for Power10 and later, or no? >> >> This patch is to turn off HTM support once we know the cpu >> setting is power10 or later, and warn something if the >> explicit option -mhtm is specified. > > We currently enable OPTION_MASK_HTM in ISA_2_7_MASKS_SERVER (in > rs6000-cpus.def), and include that in all later CPUs/archs. > > Could you fix it there instead? Easiest and most obvious is to just > add HTM to the power8, power9, and powerpc64le entries. > Thanks for the comments! The attached patch followed your suggestion. Does it look better? Bootstrapped/regtested on powerpc64le-linux-gnu P8 and P10. BR, Kewen ----- gcc/ChangeLog: * config/rs6000/rs6000.c (rs6000_option_override_internal): Use OPTION_MASK_CRYPTO for Power8 target_enable check instead of OPTION_MASK_HTM. * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove OPTION_MASK_HTM. (RS6000_CPU): Add OPTION_MASK_HTM to power8, power9 and powerpc64le entries. diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 8d2c1ffd6cf..482e1b69dde 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -51,7 +51,6 @@ | OPTION_MASK_CRYPTO \ | OPTION_MASK_DIRECT_MOVE \ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ - | OPTION_MASK_HTM \ | OPTION_MASK_QUAD_MEMORY \ | OPTION_MASK_QUAD_MEMORY_ATOMIC) @@ -240,10 +239,13 @@ RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER) -RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) -RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER) +RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER + | OPTION_MASK_HTM) +RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER + | OPTION_MASK_HTM) RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) +RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER + | OPTION_MASK_HTM) RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index d8ac2f0cd2f..4f625d98078 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3807,7 +3807,8 @@ rs6000_option_override_internal (bool global_init_p) /* If little-endian, default to -mstrict-align on older processors. Testing for htm matches power8 and later. */ if (!BYTES_BIG_ENDIAN - && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM)) + && !(processor_target_table[tune_index].target_enable + & OPTION_MASK_CRYPTO)) rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN; if (!rs6000_fold_gimple)