From patchwork Sun Nov 29 10:39:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean Pihet X-Patchwork-Id: 1407910 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=newoldbits.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=newoldbits-com.20150623.gappssmtp.com header.i=@newoldbits-com.20150623.gappssmtp.com header.a=rsa-sha256 header.s=20150623 header.b=1LjtyMQ8; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ckldt3ZJJz9sVH for ; Mon, 30 Nov 2020 10:57:06 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BCD3182618; Mon, 30 Nov 2020 00:56:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=newoldbits.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=newoldbits-com.20150623.gappssmtp.com header.i=@newoldbits-com.20150623.gappssmtp.com header.b="1LjtyMQ8"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1430582738; Sun, 29 Nov 2020 11:40:08 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 340F982738 for ; Sun, 29 Nov 2020 11:40:04 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=newoldbits.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jean.pihet@newoldbits.com Received: by mail-ej1-x642.google.com with SMTP id x16so7935776ejj.7 for ; Sun, 29 Nov 2020 02:40:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=newoldbits-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=eMZvyPbUgHBEesVH865FSKBnYQD92Xa/zchNx3oSdVU=; b=1LjtyMQ8TaQ8c5rOgVkrnx+z3u41hiQ9LAzuOizD4D3bGyG/uMrAbVtiHPn1XkuIbC F3pe1YbQIBq0wZPSq8v2FGxz0iVvd7c1oENyXLQ4lDOn6PVBOzdLMnYwjKwHK0mhAkZC +G69qXdXmT8AYYryWb6nk9JEd9CsOEjBY3Iq+J8DlX+OVGHnmh7bbZQK0aR8shxUE26E 6Q8tMssGFu5wlvyeBAaNFXxihbolE/SzM/VZIHbdJdXKLEM0+NFc8uT474cxurUTXeKR /xXXptbmPH1heR9Hg0b9PNDtSb+1y+okVS5MI3S2gnVWjCV16lCiRK404OwcgGaEZ1s7 fQqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=eMZvyPbUgHBEesVH865FSKBnYQD92Xa/zchNx3oSdVU=; b=cDnQ2u17zpn68yZgNS9sK2fcjfzRftbZYDOCD9AFJQ5dmYMri/NSjsFleKOrnAH9eK HC8DjSf/Vr0AvinBFORRlFukG1N0E2V+dF6ojyf9o3yJlB5iF///bz7uL/XTTWqTKq6I WLsr3TkVOzDzhHOPpx6VYz8gCkTsOLENGoxc4digcMsACe2wBDyKloksZJXi3gBscoa4 Uo97lAkd8Hp7w+1UoHdd3K1IqVwK1ksro1wP5l6beF7dc1yecoV0jueJTsEHVQIvh2/4 OnD/8x0YzdSz26koI/c1f6ARQFZeAZa8+bSiqovglrt1b6j4Tz04j+t4z1Xectep7LJw njMg== X-Gm-Message-State: AOAM5305fn3x730dAIpr04xY1dE7Pdx4gw8jWF/CeAs+qLYPG0y45hgT 0qqhkEG/8GfAXo3Nean2pFtLyuLMcSi4Xg== X-Google-Smtp-Source: ABdhPJwbSjfaj6cY1iXquRD7gfJwslkFB8l1UZ0vd479/s/J4/qrZoQYT1gDtii79hMDpv3zetsx+A== X-Received: by 2002:a17:906:c04d:: with SMTP id bm13mr15738264ejb.519.1606646403403; Sun, 29 Nov 2020 02:40:03 -0800 (PST) Received: from nuc1.lan (208.2-240-81.adsl-dyn.isp.belgacom.be. [81.240.2.208]) by smtp.gmail.com with ESMTPSA id w3sm7667691edt.84.2020.11.29.02.40.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Nov 2020 02:40:02 -0800 (PST) From: Jean Pihet To: u-boot@lists.denx.de Cc: Ryan Barnett , Conrad Ratschan , Hugo Cornelis , Arnout Vandecappelle , Jean Pihet Subject: [PATCH 1/3] mtd: spi nor: add support for dual and quad bit transfers Date: Sun, 29 Nov 2020 11:39:46 +0100 Message-Id: <20201129103948.158293-1-jean.pihet@newoldbits.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-Mailman-Approved-At: Mon, 30 Nov 2020 00:56:47 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Use the flags field of the SPI slave struct to pass the dual and quad read properties, from the SPI NOR layer to the low level driver. Tested with TI QSPI in 1, 2 and 4 bits modes. Signed-off-by: Jean Pihet --- drivers/mtd/spi/spi-nor-core.c | 34 +++++++++++++++++++++++++++++++--- drivers/spi/spi-mem.c | 8 +++++++- include/spi.h | 2 ++ 3 files changed, 40 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index e16b0e1462..54569b3cba 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -94,22 +94,50 @@ static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, /* convert the dummy cycles to the number of bytes */ op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; + /* Check for dual and quad I/O read */ + switch (op.cmd.opcode) { + case SPINOR_OP_READ_1_1_2: + case SPINOR_OP_READ_1_2_2: + case SPINOR_OP_READ_1_1_2_4B: + case SPINOR_OP_READ_1_2_2_4B: + case SPINOR_OP_READ_1_2_2_DTR: + case SPINOR_OP_READ_1_2_2_DTR_4B: + nor->spi->flags |= SPI_XFER_DUAL_READ; + break; + case SPINOR_OP_READ_1_1_4: + case SPINOR_OP_READ_1_4_4: + case SPINOR_OP_READ_1_1_4_4B: + case SPINOR_OP_READ_1_4_4_4B: + case SPINOR_OP_READ_1_4_4_DTR: + case SPINOR_OP_READ_1_4_4_DTR_4B: + nor->spi->flags |= SPI_XFER_QUAD_READ; + break; + default: + break; + } + while (remaining) { op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX; ret = spi_mem_adjust_op_size(nor->spi, &op); if (ret) - return ret; + goto out; ret = spi_mem_exec_op(nor->spi, &op); if (ret) - return ret; + goto out; op.addr.val += op.data.nbytes; remaining -= op.data.nbytes; op.data.buf.in += op.data.nbytes; } - return len; + ret = len; + +out: + /* Reset dual and quad I/O read flags for upcoming transactions */ + nor->spi->flags &= ~(SPI_XFER_DUAL_READ | SPI_XFER_QUAD_READ); + + return ret; } static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index c095ae9505..24e38ea95e 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -387,9 +387,15 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) return ret; /* 2nd transfer: rx or tx data path */ + flag = SPI_XFER_END; + /* Check for dual and quad I/O reads */ + if (slave->flags & SPI_XFER_DUAL_READ) + flag |= SPI_XFER_DUAL_READ; + if (slave->flags & SPI_XFER_QUAD_READ) + flag |= SPI_XFER_QUAD_READ; if (tx_buf || rx_buf) { ret = spi_xfer(slave, op->data.nbytes * 8, tx_buf, - rx_buf, SPI_XFER_END); + rx_buf, flag); if (ret) return ret; } diff --git a/include/spi.h b/include/spi.h index ef8c1f6692..cf5f05e526 100644 --- a/include/spi.h +++ b/include/spi.h @@ -146,6 +146,8 @@ struct spi_slave { #define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */ #define SPI_XFER_END BIT(1) /* Deassert CS after transfer */ #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) +#define SPI_XFER_DUAL_READ BIT(2) /* Dual I/O read */ +#define SPI_XFER_QUAD_READ BIT(3) /* Quad I/O read */ }; /** From patchwork Sun Nov 29 10:39:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean Pihet X-Patchwork-Id: 1407911 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[81.240.2.208]) by smtp.gmail.com with ESMTPSA id w3sm7667691edt.84.2020.11.29.02.40.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Nov 2020 02:40:03 -0800 (PST) From: Jean Pihet To: u-boot@lists.denx.de Cc: Ryan Barnett , Conrad Ratschan , Hugo Cornelis , Arnout Vandecappelle , Jean Pihet Subject: [PATCH 2/3] TI QSPI: add support for dual and quad-bit I/O read Date: Sun, 29 Nov 2020 11:39:47 +0100 Message-Id: <20201129103948.158293-2-jean.pihet@newoldbits.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201129103948.158293-1-jean.pihet@newoldbits.com> References: <20201129103948.158293-1-jean.pihet@newoldbits.com> MIME-Version: 1.0 X-Mailman-Approved-At: Mon, 30 Nov 2020 00:56:47 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean TI QSPI: the TI QSPI IP has a limitation of 64MB of MMIO so use the MMIO mode to read below 64MB and fallback to the SW generated sequences to read above 64MB. The TI QSPI IP has another limitation of 4096 words per frame, so split the accesses into smaller ones. Also fix the TI QSPI operating frequency in order to correctly generate the required SPI CLK frequency. Signed-off-by: Jean Pihet --- drivers/spi/Kconfig | 9 ++++++ drivers/spi/ti_qspi.c | 68 ++++++++++++++++++++++++++++++++++++------- 2 files changed, 66 insertions(+), 11 deletions(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f7a9852565..5d24029ff0 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -395,10 +395,19 @@ config TEGRA210_QSPI config TI_QSPI bool "TI QSPI driver" imply TI_EDMA3 + imply TI_QSPI_MQX_FRAME_SIZE help Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms. This driver support spi flash single, quad and memory reads. +config TI_QSPI_MAX_FRAME_SIZE + int "TI QSPI max frame size" + default 4096 + help + TI Quad-SPI (QSPI) IP block has a maximum number of 4096 words in a + frame, in non-memory mapped mode. A frame includes the command, + arguments and dummy bytes. + config UNIPHIER_SPI bool "Socionext UniPhier SPI driver" depends on ARCH_UNIPHIER diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 5fdbb49442..57192b9c0a 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; /* ti qpsi register bit masks */ #define QSPI_TIMEOUT 2000000 -#define QSPI_FCLK 192000000 +#define QSPI_FCLK 48000000 #define QSPI_DRA7XX_FCLK 76800000 #define QSPI_WLEN_MAX_BITS 128 #define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3) @@ -41,10 +41,11 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_EN_CS(n) (n << 28) #define QSPI_WLEN(n) ((n-1) << 19) #define QSPI_3_PIN BIT(18) -#define QSPI_RD_SNGL BIT(16) +#define QSPI_RD_SNGL (1 << 16) +#define QSPI_RD_DUAL (3 << 16) +#define QSPI_RD_QUAD (7 << 16) #define QSPI_WR_SNGL (2 << 16) #define QSPI_INVAL (4 << 16) -#define QSPI_RD_QUAD (7 << 16) /* device control */ #define QSPI_CKPHA(n) (1 << (2 + n*8)) #define QSPI_CSPOL(n) (1 << (1 + n*8)) @@ -155,6 +156,7 @@ static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + struct spi_slave *spi_slave = dev_get_parent_priv(dev); struct ti_qspi_priv *priv; struct udevice *bus; uint words = bitlen >> 3; /* fixed 8-bit word length */ @@ -182,7 +184,6 @@ static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen, /* Setup command reg */ priv->cmd = 0; - priv->cmd |= QSPI_WLEN(8); priv->cmd |= QSPI_EN_CS(cs); if (priv->mode & SPI_3WIRE) priv->cmd |= QSPI_3_PIN; @@ -206,15 +207,16 @@ static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen, writel(data, &priv->base->data1); data = cpu_to_be32(*txbuf++); writel(data, &priv->base->data); - cmd &= ~QSPI_WLEN_MASK; cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS); xfer_len = QSPI_WLEN_MAX_BYTES; } else { writeb(*txp, &priv->base->data); + cmd |= QSPI_WLEN(8); xfer_len = 1; } debug("tx cmd %08x dc %08x\n", cmd | QSPI_WR_SNGL, priv->dc); + // Only 1-bit write is supported writel(cmd | QSPI_WR_SNGL, &priv->base->cmd); status = readl(&priv->base->status); timeout = QSPI_TIMEOUT; @@ -229,9 +231,17 @@ static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen, debug("tx done, status %08x\n", status); } if (rxp) { + u32 rx; + /* Check for dual and quad reads */ + u32 readcmd_cmd = QSPI_RD_SNGL | QSPI_WLEN(8); + if (spi_slave->flags & SPI_XFER_DUAL_READ) + readcmd_cmd = QSPI_RD_DUAL | QSPI_WLEN(16); + if (spi_slave->flags & SPI_XFER_QUAD_READ) + readcmd_cmd = QSPI_RD_QUAD | QSPI_WLEN(32); + debug("rx cmd %08x dc %08x\n", - ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc); - writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd); + ((u32)(priv->cmd | readcmd_cmd)), priv->dc); + writel(priv->cmd | readcmd_cmd, &priv->base->cmd); status = readl(&priv->base->status); timeout = QSPI_TIMEOUT; while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { @@ -241,10 +251,28 @@ static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen, } status = readl(&priv->base->status); } - *rxp++ = readl(&priv->base->data); - xfer_len = 1; - debug("rx done, status %08x, read %02x\n", - status, *(rxp-1)); + rx = readl(&priv->base->data); + if (spi_slave->flags & SPI_XFER_QUAD_READ) { + if (words >= 1) + *rxp++ = rx >> 24; + if (words >= 2) + *rxp++ = rx >> 16; + if (words >= 3) + *rxp++ = rx >> 8; + if (words >= 4) + *rxp++ = rx; + xfer_len = (words >= 4) ? 4 : words; + } else if (spi_slave->flags & SPI_XFER_DUAL_READ) { + if (words >= 1) + *rxp++ = rx >> 8; + if (words >= 2) + *rxp++ = rx; + xfer_len = (words >= 2) ? 2 : words; + } else { + *rxp++ = rx; + xfer_len = 1; + } + debug("rx done, status %08x, rx=%08x\n", status, rx); } words -= xfer_len; } @@ -353,6 +381,23 @@ static int ti_qspi_exec_mem_op(struct spi_slave *slave, return ret; } +static int ti_qspi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) +{ +#ifdef CONFIG_TI_QSPI_MAX_FRAME_SIZE + // Adjust the data length to fit in the QSPI max frame length + if (op->data.dir == SPI_MEM_DATA_IN) { + unsigned int data_len = CONFIG_TI_QSPI_MAX_FRAME_SIZE - + sizeof(op->cmd.opcode) - op->addr.nbytes - + op->dummy.nbytes; + // Align the data on cache line + data_len = data_len & ~(ARCH_DMA_MINALIGN - 1); + op->data.nbytes = min(op->data.nbytes, data_len); + } +#endif + + return 0; +} + static int ti_qspi_claim_bus(struct udevice *dev) { struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); @@ -482,6 +527,7 @@ static int ti_qspi_ofdata_to_platdata(struct udevice *bus) static const struct spi_controller_mem_ops ti_qspi_mem_ops = { .exec_op = ti_qspi_exec_mem_op, + .adjust_op_size = ti_qspi_adjust_size, }; static const struct dm_spi_ops ti_qspi_ops = { From patchwork Sun Nov 29 10:39:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean Pihet X-Patchwork-Id: 1407912 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=newoldbits.com Authentication-Results: ozlabs.org; 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[81.240.2.208]) by smtp.gmail.com with ESMTPSA id w3sm7667691edt.84.2020.11.29.02.40.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Nov 2020 02:40:04 -0800 (PST) From: Jean Pihet To: u-boot@lists.denx.de Cc: Ryan Barnett , Conrad Ratschan , Hugo Cornelis , Arnout Vandecappelle , Jean Pihet Subject: [PATCH 3/3] TI QSPI: prevent a 4-byte write to the flash on read access Date: Sun, 29 Nov 2020 11:39:48 +0100 Message-Id: <20201129103948.158293-3-jean.pihet@newoldbits.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201129103948.158293-1-jean.pihet@newoldbits.com> References: <20201129103948.158293-1-jean.pihet@newoldbits.com> MIME-Version: 1.0 X-Mailman-Approved-At: Mon, 30 Nov 2020 00:56:47 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean In MMIO mode, a write to the flash generates write commands to the device. Prevent this from happening when reading from the device. Signed-off-by: Jean Pihet --- drivers/spi/ti_qspi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 57192b9c0a..40e1988df5 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -305,8 +305,6 @@ static void ti_qspi_copy_mmap(void *data, void *offset, size_t len) #else memcpy_fromio(data, offset, len); #endif - - *((unsigned int *)offset) += len; } static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,