From patchwork Fri Nov 27 22:51:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1407432 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=pjVUY+14; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CjVJD2zLJz9s1l for ; Sat, 28 Nov 2020 09:52:26 +1100 (AEDT) Received: from localhost ([::1]:35788 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kimbH-0001hM-AQ for incoming@patchwork.ozlabs.org; Fri, 27 Nov 2020 17:52:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51162) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kimaW-0001hE-2E for qemu-devel@nongnu.org; Fri, 27 Nov 2020 17:51:36 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:34680) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kimaS-00058F-SN for qemu-devel@nongnu.org; Fri, 27 Nov 2020 17:51:35 -0500 Received: by mail-wr1-x442.google.com with SMTP id k14so7087789wrn.1 for ; Fri, 27 Nov 2020 14:51:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3uZMzY6oF54xbyAFQYKRwpZtvEnzb9HX015RCXLfpWQ=; b=pjVUY+14jFJUqdJgZAS0vDYpiuya/0xywop/R3q2NQVYRM/Ni426uAmoNWSzE6O4R7 UIVPmyz11JuIoIzjHA3jhNZElKAuuOfGWkrVxX5RD8qwaiE07DKaKfbZgUQHlKA/Nij9 jkmaGafUnUYJgxD7iP875NDm7+k5UgGR/O8jLU0LruVnEmA8PyCo2WYCditxhlFeB04x qWuCE3a/dVwYOQRUmd/QGiaCVD4/3mSEjZnWFTx8g6ALEDG8qNNgg9Bw9dxxpMgAxm7/ IOmB0GQ0vEL67khtI3mVFGIEdibV+Q+6vsYxC9ZzMQxZib7RSG87SAZHMze+7QNukJrr /B9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3uZMzY6oF54xbyAFQYKRwpZtvEnzb9HX015RCXLfpWQ=; b=MFgYQQeXwJli+FQd41f5IyEly4We4tyifeiFBtl/uq24yHLzfns/nfkI0OL71m+qVC 1pn4YfXRMmrX8bYDJ67Kqca11u8mGmjbG7khHqTfgCpCnhtD6BblHoM3bgRBzI94OY4O CQaP4AHSizHzYKmsrg9faqpyusF2qxNiGIQS7TMl4yS9EzycnvqrwmfhwqkAKFXenpKu Yu7bzE5n27fCaPKdU0JioPi0x23fXqDlUTmAO2pjkjK72B6raG5aXRH+VXYz31rbFH1L njt3MRhh9GQNRAhloR2a0vFxXARtHckCzR7Z3EjdGrwzzL4FBJjcjAVIQjSuVwMJvLcM XCDg== X-Gm-Message-State: AOAM533wvTjnh5ohbbiXFq1NchMgxlDos0JeDSywKY098a76YaNeIZua bksODPoFbDQLb5MqQhhRIkaHaPN+iBOhzg== X-Google-Smtp-Source: ABdhPJwG0+NWSdaIsrx6NgiJtvPXBQ9DVp2JFa5+9LRh7pYaA1eJxNDb2LWEUJYgAUJ5qENe8EW2ag== X-Received: by 2002:adf:f9c6:: with SMTP id w6mr13433437wrr.273.1606517490828; Fri, 27 Nov 2020 14:51:30 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q16sm17429756wrn.13.2020.11.27.14.51.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Nov 2020 14:51:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 1/3] hw/openrisc/openrisc_sim: Use IRQ splitter when connecting IRQ to multiple CPUs Date: Fri, 27 Nov 2020 22:51:25 +0000 Message-Id: <20201127225127.14770-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201127225127.14770-1-peter.maydell@linaro.org> References: <20201127225127.14770-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Jia Liu Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" openrisc_sim_net_init() attempts to connect the IRQ line from the ethernet device to both CPUs in an SMP configuration by simply caling sysbus_connect_irq() for it twice. This doesn't work, because the second connection simply overrides the first. Fix this by creating a TYPE_SPLIT_IRQ to split the IRQ in the SMP case. Signed-off-by: Peter Maydell Reviewed-by: Stafford Horne --- hw/openrisc/openrisc_sim.c | 13 +++++++++++-- hw/openrisc/Kconfig | 1 + 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index d752282e675..a8adf6b70d7 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -34,6 +34,7 @@ #include "hw/sysbus.h" #include "sysemu/qtest.h" #include "sysemu/reset.h" +#include "hw/core/split-irq.h" #define KERNEL_LOAD_ADDR 0x100 @@ -64,8 +65,16 @@ static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors, s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); - for (i = 0; i < num_cpus; i++) { - sysbus_connect_irq(s, 0, cpu_irqs[i][irq_pin]); + if (num_cpus > 1) { + DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); + qdev_prop_set_uint32(splitter, "num-lines", num_cpus); + qdev_realize_and_unref(splitter, NULL, &error_fatal); + for (i = 0; i < num_cpus; i++) { + qdev_connect_gpio_out(splitter, i, cpu_irqs[i][irq_pin]); + } + sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0)); + } else { + sysbus_connect_irq(s, 0, cpu_irqs[0][irq_pin]); } sysbus_mmio_map(s, 0, base); sysbus_mmio_map(s, 1, descriptors); diff --git a/hw/openrisc/Kconfig b/hw/openrisc/Kconfig index 6c1e86884e2..8f284f3ba04 100644 --- a/hw/openrisc/Kconfig +++ b/hw/openrisc/Kconfig @@ -3,3 +3,4 @@ config OR1K_SIM select SERIAL select OPENCORES_ETH select OMPIC + select SPLIT_IRQ From patchwork Fri Nov 27 22:51:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1407434 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Y54RFybo; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CjVKT5Jxgz9s1l for ; Sat, 28 Nov 2020 09:53:33 +1100 (AEDT) Received: from localhost ([::1]:40040 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kimcN-0003Tx-Pf for incoming@patchwork.ozlabs.org; Fri, 27 Nov 2020 17:53:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51214) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kimaZ-0001hz-Un for qemu-devel@nongnu.org; Fri, 27 Nov 2020 17:51:41 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:37359) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kimaX-00058e-Fp for qemu-devel@nongnu.org; Fri, 27 Nov 2020 17:51:39 -0500 Received: by mail-wm1-x342.google.com with SMTP id h21so7759970wmb.2 for ; Fri, 27 Nov 2020 14:51:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sc7E18icOEP5e/KQwDEzq3DU5Jee3GKyEtql9RrB7e4=; b=Y54RFyboULFCwummQq0MDmC7bUGgh6aURKXJjnLdvswVaFQTvHtUn3pf2jz3JZKsu4 BAsfyQzySdrHFbh9Xs31r7luP66OhZ4G3ef3dm9bU1jPU6zb/7YaaogMtLF08ll92SkZ HLQSa6bQ7yjSZjNf4953e/cuGbuUhkC6PuBNpfQagZYXQxraPOpCdXQ4NgJ2lcmIM2jt TV0Zxuip1BUfo7YBzx7EXoVbe843xVnqUTQBWyefYJcXV5U5Ts1R9pRSQBFTusb7Wbqx 9MjjLVTMmHUvVS133F2zBIGUYAuxjAVMdmCP96mfKs5/8RqL5wQ27wzsZ+P0yjkb4+YW 6VHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sc7E18icOEP5e/KQwDEzq3DU5Jee3GKyEtql9RrB7e4=; b=qhPIVvfzemf9RpkXLRZi9SyIp+Jm+5wS8F7mHCllWh8lVkIPi1i05XiRSSz2zk9Udb mepaRm87ggwd4IuDd2+R081ec2qh/jOmdH/tmJXeaHXVkQFtrXnB/fwKE+bXav0yOPg/ U8Yl3Sqfck4KPHgsDi3nBmseCIjlRQfFYICItRm8b3pqdtuzxRS2EEPLcPqMSmxNm/+4 piFAob6VzRTy38HEtAZ14EFgqSf+hB23Cz1Pq4tjJFcZQU2NiAdh3Bz7R5dAgvFETS0E KFeWnP6djFsxoDd2usSKZwfJTuEkCgvUJWNY0Yryo+/pMEPTmgVFK9K33C9gWFdH/iGJ uzUQ== X-Gm-Message-State: AOAM532D2nG0zzddn5KeGzTzyzZWy9cchLAQ8QQph02nPQIX6oVL1FL+ vV+q/zCuL4+p7zjDT5++2dmAnSo5aFiuUg== X-Google-Smtp-Source: ABdhPJzCArvJ2Du+V4PpQH3SEZhmy49qesCtwYlvzJ4OMhx/uIKOZFDcqD54K5baUCyeB/zSpne4mQ== X-Received: by 2002:a1c:491:: with SMTP id 139mr11233781wme.81.1606517491946; Fri, 27 Nov 2020 14:51:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q16sm17429756wrn.13.2020.11.27.14.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Nov 2020 14:51:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 2/3] hw/openrisc/openrisc_sim: Abstract out "get IRQ x of CPU y" Date: Fri, 27 Nov 2020 22:51:26 +0000 Message-Id: <20201127225127.14770-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201127225127.14770-1-peter.maydell@linaro.org> References: <20201127225127.14770-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Jia Liu Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We're about to refactor the OpenRISC pic_cpu code in a way that means that just grabbing the whole qemu_irq[] array of inbound IRQs for a CPU won't be possible any more. Abstract out a function for "return the qemu_irq for IRQ x input of CPU y" so we can more easily replace the implementation. Signed-off-by: Peter Maydell Reviewed-by: Stafford Horne --- hw/openrisc/openrisc_sim.c | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index a8adf6b70d7..75ba0f47444 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -52,8 +52,13 @@ static void main_cpu_reset(void *opaque) cpu_set_pc(cs, boot_info.bootstrap_pc); } +static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin) +{ + return cpus[cpunum]->env.irq[irq_pin]; +} + static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors, - int num_cpus, qemu_irq **cpu_irqs, + int num_cpus, OpenRISCCPU *cpus[], int irq_pin, NICInfo *nd) { DeviceState *dev; @@ -70,18 +75,18 @@ static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors, qdev_prop_set_uint32(splitter, "num-lines", num_cpus); qdev_realize_and_unref(splitter, NULL, &error_fatal); for (i = 0; i < num_cpus; i++) { - qdev_connect_gpio_out(splitter, i, cpu_irqs[i][irq_pin]); + qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin)); } sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0)); } else { - sysbus_connect_irq(s, 0, cpu_irqs[0][irq_pin]); + sysbus_connect_irq(s, 0, get_cpu_irq(cpus, 0, irq_pin)); } sysbus_mmio_map(s, 0, base); sysbus_mmio_map(s, 1, descriptors); } static void openrisc_sim_ompic_init(hwaddr base, int num_cpus, - qemu_irq **cpu_irqs, int irq_pin) + OpenRISCCPU *cpus[], int irq_pin) { DeviceState *dev; SysBusDevice *s; @@ -93,7 +98,7 @@ static void openrisc_sim_ompic_init(hwaddr base, int num_cpus, s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); for (i = 0; i < num_cpus; i++) { - sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]); + sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin)); } sysbus_mmio_map(s, 0, base); } @@ -136,26 +141,24 @@ static void openrisc_sim_init(MachineState *machine) { ram_addr_t ram_size = machine->ram_size; const char *kernel_filename = machine->kernel_filename; - OpenRISCCPU *cpu = NULL; + OpenRISCCPU *cpus[2] = {}; MemoryRegion *ram; - qemu_irq *cpu_irqs[2]; qemu_irq serial_irq; int n; unsigned int smp_cpus = machine->smp.cpus; assert(smp_cpus >= 1 && smp_cpus <= 2); for (n = 0; n < smp_cpus; n++) { - cpu = OPENRISC_CPU(cpu_create(machine->cpu_type)); - if (cpu == NULL) { + cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type)); + if (cpus[n] == NULL) { fprintf(stderr, "Unable to find CPU definition!\n"); exit(1); } - cpu_openrisc_pic_init(cpu); - cpu_irqs[n] = (qemu_irq *) cpu->env.irq; + cpu_openrisc_pic_init(cpus[n]); - cpu_openrisc_clock_init(cpu); + cpu_openrisc_clock_init(cpus[n]); - qemu_register_reset(main_cpu_reset, cpu); + qemu_register_reset(main_cpu_reset, cpus[n]); } ram = g_malloc(sizeof(*ram)); @@ -164,15 +167,16 @@ static void openrisc_sim_init(MachineState *machine) if (nd_table[0].used) { openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus, - cpu_irqs, 4, nd_table); + cpus, 4, nd_table); } if (smp_cpus > 1) { - openrisc_sim_ompic_init(0x98000000, smp_cpus, cpu_irqs, 1); + openrisc_sim_ompic_init(0x98000000, smp_cpus, cpus, 1); - serial_irq = qemu_irq_split(cpu_irqs[0][2], cpu_irqs[1][2]); + serial_irq = qemu_irq_split(get_cpu_irq(cpus, 0, 2), + get_cpu_irq(cpus, 1, 2)); } else { - serial_irq = cpu_irqs[0][2]; + serial_irq = get_cpu_irq(cpus, 0, 2); } serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq, From patchwork Fri Nov 27 22:51:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1407436 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q16sm17429756wrn.13.2020.11.27.14.51.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Nov 2020 14:51:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 3/3] target/openrisc: Move pic_cpu code into CPU object proper Date: Fri, 27 Nov 2020 22:51:27 +0000 Message-Id: <20201127225127.14770-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201127225127.14770-1-peter.maydell@linaro.org> References: <20201127225127.14770-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Jia Liu Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The openrisc code uses an old style of interrupt handling, where a separate standalone set of qemu_irqs invoke a function openrisc_pic_cpu_handler() which signals the interrupt to the CPU proper by directly calling cpu_interrupt() and cpu_reset_interrupt(). Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they can have GPIO input lines themselves, and the neater modern way to implement this is to simply have the CPU object itself provide the input IRQ lines. Create GPIO inputs to the OpenRISC CPU object, and make the only user of cpu_openrisc_pic_init() wire up directly to those instead. This allows us to delete the hw/openrisc/pic_cpu.c file entirely. This fixes a trivial memory leak reported by Coverity of the IRQs allocated in cpu_openrisc_pic_init(). Fixes: Coverity CID 1421934 Signed-off-by: Peter Maydell Reviewed-by: Stafford Horne --- target/openrisc/cpu.h | 1 - hw/openrisc/openrisc_sim.c | 3 +- hw/openrisc/pic_cpu.c | 61 -------------------------------------- target/openrisc/cpu.c | 32 ++++++++++++++++++++ hw/openrisc/meson.build | 2 +- 5 files changed, 34 insertions(+), 65 deletions(-) delete mode 100644 hw/openrisc/pic_cpu.c diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index bd42faf144f..82cbaeb4f84 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -293,7 +293,6 @@ typedef struct CPUOpenRISCState { uint32_t picmr; /* Interrupt mask register */ uint32_t picsr; /* Interrupt contrl register*/ #endif - void *irq[32]; /* Interrupt irq input */ } CPUOpenRISCState; /** diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 75ba0f47444..39f1d344ae9 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -54,7 +54,7 @@ static void main_cpu_reset(void *opaque) static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin) { - return cpus[cpunum]->env.irq[irq_pin]; + return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin); } static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors, @@ -154,7 +154,6 @@ static void openrisc_sim_init(MachineState *machine) fprintf(stderr, "Unable to find CPU definition!\n"); exit(1); } - cpu_openrisc_pic_init(cpus[n]); cpu_openrisc_clock_init(cpus[n]); diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c deleted file mode 100644 index 36f93508309..00000000000 --- a/hw/openrisc/pic_cpu.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * OpenRISC Programmable Interrupt Controller support. - * - * Copyright (c) 2011-2012 Jia Liu - * Feng Gao - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#include "qemu/osdep.h" -#include "hw/irq.h" -#include "cpu.h" - -/* OpenRISC pic handler */ -static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) -{ - OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; - CPUState *cs = CPU(cpu); - uint32_t irq_bit; - - if (irq > 31 || irq < 0) { - return; - } - - irq_bit = 1U << irq; - - if (level) { - cpu->env.picsr |= irq_bit; - } else { - cpu->env.picsr &= ~irq_bit; - } - - if (cpu->env.picsr & cpu->env.picmr) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - cpu->env.picsr = 0; - } -} - -void cpu_openrisc_pic_init(OpenRISCCPU *cpu) -{ - int i; - qemu_irq *qi; - qi = qemu_allocate_irqs(openrisc_pic_cpu_handler, cpu, NR_IRQS); - - for (i = 0; i < NR_IRQS; i++) { - cpu->env.irq[i] = qi[i]; - } -} diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 5528c0918f4..b0bdfbe4fe2 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -65,6 +65,34 @@ static void openrisc_cpu_reset(DeviceState *dev) #endif } +#ifndef CONFIG_USER_ONLY +static void openrisc_cpu_set_irq(void *opaque, int irq, int level) +{ + OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; + CPUState *cs = CPU(cpu); + uint32_t irq_bit; + + if (irq > 31 || irq < 0) { + return; + } + + irq_bit = 1U << irq; + + if (level) { + cpu->env.picsr |= irq_bit; + } else { + cpu->env.picsr &= ~irq_bit; + } + + if (cpu->env.picsr & cpu->env.picmr) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + cpu->env.picsr = 0; + } +} +#endif + static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -88,6 +116,10 @@ static void openrisc_cpu_initfn(Object *obj) OpenRISCCPU *cpu = OPENRISC_CPU(obj); cpu_set_cpustate_pointers(cpu); + +#ifndef CONFIG_USER_ONLY + qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_IRQS); +#endif } /* CPU models */ diff --git a/hw/openrisc/meson.build b/hw/openrisc/meson.build index 57c42558e18..947f63ee087 100644 --- a/hw/openrisc/meson.build +++ b/hw/openrisc/meson.build @@ -1,5 +1,5 @@ openrisc_ss = ss.source_set() -openrisc_ss.add(files('pic_cpu.c', 'cputimer.c')) +openrisc_ss.add(files('cputimer.c')) openrisc_ss.add(when: 'CONFIG_OR1K_SIM', if_true: files('openrisc_sim.c')) hw_arch += {'openrisc': openrisc_ss}