From patchwork Fri Nov 27 13:05:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1407191 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CjFJl5j4kz9s0b for ; Sat, 28 Nov 2020 00:07:03 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.vnet.ibm.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=dkjs+0nc; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4CjFJl1q8gzDrc4 for ; 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Fri, 27 Nov 2020 13:05:23 +0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 0ARD5LeW6619692 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 27 Nov 2020 13:05:21 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A2705A4057; Fri, 27 Nov 2020 13:05:21 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CF444A4053; Fri, 27 Nov 2020 13:05:20 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.87.233]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 27 Nov 2020 13:05:20 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 27 Nov 2020 18:35:04 +0530 Message-Id: <20201127130505.724814-1-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-27_06:2020-11-26, 2020-11-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 suspectscore=1 spamscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011270076 Subject: [Skiboot] [PATCH 1/2] hw/ocmb: Fix log message X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Fix log message and convert perror to prlog. Also reduce message severity as its informational message, not error. Signed-off-by: Vasant Hegde --- hw/ocmb.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/ocmb.c b/hw/ocmb.c index 19b15dd68..30a5ad726 100644 --- a/hw/ocmb.c +++ b/hw/ocmb.c @@ -149,11 +149,10 @@ static bool ocmb_probe_one(struct dt_node *ocmb_node) } if (scom_register(&ocmb->scom)) - prerror("error registienr fake socm\n"); + prerror("Error registering fake scom\n"); dt_add_property(ocmb_node, "scom-controller", NULL, 0); - - prerror("XXX: Added scom controller for %s\n", ocmb_node->name); + prlog(PR_NOTICE, "Added scom controller for %s\n", ocmb_node->name); return true; } From patchwork Fri Nov 27 13:05:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1407190 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CjFHY1K4Dz9sSf for ; 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Fri, 27 Nov 2020 13:05:21 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.87.233]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 27 Nov 2020 13:05:21 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 27 Nov 2020 18:35:05 +0530 Message-Id: <20201127130505.724814-2-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201127130505.724814-1-hegdevasant@linux.vnet.ibm.com> References: <20201127130505.724814-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-27_06:2020-11-26, 2020-11-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 mlxlogscore=831 suspectscore=1 phishscore=0 malwarescore=0 spamscore=0 adultscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011270076 Subject: [Skiboot] [PATCH 2/2] hw/ocmb: Clear top bit from offset before searching addr range X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Looks like HBRT sets top bit in pcbaddress before making OCMB SCOM request. We have to clear that bit so that we can find proper address range for SCOM operation. Sample failure: [ 2578.156011925,3] OCMB: no matching address range! [ 2578.156044481,3] scom_read: to 80000028 off: 8006430d4008c000 rc = -26 Also move HRMOR_BIT macro to common include file (hdata/spira.h -> skiboot.h). Signed-off-by: Vasant Hegde --- hdata/spira.h | 6 ------ hw/ocmb.c | 3 ++- include/skiboot.h | 6 ++++++ 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/hdata/spira.h b/hdata/spira.h index f7a1b8237..0e658795c 100644 --- a/hdata/spira.h +++ b/hdata/spira.h @@ -6,12 +6,6 @@ #include "hdif.h" -/* - * To help the FSP to distinguish between physical address and TCE mapped address. - * Also to help hostboot to distinguish physical and relative address. - */ -#define HRMOR_BIT (1ul << 63) - /* * The SPIRA structure * diff --git a/hw/ocmb.c b/hw/ocmb.c index 30a5ad726..bc470d0ab 100644 --- a/hw/ocmb.c +++ b/hw/ocmb.c @@ -35,12 +35,13 @@ struct ocmb { static const struct ocmb_range *find_range(const struct ocmb *o, uint64_t offset) { int i; + uint64_t addr = offset & ~(HRMOR_BIT); for (i = 0; i < o->range_count; i++) { uint64_t start = o->ranges[i].start; uint64_t end = o->ranges[i].end; - if (offset >= start && offset <= end) + if (addr >= start && addr <= end) return &o->ranges[i]; } diff --git a/include/skiboot.h b/include/skiboot.h index 7b71ebd9f..d33c02506 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -143,6 +143,12 @@ static inline bool is_pow2(unsigned long val) #define PCI_DEV(bdfn) (((bdfn) >> 3) & 0x1f) #define PCI_FUNC(bdfn) ((bdfn) & 0x07) +/* + * To help the FSP to distinguish between physical address and TCE mapped address. + * Also to help hostboot to distinguish physical and relative address. + */ +#define HRMOR_BIT (1ul << 63) + /* Clean the stray high bit which the FSP inserts: we only have 52 bits real */ static inline u64 cleanup_addr(u64 addr) {