From patchwork Wed Nov 25 10:32:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 1406005 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CgxzX10xZz9sRK for ; Wed, 25 Nov 2020 21:32:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728889AbgKYKcX (ORCPT ); Wed, 25 Nov 2020 05:32:23 -0500 Received: from relay8-d.mail.gandi.net ([217.70.183.201]:34003 "EHLO relay8-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726591AbgKYKcW (ORCPT ); Wed, 25 Nov 2020 05:32:22 -0500 X-Originating-IP: 91.175.115.186 Received: from localhost (91-175-115-186.subs.proxad.net [91.175.115.186]) (Authenticated sender: gregory.clement@bootlin.com) by relay8-d.mail.gandi.net (Postfix) with ESMTPSA id 1C0A71BF205; Wed, 25 Nov 2020 10:32:18 +0000 (UTC) From: Gregory CLEMENT To: Thomas Gleixner , Jason Cooper , Marc Zyngier , linux-kernel@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org Cc: Thomas Petazzoni , Alexandre Belloni , Lars Povlsen , , Gregory CLEMENT Subject: [PATCH v5 1/6] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema Date: Wed, 25 Nov 2020 11:32:01 +0100 Message-Id: <20201125103206.136498-2-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201125103206.136498-1-gregory.clement@bootlin.com> References: <20201125103206.136498-1-gregory.clement@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert device tree bindings for Microsemi Ocelot SoC ICPU Interrupt Controller to YAML format Signed-off-by: Gregory CLEMENT Reviewed-by: Rob Herring --- .../mscc,ocelot-icpu-intr.txt | 21 ------- .../mscc,ocelot-icpu-intr.yaml | 60 +++++++++++++++++++ 2 files changed, 60 insertions(+), 21 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt deleted file mode 100644 index f5baeccb689f..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt +++ /dev/null @@ -1,21 +0,0 @@ -Microsemi Ocelot SoC ICPU Interrupt Controller - -Required properties: - -- compatible : should be "mscc,ocelot-icpu-intr" -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. -- interrupts : Specifies the CPU interrupt the controller is connected to. - -Example: - - intc: interrupt-controller@70000070 { - compatible = "mscc,ocelot-icpu-intr"; - reg = <0x70000070 0x70>; - #interrupt-cells = <1>; - interrupt-controller; - interrupt-parent = <&cpuintc>; - interrupts = <2>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml new file mode 100644 index 000000000000..be82920f6798 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microsemi Ocelot SoC ICPU Interrupt Controller + +maintainers: + - Alexandre Belloni + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +description: | + the Microsemi Ocelot interrupt controller that is part of the + ICPU. It is connected directly to the MIPS core interrupt + controller. + +properties: + compatible: + items: + - enum: + - mscc,ocelot-icpu-intr + + '#interrupt-cells': + const: 1 + + '#address-cells': + const: 0 + + interrupt-controller: true + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - '#interrupt-cells' + - '#address-cells' + - interrupt-controller + - reg + +additionalProperties: false + +examples: + - | + intc: interrupt-controller@70000070 { + compatible = "mscc,ocelot-icpu-intr"; + reg = <0x70000070 0x70>; + #interrupt-cells = <1>; + #address-cells = <0>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; +... From patchwork Wed Nov 25 10:32:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 1406004 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CgxzV1tpXz9sSf for ; Wed, 25 Nov 2020 21:32:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728910AbgKYKcX (ORCPT ); Wed, 25 Nov 2020 05:32:23 -0500 Received: from relay2-d.mail.gandi.net ([217.70.183.194]:39907 "EHLO relay2-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728885AbgKYKcX (ORCPT ); Wed, 25 Nov 2020 05:32:23 -0500 X-Originating-IP: 91.175.115.186 Received: from localhost (91-175-115-186.subs.proxad.net [91.175.115.186]) (Authenticated sender: gregory.clement@bootlin.com) by relay2-d.mail.gandi.net (Postfix) with ESMTPSA id D124740016; Wed, 25 Nov 2020 10:32:20 +0000 (UTC) From: Gregory CLEMENT To: Thomas Gleixner , Jason Cooper , Marc Zyngier , linux-kernel@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org Cc: Thomas Petazzoni , Alexandre Belloni , Lars Povlsen , , Gregory CLEMENT Subject: [PATCH v5 2/6] dt-bindings: interrupt-controller: Add binding for few Microsemi interrupt controllers Date: Wed, 25 Nov 2020 11:32:02 +0100 Message-Id: <20201125103206.136498-3-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201125103206.136498-1-gregory.clement@bootlin.com> References: <20201125103206.136498-1-gregory.clement@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the Device Tree binding documentation for the Microsemi Jaguar2, Luton and Serval interrupt controller that is part of the ICPU. It is connected directly to the MIPS core interrupt controller. Signed-off-by: Gregory CLEMENT Reviewed-by: Rob Herring --- .../bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml index be82920f6798..27b798bfe29b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml @@ -21,7 +21,11 @@ properties: compatible: items: - enum: + - mscc,jaguar2-icpu-intr + - mscc,luton-icpu-intr - mscc,ocelot-icpu-intr + - mscc,serval-icpu-intr + '#interrupt-cells': const: 1