From patchwork Thu Nov 19 14:38:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 1403059 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=jSGBGj6T; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CcMkX5vfwz9sTv for ; Fri, 20 Nov 2020 01:39:00 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727687AbgKSOis (ORCPT ); Thu, 19 Nov 2020 09:38:48 -0500 Received: from esa1.microchip.iphmx.com ([68.232.147.91]:59075 "EHLO esa1.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727214AbgKSOir (ORCPT ); Thu, 19 Nov 2020 09:38:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1605796727; x=1637332727; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=B6iK+n7nM/nQQNkN9ji7/vC55A4k5oqZAjN/W6Ui+Vw=; b=jSGBGj6TXqQT3bI4AM7PqhEGhTEHdq+f31yz+kkDXfT6ORlzPx5iz/H4 0FIv93DAc/CljMUKI5fx+xOwV8qTza4duvY15njKd/dNOKfNe7c8JhD8K yIJmCe2DjG/HmLyzcdf8MHsV26A50fKjF/tlDbkAOPczOVUx6WvhLMmkp E72zorK1XG/5Cm6w1zHdbIWMaiNioMi0EGcPa8DF7kfjFnlnOC1HALs5F GNNHQMJMVQzTgiznFdoLS8w9Oi/HGBK8IVgc9+r/yHSMs/xWnWFUilgru f71R73OuNMTTConF6/2flEfJPn/IfP3k7HWw7dj3KRmyC8Rjc3Jx2i9FC g==; IronPort-SDR: vLWaigX4mSxtPucuUExkuSflpXyLsDP7aee2Yh6mx+z4lA5yjQ1/t5fkVbvlx/6gtR4yHAgfjo kMxq54BGshN9Qbu8JZ5niUxYJhoyQcSumzpuUEU4tiIfqIaTsXwI2NWPUhlJwrCUpu5R7LuC2T s9R4Ew8+jEwPhQOO+RPdGyGrMzW9MT3U7fEBelN8BUOSLayGxpIzsklS8OOA8p3sc6wy4lj5rQ Q3+gH5DX9N2EjtqCkLp+kIK8m1bCsDQxUa12RQwWlbPsTI33RKhh5HcEuhUjO19vLFHtKexueP Wys= X-IronPort-AV: E=Sophos;i="5.77,490,1596524400"; d="scan'208";a="104251712" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Nov 2020 07:38:46 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 19 Nov 2020 07:38:46 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 19 Nov 2020 07:38:41 -0700 From: Claudiu Beznea To: , , , , , CC: , , , , Eugen Hristev , Claudiu Beznea Subject: [PATCH v5 02/11] dt-bindings: clock: at91: add sama7g5 pll defines Date: Thu, 19 Nov 2020 16:38:18 +0200 Message-ID: <1605796707-8378-3-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1605796707-8378-1-git-send-email-claudiu.beznea@microchip.com> References: <1605796707-8378-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Eugen Hristev Add SAMA7G5 specific PLL defines to be referenced in a phandle as a PMC_TYPE_CORE clock. Suggested-by: Claudiu Beznea Signed-off-by: Eugen Hristev [claudiu.beznea@microchip.com: adapt comit message, adapt sama7g5.c] Signed-off-by: Claudiu Beznea --- drivers/clk/at91/sama7g5.c | 6 +++--- include/dt-bindings/clock/at91.h | 10 ++++++++++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index a092a940baa4..7ef7963126b6 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -182,13 +182,13 @@ static const struct { .p = "audiopll_fracck", .l = &pll_layout_divpmc, .t = PLL_TYPE_DIV, - .eid = PMC_I2S0_MUX, }, + .eid = PMC_AUDIOPMCPLL, }, { .n = "audiopll_diviock", .p = "audiopll_fracck", .l = &pll_layout_divio, .t = PLL_TYPE_DIV, - .eid = PMC_I2S1_MUX, }, + .eid = PMC_AUDIOIOPLL, }, }, [PLL_ID_ETH] = { @@ -835,7 +835,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) if (IS_ERR(regmap)) return; - sama7g5_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1, + sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1, nck(sama7g5_systemck), nck(sama7g5_periphck), nck(sama7g5_gck), 8); diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h index eba17106608b..fab313f62e8f 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -25,6 +25,16 @@ #define PMC_PLLBCK 8 #define PMC_AUDIOPLLCK 9 +/* SAMA7G5 */ +#define PMC_CPUPLL (PMC_MAIN + 1) +#define PMC_SYSPLL (PMC_MAIN + 2) +#define PMC_DDRPLL (PMC_MAIN + 3) +#define PMC_IMGPLL (PMC_MAIN + 4) +#define PMC_BAUDPLL (PMC_MAIN + 5) +#define PMC_AUDIOPMCPLL (PMC_MAIN + 6) +#define PMC_AUDIOIOPLL (PMC_MAIN + 7) +#define PMC_ETHPLL (PMC_MAIN + 8) + #ifndef AT91_PMC_MOSCS #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ #define AT91_PMC_LOCKA 1 /* PLLA Lock */ From patchwork Thu Nov 19 14:38:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 1403061 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=rnWqg6tv; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CcMlX1mlwz9sT6 for ; Fri, 20 Nov 2020 01:39:52 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728159AbgKSOj0 (ORCPT ); Thu, 19 Nov 2020 09:39:26 -0500 Received: from esa4.microchip.iphmx.com ([68.232.154.123]:41650 "EHLO esa4.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728155AbgKSOjY (ORCPT ); Thu, 19 Nov 2020 09:39:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1605796764; x=1637332764; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=h/XRQsr7glEa2g/r6SVO2kTjj0kdJnjJ6hTe5rBjWKs=; b=rnWqg6tv2K21WDh8XLZIbFB7obcVbT4atwlIVMzojOKxG2vFy3cSekjA F557X934h4s2c6SWndCE6M2/NdwVr+4/oH+JNib8JP0LtNuX5J8QMTuwY TgpN4IBrBKA/oBKjbZXA2/VV7fpPpSfOp+ciQQt23kCIRufEjrV7CG6lL vA6Z7JmBXnktHtMDBO5/UGRixmTdT5fq1rR0hJxJiD1dI/88Eavsl4vNA cqONtxALvCWeXOj+TjiM+0O0LIh8A4oiaqZ0dET86cg0HZvVFBHMG0wR7 mgMohJmmTufPxOFpyqSYG3TrvjAOZWRpJF2RnZ6h/JwY6pyzpO4TVAgHT w==; IronPort-SDR: Pg28csdAmG+y2YdnZMckNF25qJuOttZZgdP2Z0TaaC69QrUwNXQUZSHOy7rat3dnKibUMwba0z g0UjwVMLSSGPr77ZYNOtO6dga5Euk5rCtzERnFbGURlwRlbf4iLq1uRpCQ3/INXsuELedQuoLA SPfzSCz93m443Y7TcBVGyulRmPqmy0OiHjq90/1g+5D/JSNgVQhFdrQQpou9ldBJRlvkVRVCpf Y015Rpa59C4lC2mrVnFz5T6luOrMGm21+2ZlkAY4CCLoR24bBQ+6GujTkFs65WPCfbJwV61/1i 9GM= X-IronPort-AV: E=Sophos;i="5.77,490,1596524400"; d="scan'208";a="94238056" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Nov 2020 07:39:23 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 19 Nov 2020 07:39:23 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 19 Nov 2020 07:39:20 -0700 From: Claudiu Beznea To: , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v5 11/11] clk: at91: sama7g5: register cpu clock Date: Thu, 19 Nov 2020 16:38:27 +0200 Message-ID: <1605796707-8378-12-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1605796707-8378-1-git-send-email-claudiu.beznea@microchip.com> References: <1605796707-8378-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Register CPU clock as being the master clock prescaler. This would be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the frequencies supported by SAMA7G5 could be directly received from CPUPLL + master clock prescaler and the extra divider would do no work in case it would be enabled. Signed-off-by: Claudiu Beznea --- drivers/clk/at91/sama7g5.c | 13 ++++++------- include/dt-bindings/clock/at91.h | 1 + 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 927eb3b2b126..a6e20b35960e 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -904,7 +904,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) if (IS_ERR(regmap)) return; - sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1, + sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1, nck(sama7g5_systemck), nck(sama7g5_periphck), nck(sama7g5_gck), 8); @@ -981,18 +981,17 @@ static void __init sama7g5_pmc_setup(struct device_node *np) } } - parent_names[0] = md_slck_name; - parent_names[1] = "mainck"; - parent_names[2] = "cpupll_divpmcck"; - parent_names[3] = "syspll_divpmcck"; - hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names, + parent_names[0] = "cpupll_divpmcck"; + hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names, &mck0_layout, &mck0_characteristics, &pmc_mck0_lock, CLK_SET_RATE_PARENT, 0); if (IS_ERR(hw)) goto err_free; - hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres", + sama7g5_pmc->chws[PMC_CPU] = hw; + + hw = at91_clk_register_master_div(regmap, "mck0", "cpuck", &mck0_layout, &mck0_characteristics, &pmc_mck0_lock, 0); if (IS_ERR(hw)) diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h index fab313f62e8f..98e1b2ab6403 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -34,6 +34,7 @@ #define PMC_AUDIOPMCPLL (PMC_MAIN + 6) #define PMC_AUDIOIOPLL (PMC_MAIN + 7) #define PMC_ETHPLL (PMC_MAIN + 8) +#define PMC_CPU (PMC_MAIN + 9) #ifndef AT91_PMC_MOSCS #define AT91_PMC_MOSCS 0 /* MOSCS Flag */